Semiconductor chip and semiconductor component

Abstract

Embodiments of the invention relate to a semiconductor chip (10), the sidewall (109) of which has a region which protrudes laterally by more than 2 µm in relation to a vertically adjoining sidewall region and forms an anchor structure (113). Further embodiments relate to a semiconductor component (20) comprising the semiconductor chip (10), a support (125) and an adhesive (128) for fastening the semiconductor chip (10) to the support (125). The adhesive (128) laterally adjoins the anchor structure (113) and extends vertically as far as a region of the anchor structure (113) that is remote from the support (125).

Description

[0001] SEMICONDUCTOR CHIP AND SEMICONDUCTOR COMPONENT

[0002] DESCRIPTION

[0003] For many applications, semiconductor chips are bonded to a suitable chip carrier or substrate using an adhesive. Generally, concepts are being sought that can make the bond between adhesive, substrate, and semiconductor chip more reliable.

[0004] The present invention is based on the object of providing an improved semiconductor chip, an improved semiconductor component and an improved method for producing a semiconductor chip.

[0005] According to embodiments, the problem is solved by the subject matter of the independent patent claims. Further developments are defined in the dependent patent claims.

[0006] According to embodiments, a semiconductor chip is provided, the side wall of which has a region which is larger than a vertically adjacent side wall region by more than

[0007] 2 pm laterally and forms an anchor structure. According to further embodiments, the anchor structure can protrude from a vertically adjacent side wall area by more than

[0008] 3 pm protrude laterally.

[0009] For example, the semiconductor chip may have at least two anchor structures arranged along a vertical direction of the sidewall.

[0010] According to embodiments, the semiconductor chip may further comprise a region of the sidewall that is retracted relative to a vertical sidewall of the chip extending from a chip top or bottom and forms a tapered region.

[0011] For example, the semiconductor chip may have two anchor structures arranged vertically along the sidewall of the semiconductor chip. Furthermore, the tapered region may be arranged between the two anchor structures.

[0012] According to further embodiments, a semiconductor component comprises a semiconductor chip as described above, a carrier, and an adhesive for attaching the semiconductor chip to the carrier. The adhesive is arranged laterally adjacent to the anchor structure and extends vertically to a region of the anchor structure facing away from the carrier.

[0013] For example, the following relationship can apply to the distance h of the anchor structure from a surface of the semiconductor chip facing away from the carrier: t / 4 < h < 0 , 4 * t , where t denotes the thickness of the semiconductor chip.

[0014] According to embodiments, the semiconductor chip comprises at least two anchor structures arranged along a vertical direction of the side wall. The adhesive extends to a bottom side of the anchor structure that is spaced furthest from the carrier.

[0015] For example, the following relationship may apply to the distance hl of the anchor structure which is furthest away from the carrier from the surface facing away from the carrier 125: hl < t / 3 , where t denotes the thickness of the semiconductor chip.

[0016] The semiconductor component may further comprise a region of the sidewall that is recessed relative to a vertical sidewall of the chip extending from a top or bottom side of the chip and forms a tapered region. The adhesive may be arranged along the tapered region.

[0017] For example, the tapered region can be positioned on a side of the anchor structure facing away from the support, which is arranged adjacent to the support. According to further embodiments, the tapered region can be positioned on a side of the anchor structure facing the support, which is arranged adjacent to the support.

[0018] A method for processing a semiconductor wafer comprises forming semiconductor chip components in or over the semiconductor wafer and dicing the semiconductor wafer into individual semiconductor chips. Dicing comprises forming separation trenches using a laser and plasma etching with a lateral component, wherein this process is stopped before the semiconductor wafer is severed. Dicing further comprises vertically expanding the separation trench using the laser and further plasma etching with a lateral component.

[0019] The accompanying drawings provide an understanding of embodiments of the invention. The drawings illustrate embodiments and, together with the description, serve to explain the same. Further embodiments and many of the intended advantages will be apparent from the following detailed description. The elements and structures shown in the drawings are not necessarily to scale. Like reference numerals refer to like or corresponding elements and structures.

[0020] Fig. 1A shows a schematic cross-sectional view of a

[0021] Semiconductor component according to embodiments.

[0022] Fig. 1B shows a schematic cross-sectional view of a

[0023] Semiconductor component according to further embodiments.

[0024] Fig. 2A shows a schematic cross-sectional view of a

[0025] Semiconductor component according to embodiments.

[0026] Fig. 2B shows a schematic cross-sectional view of a

[0027] Semiconductor component according to embodiments.

[0028] Figs. 3A and 3B each illustrate a semiconductor wafer in perspective view and in cross-sectional view to illustrate a method according to embodiments.

[0029] Fig. 4 summarizes a method according to embodiments.

[0030] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which specific embodiments are shown for purposes of illustration. In this context, directional terminology such as "top," "bottom," "front," "back," "over," "on," "in front of," "behind," "fore," "rear," etc., refers to the orientation of the figures just described. Since the components of the embodiments can be positioned in different orientations, the directional terminology is for the purpose of explanation only and is in no way limiting.

[0031] The description of the embodiments is not limiting, as other embodiments exist and structural or logical changes may be made without departing from the scope defined by the claims. In particular, elements of embodiments described below may be combined with elements of other described embodiments, unless the context indicates otherwise.

[0032] The terms "wafer" or "semiconductor substrate" used in the following description can encompass any semiconductor-based structure having a semiconductor surface. Wafer and structure are to be understood as including doped and undoped semiconductors, epitaxial semiconductor layers, optionally supported by a base support, and other semiconductor structures. For example, a layer of a first semiconductor material can be grown on a growth substrate of a second semiconductor material, for example a GaAs substrate, a GaN substrate, or a Si substrate, or of an insulating material, for example a sapphire substrate.

[0033] Depending on the intended use, the semiconductor can be based on a direct or an indirect semiconductor material. Examples of semiconductor materials particularly suitable for generating electromagnetic radiation include, in particular, nitride semiconductor compounds, which can be used to generate ultraviolet, blue, or longer-wavelength light, for example, such as GaN, InGaN, AlN, AlGaN, AlGaInN, AlGaInBN, phosphide semiconductor compounds, which can be used to generate green or longer-wavelength light, for example, such as GaAsP, AlGaInP, GaP, AlGaP, as well as other semiconductor materials such as GaAs, AlGaAs, InGaAs, AlInGaAs, SiC, ZnSe, ZnO, Ga2Oa, diamond, hexagonal BN, and combinations of the materials mentioned. The stoichiometric ratio of the compound semiconductor materials can vary. Further examples of semiconductor materials can include silicon, silicon-germanium, and germanium.In the context of this description, the term "semiconductor" also includes organic semiconductor materials.

[0034] The term "substrate" generally includes insulating, conductive, or semiconductor substrates.

[0035] The terms "lateral" and "horizontal," as used in this description, are intended to describe an orientation or alignment that is substantially parallel to a first surface of a substrate or semiconductor body. This can be, for example, the surface of a wafer or a chip (die).

[0036] The horizontal direction can, for example, lie in a plane perpendicular to a growth direction when growing layers.

[0037] The term "vertical," as used in this description, is intended to describe an orientation that is substantially perpendicular to the first surface of a substrate or semiconductor body. The vertical direction may, for example, correspond to a growth direction during layer growth.

[0038] Fig. 1A shows a cross-sectional view of a semiconductor device 20. The semiconductor device 20 includes a semiconductor chip 10 and a suitable carrier 125. For example, the carrier 125 may comprise a printed circuit board ("PCB") or a lead frame. The semiconductor chip 10 is attached to the carrier 125 via a suitable adhesive 128. Examples of the adhesive include, for example, an epoxy or silicone adhesive.

[0039] The semiconductor chip 10 can be designed in any desired way. For example, it can contain a substrate 100, for example a growth substrate made of a suitable material, for example Si or sapphire, and a semiconductor body 105. The semiconductor body 105 can have epitaxially grown layers. For example, a plurality of epitaxially grown layers can be arranged above the substrate 100. The semiconductor chip 10 can be suitable for generating or absorbing electromagnetic radiation. Accordingly, the epitaxially grown layers of the semiconductor body 105 can have layers for generating or absorbing electromagnetic radiation. According to further embodiments, the semiconductor chip 10 can also be suitable for other purposes, for example general electronics applications.For example, the semiconductor body 105 may comprise different semiconductor layers, for example dielectric or metallic layers. For example, a functional region of the semiconductor chip 10 may be formed in the semiconductor body 105. According to further embodiments, the semiconductor body may be omitted, and the functional region of the semiconductor chip is arranged in the substrate.

[0040] As shown in Fig. 1A, a sidewall 109 of the semiconductor chip 10 has a region which protrudes laterally from a vertically adjacent sidewall region by a distance w of, for example, more than 2 pm. This region forms an anchor structure, for example a first anchor structure 113. The adhesive 128 is arranged between the carrier 125 and the semiconductor chip 10 and further laterally adjacent to the anchor structure 113. Because the protruding region protrudes laterally by the distance w of, for example, more than 2 pm, the semiconductor chip 10 can be prevented from being pulled out of the adhesive bed 128. More precisely, the anchor structure 113 forms a type of hook, by means of which a resistance to pulling out the semiconductor chip 10 is increased. According to further embodiments, the distance w can be greater than 3 pm. In this way, the resistance can be further increased.

[0041] For example, an edge length d of the semiconductor chip 10, measured in the horizontal direction, can be greater than 200 or 300 pm. Correspondingly, a lateral dimension w of the protruding region can be greater than 1% of the edge length d of the semiconductor chip. According to further embodiments, the edge length d can also be greater than 500 pm. According to embodiments, the edge length d can also be less than 200 pm, for example less than 150 pm. As further shown in Fig. 1A, the adhesive 128 extends in the vertical direction up to a region of the first anchor structure 113 facing away from the carrier 125. In this way, anchoring of the semiconductor chip 10 can be ensured.

[0042] The semiconductor chip 10 shown in Fig. 1A furthermore has a tapered region 118. The tapered region is set back from an imaginary vertical sidewall 110 extending from a top or bottom side of the chip. More precisely, a concave region is formed in which the horizontal width is, for example, smaller than the width d of the semiconductor chip 10. Due to the presence of the tapered region 118, the effective surface area of ​​the sidewall 109 is enlarged, so that the adhesive 128 adjoins a larger area compared to a vertical sidewall. In this way, the adhesive effect can be increased.

[0043] As further illustrated in Fig. 1A, according to embodiments the tapered region 118 is arranged on a side of the first anchor structure 113 facing away from the carrier 125. As further shown in Fig. 1A, the adhesive 128 extends to a region of the semiconductor chip 10 which is arranged on a side of the tapered region 118 facing away from the carrier 125. At the transition between the tapered region 118 and a vertical side wall 110 of the semiconductor chip 10, for example, a second anchor structure 115 is arranged. For example, the adhesive 128 does not extend into a region with a greater distance from the carrier 125 than the distance between the second anchor structure 115 and the carrier 125. In this way, the second anchor structure 115 acts as an adhesive stop.The presence of the second anchor structure 115, which acts as an adhesive stop, can prevent adhesive 128 from getting into the region of the semiconductor body 105. Accordingly, the reliability of the semiconductor component can be increased. As further shown in Fig. 1A, the tapered region 118 is arranged between the first anchor structure 113 and the second anchor structure 115. For example, the anchor structure that acts as an adhesive stop can be arranged in the uppermost third of the semiconductor chip 10. With a thickness t of the semiconductor chip 10 measured in the vertical direction, the following relationship can apply, for example, to the distance hl of the uppermost anchor structure from the surface of the semiconductor chip 10 facing away from the carrier 125: hl < t / 3. Fig. 1B shows a cross-sectional view of a semiconductor component 20 with a semiconductor chip 10 according to further embodiments. Unlike in Fig.1A, the semiconductor chip 10 has an anchor structure 113 that protrudes from a vertical sidewall 110 of the semiconductor chip 10. This means that in a region facing the carrier 125, a width s of the semiconductor chip 10 is greater than in the region of the semiconductor body 105. The semiconductor chip 10 shown in FIG. 1B, for example, has only one anchor structure 113. Optionally, the anchor structure 113 can directly adjoin a vertical sidewall region 110. According to further embodiments, a tapered region 118, as described with reference to FIG. 1A, can be arranged directly above the first anchor structure 113. The first anchor structure 113, or the anchor structure that has the shortest distance from the carrier 125, can be arranged at a height h measured from the surface of the semiconductor chip 10 facing away from the carrier.For a thickness t of the semiconductor chip 10 measured in the vertical direction, the following relationship may apply: t / 4 < h < 0.4*t. For example, h may be less than approximately 50 pm.

[0044] Fig. 2A shows an example of a semiconductor component 20 according to further embodiments. The semiconductor component 20 in turn has a semiconductor chip 10, a carrier 125 and an adhesive 128. As shown in Fig. 2A, the semiconductor chip 10 has a first anchor structure 113 and a second anchor structure 115. A tapered region 118 is arranged between the first anchor structure 113 and the second anchor structure 115. The adhesive 128 extends as far as the second anchor structure 115. The second anchor structure 115 thus acts as an adhesive stop. Starting from a surface of the semiconductor chip 10 adjacent to the semiconductor body 105, a width of the semiconductor chip 10 decreases until a minimum width is reached. The width of the semiconductor chip then increases abruptly and subsequently the width of the semiconductor chip gradually decreases again.For example, a further tapered region 118 may be arranged on a side of the first anchor structure 113 facing the carrier 125. This type of step function may be generated by a suitable etching process, as will be explained below with reference to Figs. 3A and 3B.

[0045] Fig. 2B shows an example of a semiconductor component 20 according to further embodiments. The semiconductor chip 10 has, for example, a first anchor structure 113, a second anchor structure 115, and a third anchor structure 117. For example, the adhesive 128 can extend only as far as the third anchor structure 117. In this way, the third anchor structure 117 can act as an adhesive stop. The third anchor structure 117 is arranged on the side of the second anchor structure 115 facing the semiconductor body 105.

[0046] In embodiments shown in Fig. 2B, a width of the semiconductor chip 10 gradually increases, starting from a region adjacent to the semiconductor body 105. When a local maximum is reached, which is present at a position of the third anchor structure 117, the width of the semiconductor chip 10 decreases abruptly and then gradually increases again until the second anchor structure 115 is reached. Then, the width of the semiconductor chip 10 gradually increases again in the direction of the carrier 125. The first anchor structure 113 is present at the lowest maximum of the width.

[0047] For example, the structure shown in Fig. 2B can be manufactured by etching from a back side of the semiconductor chip, i.e., the side facing the carrier 125. Fig. 3A illustrates parts of a method for processing a semiconductor wafer according to embodiments. Typically, during the manufacture of semiconductor chips, components of the semiconductor chip are fabricated at wafer level. Subsequently, the wafer is diced into individual chips. Accordingly, the method for processing a semiconductor wafer 130 includes forming semiconductor chip components in or over the semiconductor wafer 130 and dicing the semiconductor wafer 130 into individual semiconductor chips 10.

[0048] The method comprises, in particular, forming separation trenches 133 using a laser 135. The upper part of Fig. 3A schematically illustrates the formation of the separation trenches 133 using the laser 135 in a perspective view. The lower part of Fig. 3A shows a cross-sectional view of the semiconductor wafer 130. As can be seen, separation trenches 133 are formed in the surface of the semiconductor wafer 130, i.e., in the semiconductor body 105 and in a part of the substrate 100 adjacent to the semiconductor body 105.

[0049] Plasma etching with a lateral component then takes place. This is illustrated schematically in Fig. 3B. The upper part of Fig. 3B shows a plasma chamber 139 in which the semiconductor wafer 130 with the formed separation trenches 133 is arranged. The lower part of Fig. 3B shows a schematic cross-sectional view of the semiconductor wafer 130 after this etching step has been carried out. As can be seen, the separation trenches widen in the etching direction, i.e. in the direction of a side of the workpiece facing away from the semiconductor body 105. As a result, the width of the resulting semiconductor chips 10 decreases towards the bottom. This process is carried out and ended before the semiconductor wafer 130 is severed. In a next step, the generated separation trench 133 is extended in the vertical direction using the laser 135, as indicated by broken lines in Fig. 3B.A further plasma etching process with a lateral component then takes place, resulting in a duplication of the pattern shown in Fig. 3B. This process can be repeated any number of times until the semiconductor wafer 130 is severed.

[0050] Fig. 4 summarizes a method according to embodiments. A method for processing a semiconductor wafer includes forming (S100) semiconductor chip components in or above the semiconductor wafer and dicing (S110) the semiconductor wafer into individual semiconductor chips. The dicing (S110) includes forming (S120) separation trenches using a laser, plasma etching (S125) with a lateral component, this process being stopped before the semiconductor wafer is severed. The method further includes vertically extending (S130) the separation trench using the laser, and further plasma etching (S135) with a lateral component.

[0051] As described, the semiconductor chip 10 having an anchor structure can ensure improved adhesion between the semiconductor chip 10 and the carrier 125. As a result, it is possible to ensure increased reliability even with a smaller chip size.

[0052] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent designs may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is limited only by the claims and their equivalents.

[0053] LIST OF REFERENCE SYMBOLS

[0054] 10 semiconductor chips

[0055] 20 semiconductor device 100 substrate

[0056] 105 semiconductor bodies

[0057] 109 Side wall

[0058] 110 vertical side wall

[0059] 113 first anchor structure 115 second anchor structure

[0060] 117 third anchor structure

[0061] 118 Rejuvenation area

[0062] 125 carriers

[0063] 128 Adhesive 130 Semiconductor wafer

[0064] 133 dividing ditch

[0065] 135 lasers

[0066] 139 Plasma Chamber

Claims

CLAIMS 1. A semiconductor component (20) comprising: a semiconductor chip (10); a carrier (125); and an adhesive (128) for fastening the semiconductor chip (10) to the carrier (125), wherein a side wall (109) of the semiconductor chip (10) has a region which protrudes laterally by more than 2 pm relative to a vertically adjacent side wall region and forms a first anchor structure (113), and the adhesive (128) is arranged between the carrier (125) and the semiconductor chip (10) and further laterally adjacent to the anchor structure (113) and extends vertically to a region of the anchor structure (113) facing away from the carrier (125).

2. Semiconductor component (20) according to claim 1, wherein a region of the side wall of the semiconductor chip (10) which adjoins a surface of the semiconductor chip (10) facing away from the carrier (125) is free of adhesive (128).

3. The semiconductor device (20) according to claim 1 or 2, wherein the semiconductor chip (10) further comprises a second anchor structure (115), wherein the first and second anchor structures (113, 115) are arranged along a vertical direction of the sidewall (109).

4. Semiconductor component (20) according to one of the preceding claims, wherein the semiconductor chip (10) further comprises a region of the sidewall (109) which is retracted relative to a vertical sidewall (110) of the semiconductor chip (10) extending from a chip top or bottom side and forms a tapered region (118).

5. Semiconductor component (20) according to claim 4, wherein the Semiconductor chip (10) has a second anchor structure (115), the first and the second anchor structure (113, 115) are arranged in the vertical direction along the side wall (109) of the semiconductor chip (10), and the tapered region (118) is arranged between the first and the second anchor structure (113, 115).

6. Semiconductor component (20) according to one of the preceding Claims, wherein the following relationship applies to the distance h of the anchor structure (113) from a surface of the semiconductor chip (10) facing away from the carrier (125): t / 4 < h < 0.4*t, where t denotes the thickness of the semiconductor chip (10).

7. Semiconductor component (20) according to claim 5 or 6, wherein the semiconductor chip (10) has a second anchor structure (115), the first and the second anchor structure (113, 115) are arranged along a vertical direction of the side wall (109), wherein the adhesive (128) extends to a bottom side of the anchor structure (115) which is spaced furthest from the carrier (125) and is not present in a region above the anchor structure (115).

8. Semiconductor component (20) according to claim 7, wherein the following relationship applies to the distance hl of that anchor structure (115) which is spaced furthest from the carrier (125) from the surface facing away from the carrier (125): hl < t / 3, where t denotes the thickness of the semiconductor chip (10).

9. Semiconductor component (20) according to one of claims 5 to 8, further comprising a region of the sidewall (109) which is retracted relative to a vertical sidewall (110) of the semiconductor chip (10) extending from a chip top or bottom and forms a tapered region (118), wherein the adhesive (128) is arranged along the tapered region (118).

10. The semiconductor component (20) according to claim 9, wherein the tapered region (118) is positioned on a side of the anchor structure (113) facing away from the carrier (125) and arranged adjacent to the carrier (125).

11. The semiconductor component (20) according to claim 9, wherein the tapered region (118) is positioned on a side of the anchor structure (113) facing the carrier (125) and arranged adjacent to the carrier (125).

12. A method for processing a semiconductor wafer (130), comprising forming (S100) semiconductor chip components in or over the semiconductor wafer (130) and singulating (S110) the semiconductor wafer (130) into individual semiconductor chips (10), wherein the singulating (S110) comprises: Forming (S120) separation trenches (133) using a laser (135); Plasma etching (S125) with a lateral component, wherein this process is stopped before the semiconductor wafer (130) is severed; vertical extension (S130) of the separation trench (133) using the laser (135); further plasma etching (S135) with a lateral component.

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