Semiconductor device

Abstract

The present invention provides a semiconductor device which is capable of achieving stable characteristics. According to an embodiment of the present invention, a semiconductor device includes an element part. The element part includes a semiconductor member that includes a pad part semiconductor region and a cell semiconductor region, a gate electrode, and a gate pad part which is electrically connected to the gate electrode. The gate pad part includes a first conductive member and a first member that is provided between the pad part semiconductor region and the first conductive member. The first member includes a first region and a second region, which are aligned in a second direction that intersects with a first direction from the pad part semiconductor region to the first conductive member. At least a part of the first conductive member is located between the first region and the second region. A first surface of the at least a part of the first conductive member includes first irregularities.

Description

Semiconductor Devices

[0001] FIELD An embodiment of the present invention relates to a semiconductor device.

[0002] For example, stable characteristics are desired in semiconductor devices.

[0003] Japanese Patent Application Laid-Open No. 2022-50887

[0004] The embodiment provides a semiconductor device that can obtain stable characteristics.

[0005] According to an embodiment, a semiconductor device includes an element portion. The element portion includes a semiconductor member including a pad portion semiconductor region and a cell semiconductor region, a gate electrode, and a gate pad portion electrically connected to the gate electrode. The gate pad portion includes a first conductive member and a first member provided between the pad portion semiconductor region and the first conductive member. The first member includes a first region and a second region aligned in a second direction intersecting a first direction from the pad portion semiconductor region to the first conductive member. At least a portion of the first conductive member is located between the first region and the second region. A first surface of the at least a portion of the first conductive member includes a first asperity.

[0006] FIG. 1 is a schematic cross-sectional view illustrating a portion of a semiconductor device according to a first embodiment. FIG. 2 is a schematic cross-sectional view illustrating a portion of a semiconductor device according to the first embodiment. FIG. 3 is a schematic plan view illustrating the semiconductor device according to the first embodiment. FIG. 4 is a schematic cross-sectional view illustrating a portion of a semiconductor device according to a second embodiment. FIG. 5 is a schematic cross-sectional view illustrating a portion of a semiconductor device according to a third embodiment. FIG. 6 is a schematic plan view illustrating a semiconductor device according to a fourth embodiment.

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions will be omitted as appropriate.

[0008] First Embodiment FIG. 1 is a schematic cross-sectional view illustrating a portion of a semiconductor device according to a first embodiment. FIG. 2 is a schematic cross-sectional view illustrating a portion of a semiconductor device according to the first embodiment. FIG. 3 is a schematic plan view illustrating a semiconductor device according to the first embodiment. FIG. 1 is a cross-sectional view taken along line A1-A2 in FIG. 3. FIG. 2 is a cross-sectional view taken along line B1-B2 in FIG. 3. As shown in FIGS. 1 to 3, a semiconductor device 110 according to the embodiment includes an element portion 10E. The element portion 10E includes a semiconductor member 10M, a gate electrode 53, and a gate pad portion 53P.

[0009] 1 and 2, the semiconductor member 10M includes a pad portion semiconductor region 18 and a cell semiconductor region 10s. The gate pad portion 53P is electrically connected to the gate electrode 53.

[0010] 1, the gate pad portion 53P includes a first conductive member 61. For example, the first conductive member 61 is electrically connected to the gate electrode 53 by a connection layer 53c (see FIGS. 1 and 2). The connection layer 53c may be provided at a position different from that shown in the cross section of FIGS. 1 and 2. The connection layer 53c may include, for example, at least one of polysilicon and metal. The first conductive member 61 functions as a pad portion conductive layer.

[0011] In this example, the gate pad portion 53P includes a first member 31. The first member 31 is provided between the pad portion semiconductor region 18 and a first conductive member 61. The first member 31 includes a first region 31a and a second region 31b. A second direction D2 from the first region 31a to the second region 31b intersects with the first direction D1 from the pad portion semiconductor region 18 to the first conductive member 61.

[0012] The first direction D1 is the Z-axis direction. One direction perpendicular to the Z-axis direction is the X-axis direction. The direction perpendicular to the Z-axis direction and the X-axis direction is the Y-axis direction. The second direction D2 may be, for example, the X-axis direction.

[0013] At least a portion of the first conductive member 61 is provided between the first region 31a and the second region 31b. At least a portion of a first surface 61F of the first conductive member 61 includes a first asperity 61dp. The first asperity 61dp is located above a step S1 provided between the first region 31a and the second region 31b. For example, the first asperity 61dp reflects the step S1 based on the first region 31a and the second region 31b. For example, the first asperity 61dp corresponds to the step S1 based on the first region 31a and the second region 31b. The step S1 is formed, for example, by the first region 31a and the second region 31b.

[0014] 2 illustrates the cell portion 10C of the element portion 10E. As shown in FIG. 2, the element portion 10E further includes a drain electrode 51 and a source electrode 52. For example, a semiconductor member 10M (cell semiconductor region 10s) is provided between the drain electrode 51 and the source electrode 52. A gate electrode 53 is provided between the semiconductor member 10M and the source electrode 52. An insulating layer 45 is provided between the gate electrode 53 and the source electrode 52, and between the gate electrode 53 and the semiconductor member 10M. The source electrode 52 functions as a source pad portion 52P.

[0015] The current flowing between the drain electrode 51 and the source electrode 52 can be controlled by the potential of the gate electrode 53. The semiconductor device 110 is a transistor. An example of the cell portion 10C will be described later.

[0016] In the embodiment, in the gate pad portion 53P, the first surface 61F of the first conductive member 61 includes the first asperity 61dp. This has been found to suppress various defects in wire bonding. This is thought to be because the provision of the first asperity 61dp makes the appropriate conditions for the wire bonding process closer to (or identical to) the appropriate conditions for the wire bonding process in the cell portion 10C.

[0017] As shown in FIG. 2 , in the cell unit 10C, second asperities 52dp are formed on the second surface 52F of the source electrode 52 due to the multiple gate electrodes 53. Appropriate conditions (e.g., second conditions) exist for wire bonding on the second surface 52F, including the second asperities 52dp. In the embodiment, by providing the first asperities 61dp on the first surface 61F of the first conductive member 61, the appropriate conditions (e.g., first conditions) for wire bonding on the first surface 61F can be made to match (or be close to) the second conditions. This makes it possible to suppress various defects (e.g., peeling, cracking, etc.) during the wire bonding process. Various defects are suppressed, resulting in stable characteristics. According to the embodiment, a semiconductor device capable of achieving stable characteristics can be provided.

[0018] When the first condition is identical to or close to the second condition, bonding can be performed with high productivity.

[0019] According to the embodiment, defects in the wire bonding process are suppressed, and a high yield is obtained. According to the embodiment, high reliability is obtained.

[0020] 3, for example, the gate electrode 53 extends along a third direction D3. The third direction D3 intersects with a plane including the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction. As shown in FIG. 3, the first region 31a and the second region 31b may extend along the third direction D3.

[0021] When the gate electrode 53 extends along the third direction D3, the second asperity 52dp on the second surface 52F of the source electrode 52 preferably extends along the third direction D3. When the first region 31a and the second region 31b extend along the third direction D3, the first asperity 61dp on the first surface 61F of the first conductive member 61 extends along the third direction D3. When the direction of the first asperity 61dp is aligned with the direction of the second asperity 52dp, bonding conditions are more likely to match. For example, characteristics become more stable. For example, defects are more effectively suppressed.

[0022] In the embodiment, the direction of the first irregularities 61dp may intersect with the direction of the second irregularities 52dp. In the embodiment, the first irregularities 61dp may extend in any direction along the XY plane. The first irregularities 61dp may be in a lattice shape or an island shape extending in two directions along the XY plane.

[0023] As shown in FIG. 1, a first length L1 and a first distance d1 can be defined. As shown in FIG. 2, a second length L2 and a second distance d2 can be defined. It is preferable that a first ratio of the first length L1 to the first distance d1 is equal to or close to a second ratio of the second length L2 to the second distance d2. This allows appropriate bonding conditions for the cell portion 10C (source pad portion 52P) and the gate pad portion 53P to match. Alternatively, it becomes easy to bring these appropriate conditions close to each other.

[0024] 1, the first length L1 is the length of the first region 31a along the second direction D2. The first distance d1 is the distance between the first region 31a and the second region 31b along the second direction D2. The length of the second region 31b along the second direction D2 may be the same as the first length L1.

[0025] 2 and 3, a plurality of gate electrodes 53 are provided. The plurality of gate electrodes 53 are arranged in a cross direction Dx that crosses the first direction D1. In this example, the cross direction Dx is the second direction D2. A second length L2 is the length of one of the plurality of gate electrodes 53 along the cross direction Dx. Another one of the plurality of gate electrodes 53 is adjacent to the above-mentioned one of the plurality of gate electrodes 53. A second distance d2 is the distance along the cross direction Dx between another one of the plurality of gate electrodes 53 and one of the plurality of gate electrodes 53.

[0026] The first and second ratios are defined based on these lengths. In this embodiment, the first ratio is preferably 0.5 to 1.5 times the second ratio. This makes it easier for the appropriate bonding conditions to match or be close to each other.

[0027] In one example, the first member 31 includes, for example, polysilicon.

[0028] 1, the gate pad portion 53P may further include a first insulating member 41. The first insulating member 41 includes a first insulating region 41a, a second insulating region 41b, and a third insulating region 41c. The first insulating region 41a is provided between the pad portion semiconductor region 18 and the first region 31a in the first direction D1. The second insulating region 41b is provided between the pad portion semiconductor region 18 and the second region 31b in the first direction D1. The third insulating region 41c is provided between the first insulating region 41a and the second insulating region 41b in the second direction D2. In one example, the first insulating member 41 includes, for example, silicon oxide.

[0029] 1, the gate pad portion 53P may further include a second member 32. The second member 32 is provided between the first region 31a and the first conductive member 61 in the first direction D1, between the second region 31b and the first conductive member 61 in the first direction D1, and between the third insulating region 41c and the first conductive member 61 in the first direction D1.

[0030] The second member 32 may include, for example, at least one selected from the group consisting of Ti, Mo, V, and TiW. For example, high adhesion can be easily obtained.

[0031] In the semiconductor device 110, the thickness of the first insulating member 41 may be, for example, 200 nm or more and 1000 nm or less. The thickness of the first member 31 may be, for example, 250 nm or more and 450 nm or less. The thickness of the second member 32 may be, for example, 100 nm or more and 200 nm or less. The thickness of the first conductive member 61 may be, for example, 3500 nm or more and 5000 nm or less. These thicknesses are lengths along the first direction D1.

[0032] As shown in FIG. 3 , the semiconductor device 110 may include a source electrode 52, a source connecting wire 52W, and a gate connecting wire 53W. The source connecting wire 52W is electrically connected to the source electrode 52. The gate connecting wire 53W is electrically connected to a gate pad portion 53P. The first thickness t53W of the gate connecting wire 53W may be the same as or close to the second thickness t52W of the source connecting wire 52W. This allows the appropriate bonding conditions for both to be the same or close to each other. For example, the first thickness t53W is 0.8 to 1.2 times the second thickness t52W. The materials of these wires may be the same.

[0033] 2, the cell semiconductor region 10s may include a first semiconductor region 11 of a first conductivity type, a second semiconductor region 12 of a second conductivity type, and a third semiconductor region 13 of the first conductivity type. In this example, the cell semiconductor region 10s further includes a fourth semiconductor region 14 of the second conductivity type. In this example, the cell semiconductor region 10s further includes a fifth semiconductor region 15 of the first conductivity type.

[0034] The first conductivity type is one of n-type and p-type. The second conductivity type is the other of n-type and p-type. Hereinafter, the first conductivity type is n-type and the second conductivity type is p-type.

[0035] The first semiconductor region 11 includes, for example, a first partial region 11 a, a second partial region 11 b, and a third partial region 11 c. The direction from the first partial region 11 a to the second partial region 11 b is along the intersecting direction Dx (for example, the second direction D2). The third partial region 11 c is located between the first partial region 11 a and the gate electrode 53 in the first direction D1.

[0036] The direction from the second partial region 11b to the second semiconductor region 12 is along the first direction D1. A part of the second semiconductor region 12 is located between the third partial region 11c and the third semiconductor region 13 in the intersecting direction Dx (e.g., the second direction D2). A part of the second semiconductor region 12 is located between the second partial region 11b and the third semiconductor region 13 in the first direction D1.

[0037] The third semiconductor region 13 is provided between the third partial region 11c and the fourth semiconductor region 14 in the intersecting direction Dx. A part of the second semiconductor region 12 is provided between the third partial region 11c and the third semiconductor region 13 in the intersecting direction Dx.

[0038] The source electrode 52 is electrically connected to the third semiconductor region 13 and the fourth semiconductor region 14. The source electrode 52 contacts the third semiconductor region 13 and the fourth semiconductor region 14.

[0039] A portion of the insulating layer 45 is provided between the third region 11c and the gate electrode 53. The portion of the insulating layer 45 functions as a gate insulating film. The portion of the insulating layer 45 includes silicon oxide.

[0040] In the semiconductor device 110, the impurity concentration of the first conductivity type in the third semiconductor region 13 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 11. The impurity concentration of the second conductivity type in the fourth semiconductor region 14 is higher than the impurity concentration of the second conductivity type in the second semiconductor region 12.

[0041] The fifth semiconductor region 15 is provided between the drain electrode 51 and the first semiconductor region 11. The fifth semiconductor region 15 is of the first conductivity type. The impurity concentration of the first conductivity type in the fifth semiconductor region 15 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 11.

[0042] Second Embodiment Fig. 4 is a schematic cross-sectional view illustrating a portion of a semiconductor device according to a second embodiment. As shown in Fig. 4, in a semiconductor device 111 according to the embodiment, an element portion 10E includes a gate pad portion 53P. The configuration of the gate pad portion 53P in the semiconductor device 111 is different from the configuration of the gate pad portion 53P in the first embodiment. Except for this, the configuration of the semiconductor device 111 may be similar to the configuration of the semiconductor device 110.

[0043] In the semiconductor device 111, the element portion 10E also includes a semiconductor member 10M, a gate electrode 53 (see FIG. 2), and a gate pad portion 53P. The semiconductor member 10M includes a pad portion semiconductor region 18 and a cell semiconductor region 10s (see FIG. 2). The gate pad portion 53P is electrically connected to the gate electrode 53.

[0044] 4, the gate pad portion 53P includes a first conductive member 61 and a first insulating member 41. The first insulating member 41 is provided between the pad portion semiconductor region 18 and the first conductive member 61. The first insulating member 41 includes a first insulating region 41a and a second insulating region 41b. A second direction D2 from the first insulating region 41a to the second insulating region 41b intersects with the first direction D1 from the pad portion semiconductor region 18 to the first conductive member 61. The second insulating region 41b is spaced apart from the first insulating region 41a in the second direction D2.

[0045] 4, the first surface 61F of the first conductive member 61 includes a first asperity 61dp. The first asperity 61dp reflects a step S1 formed by the first insulating region 41a and the second insulating region 41b. For example, the first asperity 61dp corresponds to the step S1 formed by the first insulating region 41a and the second insulating region 41b. The step S1 is formed by, for example, the first insulating region 41a and the second insulating region 41b.

[0046] In the semiconductor device 111, the appropriate bonding conditions for the gate pad portion 53P are the same as or close to the appropriate bonding conditions for the cell portion 10C (source pad portion 52P). Bonding defects are suppressed. Stable characteristics are obtained. According to the embodiment, a semiconductor device capable of obtaining stable characteristics can be provided. Bonding can be performed with high productivity. A high yield is obtained. High reliability is obtained.

[0047] In the semiconductor device 111, the gate electrode 53 also extends along a third direction D3 that intersects with a plane including the first direction D1 and the second direction D2 (see FIG. 3). It is preferable that the first insulating region 41 a and the second insulating region 41 b extend along the third direction D3.

[0048] As shown in Fig. 4, a first length L1 and a first distance d1 can also be defined for the semiconductor device 111. A second length L2 and a second distance d2 can also be defined for the semiconductor device 111 (see Fig. 2). As shown in Fig. 4, the first length L1 is the length of the first insulating region 41a along the second direction D2. The first distance d1 is the distance between the first insulating region 41a and the second insulating region 41b along the second direction D2.

[0049] In the semiconductor device 111, a plurality of gate electrodes 53 may be provided (see FIG. 2). The plurality of gate electrodes 53 are aligned in a cross direction Dx that crosses the first direction D1. The second distance d2 is the length of one of the plurality of gate electrodes 53 along the cross direction Dx. Another one of the plurality of gate electrodes 53 is adjacent to the above-mentioned one of the plurality of gate electrodes 53. The second distance d2 is the distance between another one of the plurality of gate electrodes 53 and one of the plurality of gate electrodes 53 along the cross direction Dx (see FIG. 2).

[0050] In the semiconductor device 111, the first ratio of the first length L1 to the first distance d1 may be 0.5 to 1.5 times the second ratio of the second length L2 to the second distance d2.

[0051] 4, in the semiconductor device 111, the gate pad portion 53P may further include a first member 31. The first member 31 includes a first region 31a, a second region 31b, and a third region 31c. The first region 31a is provided between the pad portion semiconductor region 18 and the first insulating region 41a. The second region 31b is provided between the pad portion semiconductor region 18 and the second insulating region 41b. The third region 31c is provided between the first region 31a and the second region 31b in the second direction D2. The first insulating member 41 is not provided between the third region 31c and the first conductive member 61 in the first direction D1.

[0052] 4, in the semiconductor device 111, the gate pad portion 53P may further include a second member 32. The second member 32 is provided between the first insulating region 41a and the first conductive member 61 in the first direction D1, between the second insulating region 41b and the first conductive member 61 in the first direction D1, and between the third region 31c and the first conductive member 61 in the first direction D1. The second member 32 may include at least one selected from the group consisting of Ti, Mo, V, and TiW, for example. This makes it easier to obtain high adhesion, for example.

[0053] 4, in the semiconductor device 111, the gate pad portion 53P may further include a second insulating member 42. The second insulating member 42 is provided between the pad portion semiconductor region 18 and the first member 31. The second insulating member 42 includes, for example, silicon oxide.

[0054] Third Embodiment Fig. 5 is a schematic cross-sectional view illustrating a portion of a semiconductor device according to a third embodiment. As shown in Fig. 5, in a semiconductor device 112 according to the embodiment, an element portion 10E includes a gate pad portion 53P. The configuration of the gate pad portion 53P in the semiconductor device 112 is different from the configuration of the gate pad portion 53P in the first embodiment. Except for this, the configuration of the semiconductor device 112 may be similar to the configuration of the semiconductor device 110.

[0055] In the semiconductor device 112, the element portion 10E also includes a semiconductor member 10M, a gate electrode 53 (see FIG. 2), and a gate pad portion 53P. The semiconductor member 10M includes a pad portion semiconductor region 18 and a cell semiconductor region 10s (see FIG. 2). The gate pad portion 53P is electrically connected to the gate electrode 53.

[0056] 5 , in the semiconductor device 112, the gate pad portion 53P includes a first conductive member 61 and a first insulating member 41. The first insulating member 41 is provided between the pad portion semiconductor region 18 and the first conductive member 61.

[0057] 5 , in the semiconductor device 112, the first insulating member 41 includes a first insulating region 41 a, a second insulating region 41 b, and a third insulating region 41 c. A second direction D2 from the first insulating region 41 a to the second insulating region 41 b intersects with a first direction D1 from the pad portion semiconductor region 18 to the first conductive member 61.

[0058] The position of the third insulating region 41c in the second direction D2 is between the positions of the first insulating region 41a and the second insulating region 41b in the second direction D2. The third thickness t3 of the third insulating region 41c in the first direction D1 is thinner than the first thickness t1 of the first insulating region 41a in the first direction D1. The third thickness t3 is thinner than the second thickness t2 of the second insulating region 41b in the first direction D1.

[0059] As shown in FIG. 5 , the first surface 61F of the first conductive member 61 includes a first asperity 61dp. The first asperity 61dp reflects, for example, a step S1 due to the first insulating region 41a, the second insulating region 41b, and the third insulating region 41c. The first asperity 61dp reflects, for example, a step S1 due to the first insulating region 41a, the second insulating region 41b, and the third insulating region 41c. The step S1 is formed, for example, by the first insulating region 41a, the second insulating region 41b, and the third insulating region 41c. Stable characteristics can also be obtained in the semiconductor device 112. According to the embodiment, a semiconductor device that can obtain stable characteristics can be provided. Bonding can be performed with high productivity. A high yield can be obtained. High reliability can be obtained.

[0060] In the semiconductor device 112, the gate electrode 53 also extends along a third direction D3 that intersects with a plane including the first direction D1 and the second direction D2 (see FIG. 2). The first insulating region 41 a and the second insulating region 41 b preferably extend along the third direction D3.

[0061] As shown in Fig. 5, a first length L1 and a first distance d1 can also be defined for the semiconductor device 112. A second length L2 and a second distance d2 can also be defined for the semiconductor device 112 (see Fig. 2). As shown in Fig. 5, the first length L1 is the length of the first insulating region 41a along the second direction D2. The first distance d1 is the distance between the first insulating region 41a and the second insulating region 41b along the second direction D2.

[0062] In the semiconductor device 112, a plurality of gate electrodes 53 may be provided (see FIG. 2). The plurality of gate electrodes 53 are aligned in a cross direction Dx that crosses the first direction D1. The second distance d2 is the length of one of the plurality of gate electrodes 53 along the cross direction Dx. Another one of the plurality of gate electrodes 53 is adjacent to the above-mentioned one of the plurality of gate electrodes 53. The second distance d2 is the distance between another one of the plurality of gate electrodes 53 and one of the plurality of gate electrodes 53 along the cross direction Dx (see FIG. 2).

[0063] In the semiconductor device 112, the first ratio of the first length L1 to the first distance d1 may be 0.5 to 1.5 times the second ratio of the second length L2 to the second distance d2.

[0064] 5, in the semiconductor device 112, the gate pad portion 53P may further include a first member 31. At least a portion of the first member 31 is provided between the first insulating region 41a and the second insulating region 41b in the second direction D2. At least a portion of the first member 31 is provided between the third insulating region 41c and the first conductive member 61 in the first direction D1. The first member 31 may include, for example, polysilicon.

[0065] 5, in the semiconductor device 112, the gate pad portion 53P may further include a second member 32. The second member 32 is provided between the first insulating region 41a and the first conductive member 61 in the first direction D1, between the second insulating region 41b and the first conductive member 61 in the first direction D1, and between the first member 31 and the first conductive member 61 in the first direction D1. The second member 32 may include, for example, at least one selected from the group consisting of Ti, Mo, V, and TiW. For example, this makes it easier to obtain high adhesion.

[0066] The semiconductor device 111 and the semiconductor device 112 may include a source electrode 52, a source connecting wire 52W, and a gate connecting wire 53W (see FIG. 3). The source connecting wire 52W is electrically connected to the source electrode 52. The gate connecting wire 53W is electrically connected to the gate pad portion 53P. The first thickness t53W of the gate connecting wire 53W may be the same as or close to the second thickness t52W of the source connecting wire 52W. This allows the appropriate bonding conditions for both to be the same or close to each other. For example, the first thickness t53W is 0.8 to 1.2 times the second thickness t52W. The materials of these wires may be the same.

[0067] (Fourth Embodiment) FIG. 6 is a schematic plan view illustrating a semiconductor device according to a fourth embodiment. As shown in FIG. 6, a semiconductor device 120 according to the embodiment has a plurality of element portions 10E. The configuration of the element portions 10E in the semiconductor devices 110, 111, and 112 is applied to the plurality of element portions 10E. The semiconductor device 120 is, for example, a semiconductor module. When a plurality of element portions 10E are provided, the number of bonding wires (such as source connection wires 52W and gate connection wires 53W) is large. By making the bonding process conditions uniform for many bonding wires, high manufacturing efficiency can be achieved. The effect of providing the first asperities 61dp is further enhanced.

[0068] In the embodiment, for example, the semiconductor member 10M (the pad portion semiconductor region 18 and the cell semiconductor region 10s) contains SiC. The semiconductor member 10M may contain at least one selected from the group consisting of 4H—SiC, 6H—SiC, and 3C—SiC. The semiconductor member 10M includes a crystal.

[0069] For example, the impurities of the first conductivity type include at least one selected from the group consisting of N, P, and As. For example, the impurities of the second conductivity type include at least one selected from the group consisting of B, Al, and Ga.

[0070] In an embodiment, information about the length and thickness can be obtained by electron microscopy, etc. Information about the composition of the material can be obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy Dispersive X-ray spectroscopy), etc.

[0071] The embodiments may include the following technical proposals: (Technical proposal 1) A semiconductor device comprising: an element portion including: a semiconductor member including a pad portion semiconductor region and a cell semiconductor region, a gate electrode, and a gate pad portion electrically connected to the gate electrode, wherein the gate pad portion includes: a first conductive member; and a first member provided between the pad portion semiconductor region and the first conductive member, wherein the first member includes a first region and a second region aligned in a second direction intersecting a first direction from the pad portion semiconductor region to the first conductive member, at least a portion of the first conductive member is located between the first region and the second region, and a first surface of the at least portion of the first conductive member includes a first unevenness.

[0072] (Technical Solution 2) The semiconductor device described in Technical Solution 1, wherein the gate electrode extends along a third direction intersecting a plane including the first direction and the second direction, and the first region and the second region extend along the third direction.

[0073] (Technical Solution 3) The semiconductor device according to Technical Solution 1, wherein the first member includes polysilicon.

[0074] (Technical proposal 4) A semiconductor device described in any one of Technical proposals 1 to 3, wherein the gate pad portion further includes a first insulating member, and the first insulating member includes a first insulating region, a second insulating region, and a third insulating region, and the first insulating region is provided between the pad portion semiconductor region and the first region in the first direction, the second insulating region is provided between the pad portion semiconductor region and the second region in the first direction, and the third insulating region is provided between the first insulating region and the second insulating region in the second direction.

[0075] (Technical proposal 5) A semiconductor device described in Technical proposal 4, wherein the gate pad portion further includes a second member, and the second member is provided between the first region and the first conductive member in the first direction, between the second region and the first conductive member in the first direction, and between the third insulating region and the first conductive member in the first direction.

[0076] (Technical Proposal 6) A semiconductor device according to any one of Technical Proposals 1 to 5, wherein a first ratio of a first length to a first distance is 0.5 to 1.5 times a second ratio of a second length to a second distance, the first length being a length of the first region along the second direction, and the first distance being a distance between the first region and the second region along the second direction, a plurality of the gate electrodes are provided, and the plurality of gate electrodes are arranged in an intersecting direction that intersects with the first direction, the second distance being a length of one of the plurality of gate electrodes along the intersecting direction, another of the plurality of gate electrodes being adjacent to the one of the plurality of gate electrodes, and the second distance being a distance along the intersecting direction between the other one of the plurality of gate electrodes and the one of the plurality of gate electrodes.

[0077] (Technical Proposal 7) A semiconductor device comprising: an element portion including: a semiconductor member including a pad portion semiconductor region and a cell semiconductor region; a gate electrode; and a gate pad portion electrically connected to the gate electrode, wherein the gate pad portion includes: a first conductive member; and a first insulating member provided between the pad portion semiconductor region and the first conductive member, wherein the first insulating member includes a first insulating region and a second insulating region aligned in a second direction intersecting a first direction from the pad portion semiconductor region to the first conductive member, the second insulating region being spaced apart from the first insulating region in the second direction, and a first surface of the first conductive member including a first unevenness.

[0078] (Technical Solution 8) A semiconductor device described in Technical Solution 7, wherein the gate electrode extends along a third direction intersecting a plane including the first direction and the second direction, and the first insulating region and the second insulating region extend along the third direction.

[0079] (Technical proposal 9) A semiconductor device according to Technical proposal 7 or 8, wherein the gate pad portion further includes a first member, the first member including a first region, a second region, and a third region, the first region being provided between the pad portion semiconductor region and the first insulating region, the second region being provided between the pad portion semiconductor region and the second insulating region, the third region being provided between the first region and the second region in the second direction, and the first insulating member not being provided between the third region and the first conductive member in the first direction.

[0080] (Technical proposal 10) A semiconductor device described in Technical proposal 9, wherein the gate pad portion further includes a second member, and the second member is provided between the first insulating region and the first conductive member in the first direction, between the second insulating region and the first conductive member in the first direction, and between the third region and the first conductive member in the first direction.

[0081] (Technical Solution 11) The semiconductor device according to Technical Solution 9 or 10, wherein the gate pad portion further includes a second insulating member, and the second insulating member is provided between the pad portion semiconductor region and the first member.

[0082] (Technical Proposal 12) A semiconductor device according to any one of Technical Proposals 7 to 11, wherein a first ratio of a first length to a first distance is 0.5 to 1.5 times a second ratio of a second length to a second distance, the first length being a length of the first insulating region along the second direction, the first distance being a distance between the first insulating region and the second insulating region along the second direction, a plurality of the gate electrodes are provided, the plurality of gate electrodes are arranged in an intersecting direction intersecting the first direction, the second distance being a length of one of the plurality of gate electrodes along the intersecting direction, another of the plurality of gate electrodes is adjacent to the one of the plurality of gate electrodes, and the second distance being a distance along the intersecting direction between the other one of the plurality of gate electrodes and the one of the plurality of gate electrodes.

[0083] (Technical Proposal 13) A semiconductor device comprising: an element portion including: a semiconductor member including a pad portion semiconductor region and a cell semiconductor region; a gate electrode; and a gate pad portion electrically connected to the gate electrode, wherein the gate pad portion includes: a first conductive member; and a first insulating member provided between the pad portion semiconductor region and the first conductive member, wherein the first insulating member includes a first insulating region, a second insulating region, and a third insulating region, a second direction from the first insulating region to the second insulating region intersects with a first direction from the pad portion semiconductor region to the first conductive member, a position of the third insulating region in the second direction is between a position of the first insulating region in the second direction and a position of the second insulating region in the second direction, a third thickness of the third insulating region in the first direction is thinner than a first thickness of the first insulating region in the first direction, and the third thickness is thinner than a second thickness of the second insulating region in the first direction, and a first surface of the first conductive member includes a first unevenness.

[0084] (Technical Solution 14) The semiconductor device described in Technical Solution 13, wherein the gate electrode extends along a third direction intersecting a plane including the first direction and the second direction, and the first insulating region and the second insulating region extend along the third direction.

[0085] (Technical proposal 15) The semiconductor device described in Technical proposal 13 or 14, wherein the gate pad portion further includes a first member, at least a portion of the first member being provided between the first insulating region and the second insulating region in the second direction, the at least a portion of the first member being provided between the third insulating region and the first conductive member in the first direction, and the first member including polysilicon.

[0086] (Technical Proposal 16) The semiconductor device described in Technical Proposal 15, wherein the gate pad portion further includes a second member, and the second member is provided between the first insulating region and the first conductive member in the first direction, between the second insulating region and the first conductive member in the first direction, and between the first member and the first conductive member in the first direction.

[0087] (Technical Proposal 17) A semiconductor device according to any one of Technical Proposals 13 to 16, wherein a first ratio of a first length to a first distance is 0.5 to 1.5 times a second ratio of a second length to a second distance, the first length being a length of the first insulating region along the second direction, and the first distance being a distance between the first insulating region and the second insulating region along the second direction, a plurality of the gate electrodes are provided, and the plurality of gate electrodes are arranged in an intersecting direction intersecting the first direction, the second distance being a length of one of the plurality of gate electrodes along the intersecting direction, and another of the plurality of gate electrodes is adjacent to the one of the plurality of gate electrodes, and the second distance being a distance along the intersecting direction between the other one of the plurality of gate electrodes and the one of the plurality of gate electrodes.

[0088] (Technical Proposal 18) A semiconductor device described in any one of Technical Proposals 1 to 17, further comprising: a source electrode; a source connecting wire electrically connected to the source electrode; and a gate connecting wire electrically connected to the gate pad portion, wherein the first thickness of the gate connecting wire is 0.8 to 1.2 times the second thickness of the source connecting wire.

[0089] (Technical Solution 19) The semiconductor device according to Technical Solution 18, wherein a plurality of the element portions are provided.

[0090] (Technical Solution 20) The semiconductor device according to any one of Technical Solutions 1 to 19, wherein the semiconductor member includes SiC.

[0091] According to the embodiment, a semiconductor device with improved characteristics can be provided.

[0092] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element included in the semiconductor device, such as electrodes, semiconductor members, conductive members, and insulating members, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0093] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0094] In addition, all semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0095] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0096] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0097] 10C: Cell portion, 10E: Element portion, 10M: Semiconductor member, 10s: Cell semiconductor region, 11-15: First to fifth semiconductor regions, 11a-11c: First to third partial regions, 18: Pad portion semiconductor region, 31, 32: First and second members, 31a-31c: First to third regions, 41, 42: First and second insulating members, 41a-41c: First to third insulating regions, 45: Insulating layer, 51: Drain electrode, 52: Source electrode, 52F: Second surface, 52P: Source pad portion, 52W: Source connecting wire, 52dp: Second unevenness, 53: Gate electrode, 53P: Gate pad portion, 53W: Gate connecting wire, 53c: Connection layer, 61: First conductive member, 61F: First surface, 61dp: first unevenness, 110-112, 120: semiconductor device, D1-D3: first to third directions, Dx: intersecting direction, S1: step, d1, d2: first and second distances, t1-t3: first to third thicknesses, t52W: second width, t53W: first width

Claims

1. A semiconductor device comprising: an element portion including: a semiconductor member including a pad portion semiconductor region and a cell semiconductor region; a gate electrode; and a gate pad portion electrically connected to the gate electrode, wherein the gate pad portion includes: a first conductive member; and a first member provided between the pad portion semiconductor region and the first conductive member, the first member including a first region and a second region aligned in a second direction intersecting a first direction from the pad portion semiconductor region to the first conductive member, at least a portion of the first conductive member being located between the first region and the second region, and a first surface of the at least a portion of the first conductive member including a first irregularity.

2. The semiconductor device according to claim 1, wherein the gate electrode extends along a third direction intersecting a plane including the first direction and the second direction, and the first region and the second region extend along the third direction.

3. The semiconductor device of claim 1, wherein a first ratio of a first length to a first distance is 0.5 to 1.5 times a second ratio of a second length to a second distance, the first length being a length of the first region along the second direction, the first distance being a distance between the first region and the second region along the second direction, a plurality of the gate electrodes are provided, the plurality of gate electrodes are arranged in an intersecting direction intersecting the first direction, the second distance being a length of one of the plurality of gate electrodes along the intersecting direction, another of the plurality of gate electrodes is adjacent to the one of the plurality of gate electrodes, and the second distance being a distance along the intersecting direction between the other one of the plurality of gate electrodes and the one of the plurality of gate electrodes.

4. A semiconductor device comprising: an element portion including a semiconductor member including a pad portion semiconductor region and a cell semiconductor region; a gate electrode; and a gate pad portion electrically connected to the gate electrode, wherein the gate pad portion includes: a first conductive member; and a first insulating member provided between the pad portion semiconductor region and the first conductive member, the first insulating member including a first insulating region and a second insulating region aligned in a second direction intersecting a first direction from the pad portion semiconductor region to the first conductive member, the second insulating region being spaced apart from the first insulating region in the second direction, and a first surface of the first conductive member including a first irregularity.

5. The semiconductor device according to claim 4, wherein the gate electrode extends along a third direction intersecting a plane including the first direction and the second direction, and the first insulating region and the second insulating region extend along the third direction.

6. The semiconductor device according to claim 4, wherein a first ratio of a first length to a first distance is 0.5 to 1.5 times a second ratio of a second length to a second distance, the first length being a length of the first insulating region along the second direction, the first distance being a distance along the second direction between the first insulating region and the second insulating region, a plurality of the gate electrodes are provided, the plurality of gate electrodes are arranged in an intersecting direction intersecting the first direction, the second distance being a length of one of the plurality of gate electrodes along the intersecting direction, another of the plurality of gate electrodes is adjacent to the one of the plurality of gate electrodes, and the second distance being a distance along the intersecting direction between the other one of the plurality of gate electrodes and the one of the plurality of gate electrodes.

7. A semiconductor device comprising: an element portion including a semiconductor member including a pad portion semiconductor region and a cell semiconductor region; a gate electrode; and a gate pad portion electrically connected to the gate electrode, wherein the gate pad portion includes: a first conductive member; and a first insulating member provided between the pad portion semiconductor region and the first conductive member, the first insulating member including a first insulating region, a second insulating region, and a third insulating region, a second direction from the first insulating region to the second insulating region intersects with a first direction from the pad portion semiconductor region to the first conductive member, a position of the third insulating region in the second direction is between a position of the first insulating region in the second direction and a position of the second insulating region in the second direction, a third thickness of the third insulating region in the first direction is thinner than a first thickness of the first insulating region in the first direction, and the third thickness is thinner than a second thickness of the second insulating region in the first direction, and a first surface of the first conductive member includes a first unevenness.

8. The semiconductor device according to claim 7, wherein the gate electrode extends along a third direction intersecting a plane including the first direction and the second direction, and the first insulating region and the second insulating region extend along the third direction.

9. The semiconductor device of claim 7, wherein a first ratio of a first length to a first distance is 0.5 to 1.5 times a second ratio of a second length to a second distance, the first length being a length of the first insulating region along the second direction, the first distance being a distance along the second direction between the first insulating region and the second insulating region, a plurality of the gate electrodes are provided, the plurality of gate electrodes are arranged in an intersecting direction intersecting the first direction, the second distance being a length of one of the plurality of gate electrodes along the intersecting direction, another of the plurality of gate electrodes is adjacent to the one of the plurality of gate electrodes, and the second distance being a distance along the intersecting direction between the other one of the plurality of gate electrodes and the one of the plurality of gate electrodes.

10. A semiconductor device according to any one of claims 1 to 8, further comprising: a source electrode; a source connection wire electrically connected to the source electrode; and a gate connection wire electrically connected to the gate pad portion, wherein a first thickness of the gate connection wire is 0.8 to 1.2 times the second thickness of the source connection wire.

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