Light detection element

Abstract

The present invention achieves the size reduction of a light detection element. This light detection element comprises a pixel provided with: a photoelectric conversion unit that is disposed on a semiconductor substrate and generates a charge; a first charge holding unit that holds the charge; a charge transfer unit that transfers the charge to the first charge holding unit; a signal generation unit that generates a signal corresponding to the charge held by the first charge holding unit; and a second charge holding unit that is composed of a capacitive element, which is formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate, and is coupled to the first charge holding unit. The capacitive element is composed of: a lower electrode which is disposed adjacent to the inner wall of an opening that is formed in a capacitive element insulating layer in which the capacitive element itself is formed; an insulating film which is configured into a shape that covers the lower electrode; and an upper electrode which is configured into a shape that faces the lower electrode in the opening, with the insulating film being interposed therebetween. The lower electrode is connected to a lower layer wiring line which is disposed in a lower layer of the wiring region. The upper electrode is connected to an upper layer wiring line which is disposed in an upper layer of the wiring region.

Description

Photodetector element

[0001] The present disclosure relates to a light-detecting element.

[0002] Among photodetector elements that generate image signals based on light from a subject, CMOS (Complementary Metal Oxide Semiconductor) photodetector elements include multiple pixels arranged in a two-dimensional matrix. Each pixel includes a photoelectric conversion unit that performs photoelectric conversion of incident light, a charge storage unit that stores charges generated by the photoelectric conversion unit, and a signal generation unit that generates a signal based on the charges stored in the charge storage unit. The photoelectric conversion unit performs photoelectric conversion during an exposure period and accumulates charges. After the exposure period, the charges are transferred to and stored in the charge storage unit. The signal generation unit then generates a signal based on the charges stored in the charge storage unit and outputs it as an image signal.

[0003] This charge storage portion uses a floating diffusion region (FD), which is a semiconductor region formed in a semiconductor substrate. When the charge storage capacity of this FD is insufficient or when the pixel is used for applications requiring switching of the charge storage capacity, an auxiliary charge storage portion is added to the pixel. A photodetector (image sensor) using a metal-insulator-metal (MIM) capacitance element as such an additional charge storage portion has been proposed (see, for example, Patent Document 1). This MIM capacitance element is disposed in an insulating layer in a wiring region adjacent to the semiconductor substrate, and is composed of a lower electrode, an insulating film, and an upper electrode disposed on the sidewall of a trench formed in the insulating layer.

[0004] The above-mentioned MIM capacitance element uses upper and lower electrodes whose ends are spaced apart to prevent short circuits between the upper and lower electrodes and an increase in leakage current due to insufficient creepage distance. Specifically, the lower electrode and insulating film of the MIM capacitance element are configured so that their ends extend in a direction parallel to the surface of the semiconductor substrate relative to the end of the upper electrode. This separates the ends of the upper and lower electrodes of the MIM capacitance element.

[0005] International Publication No. 2022 / 264939

[0006] However, in the above-mentioned conventional technology, the lower electrode has an end that extends in a direction parallel to the surface of the semiconductor substrate relative to the end of the upper electrode, which increases the area of ​​the MIM capacitance element, making it difficult to miniaturize the photodetector element.

[0007] Therefore, the present disclosure proposes a photodetector element that uses a capacitive element with a reduced size.

[0008] The photodetector element according to the present disclosure has a pixel including: a photoelectric conversion unit disposed on a semiconductor substrate and performing photoelectric conversion of incident light to generate charges; a first charge holding unit that holds the charges; a charge transfer unit that transfers the charges to the first charge holding unit; a signal generation unit that generates a signal according to the charges held in the first charge holding unit; and a second charge holding unit constituted by a capacitive element formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate and coupled to the first charge holding unit, wherein the capacitive element is constituted by a lower electrode disposed adjacent to an inner wall of an opening formed in a capacitive element insulating layer that is the insulating layer in which the capacitive element is formed; an insulating film configured to cover the lower electrode; and an upper electrode configured to face the lower electrode in the opening via the insulating film, wherein the lower electrode is connected to a lower layer wiring that is wiring disposed in a layer below the wiring region, and the upper electrode is connected to an upper layer wiring that is wiring disposed in a layer above the wiring region.

[0009] 1 is a diagram illustrating an example of a configuration of a photodetector element according to an embodiment of the present disclosure; FIG. 2 is a diagram illustrating an example of a configuration of a pixel according to an embodiment of the present disclosure; FIG. 3 is a cross-sectional view illustrating an example of a configuration of a pixel according to an embodiment of the present disclosure; FIG. 4 is a diagram illustrating an example of a configuration of a second charge holding unit according to a first embodiment of the present disclosure; FIG. 5 is a diagram illustrating an example of a configuration of a pixel according to the first embodiment of the present disclosure; FIG. 6 is a diagram illustrating an example of a configuration of a pixel according to the first embodiment of the present disclosure; FIG. 7 is a diagram illustrating an example of a manufacturing method of a photodetector element according to the first embodiment of the present disclosure; FIG. 8 is a diagram illustrating an example of a manufacturing method of a photodetector element according to the first embodiment of the present disclosure; FIG. 9 is a diagram illustrating an example of a manufacturing method of a photodetector element according to the first embodiment of the present disclosure; FIG. 10 is a diagram illustrating an example of a manufacturing method of a photodetector element according to the first embodiment of the present disclosure; FIG. 1 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the first embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating another example of a pixel configuration according to the first embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of a pixel configuration according to a second embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the second embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the second embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the second embodiment of the present disclosure.FIG. 1 is a diagram illustrating an example of a method for manufacturing a photodetector element according to a second embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the second embodiment of the present disclosure. FIG. 3 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the second embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of a configuration of a pixel according to a third embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the third embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example of a configuration of a pixel according to a fourth embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a configuration of a pixel according to a fourth embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example of a configuration of a pixel according to a fourth embodiment of the present disclosure. FIG. 9 is a diagram illustrating an example of a configuration of a pixel according to a fourth embodiment of the present disclosure. FIG. 10 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the fourth embodiment of the present disclosure. FIG. 11 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the fourth embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the fourth embodiment of the present disclosure. FIG. 10 is a diagram illustrating an example of a configuration of a pixel according to a fifth embodiment of the present disclosure. FIG. 11 is a diagram illustrating an example of a manufacturing method of a photodetector element according to a fifth embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example of a manufacturing method of a photodetector element according to a fifth embodiment of the present disclosure. FIG. 13 is a diagram illustrating an example of a manufacturing method of a photodetector element according to a fifth embodiment of the present disclosure. FIG. 14 is a diagram illustrating an example of a manufacturing method of a photodetector element according to a fifth embodiment of the present disclosure. FIG. 15 is a diagram illustrating an example of a manufacturing method of a photodetector element according to a sixth embodiment of the present disclosure. FIG. 16 is a diagram illustrating an example of a configuration of a pixel according to a sixth embodiment of the present disclosure.FIG. 10 is a diagram illustrating an example of a method for manufacturing a photodetector element according to a sixth embodiment of the present disclosure. FIG. 11 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the sixth embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the sixth embodiment of the present disclosure. FIG. 13 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the sixth embodiment of the present disclosure. FIG. 14 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the sixth embodiment of the present disclosure. FIG. 15 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the sixth embodiment of the present disclosure. FIG. 16 is a diagram illustrating an example of a method for manufacturing a photodetector element according to the sixth embodiment of the present disclosure. FIG. 17 is a diagram illustrating an example of a configuration of a pixel according to a seventh embodiment of the present disclosure. FIG. 18 is a diagram illustrating an example of a configuration of a pixel according to the seventh embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a configuration of a pixel according to the seventh embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a configuration of a pixel according to the seventh embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a configuration of a pixel according to the seventh embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a configuration of a pixel according to the seventh embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a configuration of a pixel according to the seventh embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a configuration of a pixel according to an eighth embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a configuration of a pixel according to an eighth embodiment of the present disclosure. FIG. 19 is a diagram illustrating another example of a pixel configuration according to the eighth embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example of a configuration of a pixel according to a ninth embodiment of the present disclosure. FIG. 13 is a diagram illustrating an example of a configuration of a pixel according to a ninth embodiment of the present disclosure. FIG. 14 is a diagram illustrating an example of a configuration of a pixel according to a ninth embodiment of the present disclosure. FIG. 15 is a diagram illustrating an example of a manufacturing method of a photodetector according to a ninth embodiment of the present disclosure. FIG. 16 is a diagram illustrating an example of a manufacturing method of a photodetector according to a ninth embodiment of the present disclosure. FIG. 17 is a diagram illustrating an example of a manufacturing method of a photodetector according to a ninth embodiment of the present disclosure. FIG. 18 is a diagram illustrating an example of a manufacturing method of a photodetector according to a ninth embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a manufacturing method of a photodetector according to a tenth embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a configuration of a pixel according to a tenth embodiment of the present disclosure.10 is a diagram illustrating an example of a method for manufacturing a photodetector according to a tenth embodiment of the present disclosure. FIG. 11 is a diagram illustrating an example of a method for manufacturing a photodetector according to a tenth embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example of a method for manufacturing a photodetector according to a tenth embodiment of the present disclosure. FIG. 13 is a diagram illustrating an example of a method for manufacturing a pixel according to a thirteenth embodiment of the present disclosure. FIG. 14 is a diagram illustrating an example of a method for manufacturing a pixel according to a thirteenth embodiment of the present disclosure. FIG. 15 is a diagram illustrating an example of a method for manufacturing a pixel according to a thirteenth embodiment of the present disclosure. FIG. 16 is a diagram illustrating an example of a pixel according to a thirteenth embodiment of the present disclosure. FIG. 17 is a diagram illustrating an example of a pixel according to a thirteenth embodiment of the present disclosure. FIG. 18 is a diagram illustrating another example of a pixel according to a thirteenth embodiment of the present disclosure. FIG. 19 is a diagram illustrating another example of a pixel according to a thirteenth embodiment of the present disclosure.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order. Note that in the following embodiments, the same components will be assigned the same reference numerals to avoid redundant description. 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Sixth embodiment 7. Seventh embodiment 8. Eighth embodiment 9. Ninth embodiment 10. Tenth embodiment 11. Eleventh embodiment 12. Twelfth embodiment 13. Thirteenth embodiment

[0011] (1. First Embodiment) [Configuration of Image Sensor] FIG. 1 is a diagram illustrating a configuration example of a photodetector according to an embodiment of the present disclosure. The figure is a block diagram illustrating a configuration example of a photodetector 1. The photodetector 1 is a semiconductor element that generates image data of a subject. The photodetector 1 includes a pixel array unit 10, a vertical drive unit 20, a column signal processing unit 30, and a control unit 40.

[0012] The pixel array unit 10 is configured by arranging a plurality of pixels 100. In this pixel array unit 10, the plurality of pixels 100 are arranged in a two-dimensional matrix. Here, each pixel 100 is configured to include a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit (a first charge holding unit 106 described later) that holds charges generated by the photoelectric conversion. For example, a photodiode can be used for the photoelectric conversion unit. In addition, a signal generation unit (a signal generation unit 110 described later) is arranged for each pixel 100. This signal generation unit 110 generates a pixel signal based on the charges held in the first charge holding unit 106 of the pixel 100.

[0013] A signal line 11 is wired to each pixel 100. The pixel 100 is controlled by a control signal transmitted through the signal line 11. A signal line 12 is also wired to the pixel 100. A pixel signal is output from a signal generating unit 110 to this signal line 12. The signal lines 11 are arranged in rows in the shape of a two-dimensional matrix, and are wired in common to the multiple pixels 100 arranged in one row. The signal line 12 is arranged in columns in the shape of a two-dimensional matrix, and is wired in common to the multiple pixels 100 arranged in one column.

[0014] The vertical drive unit 20 generates control signals for the above-described pixels 100. The vertical drive unit 20 in Fig. 1 generates a control signal for each row of the two-dimensional matrix of the pixel array unit 10 and sequentially outputs the control signals via signal lines 11. The vertical drive unit 20 is an example of a control signal generation unit described in the claims.

[0015] The column signal processing unit 30 processes pixel signals generated by the pixels 100. The column signal processing unit 30 in FIG. 1 simultaneously processes pixel signals from a plurality of pixels 100 arranged in one row of the pixel array unit 10, which are transmitted via signal lines 12. This processing can include, for example, analog-to-digital conversion, which converts analog pixel signals generated by the pixels 100 into digital pixel signals, and correlated double sampling (CDS), which removes offset errors in the pixel signals. The processed pixel signals are output as image signals to a circuit or the like external to the photodetector element 1.

[0016] The control unit 40 controls the vertical drive unit 20 and the column signal processing unit 30. The control unit 40 in Fig. 1 controls the vertical drive unit 20 and the column signal processing unit 30 by outputting control signals via signal lines 41 and 42, respectively.

[0017] 2 is a diagram showing an example of the configuration of a pixel according to an embodiment of the present disclosure. The figure is a circuit diagram showing an example of the configuration of a pixel 100.

[0018] The pixel 100 includes a photoelectric conversion unit 101, a charge transfer unit 102, a first charge holding unit 106, a reset unit 105, coupling transistors 103 and 104, second charge holding units 107 and 108, and a signal generation unit 110. The signal generation unit 110 also includes an amplification transistor 111 and a selection transistor 112.

[0019] The charge transfer unit 102, the coupling transistors 103 and 104, the amplifying transistor 111, and the selection transistor 112 can be configured using n-channel MOS transistors. The first charge holding unit 106 can be configured using a semiconductor region similar to the FD described above.

[0020] As described above, signal lines 11 and 12 are wired to the pixel 100. The signal lines 11 in FIG. 2 include signal lines TG, FDG, FCG, RST, and SEL. The signal lines 12 include signal line VSL. In addition, power supply lines VDD and MIMVDD are wired to the pixel 100. MIMVDD is a wire that supplies the applied voltage to the second charge holding units 107 and 108.

[0021] The anode of the photoelectric conversion unit 101 is grounded, and the cathode is connected to the source of the charge transfer unit 102. The drain of the charge transfer unit 102 is connected to the gate of the amplification transistor 111, the drain of the coupling transistor 103, and one end of the first charge holding unit 106. The other end of the first charge holding unit 106 is grounded. The drain of the reset unit 105 and the drain of the amplification transistor 111 are connected to a power supply line Vdd. The source of the reset unit 105 is connected to a node 302. The drain of the coupling transistor 104 and one end of the second charge holding unit 108 are connected to this node 302. The other end of the second charge holding unit 108 is connected to MIMVDD. The source of the coupling transistor 104 is connected to a node 301. The drain of the coupling transistor 103 and one end of the second charge holding unit 107 are connected to this node 301. The other end of the second charge holding unit 107 is connected to MIMVDD. The source of the amplification transistor 111 is connected to the drain of the selection transistor 112, and the source of the selection transistor 112 is connected to a signal line VSL.

[0022] The gate of the charge transfer unit 102 is connected to a signal line TG. The gate of the reset unit 105 is connected to a signal line RST. The gate of the coupling transistor 103 is connected to a signal line FDG. The gate of the coupling transistor 104 is connected to a signal line FCG. The gate of the selection transistor 112 is connected to a signal line SEL.

[0023] The reset unit 105 resets the first charge holding unit 106 and the second charge holding units 107 and 108. This resetting can be performed by discharging the charges in the first charge holding unit 106 and the like to the power supply line VDD. A control signal for the reset unit 105 is transmitted via a signal line RST.

[0024] The amplification transistor 111 amplifies the voltage of the first charge holding unit 106. The gate of the amplification transistor 111 is connected to the first charge holding unit 106. Therefore, a pixel signal having a voltage corresponding to the charge held in the first charge holding unit 106 is generated at the source of the amplification transistor 111. Furthermore, by making the selection transistor 112 conductive, this pixel signal can be output to a signal line VSL. A control signal for the selection transistor 112 is transmitted via a signal line SEL.

[0025] The second charge holding units 107 and 108 are capacitors coupled to the first charge holding unit 106. By coupling the second charge holding units 107 and 108 to the first charge holding unit 106, the charge holding capacity of the pixel 100 can be adjusted. That is, by coupling the second charge holding units 107 and 108 to the first charge holding unit 106, the charge holding capacity of the pixel 100 can be increased. This allows the sensitivity of the pixel 100 to be adjusted. When the second charge holding units 107 and 108 are not coupled to the first charge holding unit 106, the pixel operates in a high sensitivity mode. When the second charge holding units 107 and 108 are coupled to the first charge holding unit 106, the pixel operates in a low sensitivity mode. When only the second charge holding unit 107 is coupled to the first charge holding unit 106, the pixel operates in a medium sensitivity mode.

[0026] The coupling transistor 103 couples the second charge holding portion 107 to the first charge holding portion 106. The coupling transistor 104 couples the second charge holding portion 108 to the first charge holding portion 106.

[0027] 3 is a timing diagram illustrating an example of pixel signal generation in the pixel 100 according to an embodiment of the present disclosure.

[0028] 3, "SEL," "RST," "FCG," "FDG," and "TG" represent signals on the signal lines SEL, RST, FCG, FDG, and TG in the pixel 100. Also, "MIMVDD" represents a voltage supplied by MIMVDD. "VSL" represents a pixel signal output to the signal line VSL.

[0029] For the "SEL", "RST", "FCG", "FDG", and "TG" signals, the portion of the binarized waveform with a value of "1" represents the on-voltage (Von). A voltage of 3 V, for example, can be applied as this on-voltage. The portion with a value of "0" represents the off-voltage. The dashed line in FIG. 3 represents the level of the off-voltage. For example, 0 V or a negative voltage (for example, -1.2 V) can be applied as this off-voltage.

[0030] In the initial state, an off voltage is input to the signal lines SEL, RST, FCG, FDG, and TG. Also, a voltage of the second charge holding unit 107 and the like is applied to the MIMVDD.

[0031] At T1, an on-voltage is input from the signal lines RST, FCG, FDG, and TG, which turns on the reset unit 105, the coupling transistors 103 and 104, and the charge transfer unit 102, thereby resetting the photoelectric conversion unit 101, the first charge holding unit 106, and the second charge holding units 107 and 108.

[0032] At T2, the input of on-voltage to the signal lines RST, FCG, FDG, and TG is stopped. This stops the resetting of the photoelectric conversion unit 101, the first charge holding unit 106, and the second charge holding units 107 and 108, and an exposure period begins. Charges generated by photoelectric conversion are accumulated in the photoelectric conversion unit 101. Furthermore, the application of the MIMVDD voltage is stopped.

[0033] At T3, an on voltage is input from the signal line FCG and the signal line FDG, and a voltage of the second charge holding unit 107 and the like is applied to MIMVDD.

[0034] At T4, the input of the on voltage from the signal line FCG is stopped. As a result, only the coupling transistor 103 is in a conductive state. This state is the reset state of the medium sensitivity mode. Also, an on voltage is input from the signal line SEL, and the selection transistor 112 is in a conductive state. As a result, the signal generation unit 110 starts outputting a pixel signal at the reset time of the medium sensitivity mode. "A" in FIG. 3 for the signal line VSL represents a pixel signal at the reset level of the medium sensitivity mode.

[0035] At T5, the input of the on-voltage from the signal line FDG is stopped. This causes the coupling transistor 103 to enter a non-conductive state. This state is the reset state of the high-sensitivity mode. The signal generation unit 110 starts outputting pixel signals at the reset time of the high-sensitivity mode. "B" in FIG. 3 for the signal line VSL represents the pixel signal at the reset level of the high-sensitivity mode.

[0036] At T6, an on-voltage is input from the signal line TG, which causes the charge transfer unit 102 to become conductive, and the charge in the photoelectric conversion unit 101 is transferred to the first charge holding unit 106.

[0037] At T7, the input of the ON voltage from the signal line TG is stopped, thereby ending the exposure period. The signal generation unit 110 generates a pixel signal "C" and outputs it to the signal line VSL. This pixel signal corresponds to the pixel signal with a signal level in the high-sensitivity mode.

[0038] At T8, an on-voltage is input from the signal lines FDG and TG, and the coupling transistor 103 and the charge transfer unit 102 become conductive. The charge in the first charge holding unit 106 is distributed to the first charge holding unit 106 and the second charge holding unit 107.

[0039] At T9, the input of the on-voltage from the signal line TG is stopped. The signal generation unit 110 generates a pixel signal "D" and outputs it to the signal line VSL. This pixel signal corresponds to a pixel signal with a signal level in the medium sensitivity mode.

[0040] At T10, an on-voltage is input from the signal lines FCG and TG, and the coupling transistors 103 and 104 and the charge transfer unit 102 are turned on. The charges in the first charge holding unit 106 and the second charge holding unit 107 are distributed to the first charge holding unit 106, the second charge holding unit 107, and the second charge holding unit 108.

[0041] At T11, the input of the on-voltage from the signal line TG is stopped. The signal generation unit 110 generates a pixel signal "E" and outputs it to the signal line VSL. This pixel signal corresponds to the pixel signal with a signal level in the low-sensitivity mode.

[0042] At T12, an on-voltage is input from the signal line RST, and the reset unit 105 becomes conductive. Since the coupling transistors 103 and 104 are conductive, the first charge holding unit 106 and the second charge holding units 107 and 108 are reset.

[0043] At T13, the input of the on-voltage from the signal line RST is stopped. The signal generation unit 110 starts outputting the pixel signal at the reset time in the low-sensitivity mode. "F" in FIG. 3 on the signal line VSL represents the pixel signal at the reset level in the low-sensitivity mode.

[0044] At T14, the application of the on-voltage to the signal line SEL is stopped, and the pixel 100 is placed in a non-selected state, thereby returning to the initial state.

[0045] Thereafter, CDS can be performed by subtracting the pixel signal of the reset level (corresponding to value F) from the pixel signal of the signal level in the low sensitivity mode (corresponding to value E). Similarly, the pixel signal of the reset level (corresponding to value A) is subtracted from the pixel signal of the signal level in the medium sensitivity mode (corresponding to value D), and the pixel signal of the reset level (corresponding to value B) is subtracted from the pixel signal of the signal level in the high sensitivity mode (corresponding to value C). These pixel signals after CDS are output from the column signal processing unit 30.

[0046] Through the above procedure, a pixel signal can be generated in the pixel 100.

[0047] 4 is a cross-sectional view showing an example of the configuration of a pixel according to an embodiment of the present disclosure. The figure is a cross-sectional view showing an example of the configuration of a pixel 100. The pixel 100 includes a semiconductor substrate 120, a wiring region 140, a color filter 192, and an on-chip lens 193.

[0048] The semiconductor substrate 120 is a semiconductor substrate on which diffusion layers of the semiconductor elements of the pixel 100 are disposed. The semiconductor substrate 120 can be made of, for example, silicon (Si). The semiconductor elements and the like are disposed in well regions formed in the semiconductor substrate 120. For convenience, it is assumed that the semiconductor substrate 120 in FIG. 4 is configured in a p-type well region. A semiconductor element can be formed by disposing an n-type or p-type semiconductor region in this p-type well region. An insulating film 139 is disposed on the front surface of the semiconductor substrate 120. This insulating film 139 can be made of, for example, silicon oxide (SiO ２ ) or silicon nitride (SiN) can be applied.

[0049] 4 shows the semiconductor substrate 120 including the photoelectric conversion unit 101, the first charge holding unit 106, the charge transfer unit 102, and the amplification transistor 111. The photoelectric conversion unit 101 is composed of an n-type semiconductor region 121. Specifically, the photodiode formed by the pn junction at the interface between the n-type conductivity semiconductor region 121 and a surrounding p-type well region corresponds to the photoelectric conversion unit 101. The semiconductor region 121 is configured so that a portion of it protrudes near the surface on the front side of the semiconductor substrate 120.

[0050] The first charge holding portion 106 is configured by a semiconductor region 122. This semiconductor region 122 is an n-type semiconductor region with a relatively high impurity concentration. The semiconductor region 122 corresponds to the FD described above.

[0051] The charge transfer unit 102 is composed of a MOS transistor including semiconductor regions 121 and 122 and a gate electrode 131. The semiconductor region 121 corresponds to the source region, and the semiconductor region 122 corresponds to the drain region. Note that an insulating film 139 directly below the gate electrode 131 corresponds to the gate insulating film.

[0052] Only the gate electrode of the amplification transistor 111 is shown. This gate electrode is connected to the semiconductor region 122 of the first charge holding unit 106 by a wiring 151 and a contact plug 153, which will be described later. An isolation unit 129 for isolating the amplification transistor 111 from other elements is disposed in the semiconductor substrate 120 near the amplification transistor 111. This isolation unit 129 can be configured by STI (Shallow Trench Isolation).

[0053] The wiring region 140 is a region disposed on the front surface of the semiconductor substrate 120 where wiring for elements is formed. This wiring region 140 includes wiring 151, via plugs 152, contact plugs 153, and an insulating layer 141. The wiring 151 is a conductor that transmits signals to elements, etc., of the semiconductor substrate 120. This wiring 151 can be made of metal, such as copper (Cu) or tungsten (W). The insulating layer 141 insulates the wiring 151, etc. This insulating layer 141 can be made of, for example, SiO ２ As shown in FIG. 4, the wiring can be configured in multiple layers. In this case, the insulating film is also configured in multiple layers. The insulating layer disposed between layers is also called an interlayer insulating film. The via plug 152 connects the wiring 151 disposed on different layers. This via plug 152 can be configured, for example, from a pillar-shaped metal. The contact plug 153 connects the elements of the semiconductor substrate 120 and the wiring 151.

[0054] Furthermore, isolation sections 138 are arranged on the semiconductor substrate 120. These isolation sections 138 are arranged on the boundaries of the pixels 100 on the semiconductor substrate 120 to electrically and optically isolate the pixels 100. These isolation sections 138 can be made of an insulating material embedded in the semiconductor substrate 120. The isolation sections 138 can be formed, for example, by filling SiO 2 into grooves that penetrate the semiconductor substrate 120 and are formed on the boundaries of the pixels 100. ２ The insulating layer can be formed by disposing an insulating material such as the above.

[0055] A protective film 191 is disposed on the rear surface of the semiconductor substrate 120. This protective film 191 is a film that protects the rear surface of the semiconductor substrate 120. This protective film 191 is made of SiO ２ The insulating material may be used.

[0056] The color filter 192 is an optical filter that transmits incident light of a predetermined wavelength. For example, a color filter that transmits red light, green light, and blue light can be used as the color filter 192. In this case, one color filter 192 corresponding to any of red light, green light, and blue light is disposed in each pixel 100. The pixel 100 generates a pixel signal for the incident light of the wavelength corresponding to the color filter 192.

[0057] The on-chip lens 193 has a hemispherical cross section and focuses incident light onto the photoelectric conversion unit 101. The on-chip lens 193 can be made of an organic material such as acrylic resin or an inorganic material such as SiN.

[0058] 4, second charge holding portions 107 and 108 are arranged in the wiring region 140. Unlike the above-described first charge holding portion 106, the second charge holding portions 107 and 108 are charge holding portions configured by a capacitance element 160. The details of the configuration of the second charge holding portions 107 and 108 will be described with reference to FIG.

[0059] [Configuration of Second Charge Retention Section] FIG. 5 is a diagram showing a configuration example of the second charge retention section according to the first embodiment of the present disclosure. This figure is a schematic cross-sectional view showing a configuration example of the second charge retention section 107. The second charge retention section 108 can also have a similar configuration. The wiring region 140 in the figure is configured by stacking multiple insulating layers. The figure shows insulating layers 142 and 144 and a capacitor element insulating layer 143, which will be described later. Wiring is formed between these insulating layers. A blocking film 149 is disposed between the insulating layer 142 and the capacitor element insulating layer 143. This blocking film 149 can be made of SiN or silicon carbonitride (SiCN).

[0060] As described above, the second charge holding unit 107 is composed of a capacitor 160. The capacitor 160 in FIG. 5 is formed on an insulating layer. The insulating layer on which the capacitor 160 is formed is referred to as a capacitor insulating layer (capacitor insulating layer 143). The capacitor 160 includes a lower electrode 162, an insulating film 163, and an upper electrode 164.

[0061] The lower electrode 162 is an electrode disposed adjacent to the inner wall of the opening 161 formed in the capacitor element insulating layer 143. The lower electrode 162 can be made of, for example, a metal or a metal nitride. For example, the lower electrode 162 can be made of titanium nitride (TiN) or tantalum nitride (TaN).

[0062] The insulating film 163 is an insulating film configured to cover the lower electrode 162. This insulating film 163 can be made of oxide or nitride. In addition, the insulating film 163 may be made of a material with a high relative dielectric constant called High-k, such as aluminum oxide (Al ２ O ３ ) and hafnium oxide (HfO ２ ) can also be applied. The insulating film 163 can also be configured by laminating these materials.

[0063] The upper electrode 164 is an electrode configured to face the lower electrode 162 through the insulating film 163 in the opening 161. This upper electrode 164 can be configured from the same material as the lower electrode 162. The second charge holding portion 107 can be configured from a plurality of capacitance elements 160. The second charge holding portion 107 in FIG. 5 illustrates an example configured from two capacitance elements 160. The upper electrode 164 can be configured to have a shape with a plurality of protrusions disposed in the opening 161 of each capacitance element 160. The upper electrode 164 can also be considered as an electrode portion disposed in the opening 161. In this case, the second charge holding portion 107 in FIG. 5 can be considered to have an electrode structure configured by connecting a plurality of upper electrodes 164 disposed in a plurality of openings 161, respectively, by a common electrode.

[0064] The lower electrode 162 is connected to a lower layer wiring 154, which is a wiring arranged in a layer below the wiring region 140. The upper electrode 164 is connected to an upper layer wiring 156, which is a wiring arranged in a layer above the wiring region 140. The upper layer wiring 156 in FIG. 5 is connected to the upper electrode 164 through a via plug 152.

[0065] The second charge holding portion 107 can also be configured by one capacitance element 160 .

[0066] 5, the lower electrode 162 is disposed only inside the opening 161. In addition, the end of the lower electrode 162 is covered with the insulating film 163, and therefore the lower electrode 162 is separated from the end of the upper electrode 164. This can improve the electrical resistance between the lower electrode 162 and the upper electrode 164, and can reduce leakage current.

[0067] [Configuration of Pixel and Second Charge Retention Unit] FIGS. 6 and 7 are diagrams illustrating an example configuration of a pixel according to the first embodiment of the present disclosure. FIG. 6 is a plan view illustrating an example configuration of a pixel 100. FIG. 7 is a schematic cross-sectional view illustrating an example configuration of a pixel 100. Note that FIGS. 6 and 7 illustrate adjacent pixels 100a and 100b. Second charge retention units 107 and 108 are disposed in the pixels 100a and 100b, respectively. The dashed circle in FIG. 6 represents an opening 161 of the capacitance element 160. The second charge retention units 107 and 108 in FIG. 6 illustrate an example in which 16 capacitance elements 160 are arranged in four rows and four columns. The upper electrode 164 is commonly connected in the second charge retention units 107 and 108 of the pixels 100a and 100b. This upper electrode 164 is connected to an upper layer wiring 156 via a via plug 152. The upper layer wiring 156 is connected to the MIMVDD in FIG. 2. 2. Also, the lower layer wiring 154 connected to the second charge holding portion 107 is connected to the node 301 in FIG. 2. Also, the lower layer wiring 155 connected to the second charge holding portion 108 is connected to the node 302 in FIG.

[0068] The via plug 152 can be disposed at a position that does not overlap the second charge holding portion 108 and the like in a plan view.

[0069] 8A to 8O are diagrams illustrating an example of a method for manufacturing a photodetector according to the first embodiment of the present disclosure. 8A to 8O are diagrams illustrating an example of a manufacturing process for the second charge holding portions 107 and 108 of the photodetector element 1.

[0070] First, an insulating layer 142 is formed in the wiring region 140 of the semiconductor substrate 120, and then lower layer wiring 154 and the like are formed (FIG. 8A). Note that a barrier film can also be disposed below the lower layer wiring 154 and the like. This barrier film can be made of, for example, tantalum (Ta).

[0071] Next, a blocking film 149 is formed. Next, a capacitor element insulating layer 143 is disposed. This can be performed by, for example, CVD (Chemical Vapor Deposition) (FIG. 8B).

[0072] Next, a resist 400 is placed on the surface of the capacitor element insulating layer 143. In this resist 400, an opening 401 is placed in the region where the opening 161 is to be formed (FIG. 8C).

[0073] Next, the resist 400 is used as a mask to etch the capacitor element insulating layer 143 to form an opening 161 (FIG. 8D), after which the resist 400 is removed.

[0074] Next, a material film 402 for the lower electrode 162 is formed on the surface of the capacitor element insulating layer 143 including the opening 161 (FIG. 8E).

[0075] Next, a resist 403 is placed in the opening 161 (FIG. 8F), and the surface of the capacitor element insulating layer 143 is etched back to form the lower electrode 162. Thereafter, the resist 403 is removed (FIG. 8G).

[0076] Next, an insulating film 163 is formed on the surface of the capacitor element insulating layer 143 including the opening 161 (FIG. 8H).

[0077] Next, a material film 404 of the upper electrode 164 is formed on the surface of the capacitor element insulating layer 143 including the opening 161 (FIG. 8I).

[0078] Next, a resist 405 is placed on the surface of the material film 404. In this resist 405, an opening 406 is placed in the region other than the region where the upper electrode 164 is located (FIG. 8J).

[0079] Next, the insulating film 163 and the material film 404 are etched using the resist 405 as a mask to form the upper electrode 164 (FIG. 8K). Thereafter, the resist 405 is removed.

[0080] Next, an insulating layer 144 is formed (FIG. 8L), and a resist 407 is placed thereon. In this resist 407, an opening 408 is placed in the region where the via plug 152 is to be formed (FIG. 8M).

[0081] Next, the insulating layer 144 is etched using the resist 407 as a mask to form an opening 409 (FIG. 8N), after which the resist 407 is removed.

[0082] Next, a material film for upper-layer wiring 156 is disposed on the surface of insulating layer 144 including opening 409, and via plug 152 and upper-layer wiring 156 are formed (FIG. 8O). Through the above steps, second charge retention portions 107 and 108 can be formed.

[0083] [Another Pixel Configuration] Fig. 9 is a diagram showing another example of the pixel configuration according to the first embodiment of the present disclosure. The figure is a plan view showing another example of the configuration of the pixel 100. The pixel 100 (pixels 100a and 100b) in the figure shows an example in which one second charge retention unit (second charge retention unit 107) is provided. Note that the figure shows an example in which the upper electrodes 164 of the second charge retention units 107 in adjacent pixels 100 are commonly connected.

[0084] As described above, the photodetector element 1 according to the first embodiment of the present disclosure includes the second charge holding portion 107 configured by the capacitor element 160 in the pixel 100. The capacitor element 160 has a configuration in which the lower electrode 162 is disposed in an opening formed in an insulating layer (capacitor element insulating layer 143) in the wiring region 140 and is covered with an insulating film 163. This separates the capacitor element 162 from the upper electrode 164, thereby reducing leakage current. This reduces noise caused by leakage current.

[0085] (2. Second Embodiment) In the photodetector element 1 of the first embodiment described above, the upper electrode 164 and the via plug 152 are directly connected to each other. In contrast, the photodetector element 1 of the second embodiment of the present disclosure differs from the first embodiment described above in that the via plug 152 is connected to the upper electrode 164 via a second upper electrode.

[0086] 10 is a diagram showing an example of the configuration of a pixel according to the second embodiment of the present disclosure. Similar to FIG. 5, this figure is a schematic cross-sectional view showing an example of the configuration of the second charge retention portion 107 and the like. The second charge retention portions 107 and 108 in this figure differ from the second charge retention portion 107 in FIG. 5 in that they include a second upper electrode 167.

[0087] The second upper electrode 167 in FIG. 10 is an electrode disposed in a first recess 166 formed in a region including the opening 161 on the surface of the capacitor element insulating layer 143, and stacked on the upper electrode 164. This second upper electrode 167 is connected to the upper wiring 156. The second upper electrode 167 can be made of tungsten (W) or Cu. These can be formed by CVD or plating. By being configured to be embedded in the first recess 166, the film thickness of the second upper electrode 167 can be increased. Note that the upper electrode 164 in FIG. 10 is configured such that the aforementioned common electrode portion extends along the wall surface of the first recess 166.

[0088] 8N , when the via plug 152 is formed, an opening 409 is formed in the insulating layer 144 in a shape that reaches the upper electrode 164. At this time, if the upper electrode 164 is thin or if the insulating layer 144 varies greatly in thickness, excessive etching may occur in forming the opening 409, resulting in damage to the upper electrode 164. In response to this, by providing the second upper electrode 167 described above, damage to the upper electrode 164 can be prevented.

[0089] The upper layer wiring 156 and via plug 152 in FIG. 10 can be formed by a dual damascene method. The capacitor element 160 in FIG. 10 illustrates an example including stacked upper electrodes 164 and 165. The upper electrode 164 in FIG. 10 can be made of TiN deposited by atomic layer deposition (ALD). The upper electrode 165 can be made of TiN deposited by metal organic chemical vapor deposition (MOCVD). The lower electrode 162 in FIG. 10 can also have a two-layer structure. For example, a titanium (Ti) and TiN film deposited by MOCVD can be used.

[0090] It is also preferable to configure the upper electrodes 164 and 165 from a material that suppresses etching of the capacitor element insulating layer 143. This is because, as will be described later, this makes it easier to form the second upper electrode 167.

[0091] 11A to 11J are diagrams illustrating an example of a method for manufacturing a photodetector according to the second embodiment of the present disclosure. 11A to 11J are diagrams illustrating an example of a manufacturing process for the second charge retention portions 107 and 108 of the photodetector element 1. 11A to 11J illustrate an example in which via plugs 158 are formed adjacent to each other. The via plugs 158 are made of tungsten (W) and have a relatively large aspect ratio.

[0092] First, an opening 161 is formed in the capacitor element insulating layer 143, and a lower electrode 162 is disposed therein (FIG. 11A).

[0093] Next, a resist 410 is placed in the opening 161 (FIG. 11B), and the vicinity of the opening 161 is etched back to form a recess 411. At this time, the edge of the lower electrode 162 is also etched (FIG. 11C).

[0094] Next, a resist 412 is placed on the surface of the capacitor element insulating layer 143 including the recess 411 to flatten the surface. Next, a resist 413 is placed. In this resist 413, an opening 414 is placed in the region where the first recess 166 is to be formed (FIG. 11D).

[0095] Next, the capacitor element insulating layer 143 is etched using the resist 413 as a mask to form the first recess 166. Next, the resists 412 and 413 are removed (FIG. 11E).

[0096] Next, an insulating film 163, an upper electrode 164, and an upper electrode 165 are formed, and a capacitor 160 is formed in the opening 161. Next, a material film 415 for a second upper electrode 167 is disposed on the surface of the capacitor insulating layer 143 including the first recess 166. A tungsten (W) film can be used as the material film 415 (FIG. 11F).

[0097] Next, the material film 415 is ground to form the second upper electrode 167 ( FIG. 11G ). Chemical mechanical polishing (CMP) can be used to grind the material film 415. During this CMP, the films of the upper electrodes 164 and 165 disposed on the surface of the capacitor element insulating layer 143 function as a barrier metal. This stops the grinding by CMP near the surface of the capacitor element insulating layer 143. This reduces the variation in the remaining film thickness of the material film 415 after grinding.

[0098] Next, an insulating layer 144 is disposed. Next, the insulating layer 144 and the capacitor element insulating layer 143 are etched to form an opening 157. Next, a barrier metal film 417 and a material film 416 for the via plug 158 are disposed on the surface of the insulating layer 144 including the opening 157. A TiN film can be used for the barrier metal film 417. Furthermore, a tungsten (W) film can be used for the material film 415 (FIG. 11H).

[0099] Next, the material film 416 is ground by CMP to form the via plug 158. At this time, the grinding by CMP is stopped by the barrier metal film 417 (FIG. 11I).

[0100] Next, an insulating layer 145 is disposed. Next, recesses for disposing the via plug 152 and upper layer wiring 156 are formed in the insulating layers 145 and 144. When forming this recess, the formation of the recess is stopped at the portion of the second upper electrode 167. Next, the via plug 152 and upper layer wiring 156 are disposed in the recess. This can be done by the dual damascene method. Next, a blocking film 148 is formed (FIG. 11J). Through the above steps, the second charge retention portions 107 and 108 can be formed.

[0101] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the first embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0102] In this way, in the photodetector element 1 according to the second embodiment of the present disclosure, by disposing the second upper electrode 167, damage to the upper electrode 164 during the formation of the via plug 152 can be prevented.

[0103] 3. Third Embodiment The photodetector element 1 of the second embodiment described above includes the second upper electrode 167. In contrast, the photodetector element 1 of the third embodiment of the present disclosure differs from the second embodiment described above in that it further includes an etching stop film 147 stacked on the second upper electrode 167.

[0104] [Pixel Configuration] Fig. 12 is a diagram showing a configuration example of a pixel according to the third embodiment of the present disclosure. Similar to Fig. 10, Fig. 12 is a schematic cross-sectional view showing a configuration example of the second charge retention portion 107 and the like. The second charge retention portion 107 in Fig. 12 differs from the second charge retention portion 107 in Fig. 10 in that it includes an etching stop film 147.

[0105] The etching stop film 147 is made of a material that suppresses etching of the second upper electrode 167. This etching stop film 147 can be made of, for example, SiN, SiCN, and SiON.

[0106] 13A and 13B are diagrams illustrating an example of a method for manufacturing a photodetector according to the third embodiment of the present disclosure, showing an example of a manufacturing process for the second charge holding portions 107 and 108 of the photodetector element 1.

[0107] 11A to 11G are performed, and then an etching stop film 147 is disposed (FIG. 13A).

[0108] 11H to 11J are then performed, where recesses for arranging the via plug 152 and the upper wiring 156 are formed in the insulating layers 145 and 144. During the formation of the recesses, the formation of the recesses is stopped by the etching stop film 147 (FIG. 13B).

[0109] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the second embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0110] As described above, the photodetector element 1 according to the third embodiment of the present disclosure includes the etching stop film 147, thereby improving the function of preventing damage to the upper electrode 164 when the via plug 152 is formed.

[0111] (4. Fourth Embodiment) The photodetector element 1 of the first embodiment described above uses the second charge retention portions 107 and 108 including the capacitive element 160 having the lower electrode 162 and the upper electrode 164. In contrast, a fourth embodiment of the present disclosure proposes a photodetector element 1 that reduces leakage current caused by the lower electrode 162 and the upper electrode 164 in adjacent second charge retention portions 107, etc.

[0112] [Pixel Configuration] FIG. 14 is a diagram showing an example of the configuration of a pixel according to the fourth embodiment of the present disclosure. Similar to FIG. 6 , this figure is a plan view showing an example of the configuration of a pixel 100. The figure shows pixels 100a and 100b. The pixels 100a and 100b include second charge retention portions 107 and 108, respectively. The pixels 100a and 100b in the figure also show an example in which the upper electrode 164 is commonly connected in the second charge retention portions 107 and 108. A second recess 170 and a third recess 171 are disposed on the surface of the capacitor element insulating layer 143 near the second charge retention portions 107 and 108 in the figure. The two-dot chain rectangles in the figure represent the second recess 170 and the third recess 171.

[0113] The second recess 170 is a groove-shaped recess formed in the surface of the capacitor element insulating layer 143 after the formation of the lower electrode 162. The second recess 170 can be disposed at a position overlapping with the upper layer wiring 156 in a plan view.

[0114] The third recess 171 is a groove-shaped recess formed in the surface of the capacitor element insulating layer 143 after the formation of the upper electrode 164. The third recess 171 can be disposed at a position that does not overlap with the upper layer wiring 156 in a plan view.

[0115] [Cross-Sectional Configuration of Pixel] FIG. 15 is a diagram showing an example configuration of a pixel according to the fourth embodiment of the present disclosure. This figure is a cross-sectional view showing an example configuration of a pixel 100. This figure is a cross-sectional view taken along line AA' in FIG. 14. The lower part of the figure shows an example in which the second recess 170 is not disposed. In the pixel 100 shown in the upper part of the figure, a leakage current path 305 may be formed on the surface of the capacitor insulating layer 143 between the second charge retention portions 107 and 108 due to residues or defects in the material film of the lower electrode 162. The thick dashed line in the figure represents the leakage current path 305. As shown in the upper part of the figure, the leakage current path 305 can be cut by forming the second recess 170 after forming the lower electrode 162.

[0116] In contrast, in the pixel 100 on the lower side of the figure, the second recess 170 is not disposed, so that leakage current flows through the leakage current path 305, causing noise.

[0117] FIG. 16 is a diagram showing an example of the configuration of a pixel according to the fourth embodiment of the present disclosure. This figure is a cross-sectional view showing an example of the configuration of a pixel 100. This figure is a cross-sectional view taken along line B-B' in FIG. 14. The lower part of the figure shows an example in which the third recess 171 is not provided. In the upper part of the figure, in addition to the leakage current path 305 (not shown) of the lower electrode 162, a leakage current path 306 may be formed on the surface of the capacitor insulating layer 143 between the second charge retention portion 107 of pixel 100a and the second charge retention portion 107 of pixel 100b due to residues or defects in the material film of the upper electrode 164. The thick dashed line in the figure represents the leakage current path 306. As shown in the upper part of the figure, the leakage current path 306 can be cut by forming the third recess 171 after forming the upper electrode 164.

[0118] In contrast, in the pixel 100 on the lower side of the figure, the third recess 171 is not provided, so that a leakage current flows through the leakage current path 306, causing noise.

[0119] 17A to 17D are diagrams illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of the present disclosure. These diagrams illustrate an example of a manufacturing process for the second charge holding portions 107 and 108 of the photodetector element 1.

[0120] 8A to 8E are performed. Next, a resist 403 is placed in the opening 161 (FIG. 17A).

[0121] Next, the surface of the capacitor element insulating layer 143 is etched to form the lower electrode 162. Next, the resist 403 is removed (FIG. 17B).

[0122] Next, second recesses 170 are formed in the surface of the capacitor element insulating layer 143 between the second charge holding portions 107 and the like (FIG. 17C).

[0123] Next, an insulating film 163 and an upper electrode 164 are formed, and an insulating layer 144 is disposed (FIG. 17D). Description of subsequent steps will be omitted. Through the above steps, the pixel 100 having the second recess 170 can be manufactured.

[0124] 18A to 18D are diagrams illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of the present disclosure, and are diagrams illustrating an example of a manufacturing process for the second charge holding portions 107 and 108 of the photodetector element 1.

[0125] 8A to 8I are performed (FIG. 18A). Next, the material film 404 is processed to form the upper electrode 164 (FIG. 18B).

[0126] Next, third recesses 171 are formed in the surface of the capacitor element insulating layer 143 between the second charge holding portions 107 and the like (FIG. 18C).

[0127] Next, the insulating layer 144 is disposed (FIG. 18D). A description of the subsequent steps will be omitted. Through the above steps, the pixel 100 having the third recess 171 can be manufactured.

[0128] The pixel 100 may also be configured to include either the second recess 170 or the third recess 171 .

[0129] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the first embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0130] As described above, in the photodetector element 1 according to the fourth embodiment of the present disclosure, the second recess 170 and the third recess 171 are disposed on the surface of the capacitor element insulating layer 143 near the second charge retention portions 107 and 108. This makes it possible to reduce leakage current caused by the lower electrode 162 and the upper electrode 164.

[0131] 5. Fifth Embodiment The photodetector element 1 of the first embodiment described above uses the pixel 100 having the second charge retention portions 107 and 108. In contrast, the photodetector element 1 of the fifth embodiment of the present disclosure differs from the first embodiment described above in that it includes a protective film that protects the second charge retention portions 107 and 108.

[0132] [Pixel Configuration] FIG. 19 is a diagram illustrating an example configuration of a pixel according to a fifth embodiment of the present disclosure. Similar to FIG. 6 , this figure is a plan view illustrating an example configuration of a pixel 100. The pixel 100 in FIG. 19 differs from the pixel 100 in FIG. 6 in that a protective film 180 is provided. The protective film 180 prevents low-molecular-weight gases emitted from components constituting the pixel 100 from entering the second charge retention portions 107 and 108. Examples of such low-molecular-weight gases include fluorine (F), nitrogen (N), and hydrogen (H). The entry of these gases into the second charge retention portions 107 and 108 increases leakage current. Therefore, by providing the protective film 180 shaped to cover the second charge retention portions 107 and 108, the entry of low-molecular-weight gases into the second charge retention portions 107 and 108 is reduced. The black line in FIG. 19 represents the protective film 180. Specifically, the black lines in the figure represent the side surfaces of the protective film 180 that covers the second charge retention portions 107 and 108 .

[0133] 20 is a diagram showing a configuration example of a pixel according to the fifth embodiment of the present disclosure. Similar to FIG. 7, this figure is a schematic cross-sectional view showing the configuration example of the pixel 100. The black line in this figure represents the protective film 180. As shown in this figure, the protective film 180 is configured in a shape that covers the second charge retention units 107 and 108. The protective film 180 is made of an inorganic material, for example, SiN, SiCN, and Al. ２ O ３ It can be configured as follows.

[0134] 21A to 21H are diagrams illustrating an example of a method for manufacturing a photodetector according to the fifth embodiment of the present disclosure. 21A to 21H are diagrams illustrating an example of a manufacturing process for the protective film 180 of the photodetector 1.

[0135] 8A to 8I are performed, and then a blocking film 148 is disposed (FIG. 21A).

[0136] Next, a resist 420 is placed on the surface of the block film 148. In this resist 420, an opening 421 is placed in the region where the side portion of the protective film 180 will be placed (FIG. 21B).

[0137] Next, the resist 420 is used as a mask to etch the block film 148, the material film 404, the insulating film 163, and the capacitor element insulating layer 143, thereby forming an opening 422 (FIG. 21C).

[0138] Next, the protective film 180 is placed on the surface of the blocking film 148 including the opening 422 (FIG. 21D).

[0139] Next, an insulating layer 144 and a resist 407 having an opening 408 are placed on the surface of the protective film 180 (FIG. 21E).

[0140] Next, the insulating layer 144 is etched using the resist 407 as a mask to form an opening 423 in the insulating layer 144 (FIG. 21F).

[0141] Next, the surface of the insulating layer 144 including the opening 423 is etched back to thin the insulating layer 144 and process the opening 423 into a shape whose bottom reaches the upper electrode 164 (FIG. 21G).

[0142] Next, the via plug 152 and the upper layer wiring 156 are disposed (FIG. 21H). Through the above steps, the protective film 180 can be formed.

[0143] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the first embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0144] In this way, the photodetector element 1 according to the fifth embodiment of the present disclosure can reduce the influence of low molecular weight gases by arranging the protective film 180 around the second charge retention portions 107 and 108 .

[0145] 6. Sixth Embodiment The photodetector element 1 of the above-described fifth embodiment includes the protective film 180 that covers the second charge retention portions 107 and 108. In contrast, the photodetector element 1 of the sixth embodiment of the present disclosure differs from the above-described fifth embodiment in that it includes the protective film 180 that is shaped to cover the top surfaces, side surfaces, and bottom portions of the second charge retention portions 107 and 108.

[0146] [Pixel Configuration] Fig. 22 is a diagram showing an example configuration of a pixel according to the sixth embodiment of the present disclosure. Similar to Fig. 19, Fig. 22 is a plan view showing an example configuration of a pixel 100. The pixel 100 in Fig. 22 differs from the pixel 100 in Fig. 19 in that a side protective film 182 constituting a protective film 180 is provided. As will be described later, the protective film 180 in Fig. 22 includes a top protective film 181, a side protective film 182, and a capacitor insulating layer protective film 183. The side protective film 182 is provided for each of the second charge retention portions 107 and 108.

[0147] 23 is a diagram showing a configuration example of a pixel according to the sixth embodiment of the present disclosure. Similar to FIG. 20 , this diagram is a schematic cross-sectional view showing the configuration example of the pixel 100. The protective film 180 in this diagram includes a top protective film 181, a side protective film 182, and a capacitor insulating layer protective film 183.

[0148] The top protective film 181 is a protective film disposed on the top surfaces of the second charge retention portions 107 and 108. The side protective film 182 is a protective film disposed on the side surfaces of the second charge retention portions 107 and 108. The capacitor insulating layer protective film 183 is a protective film disposed on the surface of the capacitor insulating layer 143. This capacitor insulating layer protective film 183 prevents gas from entering from the bottoms of the second charge retention portions 107 and 108.

[0149] 24A to 24H are diagrams illustrating an example of a manufacturing method of a photodetector according to the sixth embodiment of the present disclosure. 24A to 24H are diagrams illustrating an example of a manufacturing process of the protective film 180 of the photodetector 1.

[0150] 8A and 8B are performed (FIG. 24A). Next, a resist 424 is placed. An opening 425 is formed in the resist 424 in the region where the side protective film 182 is to be placed (FIG. 24B).

[0151] Next, the resist 424 is used as a mask to etch the capacitor element insulating layer 143 to form an opening 426. Next, the resist 424 is removed (FIG. 24C).

[0152] Next, a protective film member is disposed on the surface of the capacitor element insulating layer 143 including the opening 426, and a side protective film 182 and a capacitor element insulating layer protective film 183 are disposed (FIG. 24D).

[0153] Next, the capacitor element insulating layer protection film 183 and the capacitor element insulating layer 143 are processed to form an opening 161. Next, the lower electrode 162, the insulating film 163, the material film 404, and the blocking film 148 are arranged (FIG. 24E). Note that some reference numerals are omitted in FIG. 24E.

[0154] Next, a resist 420 having an opening 421 is placed (FIG. 24F). Next, the resist 420 is used as a mask to etch the block film 148, the material film 404, and the insulating film 163, forming an opening 422. Next, the resist 420 is removed (FIG. 24G).

[0155] Next, a material film for the protective film is disposed on the surface of the blocking film 148 including the opening 422 to form the upper protective film 181 (FIG. 24H). Through the above steps, the protective film 180 can be formed.

[0156] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the fifth embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0157] As described above, the photodetector element 1 according to the sixth embodiment of the present disclosure includes the top protective film 181, the side protective film 182, and the capacitive element insulating layer protective film 183. The insides of the second charge retention portions 107 and 108 can be covered with the protective film, thereby further reducing the influence of gas.

[0158] 7. Seventh Embodiment A variation of the protective film 180 of the fifth and sixth embodiments will be described.

[0159] 25A to 25H are diagrams showing an example of the configuration of a pixel according to the seventh embodiment of the present disclosure. Similar to FIG. 19, FIG. 25A to 25H are plan views showing an example of the configuration of a pixel 100.

[0160] 25A shows an example of the side protective film 182 configured to have a polygonal shape in a plan view. The side protective film 182 in the same figure shows an example configured to have a hexagonal shape.

[0161] FIG. 25B shows an example of a side protective film 182 configured in an elliptical shape in a plan view.

[0162] FIG. 25C shows an example in which a plurality of side surface protective films 182 configured in a square shape share adjacent side portions.

[0163] FIG. 25D shows an example in which a plurality of rectangular side protective films 182 share adjacent side portions.

[0164] FIG. 25E shows an example in which a plurality of side surface protective films 182 are configured in an elliptical shape such that adjacent side surface protective films 182 are in contact with each other.

[0165] FIG. 25F shows an example in which a plurality of side protective films 182 each having a rectangular shape are configured to overlap each other.

[0166] FIG. 25G shows an example in which a plurality of circular side protective films 182 are arranged in an overlapping shape.

[0167] FIG. 25H shows an example of side protective film 182 that surrounds second charge holding portions 107 and 108 .

[0168] 8. Eighth Embodiment The photodetector element 1 of the sixth embodiment described above includes the top protective film 181, the side protective film 182, and the capacitance element insulating layer protective film 183. In contrast, the photodetector element 1 of the eighth embodiment of the present disclosure differs from the sixth embodiment described above in that it further includes a partition wall that separates the inside of the side protective film 182.

[0169] [Pixel Configuration] Fig. 26 is a diagram showing a configuration example of a pixel according to the eighth embodiment of the present disclosure. Similar to Fig. 22, Fig. 26 is a plan view showing a configuration example of a pixel 100. The pixel 100 in Fig. 26 differs from the pixel 100 in Fig. 22 in that a partition wall 184 is provided. As will be described later, the partition wall 184 in Fig. 26 is configured in a shape that separates the inside of the side protective film 182.

[0170] 27 is a diagram showing a configuration example of a pixel according to an eighth embodiment of the present disclosure. Similar to FIG. 23 , this figure is a schematic cross-sectional view showing the configuration example of the pixel 100. The protective film 180 in this figure includes a plurality of partition walls 184.

[0171] As shown in FIG. 27 , the partition wall 184 separates the inside of the side protective film 182 into multiple regions. The partition wall 184 can be disposed between the capacitor elements 160. Furthermore, the partition wall 184 can also be disposed in the capacitor element insulating layer 143 between the second charge retention portions 107 and the like. In this case, the capacitor element insulating layer 143 between the second charge retention portions 107 and the like can be separated into multiple regions. In this way, by separating the capacitor element insulating layer 143 into relatively narrow regions, the intrusion of gas can be further reduced. Furthermore, by disposing multiple partition wall portions 184, the intrusion of gas into the capacitor element 160 can be prevented even if the protective film 180 is misaligned. This will be described using FIG. 28 .

[0172] FIG. 28 is a diagram showing an example of the configuration of a pixel according to the eighth embodiment of the present disclosure. This figure illustrates an example in which the protective film 180 is misaligned. The upper side of the figure is a plan view of the pixel 100, and the lower side is a schematic cross-sectional view of the pixel 100. Note that some parts of the pixel 100 in the figure are omitted. The protective film 180 in the figure is formed with a misalignment to the right in the figure. Even in this case, it is possible to cover at least one side of the side surface of the capacitor 160 with the partition wall 184. Furthermore, even if the protective film 180 is further misaligned, the capacitor insulating layer 143 is subdivided by the partition wall 184, thereby preventing gas from entering.

[0173] The partition wall 184 can be formed by the same process as the side surface protective film 182, and therefore a description of the manufacturing process will be omitted.

[0174] [Another Pixel Configuration] Fig. 29 is a diagram showing another example configuration of a pixel according to the eighth embodiment of the present disclosure. Similar to Fig. 26, this figure is a plan view showing an example configuration of a pixel 100. The pixel 100 in this figure differs from the pixel 100 in Fig. 26 in that a plurality of partition portions 184 are arranged in a lattice pattern.

[0175] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the sixth embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0176] In this way, the photodetector element 1 according to the eighth embodiment of the present disclosure further includes the partition wall portion 184, thereby making it possible to further reduce the influence of gas.

[0177] (9. Ninth Embodiment) The photodetector element 1 of the first embodiment described above includes the second charge holding portions 107 and 108 configured by the capacitance element 160. In contrast, the photodetector element 1 of the ninth embodiment of the present disclosure differs from the first embodiment described above in that it further includes second openings arranged near the capacitance elements 160 of the second charge holding portions 107 and 108.

[0178] [Pixel Configuration] Fig. 30 is a diagram showing a configuration example of a pixel according to the ninth embodiment of the present disclosure. Similar to Fig. 6, Fig. 30 is a plan view showing a configuration example of a pixel 100. The pixel 100 in Fig. 30 differs from the pixel 100 in Fig. 6 in that a second opening 169 is provided.

[0179] The second openings 169 are openings formed in the capacitor element insulating layer 143. As described above, the second openings 169 are arranged near the capacitor elements 160. The thick dashed circles in FIG. 30 represent the second openings 169. As shown in FIG. 30, the second openings 169 can be configured to have the same size as the openings 161 of the capacitor elements 160. Furthermore, the second openings 169 can be arranged at the same pitch as the capacitor elements 160.

[0180] If such second openings 169 are not provided, variations may occur in the shapes of the openings 161 of the multiple capacitive elements 160. Specifically, the openings 161 formed in the central portion of the multiple openings 161 may have different sizes from the openings 161 formed in the peripheral portion. This is because conditions change in the etching or other process steps for forming the openings 161. That is, the openings 161 formed in the peripheral portion lose the periodicity of the arrangement of the openings 161 compared to the openings 161 formed in the central portion, and this changes the processing conditions, resulting in variations in the opening size, depth, and the like.

[0181] Therefore, the second openings 169 are arranged outside the plurality of openings 161. This makes it possible to maintain the periodic arrangement of the openings 161 in the outer periphery. It is possible to reduce the variation in size of the openings 161.

[0182] In the pixel 100 of FIG. 30, a wiring 159 is disposed between the lower layer wirings 154 and the like. This wiring 159 is an isolated wiring that is not connected to other wirings. By disposing this wiring 159, incident light that has passed through the semiconductor substrate 120 can be reflected to the photoelectric conversion unit 101. This makes it possible to improve sensitivity. It is also possible to prevent the generation of stray light. The wiring 159 is an example of a "reflective film" in the present disclosure.

[0183] 31 and 32 are diagrams showing an example configuration of a pixel according to the ninth embodiment of the present disclosure. FIGS. 31 and 32 are schematic cross-sectional views showing an example configuration of a pixel 100. In FIGS. 31 and 32, the upper wiring 156 and the like are omitted. FIG. 31 is a schematic cross-sectional view taken along line CC' in FIG. 30. FIG. 32 is a schematic cross-sectional view taken along line DD' in FIG. 30. An insulating member 179 is disposed in the second opening 169. The same material as the insulating layer 144 can be used for this insulating member 179.

[0184] 33A to 33F are diagrams illustrating an example of a method for manufacturing a photodetector according to the ninth embodiment of the present disclosure. These diagrams illustrate an example of a manufacturing process for the second opening 169 of the photodetector element 1.

[0185] 8A and 8B are performed. Next, a resist 430 is placed. In this resist 430, openings 431 are formed in the regions where the opening 161 and the second opening 169 are to be placed (FIG. 33A).

[0186] Next, the resist 430 is used as a mask to etch the capacitor element insulating layer 143 to form an opening 161 and a second opening 169 (FIG. 33B).

[0187] Next, a resist 432 is placed. In this resist 432, an opening 433 is placed in the area other than the opening 161 (FIG. 33C).

[0188] Next, a material film 434 of the insulating member 179 is disposed on the surface of the capacitor element insulating layer 143 including the second opening 169 (FIG. 33D).

[0189] Next, etching is performed to remove the material film 434 and the resist 432, thereby forming the insulating member 179 (FIG. 33E).

[0190] Next, a lower electrode 162, an insulating film 163, and an upper electrode 164 are disposed in the opening 161 to form the capacitor element 160 (FIG. 33F). Through the above steps, a second opening 169 and an insulating member 179 can be formed.

[0191] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the first embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0192] In this way, the photodetector element 1 of the ninth embodiment of the present disclosure can reduce the variation in size of the opening 161 of the capacitive element 160 by arranging the second opening 169 near the capacitive element 160.

[0193] (10. Tenth Embodiment) In the photodetector element 1 of the above-described ninth embodiment, the insulating member 179 is disposed in the second opening 169. In contrast, the photodetector element 1 of the tenth embodiment of the present disclosure differs from the above-described ninth embodiment in that the lower electrode 162 and the like are disposed in the second opening 169.

[0194] [Pixel Configuration] The pixel 100 according to the ninth embodiment of the present disclosure can have a configuration similar to that of the pixel 100 in Fig. 30. Note that, in the second opening 169, a lower electrode 162, an insulating film 163, and an upper electrode 164 are arranged, similar to the opening 161.

[0195] 34 and 35 are diagrams showing an example configuration of a pixel according to the tenth embodiment of the present disclosure. FIGS. 34 and 35 are schematic cross-sectional views showing an example configuration of a pixel 100. FIG. 34 is a schematic cross-sectional view taken along line CC' in FIG. 30. FIG. 35 is a schematic cross-sectional view taken along line DD' in FIG. 30. A lower electrode 162, an insulating film 163, and an upper electrode 164 are disposed in the second opening 169 in FIGS. 34 and 35. An insulating material film 178 is disposed on the surface of the second opening 169. This insulating material film 178 insulates the lower electrode 162 and the like in the second opening 169.

[0196] 36A to 36D are diagrams illustrating an example of a method for manufacturing a photodetector according to the tenth embodiment of the present disclosure. Figures 36A to 36D are diagrams illustrating an example of a manufacturing process for the portion of the second opening 169 of the photodetector element 1.

[0197] 33A and 33B are performed to form the opening 161 and the second opening 169. Next, the steps of Figures 8E-8I are performed to arrange the material film 404 of the lower electrode 162, the insulating film 163, and the upper electrode 164 in the opening 161 and the second opening 169 (Figure 36A).

[0198] Next, a resist 432 having an opening 433 is placed (FIG. 36B). Next, the resist 432 is used as a mask to etch the material film 404 and the insulating film 163, thereby forming the capacitor element 160 (FIG. 36C).

[0199] Next, the resist 432 is removed, and the insulating material film 178 is disposed on the upper layer of the second opening 169 (FIG. 36D). Through the above steps, the second opening 169 can be formed.

[0200] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the ninth embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0201] In this way, in the photodetector element 1 according to the tenth embodiment of the present disclosure, the lower electrode 162 and the like are disposed in the second opening 169 .

[0202] 11. Eleventh Embodiment A variation of the pixel 100 of the above-described ninth and tenth embodiments will be described.

[0203] [Pixel Configuration] Fig. 37 is a diagram showing a configuration example of a pixel according to the eleventh embodiment of the present disclosure. Similar to Fig. 30, this figure is a plan view showing a configuration example of a pixel 100. The pixel 100 in this figure shows an example in which the openings 161 and the second openings 169 arranged in a matrix are shifted in different directions for each row.

[0204] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the tenth embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0205] (12. Twelfth Embodiment) In the photodetector element 1 of the first embodiment described above, the capacitive element 160 is formed in the opening 161 that is circular in plan view. In contrast, the photodetector element 1 of the twelfth embodiment of the present disclosure differs from the first embodiment described above in that the capacitive element 160 is formed in an opening that is rectangular in plan view.

[0206] [Pixel Configuration] Fig. 38 is a diagram showing a configuration example of a pixel according to a twelfth embodiment of the present disclosure. Similar to Fig. 6, Fig. 38 is a plan view showing a configuration example of a pixel 100. The pixel 100 in Fig. 38 differs from the pixel 100 in Fig. 6 in that it includes a capacitor element 160 and a third opening 172 formed in an opening 168 that is rectangular in plan view.

[0207] As described above, the opening 168 is configured to have a rectangular shape in a plan view. The pixel 100 in Fig. 38 shows an example in which six capacitance elements 160 are arranged.

[0208] The pixel 100 in FIG. 38 further includes a third opening 172. The third opening 172 is configured in a groove shape. The third opening 172 is formed in the vicinity of a region in which the second charge retention portion 107 and the like are to be formed on the surface of the capacitor element insulating layer 143, and is formed before the formation of the lower electrode 162. The third opening 172 separates the second charge retention portion 107 and the like. The pixel 100 in FIG. 38 shows an example in which two third openings 172 are arranged.

[0209] [Cross-sectional configuration of pixel] Fig. 39 is a cross-sectional view showing an example configuration of a pixel according to the twelfth embodiment of the present disclosure. The figure is a schematic cross-sectional view showing an example configuration of a pixel 100. In the figure, the upper wiring 156 and the like are omitted. The figure is also a schematic cross-sectional view taken along line E-E' in Fig. 38. The third opening 172 is configured so that its bottom is in contact with the blocking film 149. In addition, a lower electrode 162, an insulating film 163, and an upper electrode 164 are arranged in the third opening 172.

[0210] [Pixel Manufacturing Method] Figures 40A-40C are diagrams illustrating an example of a pixel manufacturing method according to the twelfth embodiment of the present disclosure. Figures 40A-40C are diagrams illustrating an example of a manufacturing process for a pixel 100. First, a lower wiring 154 is disposed on the insulating layer 142, a blocking film 149 is disposed, and a capacitor element insulating layer 143 is disposed (Figure 40A). Next, an opening 168 and a third opening 172 are formed (Figure 40B). This can be performed using the same process as Figures 8C-8D. Next, a material film 402 for the lower electrode 162 is disposed on the surface of the capacitor element insulating layer 143, including the inner surfaces of the opening 168 and the third opening 172 (Figure 40C). The subsequent processes are similar to those shown in Figures 8F-8O, and therefore will not be described here. Note that the upper electrode 164 disposed in the third opening 172 and the upper electrode 164 disposed in the opening 168 are separated from each other.

[0211] Because opening 168 is rectangular in plan view, dimensional variation can be reduced compared to opening 161, which is circular in plan view. Furthermore, groove-shaped opening 168 is less likely to cause defects during processing by dry etching, and can improve the embedding properties during film formation of lower electrode 162 and the like. Furthermore, opening 168 can be formed simultaneously with third opening 172, which can simplify the manufacturing process.

[0212] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the first embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0213] As described above, the photodetector 1 according to the twelfth embodiment of the present disclosure includes the capacitance element 160 formed in the opening 168 that is rectangular in plan view. This reduces dimensional variations in the opening 168, and reduces errors in the capacitance of the capacitance element 160.

[0214] 13. Thirteenth Embodiment A variation of the pixel 100 of the twelfth embodiment described above will be described.

[0215] [Pixel Configuration] Figures 41A to 41E are diagrams illustrating an example configuration of a pixel according to the thirteenth embodiment of the present disclosure. Figures 41A to 41E are plan views illustrating example configurations of an opening 168 and a third opening 172 in a pixel 100. Figure 41A illustrates an example of an opening 168 configured in a comb shape. Figure 41B illustrates an example of an opening 168 configured in a shape where multiple rectangles intersect. Figure 41C illustrates an example of an opening 168 configured in a polygonal line shape. Figure 41D illustrates an example of an opening 168 configured in a spiral shape. Figure 41E illustrates an example of multiple openings 168 configured in a nested shape. Note that a path 173 for external extraction of the capacitive element 160 is formed in the outer opening 168 in Figure 41E.

[0216] 42A-42C are diagrams showing other exemplary pixel configurations according to the thirteenth embodiment of the present disclosure. FIGS. 42A-42C are cross-sectional views showing exemplary configurations of the opening 168 and the third opening 172 in the pixel 100. The opening 168 and the third opening 172 in FIGS. 42A-42C illustrate an example in which the opening 168 and the third opening 172 are formed in a region in which the capacitor insulating layer 143, the blocking film 146, the insulating layer 144, and the blocking film 148 are stacked in this order. In this case, the insulating layer 144 corresponds to the capacitor insulating layer. FIG. 42A illustrates an example of the opening 168 and the third opening 172 having a forward tapered cross section. FIG. 42B illustrates an example of the opening 168 and the third opening 172 having a reverse tapered cross section. FIG. 42A illustrates an example of the opening 168 and the third opening 172 having a cross section with a bulging center.

[0217] 43 is a diagram showing another example of the configuration of a pixel according to the thirteenth embodiment of the present disclosure. The figure is a cross-sectional view showing the example of the configuration of a pixel 100. The figure shows an example in which the upper electrode 164 is configured in a shape that covers part of the opening 168. In the pixel 100 shown in the figure, the rectangular opening 168 is arranged, which allows for improved layout flexibility of the upper electrode 164.

[0218] Other than this, the configuration of the photodetector element 1 is the same as the configuration of the photodetector element 1 in the tenth embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0219] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0220] The present technology may also be configured as follows: (1) A photodetector element having a pixel including: a photoelectric conversion unit disposed on a semiconductor substrate and configured to perform photoelectric conversion of incident light to generate charges, a first charge retention unit that retains the charges, a charge transfer unit that transfers the charges to the first charge retention unit, a signal generation unit that generates a signal corresponding to the charges retained in the first charge retention unit, and a second charge retention unit configured by a capacitive element formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate and coupled to the first charge retention unit, wherein the capacitive element is configured by: a lower electrode disposed adjacent to an inner wall of an opening formed in a capacitive element insulating layer that is the insulating layer in which the capacitive element is formed; an insulating film configured to cover the lower electrode; and an upper electrode configured to face the lower electrode in the opening with the insulating film interposed therebetween, wherein the lower electrode is connected to a lower layer wiring that is wiring disposed in a layer below the wiring region, and the upper electrode is connected to an upper layer wiring that is wiring disposed in a layer above the wiring region. (2) The photodetector according to (1), wherein the pixel has a plurality of the second charge retention units to which the upper electrode is commonly connected, and the lower electrodes of the plurality of second charge retention units are respectively connected to different lower-layer wirings. (3) The photodetector according to (2), further comprising a via plug arranged at a position not overlapping with the plurality of second charge retention units in a plan view, and connecting the upper electrode and the upper-layer wiring. (4) The photodetector according to any of (1) to (3), wherein the second charge retention unit includes a plurality of the capacitive elements to which the upper electrode is commonly connected. (5) The photodetector according to any of (1) to (4), wherein the lower electrode is made of a metal nitride. (6) The photodetector according to any of (1) to (5), wherein the upper electrode is made of a metal nitride. (7) The photodetector according to any one of (1) to (6), wherein the capacitive element further includes a second upper electrode disposed in a first recess formed in a region including the opening in the surface of the capacitive element insulating layer and connected to the upper electrode. (8) The photodetector according to (7), wherein the upper electrode is configured in a shape extending along a wall surface of the first recess.(9) The photodetector according to (8), wherein the upper electrode is made of a material that suppresses etching of the capacitor element insulating layer. (10) The photodetector according to (7), further including an etching stop film that is stacked on the second upper electrode and is made of a material that suppresses etching of the second upper electrode. (11) The photodetector according to any of (1) to (10), further including a second groove-shaped recess that is formed after forming the lower electrode in the vicinity of a region in the surface of the capacitor element insulating layer where the second charge retention portion is to be formed. (12) The photodetector according to any of (1) to (11), further including a third groove-shaped recess that is formed after forming the upper electrode in the vicinity of a region in the surface of the capacitor element insulating layer where the second charge retention portion is to be formed. (13) The photodetector according to any of (1) to (12), further including a protective film that covers an upper surface and a side surface of the second charge retention portion. (14) The photodetector according to (13), wherein the pixel has a plurality of the second charge retention portions to which the upper electrode is commonly connected, and the protective film is configured in a shape including the plurality of second charge retention portions. (15) The photodetector according to (13), wherein the pixel has a plurality of the second charge retention portions, and the protective film is configured in a shape including the second charge retention portions of each of the plurality of pixels. (16) The photodetector according to (13), wherein the protective film includes a top protective film disposed on a top surface of the second charge retention portion and a side protective film disposed on a side surface of the second charge retention portion. (17) The photodetector according to (16), wherein the protective film further includes a capacitor insulating layer protective film disposed on a surface of the capacitor insulating layer. (18) The photodetector according to (17), wherein the protective film further includes at least one partition portion separating the capacitor insulating layer inside the side protective film. (19) The photodetector according to (18), wherein the protective film is configured to have a shape including a plurality of the second charge retention portions, and the partition wall is further disposed on the capacitive element insulating layer between the second charge retention portions. (20) The photodetector according to (13), wherein the protective film is made of an inorganic material.(21) The photodetector according to (4), further comprising a plurality of second openings arranged in the capacitive element insulating layer near the plurality of capacitive elements and configured to have approximately the same size as the openings. (22) The photodetector according to (21), wherein the plurality of second openings are arranged at approximately the same pitch as the plurality of capacitive elements. (23) The photodetector according to (21), wherein the plurality of second openings are arranged in which the capacitive elements having the upper electrode not connected to the upper layer wiring are arranged. (24) The photodetector according to (21), wherein an insulating member is arranged in the plurality of second openings. (25) The photodetector according to (21), further comprising a reflective film arranged in a layer below the second openings and reflecting the incident light. (26) The photodetector according to (1), wherein the openings are configured to have a circular shape in a plan view. (27) The photodetector according to (1), further comprising a third groove-shaped opening formed before the formation of the lower electrode in the vicinity of a region where the second charge retention portion is to be formed on the surface of the capacitance element insulating layer. (28) The photodetector according to (27), wherein the opening is configured to have a rectangular shape in a plan view.

[0221] 1 Photodetector element 100, 100a, 100b Pixel 101 Photoelectric conversion section 102 Charge transfer section 106 First charge storage section 107, 108 Second charge storage section 110 Signal generation section 120 Semiconductor substrate 140 Wiring area 141, 142, 144 Insulating layer 143 Capacitor element insulating layer 147 Etching stop film 152 Via plug 154, 155 Lower layer wiring 156 Upper layer wiring 159 Wiring 160 Capacitor element 161, 168 Opening 162 Lower electrode 163 Insulating film 164 Upper electrode 166 First recess 167 Second upper electrode 169 Second opening 170 Second recess 171 Third recess 172 Third opening 180 Protective film 181 Upper surface protective film 182 Side surface protective film 183 Capacitor element insulating layer protective film 184 Partition wall portion

Claims

1. A photodetector having a pixel including a photoelectric conversion unit disposed on a semiconductor substrate for performing photoelectric conversion of incident light to generate electric charges, a first charge retention unit for retaining the electric charges, a charge transfer unit for transferring the electric charges to the first charge retention unit, a signal generation unit for generating a signal according to the electric charges retained in the first charge retention unit, and a second charge retention unit constituted by a capacitive element formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate and coupled to the first charge retention unit, wherein the capacitive element is constituted by a lower electrode disposed adjacent to an inner wall of an opening formed in a capacitive element insulating layer, which is the insulating layer in which the capacitive element is formed, an insulating film configured to cover the lower electrode, and an upper electrode configured to face the lower electrode via the insulating film in the opening, wherein the lower electrode is connected to a lower layer wiring that is wiring disposed in a layer below the wiring region, and the upper electrode is connected to an upper layer wiring that is wiring disposed in a layer above the wiring region.

2. The photodetector element according to claim 1, wherein the pixel has a plurality of second charge holding sections to which the upper electrode is commonly connected, and the lower electrodes of the plurality of second charge holding sections are each connected to a different lower wiring.

3. The photodetector element according to claim 2, further comprising a via plug arranged at a position not overlapping with the second charge retaining portions in a plan view, the via plug connecting the upper electrode and the upper layer wiring.

4. The photodetector element according to claim 1, wherein the second charge holding portion comprises a plurality of the capacitive elements whose upper electrodes are commonly connected.

5. The photodetector according to claim 1, wherein the lower electrode is made of a metal nitride.

6. The photodetector according to claim 1, wherein the upper electrode is made of a metal nitride.

7. The photodetector element according to claim 1, further comprising a second upper electrode disposed in a first recess formed in a region including the opening on the surface of the capacitor insulating layer and connected to the upper electrode.

8. The light-detecting element according to claim 7, wherein the upper electrode is configured in a shape extending along the wall surface of the first recess.

9. The photodetector element according to claim 8, wherein the upper electrode is made of a material that suppresses etching of the capacitance element insulating layer.

10. The photodetector according to claim 7, further comprising an etching stopper film formed of a material laminated on said second upper electrode and suppressing etching of said second upper electrode.

11. The photodetector according to claim 1, further comprising a second groove-shaped recess formed after the lower electrode is formed in the vicinity of a region in the surface of the capacitance element insulating layer where the second charge retaining portion is to be formed.

12. The photodetector according to claim 1, further comprising a third groove-shaped recess formed after the upper electrode is formed in the vicinity of a region in the surface of the capacitance element insulating layer where the second charge retaining portion is to be formed.

13. The light-detecting element according to claim 1, further comprising a protective film configured to cover an upper surface and a side surface of said second charge-holding portion.

14. The photodetector element according to claim 13, wherein the pixel has a plurality of the second charge retention portions to which the upper electrode is commonly connected, and the protective film is configured in a shape including the plurality of the second charge retention portions.

15. The light detection element according to claim 13, comprising a plurality of the pixels, and the protective film is configured in a shape including the second charge retaining portion of each of the plurality of the pixels.

16. The light-detecting element according to claim 13, wherein the protective film comprises an upper protective film disposed on an upper surface of the second charge-holding portion and a side protective film disposed on a side surface of the second charge-holding portion.

17. The light-detecting element according to claim 16, wherein the protective film further comprises a capacitance element insulating layer protective film disposed on a surface of the capacitance element insulating layer.

18. The light-detecting element according to claim 17, wherein the protective film further comprises at least one partition wall portion separating the capacitance element insulating layer on the inner side of the side protective film.

19. The photodetector element according to claim 18, wherein the protective film is configured to have a shape including a plurality of the second charge retention portions, and the partition portion is further disposed in the capacitance element insulating layer between the second charge retention portions.

20. The light-detecting element according to claim 13, wherein the protective film is made of an inorganic material.

21. The photodetector element according to claim 4, further comprising a plurality of second openings arranged in said capacitance element insulating layer in the vicinity of said plurality of capacitance elements and configured to have substantially the same size as said opening.

22. The light-detecting element according to claim 21, wherein the second openings are arranged at substantially the same pitch as the capacitance elements.

23. The light-detecting element according to claim 21, wherein the plurality of second openings are provided with the capacitive element having the upper electrode that is not connected to the upper layer wiring.

24. The light-detecting element according to claim 21, wherein an insulating member is disposed in the plurality of second openings.

25. The light-detecting element according to claim 21, further comprising a reflective film disposed below said second opening and reflecting said incident light.

26. The light detection element according to claim 1, wherein the opening is configured to be circular in a plan view.

27. The photodetector element according to claim 1, further comprising a groove-shaped third opening formed in the surface of the capacitance element insulating layer in the vicinity of a region in which the second charge retaining portion is to be formed, prior to the formation of the lower electrode.

28. The light-detecting element according to claim 27, wherein the opening is rectangular in plan view.

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