Semiconductor device

Abstract

This semiconductor device includes a semiconductor element including a surface electrode formed on the element surface thereof. The element surface includes an active region in which power transistors are formed, and a control circuit region in which a control circuit for controlling the power transistors is formed. The active region is formed so as to surround the control circuit region from both sides in a second direction and one side in a first direction. The surface electrode is disposed on the active region at a position different from the control circuit region, and is formed so as to surround the control circuit region from both sides in the second direction and one side in the first direction when viewed from the thickness direction thereof.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device in which a switching circuit formed in an active region, an overcurrent protection circuit, an overheat protection circuit, and an undervoltage malfunction prevention circuit are fabricated in the surface layer of a common substrate.

[0003] JP 2017-147433 A

[0004] [Summary] There is room for improvement in the active clamping resistance of semiconductor devices.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor element including a surface of an element, a back surface of an element facing opposite to the surface of the element, and a surface electrode formed on the surface of the element, a die pad supporting the semiconductor element, a plurality of leads arranged around the die pad, and a plurality of wires connecting the surface electrode and the plurality of leads, wherein the surface of the element includes an active region in which a power transistor is formed and a control circuit region in which a control circuit for controlling the power transistor is formed, and two directions perpendicular to a thickness direction of the semiconductor element are defined as a first direction and a second direction, respectively, and the active region is formed to surround the control circuit region from both sides in the second direction and one side in the first direction, and the surface electrode is disposed on the active region at a position different from the control circuit region, and is formed to surround the control circuit region from both sides in the second direction and one side in the first direction when viewed from the thickness direction.

[0006] FIG. 1 is a schematic perspective view of a semiconductor device of a first embodiment. FIG. 2 is a schematic plan view showing the internal structure of the semiconductor device of FIG. 1. FIG. 3 is a schematic back view of the semiconductor device of FIG. 1. FIG. 4 is a schematic cross-sectional structure of the semiconductor device taken along line F4-F4 in FIG. 2. FIG. 5 is a schematic circuit diagram of the semiconductor device of FIG. 1. FIG. 6 is a schematic plan view of the semiconductor element of the semiconductor device of FIG. 2 with the surface electrodes and passivation film removed. FIG. 7 is a schematic plan view of the semiconductor element of FIG. 2. FIG. 8 is a schematic plan view of the semiconductor element of FIG. 2 with the electrode connection portions of wires connected. FIG. 9 is a schematic plan view of the semiconductor element of FIG. 2 with the wires connected. FIG. 10 is a schematic cross-sectional view of the semiconductor element taken along line F10-F10 in FIG. 9. FIG. 11 is a schematic plan view showing the internal structure of a semiconductor device of a second embodiment. FIG. 12 is a schematic plan view of the semiconductor element of the semiconductor device of FIG. 11 with the surface electrodes and passivation film removed. Fig. 13 is a schematic plan view of the semiconductor element of Fig. 12 with surface electrodes and a passivation film added. Fig. 14 is a schematic plan view of the semiconductor element of Fig. 13 with wire electrode connection portions connected. Fig. 15 is a schematic plan view of the semiconductor element of Fig. 13 with wire electrode connection portions connected. Fig. 16 is a schematic plan view of a semiconductor element in a modified semiconductor device with wire electrode connection portions connected.

[0007] DETAILED DESCRIPTION Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. For simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Furthermore, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and are not used to rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this specification, "the length (dimension) of A is equal to the length (dimension) of B" or "the length (dimension) of A and the length (dimension) of B are equal to each other" also includes a relationship in which the difference between the length of A and the length of B is, for example, within 10% of the length of A.

[0011] First Embodiment [Overall Configuration of Semiconductor Device] The overall configuration of a semiconductor device 10 according to a first embodiment will be described with reference to FIGS. 1 to 4. FIG. 1 shows a schematic perspective view of the semiconductor device 10 according to the first embodiment. FIG. 2 shows a schematic plan view of the interior of the semiconductor device 10 shown in FIG. 1. FIG. 3 shows a schematic rear view of the semiconductor device 10 shown in FIG. 1. FIG. 4 shows a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in FIG. 2. In FIG. 2, in order to show the internal structure of the semiconductor device 10, a sealing resin 60 (described later) is indicated by a two-dot chain line, and components within the sealing resin 60 are indicated by solid lines. The term "plan view" used in this disclosure refers to viewing the semiconductor device 10 in the Z direction of the X, Y, and Z axes, which are orthogonal to each other, in FIG. 1. In this disclosure, the X direction is an example of a "second direction," and the Y direction is an example of a "first direction."

[0012] As shown in FIG. 1 , the semiconductor device 10 includes a semiconductor element 20, a lead frame 30, and a sealing resin 60. The package format of the semiconductor device 10 is a small outline (SO) type, which is a small outline package (SOP) in the first embodiment. The package format of the semiconductor device 10 can be changed as desired. The package format is not limited to the SOP, and may be a quad flat non-leaded package (QFN), a dual flat package (DFP), a dual inline package (DIP), a quad flat package (QFP), a single inline package (SIP), a small outline J-leaded package (SOJ), or various similar package structures.

[0013] The semiconductor element 20 is a central element for the function of the semiconductor device 10. The semiconductor element 20 includes, for example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). In the first embodiment, the semiconductor element 20 is a SiC (Silicon Carbide) MOSFET as a power MOSFET. The semiconductor element 20 may also be a Si (Silicon) MOSFET. The semiconductor element 20 is formed in a rectangular plate shape with the thickness direction aligned in the Z direction. Therefore, the Z direction can be said to be the thickness direction of the semiconductor element 20. In one example, the semiconductor element 20 is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view.

[0014] The semiconductor element 20 includes an element front surface 20S and an element back surface 20R facing opposite to each other in the Z direction, and first to fourth element side surfaces 20A to 20D as four element side surfaces connecting the element front surface 20S and the element back surface 20R. The first element side surface 20A and the second element side surface 20B constitute both end surfaces of the semiconductor element 20 in the X direction, and the third element side surface 20C and the fourth element side surface 20D constitute both end surfaces of the semiconductor element 20 in the Y direction.

[0015] The semiconductor element 20 includes a plurality of (20 in the first embodiment) power pads 21 and a plurality of (four in the first embodiment) control pads 22 formed on the element surface 20S. The plurality of power pads 21 and the plurality of control pads 22 are arranged on the outer periphery of the element surface 20S. Details of the plurality of power pads 21 and the plurality of control pads 22 will be described later.

[0016] 4, the semiconductor element 20 includes a source electrode 23 formed on the element front surface 20S and a drain electrode 24 formed on the element rear surface 20R. The configuration of the source electrode 23 will be described later. The drain electrode 24 is formed over the entire surface of the element rear surface 20R. Here, the source electrode 23 is an example of a "front surface electrode."

[0017] 2, the lead frame 30 includes a die pad 31 that supports the semiconductor element 20 and a plurality of leads 32A to 32D, 33A to 33D arranged around the die pad 31. In the following description, the leads 32A to 32D are referred to as the "first to fourth power leads 32A to 32D," and the leads 33A to 33D are referred to as the "first to fourth control leads 33A to 33D." The first to fourth power leads 32A to 32D and the first to fourth control leads 33A to 33D constitute external terminals of the semiconductor device 10. In the present disclosure, the first to fourth power leads 32A to 32D are an example of "a plurality of leads." Furthermore, the first power lead 32A is an example of a "first lead," the second power lead 32B is an example of a "second lead," the third power lead 32C is an example of a "third lead," and the fourth power lead 32D is an example of a "fourth lead."

[0018] The die pad 31 is formed in the shape of a rectangular flat plate with its thickness direction in the Z direction. In a plan view, the die pad 31 is formed in a rectangular shape with its longitudinal direction in the X direction and its lateral direction in the Y direction. The die pad 31 includes a die pad front surface 31S and a die pad back surface 31R facing opposite each other in the Z direction, and first to fourth die pad side surfaces 31A to 31D as four die pad side surfaces connecting the die pad front surface 31S and the die pad back surface 31R. The first die pad side surface 31A and the second die pad side surface 31B constitute both end surfaces of the die pad 31 in the X direction, and the third die pad side surface 31C and the fourth die pad side surface 31D constitute both end surfaces of the die pad 31 in the Y direction.

[0019] 4, the semiconductor element 20 is disposed on the die pad 31 so that the drain electrode 24 faces the die pad surface 31S. The semiconductor element 20 is bonded to the die pad surface 31S by a conductive bonding material SD. This electrically connects the drain electrode 24 to the die pad 31. The conductive bonding material SD may be, for example, a solder paste or an Ag (silver) paste.

[0020] The first to fourth power leads 32A to 32D are arranged closer to the third die pad side surface 31C than the center of the die pad 31 in the Y direction in a plan view. The first power lead 32A and the second power lead 32B are arranged in a position facing the third die pad side surface 31C in the Y direction. The first power lead 32A and the second power lead 32B are arranged side by side in the X direction. The third power lead 32C is arranged closer to the first die pad side surface 31A than the first power lead 32A and the second power lead 32B. The third power lead 32C is arranged in a position facing a corner portion of the die pad 31 formed by the first die pad side surface 31A and the third die pad side surface 31C. The fourth power lead 32D is arranged closer to the second die pad side surface 31B than the first power lead 32A and the second power lead 32B. The fourth power lead 32D is disposed at a position facing a corner portion of the die pad 31 formed by the second die pad side surface 31B and the third die pad side surface 31C.

[0021] Each of the first to fourth power leads 32A to 32D includes a wire pad 32P and a lead portion 32Q. In one example, the wire pad 32P and the lead portion 32Q are integrated. In one example, the first power lead 32A and the second power lead 32B have the same shape. In one example, the third power lead 32C and the fourth power lead 32D have symmetrical shapes. The wire pad 32P of each of the first power lead 32A and the second power lead 32B is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction. The wire pad 32P of the third power lead 32C is formed in an L-shape surrounding the first die pad side surface 31A and the third die pad side surface 31C in a plan view. The wire pad 32P of the fourth power lead 32D is formed in an L-shape surrounding the second die pad side surface 31B and the third die pad side surface 31C in a plan view.

[0022] The lead portion 32Q of each of the first to fourth power leads 32A to 32D extends in the Y direction in a plan view. A portion of the lead portion 32Q protrudes outside the sealing resin 60 to form an external terminal.

[0023] The first to fourth control leads 33A to 33D are arranged closer to the fourth die pad side surface 31D than the center of the die pad 31 in the Y direction in a plan view. The first control lead 33A and the second control lead 33B are arranged in a position facing the fourth die pad side surface 31D in the Y direction. The first control lead 33A and the second control lead 33B are arranged side by side in the X direction. In one example, the first control lead 33A and the second control lead 33B have the same shape as the first power lead 32A and the second power lead 32B. The third control lead 33C is arranged closer to the first die pad side surface 31A than the first control lead 33A and the second control lead 33B. The third control lead 33C is arranged in a position facing a corner of the die pad 31 formed by the first die pad side surface 31A and the fourth die pad side surface 31D. In one example, the third control lead 33C has the same shape as the fourth power lead 32D. The fourth control lead 33D is disposed closer to the second die pad side surface 31B than the first control lead 33A and the second control lead 33B. The fourth control lead 33D is disposed in a position facing a corner portion of the die pad 31 formed by the second die pad side surface 31B and the fourth die pad side surface 31D. In one example, the fourth control lead 33D has the same shape as the third power lead 32C. Like the first to fourth power leads 32A to 32D, the first to fourth control leads 33A to 33D include wire pads 33P and lead portions 33Q. Portions of the lead portions 33Q of the first to fourth control leads 33A to 33D protrude outside the sealing resin 60 to form external terminals.

[0024] The plurality of power pads 21 of the semiconductor element 20 and the first to fourth power leads 32A to 32D are individually electrically connected by a plurality of first to fourth wires 71 to 74. The plurality of control pads 22 and the first to fourth control leads 33A to 33D are individually electrically connected by fifth to eighth wires 75 to 78.

[0025] 2, the sealing resin 60 seals the semiconductor element 20 and the first to eighth wires 71 to 78, and also partially seals the lead frame 30. The sealing resin 60 is made of an insulating material, such as a black epoxy resin.

[0026] The sealing resin 60 is formed in a rectangular plate shape with its thickness direction in the Z direction. The sealing resin 60 includes a sealing front surface 61 and a sealing back surface 62 facing opposite each other in the Z direction, and first to fourth sealing side surfaces 63 to 66 as four sealing side surfaces connecting the sealing front surface 61 and the sealing back surface 62. The first sealing side surface 63 and the second sealing side surface 64 constitute both end surfaces of the sealing resin 60 in the X direction, and the third sealing side surface 65 and the fourth sealing side surface 66 constitute both end surfaces of the sealing resin 60 in the Y direction. As shown in FIG. 3 , the sealing front surface 61 faces the same side as the die pad front surface 31S, and the sealing back surface 62 faces the same side as the die pad back surface 31R. Therefore, the sealing front surface 61 faces the same side as the element front surface 20S of the semiconductor element 20, and the sealing back surface 62 faces the same side as the element back surface 20R. As shown in FIGS. 3 and 4 , the die pad back surface 31R is exposed from the sealing back surface 62. 2, the first sealing side surface 63 faces the same side as the first die pad side surface 31A, and the second sealing side surface 64 faces the same side as the second die pad side surface 31B. The third sealing side surface 65 faces the same side as the third die pad side surface 31C, and the fourth sealing side surface 66 faces the same side as the fourth die pad side surface 31D.

[0027] The lead portion 32Q of each of the first to fourth power leads 32A to 32D protrudes from the third sealing side surface 65 to the outside of the sealing resin 60. The lead portion 33Q of each of the first to fourth control leads 33A to 33D protrudes from the fourth sealing side surface 66 to the outside of the sealing resin 60.

[0028] [Circuit Configuration of Semiconductor Device] An example of the circuit configuration of the semiconductor device 10 will be described with reference to Fig. 5. As shown in Fig. 5, the semiconductor device 10 includes a switching circuit 100 including a power transistor (a power MOSFET in the first embodiment), and a control circuit 110 that controls the switching circuit 100. Both the switching circuit 100 and the control circuit 110 are provided in the semiconductor element 20. In one example, the control circuit 110 includes a current sensor circuit 111, a temperature sensor circuit 112, an overcurrent protection (OCD: Over Charge Current Detection) circuit 113, an overheat protection (TSD: Thermal Shut Down) circuit 114, and an under voltage lock out (UVLO) circuit 115.

[0029] The semiconductor device 10 includes an input terminal 116, an input ground terminal 117, an output terminal 118, and an output ground terminal 119. The input terminal 116 is formed, for example, by one of the first to fourth control leads 33A to 33D (see FIG. 2). The input ground terminal 117 is formed, for example, by another control lead of the first to fourth control leads 33A to 33D. The output terminal 118 is formed by the die pad 31 (see FIG. 3). The output ground terminal 119 is formed by the first to fourth power leads 32A to 32D.

[0030] 5, a series circuit 200 including a power supply 201 and an inductive load 202 is electrically connected to the output terminal 118 and the output-side ground terminal 119. In addition, in the example shown in Fig. 5, the inductive load 202 is a relay including a switch Sw and a coil L.

[0031] The switching circuit 100 is electrically connected between an output terminal 118 and an output-side ground terminal 119. The switching circuit 100 includes a power MOSFET. The power MOSFET includes a gate terminal G, a drain terminal D, and a source terminal S. In the switching circuit 100, the drain terminal D is electrically connected to the output terminal 118, and the source terminal S is electrically connected to the output-side ground terminal 119.

[0032] The semiconductor device 10 includes an input wiring 121 connecting an input terminal 116 and a gate terminal G of the switching circuit 100, and a ground wiring 122 connecting an input ground terminal 117 and an output ground terminal 119. Between the input wiring 121 and the ground wiring 122, in order from the input terminal 116 side, a diode D1, a first resistor R1, an overcurrent protection circuit 113, an overheat protection circuit 114, an undervoltage lockout circuit 115, and a second resistor R2 are connected in parallel. A third resistor R3 is connected in series between the first resistor R1 and the overcurrent protection circuit 113 on the input wiring 121. A fourth resistor R4 is connected in series between the undervoltage lockout circuit 115 and the second resistor R2 on the input wiring 121.

[0033] The current sensor circuit 111 is electrically connected to the overcurrent protection circuit 113. The current sensor circuit 111 is configured to detect, for example, a current flowing through the input wiring 121. The current value detected by the current sensor circuit 111 is output to the overcurrent protection circuit 113. The overcurrent protection circuit 113 is driven in accordance with the current value from the current sensor circuit 111. In one example, when a current (overcurrent) greater than or equal to a predetermined value flows through the input wiring 121 due to a short circuit or static electricity, the overcurrent protection circuit 113 is configured to protect other circuits from the overcurrent by flowing the overcurrent from the input wiring 121 side to the ground wiring 122 side.

[0034] The temperature sensor circuit 112 is electrically connected to the overheat protection circuit 114. The temperature sensor circuit 112 is configured to detect the temperature of the semiconductor element 20. The temperature detected by the temperature sensor circuit 112 is output to the overheat protection circuit 114. The overheat protection circuit 114 is driven in accordance with the temperature detected by the temperature sensor circuit 112. In one example, the overheat protection circuit 114 is configured to prohibit the passage of electricity through the input wiring 121 when the temperature of the semiconductor element 20 reaches or exceeds a predetermined temperature. This suppresses a rise in temperature of the semiconductor element 20.

[0035] The low voltage malfunction prevention circuit 115 is configured to prohibit the switching circuit 100 from operating when the potential difference between the input wiring 121 and the ground wiring 122 is less than a predetermined value, and to allow the switching circuit 100 to operate when the potential difference is equal to or greater than the predetermined value.

[0036] A clamp diode D2 is electrically connected between the gate terminal G and the drain terminal D of the switching circuit 100. The clamp diode D2 is configured by connecting two diodes in reverse bias. The two diodes may include, for example, Zener diodes. The clamp diode D2 has a breakdown voltage V2 that is lower than the breakdown voltage V1 between the drain terminal D and the source terminal S of the power MOSFET. Therefore, the clamp diode D2 is configured to break down before the switching circuit 100 when the breakdown voltage V1 is applied between the drain terminal D and the source terminal S.

[0037] When the inductive load 202 is turned off, a back electromotive force V3 higher than the breakdown voltage V1 between the drain terminal D and the source terminal S is generated in the coil L, causing the clamp diode D2 to break down. When the clamp diode D2 breaks down, a current flows through the second resistor R2, generating a voltage (gate voltage) between the gate terminal G and the source terminal S. This gate voltage turns on the switching circuit 100 (power MOSFET), causing a current generated due to the back electromotive force V3 to flow between the drain terminal D and the source terminal S.

[0038] In this way, the load on the switching circuit 100 is reduced by the clamp diode D2, and the energy stored in the inductive load 202 is absorbed by the switching circuit 100. The amount of energy stored in the inductive load 202 that is absorbed is represented by the dynamic clamping capability Eac, which is one of the characteristics of a power MOSFET. The larger the value of the dynamic clamping capability Eac, the more energy stored in the inductive load 202 is absorbed. Note that the configuration of the control circuit 110 can be changed as desired.

[0039] [Configuration of Semiconductor Element] The internal configuration of the semiconductor element 20 will be described with reference to Figures 6 and 7. Figure 6 shows a schematic planar structure of the interior of the semiconductor element 20. Figure 7 shows a schematic planar structure in which a source electrode 23 and a passivation film 25, which will be described later, are added to the semiconductor element 20 of Figure 6.

[0040] The element surface 20S of the semiconductor element 20 includes an active region 40 in which a power transistor (a power MOSFET in the first embodiment) is formed, and a control circuit region 50 in which a control circuit 110 is formed. The active region 40 can also be said to be the region in which the switching circuit 100 in FIG. 5 is formed.

[0041] The control circuit region 50 is disposed at the center in the X direction and closer to the fourth element side surface 20D in the Y direction. The control circuit region 50 is formed in a substantially rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. The control circuit region 50 includes a first side 51 closer to the first element side surface 20A, a second side 52 closer to the second element side surface 20B, and a third side 53 closer to the third element side surface 20C in a plan view. Both the first side 51 and the second side 52 include portions extending in the Y direction. The third side 53 includes a portion extending in the X direction. The third side 53 is disposed closer to the third element side surface 20C than the center in the Y direction of the element surface 20S of the semiconductor element 20. The X direction dimension of the control circuit region 50 is greater than half the X direction dimension of the element surface 20S. In one example, the X direction dimension of the control circuit region 50 is greater than two-thirds the X direction dimension of the element surface 20S. In one example, the dimension of the control circuit region 50 in the X direction is about 3 / 4.

[0042] Here, the dimension of the control circuit region 50 in the X direction can be defined by the distance in the X direction between the first side 51 and the second side 52. The dimension of the element surface 20S in the X direction can be defined by the distance in the X direction between the first element side surface 20A and the second element side surface 20B.

[0043] As shown in FIG. 6 , the semiconductor element 20 may include multiple internal pads 54. The multiple internal pads 54 may include a pair of first internal pads 54A and a pair of second internal pads 54B arranged at different positions. The pair of first internal pads 54A are provided in a corner portion between the first side 51 and the third side 53 of the control circuit region 50. The control circuit region 50 is recessed to avoid the pair of first internal pads 54A in a planar view. The pair of first internal pads 54A are aligned in the Y direction. The pair of second internal pads 54B are provided in a corner portion between the second side 52 and the third side 53 of the control circuit region 50. The control circuit region 50 is recessed to avoid the pair of second internal pads 54B in a planar view. The pair of second internal pads 54B are aligned in the Y direction. In one example, the length of the second side 52 in the Y direction is shorter than the length of the first side 51 in the Y direction. Note that the lengths of the first side 51 and the second side 52 in the Y direction can each be changed as desired.

[0044] The multiple internal pads 54 may include an internal pad connected to the gate terminal G of the switching circuit 100. The multiple internal pads 54 may also include an internal pad connected to the control circuit 110. The multiple internal pads 54 may be formed to have a size different from that of at least one of the power pads 21 and the control pads 22 in a plan view. In one example, the multiple internal pads 54 may be formed to be smaller than the power pads 21 and the control pads 22 in a plan view.

[0045] A plurality of control pads 22 (four in the first embodiment) are provided between the control circuit region 50 and the fourth element side surface 20D in the Y direction. The control pads 22 are arranged at the same positions in the Y direction and spaced apart from one another in the X direction. Hereinafter, for convenience, the four control pads 22 will be referred to as "control pads 22A to 22D."

[0046] The control pads 22A and 22B are arranged between the control pads 22C and 22D in the X direction. The control pad 22A is arranged closer to the first element side surface 20A than the control pad 22B. The control pad 22C is arranged closer to the first element side surface 20A than the control pads 22A and 22B. The control pad 22D is arranged closer to the second element side surface 20B than the control pads 22A and 22B.

[0047] The control pad 22A is electrically connected to the first control lead 33A (see FIG. 2) by a fifth wire 75. The control pad 22B is electrically connected to the second control lead 33B (see FIG. 2) by a sixth wire 76. The control pad 22C is electrically connected to the third control lead 33C (see FIG. 2) by a seventh wire 77. The control pad 22D is electrically connected to the fourth control lead 33D (see FIG. 2) by an eighth wire 78. The fifth to eighth wires 75 to 78 are formed of a metal material such as copper (Cu), aluminum (Al), gold (Au), or Ag. In the first embodiment, the fifth to eighth wires 75 to 78 are formed of a material containing Cu.

[0048] The active region 40 is formed to surround the control circuit region 50 from both sides in the X direction and one side in the Y direction in a plan view. The active region 40 is disposed adjacent to the control circuit region 50 in a plan view. The active region 40 can be divided into, for example, a first transistor region 41 disposed closer to the third element side surface 20C than the control circuit region 50, a second transistor region 42 adjacent to the first side 51 of the control circuit region 50 in the X direction, and a third transistor region 43 adjacent to the second side 52 in the X direction. The dashed lines within the active region 40 indicate the boundary between the first transistor region 41 and the second transistor region 42 and the boundary between the first transistor region 41 and the third transistor region 43.

[0049] The active region 40 surrounds the control circuit region 50 from both sides in the X direction by the second transistor region 42 and the third transistor region 43. The active region 40 surrounds the control circuit region 50 from one side in the Y direction (the third element side surface 20C side) by the first transistor region 41.

[0050] The second transistor region 42 is formed in a rectangular shape with its longitudinal direction in the Y direction and its transverse direction in the X direction. The leading edge of the second transistor region 42 is located adjacent to the fourth element side surface 20D in the Y direction in a plan view. Therefore, the second transistor region 42 is formed adjacent to the fourth element side surface 20D in the X direction across the entire Y direction of the first edge 51 of the control circuit region 50. In one example, the width dimension WA2 (X direction dimension) of the second transistor region 42 is approximately 1 / 8 of the X direction dimension of the element surface 20S. The length dimension LA2 (Y direction dimension) of the second transistor region 42 is greater than the width dimension WA1 (Y direction dimension) of the first transistor region 41.

[0051] The third transistor region 43 is formed in a rectangular shape with the Y direction as its longitudinal direction and the X direction as its transverse direction. In one example, the width dimension WA3 (the dimension in the X direction) of the third transistor region 43 is approximately 1 / 8 of the X direction dimension of the element surface 20S. That is, the width dimension WA3 of the third transistor region 43 may be equal to the width dimension WA2 of the second transistor region 42. The length dimension LA3 (the dimension in the Y direction) of the third transistor region 43 is greater than the width dimension WA1 of the first transistor region 41. In one example, the length dimension LA3 of the third transistor region 43 is smaller than the length dimension LA2 of the second transistor region 42. Therefore, the leading edge of the third transistor region 43 is located closer to the first transistor region 41 in the Y direction than the leading edge of the second transistor region 42. The third transistor regions 43 are formed adjacent to each other in the X direction along the entire Y direction of the second side 52 of the control circuit region 50. The length dimension LA3 of the third transistor region 43 may be equal to the length dimension LA2 of the second transistor region 42.

[0052] The first transistor region 41 includes a region adjacent to the third side 53 of the control circuit region 50 in the Y direction. The first transistor region 41 has a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. The length dimension LA1 (dimension in the X direction) of the first transistor region 41 is longer than the X direction dimension of the control circuit region 50. In one example, the width dimension WA1 of the first transistor region 41 is less than twice the width dimension WA2 of the second transistor region 42. In one example, the width dimension WA1 of the first transistor region 41 is less than twice the width dimension WA3 of the third transistor region 43. In one example, the width dimension WA1 of the first transistor region 41 is approximately 1.5 times the width dimension WA2 (WA3) of the second transistor region 42 (third transistor region 43).

[0053] In one example, a slit 44 is formed in the first transistor region 41 so as to avoid the temperature sensor circuit 112. The slit 44 is disposed closer to the third transistor region 43 than the center of the first transistor region 41 in the X direction.

[0054] 7, a source electrode 23 is formed on the active region 40 (see FIG. 6). Although not shown, the source electrode 23 is formed on an insulating layer that covers the power MOSFET formed in the active region 40. The source electrode 23 and the power MOSFET in the active region 40 are electrically connected by a plurality of connection wirings that penetrate the insulating layer in the Z direction. In this way, the source electrode 23 is disposed on the active region 40 at a position different from that of the control circuit region 50.

[0055] In the example shown in FIG. 7 , the source electrode 23 is formed in the same shape as the active region 40 in a plan view. That is, as shown in FIGS. 6 and 7 , the source electrode 23 includes a first electrode region 23A corresponding to the first transistor region 41, a second electrode region 23B corresponding to the second transistor region 42, and a third electrode region 23C corresponding to the third transistor region 43. Therefore, the source electrode 23 is formed to surround the control circuit region 50 from both sides in the X direction and one side in the Y direction in a plan view. The first electrode region 23A is disposed adjacent to the control circuit region 50 in the Y direction in a plan view. The second electrode region 23B is disposed between the control circuit region 50 and the first element side surface 20A, and the third electrode region 23C is disposed between the control circuit region 50 and the second element side surface 20B. The second electrode region 23B and the third electrode region 23C are disposed separately on both sides of the control circuit region 50 in the X direction in a plan view.

[0056] The first electrode region 23A is an electrode region covering the first transistor region 41. Therefore, the first electrode region 23A includes a region adjacent to the third side 53 of the control circuit region 50 in the Y direction. The first electrode region 23A has a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. The length dimension LB1 (dimension in the X direction) of the first electrode region 23A is longer than the X direction dimension of the control circuit region 50. In one example, the width dimension WB1 (dimension in the Y direction) of the first electrode region 23A is less than twice the width dimension WB2 (dimension in the Y direction) of the second electrode region 23B. In one example, the width dimension WB1 of the first electrode region 23A is less than twice the width dimension WB3 (dimension in the Y direction) of the third electrode region 23C. In one example, the width dimension WB1 of the first electrode region 23A is about 1.5 times the width dimension WB2 (WB3) of the second electrode region 23B (third electrode region 23C).

[0057] In one example, a slit 23AA is formed in the first electrode region 23A so as to avoid the temperature sensor circuit 112. The slit 23AA is located closer to the third electrode region 23C than the center of the first electrode region 23A in the X direction. The slit 23AA is located at a position overlapping with the slit 44 of the first transistor region 41 in a plan view. Therefore, it can be said that the temperature sensor circuit 112 is exposed from the source electrode 23 in a plan view.

[0058] The second electrode region 23B is an electrode region that covers the second transistor region 42. Therefore, the second electrode region 23B is located adjacent to the first side 51 of the control circuit region 50 in the X direction in a plan view. The second electrode region 23B is formed in a rectangular shape with the Y direction as its longitudinal direction and the X direction as its transverse direction. The leading edge of the second electrode region 23B is located adjacent to the fourth element side surface 20D in the Y direction in a plan view. Therefore, the second electrode region 23B is formed adjacent to the fourth element side surface 20D in the X direction across the entire Y direction of the first side 51 of the control circuit region 50. In one example, the width dimension WB2 (X direction dimension) of the second electrode region 23B is approximately 1 / 8 of the X direction dimension of the element surface 20S. The length dimension LB2 (Y direction dimension) of the second electrode region 23B is greater than the width dimension WB1 of the first electrode region 23A.

[0059] The third electrode region 23C is an electrode region covering the third transistor region 43. Therefore, the third electrode region 23C is positioned adjacent to the second side 52 of the control circuit region 50 in the X direction in a plan view. The third electrode region 23C is formed in a rectangular shape with the Y direction as its longitudinal direction and the X direction as its transverse direction. In one example, the width dimension WB3 of the third electrode region 23C is approximately 1 / 8 of the X direction dimension of the element surface 20S. In other words, the width dimension WB3 of the third electrode region 23C may be equal to the width dimension WB2 of the second electrode region 23B. The length dimension LB3 (dimension in the Y direction) of the third electrode region 23C is greater than the width dimension WB1 of the first electrode region 23A. In one example, the length dimension LB3 of the third electrode region 23C is smaller than the length dimension LB2 of the second electrode region 23B. Therefore, the leading edge of the third electrode region 23C is located closer to the first electrode region 23A in the Y direction than the leading edge of the second electrode region 23B. The third electrode regions 23C are formed adjacent to each other in the X direction over the entire Y direction of the second side 52 of the control circuit region 50. Note that the length dimension LB3 of the third electrode region 23C may be equal to the length dimension LB2 of the second electrode region 23B.

[0060] The source electrode 23 and the control circuit region 50 are covered with, for example, a passivation film 25. The passivation film 25 is a protective film that protects the semiconductor element 20, and is made of, for example, silicon nitride (SiN) or silicon oxide (SiO ２ ) is formed.

[0061] The passivation film 25 includes a plurality of first to fifth openings 25A to 25E on the source electrode 23. The portions of the source electrode 23 exposed by the plurality of first to fifth openings 25A to 25E constitute the power pad 21. The power pad 21 exposed by the plurality of first to fourth openings 25A to 25D is the source pad to which the first to fourth wires 71 to 74 are connected.

[0062] The multiple first openings 25A and the multiple second openings 25B are provided in a portion of the passivation film 25 that covers the first electrode region 23A. The multiple (five in the first embodiment) first openings 25A are arranged closer to the second electrode region 23B than the center of the first electrode region 23A in the X direction in a plan view. The multiple first openings 25A are arranged at a distance from each other in the X direction. Among the multiple first openings 25A, first openings 25A adjacent to each other in the X direction are arranged with a shift in the Y direction.

[0063] The plurality of second openings 25B (five in the first embodiment) are arranged closer to the third electrode region 23C than the center of the first electrode region 23A in the X direction in a plan view. The plurality of second openings 25B are arranged at a distance from each other in the X direction. Among the plurality of second openings 25B, second openings 25B adjacent to each other in the X direction are arranged shifted in the Y direction. In one example, the arrangement of the plurality of second openings 25B is line-symmetrical to the arrangement of the plurality of first openings 25A with respect to a virtual line along the Y direction at the center of the first electrode region 23A in the X direction.

[0064] The third openings 25C are arranged in both the portion of the passivation film 25 that covers the first electrode region 23A and the portion that covers the second electrode region 23B. The third openings 25C are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction. The third openings 25C are arranged closer to the first element side surface 20A than the first openings 25A.

[0065] The plurality of fourth openings 25D are arranged over both the portion of the passivation film 25 that covers the first electrode region 23A and the portion that covers the third electrode region 23C. The plurality of fourth openings 25D are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. The plurality of fourth openings 25D are arranged closer to the second element side surface 20B than the plurality of second openings 25B.

[0066] The plurality of fifth openings 25E are provided in a portion of the passivation film 25 that covers the first electrode region 23A. The plurality of fifth openings 25E are arranged at positions adjacent to the plurality of first openings 25A in the Y direction. The plurality of fifth openings 25E are also arranged at positions adjacent to the plurality of second openings 25B in the Y direction.

[0067] [Connection Structure Between Semiconductor Element and Wires] The connection structure between the semiconductor element 20 and the first to fourth wires 71 to 74 will be described with reference to FIGS.

[0068] Fig. 8 shows a schematic planar structure of the semiconductor element 20 of Fig. 7 to which first to fourth electrode connection portions 71A to 74A of the first to fourth wires 71 to 74 and heat dissipation regions 90A to 90D (double-dashed line rectangles) for dissipating heat by the first to fourth wires 71 to 74 have been added. Fig. 9 shows a schematic planar structure of the semiconductor element 20 of Fig. 8 to which the first to fourth wires 71 to 74 have been added. Fig. 10 shows a schematic cross-sectional structure of a plurality of first wires 71 and a first heat sink 81, which will be described later. Note that the heat dissipation regions 90A to 90D have been omitted from Fig. 9 to facilitate understanding of the drawing.

[0069] 8 and 9, a plurality of first wires 71 are individually connected to the power pads 21 (source pads) exposed from the plurality of first openings 25A. Each first wire 71 includes a first electrode connection portion 71A. Here, the first wires 71 are bonding wires formed by a wire bonding device. The first electrode connection portion 71A of the first wires 71 constitutes a first bonding portion. Therefore, it can be said that the first electrode connection portion 71A constitutes a ball bond.

[0070] The multiple first electrode connection portions 71A are arranged spaced apart from each other in the X direction. The first electrode connection portions 71A adjacent to each other in the X direction are shifted in the Y direction. That is, the multiple first electrode connection portions 71A include a first electrode connection portion 71A closer to the control circuit region 50 than the center of the first electrode region 23A in the Y direction, and a first electrode connection portion 71A closer to the third element side surface 20C than the center of the first electrode region 23A in the Y direction. The first electrode connection portion 71A closest to the second element side surface 20B among the multiple first electrode connection portions 71A is disposed at the center of the first electrode region 23A in the Y direction.

[0071] A plurality of second wires 72 are individually connected to the power pads 21 (source pads) exposed through the plurality of second openings 25B. Each second wire 72 includes a second electrode connection portion 72A. Similar to the first electrode connection portion 71A of the first wire 71, the second electrode connection portion 72A forms a ball bond.

[0072] The multiple second electrode connection portions 72A are arranged spaced apart from one another in the X direction. Second electrode connection portions 72A adjacent to one another in the X direction are shifted in the Y direction. That is, the multiple second electrode connection portions 72A include a second electrode connection portion 72A closer to the control circuit region 50 than the center of the first electrode region 23A in the Y direction, and a second electrode connection portion 72A closer to the third element side surface 20C than the center of the first electrode region 23A in the Y direction. The second electrode connection portion 72A closest to the first element side surface 20A among the multiple second electrode connection portions 72A is disposed at the center of the first electrode region 23A in the Y direction.

[0073] A plurality of third wires 73 are individually connected to the power pads 21 (source pads) exposed through the plurality of third openings 25C. Each of the third wires 73 includes a third electrode connection portion 73A. The third electrode connection portion 73A forms a ball bond, similar to the first electrode connection portion 71A of the first wire 71.

[0074] The multiple third electrode connection portions 73A are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. Of the multiple third electrode connection portions 73A, three third electrode connection portions 73A are arranged in the second electrode region 23B, and the remaining two third electrode connection portions 73A are arranged in the first electrode region 23A. These two third electrode connection portions 73A are arranged at the ends of the first electrode region 23A in the X direction that are closer to the first element side surface 20A.

[0075] A plurality of fourth wires 74 are individually connected to the power pads 21 (source pads) exposed through the plurality of fourth openings 25D. Each fourth wire 74 includes a fourth electrode connection portion 74A. The fourth electrode connection portion 74A forms a ball bond, similar to the first electrode connection portion 71A of the first wire 71.

[0076] The multiple fourth electrode connection portions 74A are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. Three of the multiple fourth electrode connection portions 74A are arranged in the third electrode region 23C, and the remaining two fourth electrode connection portions 74A are arranged in the first electrode region 23A. These two fourth electrode connection portions 74A are arranged at the end closer to the second element side surface 20B of both end portions of the first electrode region 23A in the X direction.

[0077] The first to fourth wires 71 to 74 are formed of a metal material such as Cu, Al, Au, or Ag. In the first embodiment, the first to fourth wires 71 to 74 are formed of a material containing Cu. The first to fourth wires 71 to 74 may be formed of the same material as the fifth to eighth wires 75 to 78, for example.

[0078] 8, the regions where heat is dissipated from the source electrode 23 by the first to fourth wires 71 to 74 are shown as heat dissipation regions 90A to 90D indicated by two-dot chain lines. The heat dissipation regions 90A to 90D by the first to fourth wires 71 to 74 are shown as, for example, rectangular regions centered on the first to fourth electrode connection portions 71A to 74A, respectively. In one example, the heat dissipation regions 90A to 90D are all the same size.

[0079] A plurality of heat dissipation regions 90A corresponding to the first wires 71 are provided so as to surround each of the plurality of first electrode connecting portions 71A in a plan view. The heat dissipation regions 90A adjacent to each other in the X direction partially overlap, for example.

[0080] A plurality of heat dissipation regions 90B corresponding to the second wires 72 are provided so as to surround each of the plurality of second electrode connecting portions 72A in a plan view. The heat dissipation regions 90B adjacent to each other in the X direction partially overlap, for example.

[0081] A plurality of heat dissipation regions 90C corresponding to the third wires 73 are provided so as to surround each of the plurality of third electrode connection portions 73A in a plan view. Therefore, the plurality of heat dissipation regions 90C are aligned in the Y direction. Of the plurality of heat dissipation regions 90C, two heat dissipation regions 90C corresponding to the first electrode region 23A partially overlap with the heat dissipation region 90A of the plurality of heat dissipation regions 90A that is closest to the first element side surface 20A.

[0082] A plurality of heat dissipation regions 90D corresponding to the fourth wires 74 are provided so as to surround each of the plurality of fourth electrode connection portions 74A in a plan view. Therefore, the plurality of heat dissipation regions 90D are aligned in the Y direction. Of the plurality of heat dissipation regions 90D, two heat dissipation regions 90D corresponding to the first electrode regions 23A partially overlap with the heat dissipation region 90B closest to the second element side surface 20B among the plurality of heat dissipation regions 90B.

[0083] The X-direction dimension of the multiple heat dissipation regions 90C is slightly smaller than the X-direction dimension of the second electrode region 23B. The three heat dissipation regions 90C are formed over most of the second electrode region 23B. Therefore, heat from the second electrode region 23B is easily dissipated by the three heat dissipation regions 90C. Similarly, the X-direction dimension of the multiple heat dissipation regions 90D is slightly smaller than the X-direction dimension of the third electrode region 23C. The three heat dissipation regions 90D are formed over most of the third electrode region 23C. Therefore, heat from the third electrode region 23C is easily dissipated by the three heat dissipation regions 90D.

[0084] On the other hand, the width dimension WB1 (dimension in the Y direction) of the first electrode region 23A is larger than, for example, the dimension in the Y direction of the heat dissipation region 90A. In particular, in the example shown in FIG. 7 , the width dimension WB1 of the first electrode region 23A is more than twice the dimension in the Y direction of the heat dissipation region 90A. Furthermore, four of the multiple heat dissipation regions 90A are positioned offset in the Y direction from the center of the first electrode region 23A in the Y direction. Therefore, the first electrode region 23A includes a region where no heat dissipation region 90A is located (hereinafter referred to as a "non-heat dissipation region 91A"). The non-heat dissipation region 91A is a region where the temperature of the source electrode 23 is more likely to be higher than that of the heat dissipation region 90A. Multiple non-heat dissipation regions 91A (four in the first embodiment) are provided. Here, a fifth opening 25E is formed in each of the multiple non-heat dissipation regions 91A. That is, the plurality of non-heat dissipation regions 91A include power pads 21 (source pads) in which the source electrodes 23 are exposed from the passivation film 25 .

[0085] A first heat dissipation body 81 is disposed in each non-heat dissipation region 91A. The first heat dissipation body 81 is formed of, for example, the same material as the first to fourth wires 71 to 74. In the first embodiment, the first heat dissipation body 81 is formed of a material containing Cu. As shown in FIG. 10 , the first heat dissipation body 81 has the same shape as the first electrode connection portion 71A. In other words, the first heat dissipation body 81 is formed by ball bonding using a wire bonding device.

[0086] As shown in FIG. 9 , the first heat sink 81 is disposed in a direction along the extension of the first wire 71 relative to the first electrode connection portion 71A in a plan view. Therefore, the first heat sink 81 disposed adjacent to the first electrode connection portion 71A closer to the third element side surface 20C is disposed in a position overlapping the first wire 71 in a plan view. Furthermore, the first heat sink 81 disposed adjacent to the first electrode connection portion 71A closer to the fourth element side surface 20D is disposed in a position where the first wire 71 cannot be formed to connect to the first power lead 32A (see FIG. 2 ). Thus, the non-heat sink region 91A is a position where the first wire 71 cannot be formed, and the first heat sink 81 is formed in place of the first wire 71.

[0087] Furthermore, four of the heat dissipation regions 90B are positioned offset in the Y direction from the center of the first electrode region 23A in the Y direction. Therefore, the first electrode region 23A includes a region where no heat dissipation region 90B is located (hereinafter referred to as a "non-heat dissipation region 91B"). The non-heat dissipation region 91B is a region where the temperature of the source electrode 23 is more likely to be higher than that of the heat dissipation region 90B. Multiple non-heat dissipation regions 91B (four in the first embodiment) are provided. Here, a fifth opening 25E is formed in each of the multiple non-heat dissipation regions 91B. In other words, the multiple non-heat dissipation regions 91B include a power pad 21 (source pad) where the source electrode 23 is exposed from the passivation film 25.

[0088] A second heat dissipation body 82 is disposed in each non-heat dissipation region 91B. The second heat dissipation body 82 is formed, for example, from the same material as the first to fourth wires 71 to 74. In the first embodiment, the second heat dissipation body 82 is formed from a material containing Cu. That is, the second heat dissipation body 82 is formed from the same material as the first heat dissipation body 81. Like the first heat dissipation body 81, the second heat dissipation body 82 is formed by ball bonding using a wire bonding device. Therefore, the second heat dissipation body 82 has the same shape as the first heat dissipation body 81. That is, the second heat dissipation body 82 has the same shape as the second electrode connection portion 72A.

[0089] As shown in FIG. 9 , the second heat sink 82 is disposed in a direction along the extension of the second wire 72 relative to the second electrode connection portion 72A in a plan view. Therefore, the second heat sink 82 disposed adjacent to the second electrode connection portion 72A and closer to the third element side surface 20C is disposed in a position overlapping the second wire 72 in a plan view. Furthermore, the second heat sink 82 disposed adjacent to the second electrode connection portion 72A and closer to the fourth element side surface 20D is disposed in a position where the second wire 72 connected to the second power lead 32B (see FIG. 2) cannot be formed at the position where the second heat sink 82 is disposed. In this way, the non-heat dissipation region 91B is a position where the second wire 72 cannot be formed, and the second heat sink 82 is formed in place of the second wire 72.

[0090] [Operation] The operation of the semiconductor device 10 of the first embodiment will be described. When the semiconductor device 10 switches on, heat is generated between the drain electrode 24 and the source electrode 23 due to the inductance of the inductive load. At this time, the heat is dissipated from the first electrode region 23A of the source electrode 23 to the control circuit region 50, from the second electrode region 23B to the control circuit region 50, and from the third electrode region 23C to the control circuit region 50. In other words, heat from the source electrode 23 moves from the source electrode 23 to the control circuit region 50 via three heat dissipation paths. This prevents localized temperature increases in the semiconductor element 20, thereby preventing avalanche breakdown. As a result, the avalanche resistance (active clamp resistance) of the semiconductor device 10 can be improved.

[0091] [Effects] The semiconductor device 10 of the first embodiment provides the following effects. (1-1) The semiconductor device 10 includes a semiconductor element 20 including an element front surface 20S, an element back surface 20R facing the opposite side to the element front surface 20S, and a source electrode 23 formed on the element front surface 20S, a die pad 31 supporting the semiconductor element 20, first to fourth power leads 32A to 32D arranged around the die pad 31, and first to fourth wires 71 to 74 connecting the source electrode 23 to the first to fourth power leads 32A to 32D. The element front surface 20S includes an active region 40 in which a power transistor is formed, and a control circuit region 50 in which a control circuit 110 that controls the power transistor is formed. The active region 40 is formed to surround the control circuit region 50 from both sides in the X direction and one side in the Y direction. The source electrode 23 is disposed on the active region 40 at a position different from the control circuit region 50, and is formed so as to surround the control circuit region 50 from both sides in the X direction and one side in the Y direction in plan view.

[0092] With this configuration, compared to a configuration in which the source electrode and the control circuit region 50 are adjacent to each other on only one side in the Y direction, for example, there are more heat dissipation paths from the source electrode 23 to the control circuit region 50, and therefore heat is more easily dissipated from the source electrode 23 to the control circuit region 50. Therefore, the occurrence of avalanche breakdown can be avoided, and the avalanche resistance (active clamp resistance) of the semiconductor device 10 can be improved.

[0093] (1-2) The source electrode 23 includes a first electrode region 23A arranged adjacent to the control circuit region 50 in the Y direction in a plan view, and a second electrode region 23B and a third electrode region 23C arranged separately on both sides of the control circuit region 50 in the X direction in a plan view. The semiconductor device 10 includes, as the multiple power leads, a first power lead 32A and a second power lead 32B located in a region opposite the control circuit region 50 with respect to the source electrode 23 in the Y direction and arranged spaced apart in the X direction, a third power lead 32C arranged in a region close to the second electrode region 23B among regions on both sides of the source electrode 23 in the X direction, and a fourth power lead 32D arranged in a region close to the third electrode region 23C among regions on both sides of the source electrode 23 in the X direction. The multiple wires include multiple first wires 71 connecting the first electrode region 23A and the first power lead 32A, multiple second wires 72 connecting the first electrode region 23A and the second power lead 32B, multiple third wires 73 connecting the second electrode region 23B and the third power lead 32C, and multiple fourth wires 74 connecting the third electrode region 23C and the fourth power lead 32D.

[0094] According to this configuration, a plurality of wires are connected to each of the first to third electrode regions 23A to 23C of the source electrode 23. Therefore, heat from the source electrode 23 is transferred to the first to fourth power leads 32A to 32D via these wires. This makes it easier for the source electrode 23 to dissipate heat, thereby improving the avalanche resistance (active clamp resistance) of the semiconductor device 10.

[0095] (1-3) The width WB1 of the first electrode region 23A is larger than the width WB2 of the second electrode region 23B and the width WB3 of the third electrode region 23C. The first wires 71 are arranged spaced apart from one another in the X direction and offset from one another in the Y direction. The second wires 72 are arranged spaced apart from one another in the X direction and offset from one another in the Y direction.

[0096] With this configuration, the number of first wires 71 and second wires 72 arranged in the first electrode region 23A can be increased compared to a configuration in which a plurality of first wires 71 and a plurality of second wires 72 are arranged in a row along the X direction in the first electrode region 23A. Therefore, the first wires 71 and the second wires 72 facilitate heat dissipation from the source electrode 23.

[0097] (1-4) The semiconductor device 10 further includes a plurality of heat sinks 81, 82 joined to the source electrode 23. The heat sinks 81, 82 are arranged in the first electrode region 23A. With this configuration, heat from the first electrode region 23A is transferred to the sealing resin 60 via the heat sinks 81, 82. This improves the heat dissipation performance of the first electrode region 23A.

[0098] (1-5) The heat sink includes a first heat sink 81 arranged closer to the second electrode region 23B than the center of the first electrode region 23A in the X direction, and a second heat sink 82 arranged closer to the third electrode region 23C than the center of the first electrode region 23A in the X direction.

[0099] According to this configuration, heat from the first electrode region 23A is transferred to the sealing resin 60 via the first heat sink 81 and the second heat sink 82. This improves the heat dissipation performance of the first electrode region 23A.

[0100] (1-6) Each of the plurality of first wires 71 includes a first electrode connection portion 71A. The first heat sink 81 is arranged in a direction along the extension direction of the first wires 71 relative to the first electrode connection portion 71A in a plan view.

[0101] According to this configuration, the first heat sink 81 is disposed in an area of ​​the first electrode region 23A where the first wires 71 cannot be disposed. Therefore, the first heat sink 81 can further improve the heat dissipation performance of the first electrode region 23A while maintaining the maximum number of first wires 71 that can be disposed in the first electrode region 23A.

[0102] (1-7) Each of the second wires 72 includes a second electrode connection portion 72A. The second heat sink 82 is disposed in a direction along the extension direction of the second wires 72 relative to the second electrode connection portion 72A in a plan view.

[0103] According to this configuration, the second heat sink 82 is disposed in an area of ​​the first electrode region 23A where the second wires 72 cannot be disposed. Therefore, the second heat sink 82 can further improve the heat dissipation performance of the first electrode region 23A while maintaining the maximum number of second wires 72 that can be disposed in the first electrode region 23A.

[0104] (1-8) The second electrode region 23B surrounds the entire control circuit region 50 in the Y direction when viewed from the X direction. This configuration facilitates heat transfer from the second electrode region 23B to the entire control circuit region 50 in the Y direction. This improves the heat dissipation performance of the source electrode 23.

[0105] (1-9) The third electrode region 23C surrounds the entire control circuit region 50 in the Y direction when viewed from the X direction. This configuration facilitates heat transfer from the third electrode region 23C to the entire control circuit region 50 in the Y direction. This improves the heat dissipation performance of the source electrode 23.

[0106] (1-10) The width WB2 of the second electrode region 23B is equal to the width WB3 of the third electrode region 23C. This configuration reduces the imbalance in the amount of heat generated between the second electrode region 23B and the third electrode region 23C, thereby reducing the difference in temperature between the second electrode region 23B and the third electrode region 23C. This makes it possible to suppress a decrease in avalanche resistance (active clamp resistance) due to an excessive temperature in one of the second electrode region 23B and the third electrode region 23C.

[0107] (1-11) The heat sinks 81 and 82 contain Cu. With this configuration, the heat sinks 81 and 82 can improve the heat dissipation performance of the source electrode 23 compared to when the heat sinks 81 and 82 are made of, for example, Al.

[0108] (1-12) The heat sinks 81, 82 have the same shape as the first electrode connection portion 71A of the first wire 71 and the second electrode connection portion 72A of the second wire 72. With this configuration, the heat sinks 81, 82 can be formed by the same wire bonding apparatus that forms the first wire 71 and the second wire 72. Therefore, the process of forming the heat sinks 81, 82 can be shared with the process of forming the first wire 71 and the second wire 72, thereby simplifying the manufacturing process of the semiconductor device 10.

[0109] 11 to 15, a semiconductor device 10 according to a second embodiment will be described. The semiconductor device 10 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment mainly in the internal configuration of the semiconductor element 20. Below, differences from the semiconductor device 10 according to the first embodiment will be described in detail, and components common to the semiconductor device 10 according to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0110] FIG. 11 shows a schematic planar structure of the interior of a semiconductor device 10. FIG. 12 shows a schematic planar structure of the interior of a semiconductor element 20. FIG. 13 shows a schematic planar structure in which a source electrode 23 and a passivation film 25 are added to the semiconductor element 20 of FIG. 12. FIG. 14 shows a schematic planar structure in which first to fourth electrode connection portions 71A to 74A of the first to fourth wires 71 to 74 and heat dissipation regions 90A to 90D are added to the semiconductor element 20 of FIG. 13. FIG. 15 shows a schematic planar structure in which the first to fourth wires 71 to 74 are added to the semiconductor element 20 of FIG. 14. Note that the heat dissipation regions 90A to 90D are omitted in FIG. 15 to make the drawing easier to understand.

[0111] 12, the element surface 20S of the semiconductor element 20 includes an active region 130 in which a power transistor (a power MOSFET in the second embodiment) is formed, and a control circuit region 140 in which the control circuit 110 of Fig. 5 is formed. The active region 130 can also be said to be the region in which the switching circuit 100 of Fig. 5 is formed.

[0112] The control circuit region 140 is disposed on the element surface 20S closer to the first element side surface 20A and the fourth element side surface 20D. Similar to the first embodiment, the control circuit region 140 includes first to third sides 141 to 143. Unlike the first embodiment, the first side 141 is disposed adjacent to the first element side surface 20A in the X direction in plan view.

[0113] The control circuit region 140 is formed in a generally rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. In one example, the X direction dimension of the control circuit region 140 is between 2 / 3 and 3 / 4 of the X direction dimension of the element surface 20S. In another example, the Y direction dimension of the control circuit region 140 is between 1 / 2 and 2 / 3 of the Y direction dimension of the element surface 20S. The size of the control circuit region 140 can be changed as desired.

[0114] In the example shown in FIG. 12 , a plurality of first internal pads 54A (three in the second embodiment) are provided in the corner portion between the first side 141 and the third side 143 of the control circuit region 140. The control circuit region 140 is recessed in a plan view to avoid the plurality of first internal pads 54A. The plurality of first internal pads 54A are aligned in the Y direction. A second internal pad 54B is provided in the corner portion between the second side 142 and the third side 143 of the control circuit region 140. The control circuit region 140 is recessed in a plan view to avoid the second internal pad 54B. Furthermore, a plurality of control pads 22 (four in the second embodiment) are provided between the control circuit region 140 and the fourth element side surface 20D in the Y direction. The plurality of control pads 22 are arranged at the same positions relative to each other in the Y direction and spaced apart from each other in the X direction. Hereinafter, for convenience, the four control pads 22 will be referred to as "control pads 22A to 22D."

[0115] 11 , the control pad 22A is electrically connected to the first control lead 33A by a fifth wire 75. The control pad 22B is electrically connected to the second control lead 33B by a sixth wire 76. The control pad 22C is electrically connected to the third control lead 33C by a seventh wire 77. The control pad 22D is electrically connected to the fourth control lead 33D by an eighth wire 78.

[0116] 12 , the active region 130 is formed to surround the control circuit region 140 from one side in the X direction and one side in the Y direction in a plan view. In one example, the active region 130 is formed in an L-shape in a plan view. The active region 130 can be divided into, for example, a first transistor region 131 disposed closer to the third element side surface 20C than the control circuit region 140, and a second transistor region 132 adjacent to the second side 142 of the control circuit region 140 in the X direction. The dashed line in the active region 130 indicates the boundary between the first transistor region 131 and the second transistor region 132.

[0117] The active region 130 surrounds the control circuit region 140 from one side in the Y direction (the third element side surface 20C side) by the first transistor region 131. The active region 130 surrounds the control circuit region 140 from one side in the X direction (the second element side surface 20B side) by the second transistor region 132.

[0118] The second transistor region 132 is formed in a rectangular shape with its longitudinal direction in the Y direction and its transverse direction in the X direction. The leading edge of the second transistor region 132 is located adjacent to the fourth element side surface 20D in the Y direction in a plan view. Therefore, the second transistor region 132 is formed adjacent to the fourth element side surface 20D in the X direction across the entire Y direction of the second edge 142 of the control circuit region 140. In one example, the width dimension WC2 (X direction dimension) of the second transistor region 132 is approximately 1 / 4 of the X direction dimension of the element surface 20S. The length dimension LC2 (Y direction dimension) of the second transistor region 132 is greater than the width dimension WC1 (Y direction dimension) of the first transistor region 131.

[0119] The first transistor region 131 includes a region adjacent to the third side 143 of the control circuit region 140 in the Y direction. The first transistor region 131 has a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. The length dimension LC1 (the dimension in the X direction) of the first transistor region 131 is longer than the dimension in the X direction of the control circuit region 140. In the example shown in FIG. 12 , the width dimension WC1 of the first transistor region 131 is equal to the width dimension WC2 of the second transistor region 132.

[0120] In one example, a slit 133 is formed in the first transistor region 131 so as to avoid the temperature sensor circuit 112. The slit 133 is disposed closer to the second transistor region 132 than the center of the first transistor region 131 in the X direction.

[0121] 13, a source electrode 150 is formed on the active region 130 (see FIG. 12). Although not shown, the source electrode 150 is formed on an insulating layer that covers the power MOSFET formed in the active region 130. The source electrode 150 and the power MOSFET in the active region 130 are electrically connected by a plurality of connection wirings that penetrate the insulating layer in the Z direction. In this way, the source electrode 150 is disposed on the active region 130 at a position different from that of the control circuit region 140.

[0122] In the example shown in FIG. 13 , the source electrode 150 is formed in the same shape as the active region 130 in a plan view. That is, as shown in FIGS. 12 and 13 , the source electrode 150 includes a first electrode region 151 corresponding to the first transistor region 131 and a second electrode region 152 corresponding to the second transistor region 132. The first electrode region 151 can be considered to be an electrode region covering the first transistor region 131, and the second electrode region 152 can be considered to be an electrode region covering the second transistor region 132. Therefore, the source electrode 150 is formed to surround the control circuit region 140 from one side in the X direction (the second element side surface 20B side) and one side in the Y direction (the third element side surface 20C side) in a plan view. The first electrode region 151 is disposed adjacent to the control circuit region 140 in the Y direction in a plan view. The second electrode region 152 is disposed adjacent to the control circuit region 140 in the X direction in a plan view. The size of the first electrode region 151 is approximately the same as that of the first transistor region 131, and the size of the second electrode region 152 is approximately the same as that of the second transistor region 132. Therefore, the width dimension WD1 (dimension in the Y direction) of the first electrode region 151 is equal to the width dimension WD2 (dimension in the X direction) of the second electrode region 152. The length dimension LD1 (dimension in the X direction) of the first electrode region 151 is greater than the length dimension LD2 (dimension in the Y direction) of the second electrode region 152.

[0123] In one example, a slit 153 is formed in the first electrode region 151 so as to avoid the temperature sensor circuit 112. The slit 153 is disposed closer to the second electrode region 152 than the center of the first electrode region 151 in the X direction. The slit 153 is disposed at a position overlapping with the slit 133 in the first transistor region 131 in a plan view. Therefore, it can be said that the temperature sensor circuit 112 is exposed from the source electrode 150 in a plan view.

[0124] The source electrode 150 and the control circuit region 140 are covered with, for example, a passivation film 160. The passivation film 160 is a protective film that protects the semiconductor element 20, and is made of, for example, SiN or SiO ２ It is formed by

[0125] The passivation film 160 includes a plurality of first to fifth openings 161 to 165 on the source electrode 150. The portions of the source electrode 150 exposed by the plurality of first to fifth openings 161 to 165 constitute the power pad 21 (source pad). The power pad 21 (source pad) exposed by the plurality of first to fourth openings 161 to 164 is the power pad 21 (source pad) to which the first to fourth wires 71 to 74 are connected.

[0126] The first to third openings 161 to 163 are provided in a portion of the passivation film 160 that covers the first electrode region 151. The third openings 163 (three in the second embodiment) are arranged closer to the first element side surface 20A in the X direction than the first openings 161 (four in the second embodiment) and the second openings 162 (four in the second embodiment). The third openings 163 are aligned in the Y direction at an end of the first electrode region 151 that is closer to the first element side surface 20A.

[0127] Two of the multiple first openings 161 are arranged closer to the third element side surface 20C than the center of the first electrode region 151 in the Y direction. These two first openings 161 are arranged at a distance from each other in the X direction. The remaining two first openings 161 of the multiple first openings 161 are arranged closer to the control circuit region 140 than the center of the first electrode region 151 in the Y direction. These remaining two first openings 161 are arranged adjacent to each other in the X direction.

[0128] The multiple second openings 162 are arranged closer to the second element side surface 20B in the X direction than the multiple first openings 161. Two of the multiple second openings 162 are arranged closer to the third element side surface 20C than the center of the first electrode region 151 in the Y direction. These two second openings 162 are arranged at a distance from each other in the X direction. The remaining two second openings 162 of the multiple second openings 162 are arranged closer to the control circuit region 140 than the center of the first electrode region 151 in the Y direction. These remaining two second openings 162 are arranged adjacent to each other in the X direction.

[0129] The multiple fourth openings 164 are provided in both the portion of the passivation film 160 that covers the first electrode region 151 and the portion that covers the second electrode region 152. The multiple fourth openings 164 are arranged at the same position in the X direction and spaced apart from each other in the Y direction. Of the multiple fourth openings 164, two fourth openings 164 closer to the third element side surface 20C are provided in the portion of the passivation film 160 that covers the first electrode region 151. The remaining three fourth openings 164 are provided in the portion of the passivation film 160 that covers the second electrode region 152.

[0130] 13 and 15, a plurality of first wires 71 (four in the second embodiment) are individually connected to the power pads 21 (source pads) exposed from the plurality of first openings 161. The plurality of first wires 71 are connected to the first power leads 32A (see FIG. 11). Each of the first wires 71 includes a first electrode connection portion 71A. As in the first embodiment, the first electrode connection portion 71A forms a ball bond. The plurality of first electrode connection portions 71A are arranged at a distance from each other in the Y direction.

[0131] A plurality of second wires 72 (four in the second embodiment) are individually connected to the power pads 21 (source pads) exposed from the plurality of second openings 162. The plurality of second wires 72 are connected to second power leads 32B (see FIG. 11 ). Each second wire 72 includes a second electrode connection portion 72A formed by ball bonding, as in the first embodiment.

[0132] Two of the second electrode connecting portions 72A are arranged closer to the third element side surface 20C in the Y direction than the center of the first electrode region 151. The remaining two second electrode connecting portions 72A are arranged closer to the control circuit region 140 in the Y direction than the center of the first electrode region 151.

[0133] A plurality of third wires 73 (three in the second embodiment) are individually connected to the power pads 21 (source pads) exposed from the plurality of third openings 163. The plurality of third wires 73 are connected to third power leads 32C (see FIG. 11 ). Each third wire 73 includes a third electrode connection portion 73A formed by ball bonding, as in the first embodiment.

[0134] One of the multiple third electrode connection portions 73A is disposed closer to the third element side surface 20C in the Y direction than the center of the first electrode region 151. The remaining third electrode connection portion 73A is disposed in the center of the first electrode region 151 in the Y direction. The remaining third electrode connection portion 73A is disposed closer to the control circuit region 140 than the center of the first electrode region 151 in the Y direction.

[0135] A plurality of fourth wires 74 (five in the second embodiment) are individually connected to the power pads 21 (source pads) exposed from the plurality of fourth openings 164. The plurality of fourth wires 74 are connected to the fourth power leads 32D (see FIG. 11 ). Each fourth wire 74 includes a fourth electrode connection portion 74A formed by ball bonding, as in the first embodiment.

[0136] The multiple fourth electrode connection portions 74A are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. Of the multiple fourth electrode connection portions 74A, three fourth electrode connection portions 74A are arranged in the second electrode region 152, and the remaining two fourth electrode connection portions 74A are arranged in the first electrode region 151. These two fourth electrode connection portions 74A are arranged at one of both end portions in the X direction of the first electrode region 151 that is closer to the second element side surface 20B.

[0137] 14, the regions where heat is dissipated from the source electrode 23 by the first to fourth wires 71 to 74 are shown as heat dissipation regions 90A to 90D indicated by two-dot chain lines. The heat dissipation regions 90A to 90D by the first to fourth wires 71 to 74 are shown as, for example, rectangular regions centered on the first to fourth electrode connection portions 71A to 74A, respectively. In one example, the heat dissipation regions 90A to 90D are all the same size.

[0138] A plurality of heat dissipation regions 90A corresponding to the first wires 71 are provided so as to surround each of the plurality of first electrode connection portions 71A in a plan view. Heat dissipation regions 90A adjacent to each other in the Y direction partially overlap each other when viewed from the Y direction, for example.

[0139] A plurality of heat dissipation regions 90B corresponding to the second wires 72 are provided so as to surround each of the plurality of second electrode connecting portions 72A in a plan view. The heat dissipation regions 90B corresponding to the two second electrode connecting portions 72A closer to the control circuit region 140 partially overlap each other when viewed from the X direction.

[0140] A plurality of heat dissipation regions 90C corresponding to the third wires 73 are provided so as to surround each of the plurality of third electrode connection portions 73A in a plan view. A plurality of heat dissipation regions 90D corresponding to the fourth wires 74 are provided so as to surround each of the plurality of fourth electrode connection portions 74A in a plan view. Therefore, the plurality of heat dissipation regions 90D are arranged in the Y direction.

[0141] As described above, in the first electrode region 151, the first electrode connection portion 71A of the first wire 71 and the second electrode connection portion 72A of the second wire 72 are positioned offset from the center of the first electrode region 151 in the Y direction. Therefore, the first electrode region 151 includes a non-heat dissipation region 91A where the heat dissipation region 90A is not located. The non-heat dissipation region 91A is a region where the temperature of the source electrode 150 is more likely to be higher than that of the heat dissipation region 90A. Multiple non-heat dissipation regions 91A (two in the second embodiment) are provided. Here, a fifth opening 165 is formed in each of the multiple non-heat dissipation regions 91A. That is, the multiple non-heat dissipation regions 91A include a power pad 21 (source pad) where the source electrode 150 is exposed from the passivation film 160. A first heat dissipation body 81 is disposed in each non-heat dissipation region 91A. The configuration of the first heat dissipation body 81 is the same as in the first embodiment.

[0142] As shown in FIG. 15 , one of the multiple first heat sinks 81 is arranged in a direction along the extension of the first wire 71 relative to the first electrode connection portion 71A in a plan view. More specifically, the first heat sink 81 arranged adjacent to the first electrode connection portion 71A closer to the third element side surface 20C is arranged in a position overlapping the first wire 71 in a plan view. Furthermore, the first heat sink 81 arranged adjacent to the first electrode connection portion 71A closer to the fourth element side surface 20D is arranged in a position where the first wire 71 cannot be formed to connect to the first power lead 32A (see FIG. 11 ). In this way, the non-heat sink region 91A (see FIG. 14 ) is a position where the first wire 71 cannot be formed, and the first heat sink 81 is formed in place of the first wire 71.

[0143] As shown in FIG. 14 , four of the heat dissipation regions 90B are positioned offset in the Y direction from the center of the first electrode region 151 in the Y direction. Therefore, the first electrode region 151 includes non-heat dissipation regions 91B where no heat dissipation regions 90B are located. Multiple non-heat dissipation regions 91B (two in the second embodiment) are provided. Here, a fifth opening 165 is formed in each of the multiple non-heat dissipation regions 91B. That is, the multiple non-heat dissipation regions 91B include a power pad 21 (source pad) where the source electrode 150 is exposed from the passivation film 25. A second heat sink 82 is disposed in each non-heat dissipation region 91B, similar to the non-heat dissipation region 91A.

[0144] As shown in FIG. 15 , the second heat sink 82 is disposed in a direction parallel to the extension direction of the second wire 72 relative to the second electrode connection portion 72A in a plan view. Therefore, the second heat sink 82 disposed adjacent to the second electrode connection portion 72A and closer to the third element side surface 20C is disposed in a position overlapping the second wire 72 in a plan view. The second heat sink 82 disposed adjacent to the second electrode connection portion 72A and closer to the fourth element side surface 20D is disposed in a position where the second wire 72 connected to the second power lead 32B (see FIG. 11 ) cannot be formed at the position where the second heat sink 82 is disposed. Thus, the non-heat dissipation region 91B is a position where the second wire 72 cannot be formed, and the second heat sink 82 is formed in place of the second wire 72. The arrangement of the first to fourth power leads 32A to 32D (see FIG. 11 ) is the same as in the first embodiment.

[0145] [Effects] The semiconductor device 10 of the second embodiment has the following effects. (2-1) The semiconductor device 10 includes a semiconductor element 20 including an element front surface 20S, an element back surface 20R facing the opposite side to the element front surface 20S, and a source electrode 150 formed on the element front surface 20S, a die pad 31 supporting the semiconductor element 20, first to fourth power leads 32A to 32D arranged around the die pad 31, and a plurality of first to fourth wires 71 to 74 connecting the source electrode 150 to the first to fourth power leads 32A to 32D. The element front surface 20S includes an active region 130 in which a power transistor is formed, and a control circuit region 140 in which a control circuit 110 that controls the power transistor is formed. The active region 130 is formed to surround the control circuit region 140 from one side in the Y direction and one side in the X direction. The source electrode 150 is disposed on the active region 130 at a position different from the control circuit region 140, and is formed so as to surround the control circuit region 140 from one side in the Y direction and one side in the X direction in a plan view.

[0146] According to this configuration, compared to a configuration in which the source electrode 150 and the control circuit region 140 are adjacent to each other on only one side in the Y direction, for example, the number of heat dissipation paths from the source electrode 150 to the control circuit region 140 is increased. This facilitates heat dissipation from the source electrode 150 to the control circuit region 140. Therefore, it is possible to avoid the occurrence of avalanche breakdown, thereby improving the avalanche resistance (active clamp resistance) of the semiconductor device 10.

[0147] (2-2) The source electrode 150 includes a first electrode region 151 arranged in a position adjacent to the control circuit region 140 in the Y direction in a plan view, and a second electrode region 152 arranged in a position adjacent to the control circuit region 140 in the X direction in a plan view. The semiconductor device 10 includes, as the multiple power leads, a first power lead 32A and a second power lead 32B located in a region opposite the control circuit region 140 with respect to the source electrode 150 in the Y direction and arranged spaced apart in the X direction, and a third power lead 32C and a fourth power lead 32D arranged separately in regions on both sides of the source electrode 150 in the X direction. The multiple wires include multiple first wires 71 connecting the first electrode region 151 and the first power lead 32A, multiple second wires 72 connecting the first electrode region 151 and the second power lead 32B, multiple third wires 73 connecting the first electrode region 151 and the third power lead 32C, and multiple fourth wires 74 connecting the second electrode region 152 and the fourth power lead 32D.

[0148] According to this configuration, a plurality of first to fourth wires 71 to 74 are connected to each of the first electrode region 151 and the second electrode region 152 of the source electrode 150. Therefore, heat from the source electrode 150 is transferred to the first to fourth power leads 32A to 32D via these first to fourth wires 71 to 74. This makes it easier for the source electrode 150 to dissipate heat, thereby improving the avalanche resistance (active clamp resistance) of the semiconductor device 10.

[0149] (2-3) The first wires 71 are arranged spaced apart from one another in the X direction and offset from one another in the Y direction. The second wires 72 are arranged spaced apart from one another in the X direction and offset from one another in the Y direction.

[0150] With this configuration, compared to a configuration in which a plurality of first wires 71 and a plurality of second wires 72 are arranged in a row along the X direction in the first electrode region 151, it is possible to increase the number of first wires 71 and second wires 72 arranged in the first electrode region 151. Therefore, the first wires 71 and the second wires 72 make it easier for the source electrode 150 to dissipate heat.

[0151] (2-4) Each of the plurality of first wires 71 includes a first electrode connection portion 71A connected to the source electrode 150. Each of the plurality of second wires 72 includes a second electrode connection portion 72A connected to the source electrode 150. The semiconductor device 10 further includes a first heat sink 81 arranged in a direction along the extension direction of the first wires 71 relative to the first electrode connection portion 71A in a plan view, and a second heat sink 82 arranged in a direction along the extension direction of the second wires 72 relative to the second electrode connection portion 72A in a plan view.

[0152] According to this configuration, the first heat sink 81 is disposed in a region of the first electrode region 151 where the first wires 71 cannot be disposed. The second heat sink 82 is disposed in a region of the first electrode region 151 where the second wires 72 cannot be disposed. Therefore, the first heat sink 81 and the second heat sink 82 can further improve the heat dissipation performance of the first electrode region 151 while maintaining the maximum number of first wires 71 and second wires 72 that can be disposed in the first electrode region 151.

[0153] <Modifications> The above-described embodiments can be modified as follows: The following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0154] In each embodiment, the shape of the active region 40, 130 in a plan view can be changed as desired. For example, in the first embodiment, the width dimension WA1 of the first transistor region 41 may be equal to or smaller than the width dimension WA2 of the second transistor region 42. The width dimension WA1 of the first transistor region 41 may be equal to or smaller than the width dimension WA3 of the third transistor region 43. The width dimension WA2 of the second transistor region 42 may be different from the width dimension WA3 of the third transistor region 43. For example, the width dimension WA3 of the third transistor region 43 may be larger than the width dimension WA2 of the second transistor region 42. For example, the width dimension WA3 of the third transistor region 43 may be smaller than the width dimension WA2 of the second transistor region 42. The first to third electrode regions 23A to 23C of the source electrode 23 may be changed in accordance with these changes to the active region 40. For example, the width dimension WB2 of the second electrode region 23B may be different from the width dimension WB3 of the third electrode region 23C.

[0155] Furthermore, in the second embodiment, the width dimension WC1 of the first transistor region 131 may be different from, for example, the width dimension WC2 of the second transistor region 132. In one example, the width dimension WC1 of the first transistor region 131 may be larger than the width dimension WC2 of the second transistor region 132. In one example, the width dimension WC1 of the first transistor region 131 may be smaller than the width dimension WC2 of the second transistor region 132. The first electrode region 151 and the second electrode region 152 of the source electrode 150 may be changed in accordance with these changes in the active region 130. In one example, the width dimension WD1 of the first electrode region 151 may be different from the width dimension WD2 of the second electrode region 152.

[0156] In each embodiment, the relationship between the dimensions of the source electrodes 23, 150 and the dimensions of the control circuit regions 50, 140 in a plan view can be changed as desired. For example, the length dimension LB2 of the second electrode region 23B of the source electrode 23 may be shorter than the dimension of the control circuit region 50 in the Y direction. For example, the length dimension LB3 of the third electrode region 23C of the source electrode 23 may be shorter than the dimension of the control circuit region 50 in the Y direction. For example, the length dimension LD2 of the second electrode region 152 of the source electrode 150 may be shorter than the dimension of the control circuit region 140 in the Y direction.

[0157] In each embodiment, the relationship between the size of the active region 40, 130 and the size of the source electrode 23, 150 in a plan view can be changed as desired. In one example, the source electrode 23, 150 may be slightly smaller than the active region 40, 130 in a plan view. In another example, the source electrode 23, 150 may be slightly larger than the active region 40, 130 in a plan view.

[0158] In each embodiment, the positions of the first to fourth wires 71 to 74 relative to the source electrodes 23, 150 can be changed as desired. For example, in the second embodiment, as shown in Fig. 16, the fourth electrode connection portions 74A of the multiple fourth wires 74 adjacent in the Y direction may be shifted from each other in the X direction. In this case, a non-heat dissipation region 91C is formed in the second electrode region 152 of the source electrode 150. A heat sink 83 is provided in the non-heat dissipation region 91C.

[0159] In each embodiment, the first heat sink 81 and the second heat sink 82 are not limited to ball bonding and can be arbitrarily modified. In one example, the first heat sink 81 and the second heat sink 82 may be formed by joining pillars to the source electrodes 23, 150. In this case, the pillars may be formed of a metal material or a material with excellent heat dissipation properties. Examples of metal materials include a material containing at least one of Cu, Al, Fe, Ni, and Ti. Examples of materials with excellent heat dissipation properties include ceramic. In other words, the first heat sink 81 and the second heat sink 82 are not limited to a metal material and may be formed of an insulating material. In this way, the first heat sink 81 and the second heat sink 82 may have shapes different from the first to fourth electrode connection portions 71A to 74A of the first to fourth wires 71 to 74.

[0160] Furthermore, the first heat dissipation body 81 and the second heat dissipation body 82 may be formed from a material different from that of the first to fourth wires 71 to 74. According to this configuration, the first heat dissipation body 81 and the second heat dissipation body 82 can be formed from a material that has better heat dissipation properties than the material of the first to fourth wires 71 to 74. This makes it possible to improve the heat dissipation performance in the non-heat dissipation areas 91A and 91B.

[0161] In each embodiment, at least one of the plurality of first heat sinks 81 may be omitted. In each embodiment, at least one of the plurality of second heat sinks 82 may be omitted. In each embodiment, the drain electrode 24 formed on the element rear surface 20R of the semiconductor element 20 may be formed partially on the element rear surface 20R.

[0162] In each embodiment, the configuration of the semiconductor element 20 can be changed as desired. In one example, both the source electrode 23 (150) and the drain electrode 24 may be formed on the element surface 20S of the semiconductor element 20.

[0163] In each embodiment, the die pad 31 of the lead frame 30 may be entirely covered with the sealing resin 60. In other words, the die pad 31 does not have to be exposed from the sealing resin 60.

[0164] In each embodiment, the sealing resin 60 may be omitted from the semiconductor device 10. One or more of the various examples described in this specification may be combined to the extent that no technical contradiction occurs.

[0165] The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0166] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described herein being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0167] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each supplementary note are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0168] [Appendix A1] A semiconductor element (20) including an element surface (20S), an element back surface (20R) facing the opposite side to the element surface (20S), and a surface electrode (23) formed on the element surface (20S); a die pad (31) supporting the semiconductor element (20); a plurality of leads (32A-32D) arranged around the die pad (31); and a plurality of wires (71-74) connecting the surface electrode (23) and the plurality of leads (32A-32D), wherein the element surface (20S) includes: an active region (40) in which a power transistor is formed; and a control circuit region (50) in which a control circuit (110) for controlling the power transistor is formed, wherein two directions orthogonal to each other in a direction orthogonal to a thickness direction (Z direction) of the semiconductor element (20) are defined as a first direction (Y direction) and a second direction (X direction), respectively. The active region (40) is formed so as to surround the control circuit region (50) from both sides in the second direction (X direction) and one side in the first direction (Y direction), and the surface electrode (23) is arranged on the active region (40) at a position different from that of the control circuit region (50), and is formed so as to surround the control circuit region (50) from both sides in the second direction (X direction) and one side in the first direction (Y direction) when viewed from the thickness direction (Z direction).

[0169] [Appendix A2] The surface electrode (23) includes: a first electrode region (23A) arranged in a position adjacent to the control circuit region (50) in the first direction (Y direction) when viewed from the thickness direction (Z direction); and a second electrode region (23B) and a third electrode region (23C) arranged separately on both sides of the control circuit region (50) in the second direction (X direction) when viewed from the thickness direction (Z direction); and the plurality of leads (32A to 32D) include: a first lead (32A) and a second lead (32B) located in a region on the opposite side of the control circuit region (50) with respect to the surface electrode (23) in the first direction (Y direction) and arranged at a distance in the second direction (X direction); and a third lead (32C) arranged in a region close to the second electrode region (23B) among regions on both sides of the surface electrode (23) in the second direction (X direction); and a fourth lead (32D) arranged in a region close to the third electrode region (23C) among regions on both sides of the surface electrode (23) in the second direction (X direction), wherein the plurality of wires (71 to 74) include: a plurality of first wires (71) connecting the first electrode region (23A) and the first lead (32A); a plurality of second wires (72) connecting the first electrode region (23A) and the second lead (32B); a plurality of third wires (73) connecting the second electrode region (23B) and the third lead (32C); and a plurality of fourth wires (74) connecting the third electrode region (23C) and the fourth lead (32D).

[0170] [Appendix A3] The semiconductor device according to Appendix A2, wherein a width dimension (WB1) of the first electrode region (23A) is larger than a width dimension (WB2) of the second electrode region (23B) and a width dimension (WB3) of the third electrode region (23C), the plurality of first wires (71) are arranged spaced apart from one another in the second direction (X direction) while being shifted in the first direction (Y direction), and the plurality of second wires (72) are arranged spaced apart from one another in the second direction (X direction) while being shifted in the first direction (Y direction).

[0171] [Appendix A4] The semiconductor device according to Appendix A3, further comprising a plurality of heat sinks (81, 82) joined to the surface electrode (23), the heat sinks (81, 82) being arranged in the first electrode region (23A).

[0172] [Appendix A5] The semiconductor device according to Appendix A4, wherein the heat sink includes: a first heat sink (81) arranged closer to the second electrode region (23B) than the center of the first electrode region (23A) in the second direction (X direction); and a second heat sink (82) arranged closer to the third electrode region (23C) than the center of the first electrode region (23A) in the second direction (X direction).

[0173] [Appendix A6] The semiconductor device according to Appendix A5, wherein each of the plurality of first wires (71) includes a first electrode connection portion (71A), and the first heat sink (81) is arranged in a direction along the extension direction of the first wires (71) relative to the first electrode connection portion (71A) when viewed from the thickness direction (Z direction) of the semiconductor element (20).

[0174] [Appendix A7] The semiconductor device described in Appendix A5 or A6, wherein each of the plurality of second wires (72) includes a second electrode connection portion (72A), and the second heat sink (82) is arranged in a direction along the extension direction of the second wires (72) relative to the second electrode connection portion (72A) when viewed from the thickness direction (Z direction) of the semiconductor element (20).

[0175] [Appendix A8] A semiconductor element (20) including an element front surface (20S), an element back surface (20R) facing the opposite side to the element front surface (20S), and a front surface electrode (23) formed on the element front surface (20S); a die pad (31) supporting the semiconductor element (20); a plurality of leads (32A-32D) arranged around the die pad (31); and a plurality of wires (71-74) connecting the front surface electrode (23) and the plurality of leads (32A-32D), wherein the element front surface (20S) includes: an active region (130) in which a power transistor is formed; and a control circuit region (140) in which a control circuit (110) for controlling the power transistor is formed, wherein two directions orthogonal to each other in a direction orthogonal to a thickness direction (Z direction) of the semiconductor element (20) are defined as a first direction (Y direction) and a second direction (X direction), respectively. The semiconductor device (10) is configured such that the active region (130) surrounds the control circuit region (140) from one side in the first direction (Y direction) and one side in the second direction (X direction), and the surface electrode (150) is disposed on the active region (130) at a position different from that of the control circuit region (140), and is configured such that the surface electrode (150) surrounds the control circuit region (140) from one side in the first direction (Y direction) and one side in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0176] [Appendix A9] The surface electrode (150) includes: a first electrode region (151) arranged in a position adjacent to the control circuit region (140) in the first direction (Y direction) when viewed from the thickness direction (Z direction); and a second electrode region (152) arranged in a position adjacent to the control circuit region (140) in the second direction (X direction) when viewed from the thickness direction (Z direction); the multiple leads (32A to 32D) include: a first lead (32A) and a second lead (32B) located in a region on the opposite side of the surface electrode (150) from the control circuit region (140) in the first direction (Y direction) and arranged at a distance in the second direction (X direction); and a third lead (32C) and a fourth lead (32D) arranged separately in regions on both sides of the surface electrode (150) in the second direction (X direction); and the multiple wires (71 to 74) include: The semiconductor device according to Appendix A8, comprising: a plurality of first wires (71) connecting the first electrode region (151) and the first lead (32A); a plurality of second wires (72) connecting the first electrode region (151) and the second lead (32B); a plurality of third wires (73) connecting the first electrode region (151) and the third lead (32C); and a plurality of fourth wires (74) connecting the second electrode region (152) and the fourth lead (32D).

[0177] [Appendix A10] The semiconductor device according to Appendix A9, wherein the plurality of first wires (71) are arranged spaced apart from one another in the second direction (X direction) while being offset in the first direction (Y direction), and the plurality of second wires (72) are arranged spaced apart from one another in the second direction (X direction) while being offset in the first direction (Y direction).

[0178] [Appendix A11] The semiconductor device according to Appendix A10, further comprising: each of the plurality of first wires (71) includes a first electrode connection portion (71A) connected to the surface electrode (150); each of the plurality of second wires (72) includes a second electrode connection portion (72A) connected to the surface electrode (150); a first heat sink (81) arranged in a direction along the extension direction of the first wires (71) with respect to the first electrode connection portion (71A) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and a second heat sink (82) arranged in a direction along the extension direction of the second wires (72) with respect to the second electrode connection portion (72A) when viewed from the thickness direction (Z direction) of the semiconductor element (20).

[0179] [Appendix A12] The semiconductor device according to appendix A1 or A8, wherein the plurality of wires (71-74) include electrode connection portions (71A-74A) connected to the surface electrodes (23 / 150), and a heat sink (81, 82) is joined onto the surface electrodes (23 / 150), and the heat sink (81, 82) is disposed spaced apart from the electrode connection portions (71A-74A) of the plurality of wires (71-74).

[0180] [Appendix A13] The semiconductor device according to Appendix A12, wherein the heat sinks (81, 82) are arranged at positions adjacent to the electrode connection portions (71A, 72A) of the plurality of wires (71 to 74).

[0181] [Appendix A14] The semiconductor device according to Appendix A12, wherein the heat sinks (81, 82) are formed from the same material as the wires (71 to 74).

[0182] [Appendix A15] The semiconductor device according to Appendix A14, wherein the heat sink (81, 82) contains Cu.

[0183] [Appendix A16] The semiconductor device according to Appendix A15, wherein the heat sinks (81, 82) have the same shape as the electrode connecting portions (71A, 72A).

[0184] [Appendix A17] The semiconductor device according to any one of Appendices A1 to A16, wherein the semiconductor element (20) includes a source electrode (23 / 150) as the surface electrode formed on the element surface (20S) and a drain electrode (24) formed on the element back surface (20R).

[0185] [Appendix A18] The semiconductor device according to Appendix A17, wherein the drain electrode (24) is formed over the entire rear surface (20R) of the element.

[0186] [Appendix A19] The semiconductor device according to any one of Appendices A1 to A18, further comprising a sealing resin (60) that seals the semiconductor element (20) and the plurality of wires (71 to 78).

[0187] [Appendix A20] The semiconductor device according to Appendix A19, wherein the sealing resin (60) has a sealing surface (61) facing the same side as the element surface (20S) and a sealing back surface (62) facing the opposite side to the sealing surface (61), and the die pad (31) is exposed from the sealing back surface (62).

[0188] [Appendix A21] The semiconductor device according to any one of Appendices A2 to A7, wherein the second electrode region (23B) surrounds the entire control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0189] [Appendix A22] The semiconductor device according to any one of Appendices A2 to A7, wherein the third electrode region (23C) surrounds the entire control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0190] [Appendix A23] The semiconductor device according to any one of Appendices A2 to A7, wherein a width dimension (WB2) of the second electrode region (23B) is equal to a width dimension (WB3) of the third electrode region (23C).

[0191] [Appendix A24] The semiconductor device according to any one of Appendices A9 to A11, wherein the second electrode region (152) surrounds the entire control circuit region (140) in the first direction (Y direction) when viewed from the second direction (X direction).

[0192] [Appendix A25] The semiconductor device according to appendix A12 or A13, wherein the heat sinks (81, 82) are formed of a material different from that of the wires (71 to 78).

[0193] [Appendix B1] A semiconductor element (20) including: an element surface (20S) including an active region (40) in which a power transistor is formed; and a control circuit region (50) in which a control circuit (110) that controls the power transistor is formed; and a surface electrode (23) arranged on the active region (40) at a position different from the control circuit region (50), wherein two directions that are orthogonal to each other in a direction along the element surface (20S) are defined as a first direction (Y direction) and a second direction (X direction), respectively; the active region (40) is formed to surround the control circuit region (50) from both sides in the second direction (X direction) and one side in the first direction (Y direction); and the surface electrode (23) is formed to surround the control circuit region (50) from both sides in the second direction (X direction) and one side in the first direction (Y direction).

[0194] [Appendix B2] The semiconductor element described in Appendix B1, wherein the surface electrode (23) includes: a first electrode region (23A) arranged in a position adjacent to the control circuit region (50) in the first direction (Y direction) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and a second electrode region (23B) and a third electrode region (23C) arranged separately on both sides of the control circuit region (50) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0195] [Appendix B3] The semiconductor element according to Appendix B2, wherein the second electrode region (23B) entirely surrounds the control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0196] [Appendix B4] The semiconductor element according to Appendix B2 or B3, wherein the third electrode region (23C) surrounds the entire control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0197] [Appendix B5] The semiconductor element according to any one of Appendices B1 to B4, wherein the active region (40) includes: a first transistor region (41) arranged adjacent to the control circuit region (50) in the first direction (Y direction) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and a second transistor region (42) and a third transistor region (43) arranged separately on both sides of the control circuit region (50) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0198] [Appendix B6] The semiconductor element according to Appendix B5, wherein the second transistor region (42) entirely surrounds the control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0199] [Appendix B7] The semiconductor element according to Appendix B5 or B6, wherein the third transistor region (43) entirely surrounds the control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0200] [Appendix C1] A semiconductor element (20) including: an element surface (20S) including an active region (130) in which a power transistor is formed; and a control circuit region (140) in which a control circuit (110) that controls the power transistor is formed; and a surface electrode (150) arranged on the active region (130) at a position different from the control circuit region (140), wherein two directions that are orthogonal to each other in a direction along the element surface (20S) are defined as a first direction (Y direction) and a second direction (X direction), respectively; the active region (130) is formed to surround the control circuit region (140) from both sides in the second direction (X direction) and one side in the first direction (Y direction); and the surface electrode (150) is formed to surround the control circuit region (140) from one side in the second direction (X direction) and one side in the first direction (Y direction).

[0201] [Appendix C2] The semiconductor element described in Appendix C1, wherein the surface electrode (150) includes: a first electrode region (151) arranged in a position adjacent to the control circuit region (140) in the first direction (Y direction) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and a second electrode region (152) arranged in a position adjacent to the control circuit region (140) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0202] [Appendix C3] The semiconductor element according to Appendix C2, wherein the second electrode region (152) entirely surrounds the control circuit region (140) in the first direction (Y direction) when viewed from the second direction (X direction).

[0203] [Appendix C4] The semiconductor element according to any one of Appendices C1 to C3, wherein the active region (130) includes: a first transistor region (131) arranged adjacent to the control circuit region (140) in the first direction (Y direction) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and a second transistor region (132) arranged adjacent to the control circuit region (140) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0204] [Appendix C5] The semiconductor element according to Appendix C4, wherein the second transistor region (132) entirely surrounds the control circuit region (140) in the first direction (Y direction) when viewed from the second direction (X direction).

[0205] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0206] DESCRIPTION OF SYMBOLS 10...Semiconductor device 20...Semiconductor element 20S...Element surface 20R...Element back surface 20A to 20D...First to fourth element side surfaces 21...Power pad 22...Control pad 23...Source electrode 23A...First electrode region 23AA...Slit 23B...Second electrode region 23C...Third electrode region 24...Drain electrode 25...Passivation film 25A to 25E...First to fifth openings 30...Lead frame 31...Die pad 31S...Die pad surface 31R...Die pad back surface 32A to 32D...First to fourth power leads 33A to 33D...First to fourth control leads 40...Active region 41...First transistor region 42...Second transistor region 43...Third transistor region 44...Slit 50...Control circuit region 51 to 53...First to third sides 54...Internal pad 54A...First internal pad 54B...Second internal pad 60...Sealing resin 61...Sealing surface 62...Sealing back surface 63-64...First to fourth sealing side surfaces 71-78...First to eighth wires 71A-74A...First to fourth electrode connection portions 81...First heat sink 82...Second heat sink 83...Heat sink 90A-90D...Heat sink area 91A-91C...Non-heat sink area 100...Switching circuit 110...Control circuit 111...Current sensor circuit 112...Temperature sensor circuit 113...Overcurrent protection circuit 114...Overheat protection circuit 115...Low voltage malfunction prevention circuit 116...Input terminal 117...Input side ground terminal 118...Output terminal 119...Output side ground terminal 121...Input wiring 122...Ground wiring 200...Series circuit 201...Power supply 202...Inductive load 130...Active area 131...First transistor area 132...Second transistor area 133...Slit 140...Control circuit area 141-143...First to third sides 150...Source electrode 151...First electrode area 152...Second electrode area 153...Slit 160...Passivation film 161-163...First to third openings D1,D2...Diode R1 to R4...First to fourth resistors L...Coil Sw...Switch WA1...Width dimension of first transistor region WA2...Width dimension of second transistor region WA3...Width dimension of third transistor region LA1...Length dimension of first transistor region LA2...Length dimension of second transistor region LA3...Length dimension of third transistor region WB1...Width dimension of first electrode region WB2...Width dimension of second electrode region WB3...Width dimension of third electrode region LB1...Length dimension of first electrode region LB2...Length dimension of second electrode region LB3...Length dimension of third electrode region WC1...Width dimension of first transistor region WC2...Width dimension of second transistor region LC1...Length dimension of first transistor region LC2...Length dimension of second transistor region WD1...Width dimension of first electrode region WD2...Width dimension of second electrode region LD1...Length dimension of first electrode region LD2...Length dimension of second electrode region

Claims

1. A semiconductor device comprising: a semiconductor element including a front surface, a back surface of an element facing the opposite side to the front surface of the element, and a front surface electrode formed on the front surface of the element; a die pad supporting the semiconductor element; a plurality of leads arranged around the die pad; and a plurality of wires connecting the front electrode and the plurality of leads, wherein the front surface of the element includes an active region in which a power transistor is formed, and a control circuit region in which a control circuit for controlling the power transistor is formed, wherein two directions perpendicular to a thickness direction of the semiconductor element are defined as a first direction and a second direction, respectively, and the active region is formed to surround the control circuit region from both sides in the second direction and one side in the first direction, and the front surface electrode is disposed on the active region at a position different from the control circuit region, and is formed to surround the control circuit region from both sides in the second direction and one side in the first direction when viewed from the thickness direction.

2. The semiconductor device according to claim 1, wherein the surface electrode includes a first electrode region arranged adjacent to the control circuit region in the first direction when viewed from the thickness direction, and a second electrode region and a third electrode region arranged separately on both sides of the control circuit region in the second direction when viewed from the thickness direction; the multiple leads include a first lead and a second lead located in a region opposite the control circuit region with respect to the surface electrode in the first direction and arranged at a distance in the second direction, a third lead arranged in a region close to the second electrode region among the regions on both sides of the surface electrode in the second direction, and a fourth lead arranged in a region close to the third electrode region among the regions on both sides of the surface electrode in the second direction; and the multiple wires include a multiple first wires connecting the first electrode region and the first lead, a multiple second wires connecting the first electrode region and the second lead, a multiple third wires connecting the second electrode region and the third lead, and a multiple fourth wires connecting the third electrode region and the fourth lead.

3. The semiconductor device described in claim 2, wherein a width dimension of the first electrode region is larger than a width dimension of the second electrode region and a width dimension of the third electrode region, the plurality of first wires are arranged spaced apart from one another in the second direction while being shifted in the first direction, and the plurality of second wires are arranged spaced apart from one another in the second direction while being shifted in the first direction.

4. The semiconductor device according to claim 3, further comprising a plurality of heat sinks joined to said surface electrode, said heat sinks being disposed in said first electrode region.

5. The semiconductor device according to claim 4, wherein the heat sink includes: a first heat sink arranged closer to the second electrode region than the center of the first electrode region in the second direction; and a second heat sink arranged closer to the third electrode region than the center of the first electrode region in the second direction.

6. The semiconductor device according to claim 5, wherein each of the plurality of first wires includes a first electrode connection portion, and the first heat sink is arranged in a direction along which the first wires extend relative to the first electrode connection portion when viewed in the thickness direction of the semiconductor element.

7. A semiconductor device as described in claim 5 or 6, wherein each of the plurality of second wires includes a second electrode connection portion, and the second heat sink is arranged in a direction along the extension direction of the second wire relative to the second electrode connection portion when viewed from the thickness direction of the semiconductor element.

8. A semiconductor device comprising: a semiconductor element including a surface, a back surface of an element facing opposite to the surface of the element, and a surface electrode formed on the surface of the element; a die pad supporting the semiconductor element; a plurality of leads arranged around the die pad; and a plurality of wires connecting the surface electrode and the plurality of leads, wherein the surface of the element includes an active region in which a power transistor is formed, and a control circuit region in which a control circuit for controlling the power transistor is formed, wherein two directions perpendicular to a thickness direction of the semiconductor element are defined as a first direction and a second direction, respectively, and the active region is formed to surround the control circuit region from one side in the first direction and one side in the second direction, and the surface electrode is disposed on the active region at a position different from the control circuit region, and is formed to surround the control circuit region from one side in the first direction and one side in the second direction when viewed from the thickness direction.

9. The semiconductor device according to claim 8, wherein the surface electrode includes: a first electrode region arranged in a position adjacent to the control circuit region in the first direction when viewed from the thickness direction; and a second electrode region arranged in a position adjacent to the control circuit region in the second direction when viewed from the thickness direction; the multiple leads include: a first lead and a second lead located in a region on the opposite side of the surface electrode from the control circuit region in the first direction and arranged at a distance in the second direction; and a third lead and a fourth lead arranged separately in regions on both sides of the surface electrode in the second direction; and the multiple wires include: a multiple first wires connecting the first electrode region and the first lead, a multiple second wires connecting the first electrode region and the second lead, a multiple third wires connecting the first electrode region and the third lead, and a multiple fourth wires connecting the second electrode region and the fourth lead.

10. The semiconductor device according to claim 9, wherein the plurality of first wires are arranged spaced apart from one another in the second direction while being offset in the first direction, and the plurality of second wires are arranged spaced apart from one another in the second direction while being offset in the first direction.

11. The semiconductor device described in claim 10, further comprising: each of the plurality of first wires includes a first electrode connection portion connected to the surface electrode; each of the plurality of second wires includes a second electrode connection portion connected to the surface electrode; a first heat sink arranged in a direction along the extension direction of the first wire relative to the first electrode connection portion when viewed from the thickness direction of the semiconductor element; and a second heat sink arranged in a direction along the extension direction of the second wire relative to the second electrode connection portion when viewed from the thickness direction of the semiconductor element.

12. The semiconductor device according to claim 1 or 8, wherein the plurality of wires include electrode connection portions connected to the surface electrode, a heat sink is joined onto the surface electrode, and the heat sink is positioned away from the electrode connection portions of the plurality of wires.

13. The semiconductor device according to claim 12, wherein the heat sink is disposed adjacent to the electrode connection portions of the plurality of wires.

14. The semiconductor device according to claim 12, wherein the heat sink is made of the same material as the wire.

15. The semiconductor device according to claim 14, wherein the heat sink contains Cu.

16. The semiconductor device according to claim 15, wherein the heat sink has the same shape as the electrode connection portion.

17. The semiconductor device according to any one of claims 1 to 16, wherein the semiconductor element includes a source electrode as the front surface electrode formed on the front surface of the element, and a drain electrode formed on the back surface of the element.

18. The semiconductor device according to claim 17, wherein the drain electrode is formed over the entire back surface of the element.

19. The semiconductor device according to any one of claims 1 to 18, further comprising a sealing resin that seals the semiconductor element and the plurality of wires.

20. The semiconductor device according to claim 19, wherein the sealing resin has a sealing surface facing the same side as the element surface and a sealing back surface facing the opposite side to the sealing surface, and the die pad is exposed from the sealing back surface.

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