Chip-on-wafer manufacturing method for micro LED display

Abstract

The present invention relates to a chip-on-wafer manufacturing method for a micro LED display, which can manufacture a high-quality high-brightness micro LED display chip of 3 ㎛ or less by forming an undoped semiconductor region to a desired thickness without damaging the chip, in manufacturing a lateral chip, a flip chip, and a vertical chip for a micro LED display by using a chip-on-wafer method.

Description

Method for manufacturing chip-on-wafer for micro LED display

[0001] The present invention relates to a method for manufacturing a chip-on-wafer for a micro LED display, and more particularly, to a method for manufacturing a chip-on-wafer for a micro LED display, which can manufacture a high-quality, high-brightness micro LED display chip of 3 ㎛ or less by forming an undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, uAlGaInN, uGaP, uInGaP, uAlGaP or uAlGaInP) to a desired thickness without damaging the chip, in manufacturing a lateral chip, a flip chip and a vertical chip for a micro LED display using a chip-on-wafer method.

[0002] In general, micro LED (including mini LED) displays can be divided into micro LED displays using PM (passive matrix) driving method and micro LED displays using AM (active matrix) driving method.

[0003] Here, a typical PM (passive matrix) driven micro LED display has a sapphire support substrate as the final substrate, sorted thick BGR (blue, green, red) chips (both LED anodes and cathodes are completed), and is transferred through a chip die-level process, and generally horizontal chips or flip chips can be used.

[0004] Additionally, micro LED displays driven by AM (active matrix) typically do not have a sapphire support substrate, so they have thin, unsorted BGR chips (both LED anodes and cathodes are completed) that are transferred through a wafer-level process, and generally horizontal chips, flip chips, or vertical chips can all be used.

[0005] Recently, there has been a growing demand for ever-smaller chips for the production of micro-level LED displays. To meet this market demand, currently manufactured micro-LED display chips are 5 to 7 μm thick. However, achieving a thickness of less than 5 μm is reportedly difficult due to issues such as chip breakage.

[0006] Meanwhile, the chip-on-wafer method refers to a method in which the entire process, from the process of epitaxially growing a semiconductor layer on the initial growth substrate to the final fab process, is performed on the initial growth wafer.

[0007] According to this conventional chip-on-wafer method, since the stacked structure of the chip is completed using only the initial growth substrate, the thickness of the undoped semiconductor region (uGaN) or n-type semiconductor region (nGaN) cannot be controlled, making it impossible to manufacture micro LEDs with a thickness of 5 μm or less. In addition, there is also a disadvantage in that the light extraction efficiency is lowered by such thick undoped semiconductor regions (e.g., uGaN, uInGaN, uAlGaN, uAlGaInN, uGaP, uInGaP, uAlGaP, or uAlGaInP).

[0008] Meanwhile, in the conventional chip-on-wafer method, the completed chip is attached to TFT Glass, an interposer, etc., and then the initial growth substrate on the opposite side is removed to expose an undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, uAlGaInN, uGaP, uInGaP, uAlGaP, or uAlGaInP). However, even if the undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, uAlGaInN, uGaP, uInGaP, uAlGaP, or uAlGaInP) is etched, there is a problem in that the completed chip is damaged by the high temperature generated during etching and the gas injected.

[0009] Furthermore, when the initial growth substrate is removed using the laser lift off (LLO) process, a large number of gallium (Ga) droplets (solid, powder) that interfere with the scattering of the generated light are generated on the surface of the semiconductor layer from which the initial growth substrate was removed. Currently, the gallium (Ga) droplets are removed using hydrochloric acid vapor or taping. However, when hydrochloric acid vapor is used, there are problems such as excessive process costs and the chip may be damaged during the gallium (Ga) droplet removal process. In addition, when taping is used, there is a problem that complete removal of the gallium (Ga) droplets is impossible. However, when the growth substrate for Si (a nitride that emits blue, green, and red) or GaAs (a phosphide that emits red) micro LED is removed using the chemical lift off (CLO) process, there is no issue with gallium (Ga) droplets.

[0010] Furthermore, since conventional chip-on-wafer methods use only the initial growth substrate to complete the chip's stacked structure, ohmic contact electrodes must be formed in a later (back-end) process. In this case, heat treatment at temperatures above 300°C is essential to form these ohmic contact electrodes, posing the problem of chips already stacked with multiple layers being damaged by the high temperatures.

[0011] The purpose of the present invention is to solve the above-described conventional problems, and to provide a method for manufacturing a chip-on-wafer for a micro LED display, which can manufacture a high-quality, high-brightness micro LED display chip of 3㎛ or less by forming an undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, uAlGaInN, uGaP, uInGaP, uAlGaP or uAlGaInP) to a desired thickness without damaging the chip, in manufacturing a lateral chip, a flip chip and a vertical chip for a micro LED display using a chip-on-wafer method.

[0012] The above object is achieved by a method for manufacturing a chip-on-wafer for a micro LED display according to the present invention, comprising: a growth step of epitaxy-growing a semiconductor layer on a growth substrate; an electrode formation step of forming an ohmic contact electrode on the semiconductor layer; a bonding step of bonding the ohmic contact electrode to a temporary substrate through an adhesive layer; an exposure step of removing the growth substrate to expose one surface of the semiconductor layer; a pattern formation step of forming a surface texture pattern on the exposed one surface of the semiconductor layer; a bonding step of bonding the exposed one surface of the semiconductor layer to a support substrate; and a removal step of removing the temporary substrate and the adhesive layer.

[0013] In addition, the present invention further includes a forming step of forming the semiconductor layer to a preset thickness by etching one surface of the exposed semiconductor layer, and the pattern forming step can form a surface roughness pattern on one surface of the semiconductor layer formed to a preset thickness.

[0014] In addition, in the growth step, a third semiconductor region, a second semiconductor region, an active region, and a first semiconductor region are sequentially epitaxially grown, and in the forming step, the exposed third semiconductor region is etched to form the semiconductor layer to a preset thickness, and the third semiconductor region may be an undoped semiconductor region.

[0015] In addition, the present invention further includes a reflective layer forming step of forming a reflective layer on one surface of the semiconductor layer on which a surface roughness pattern is formed, and the bonding step can bond one surface of the semiconductor layer on which the reflective layer is formed to the support substrate through the bonding layer.

[0016] Additionally, the reflective layer can be in ohmic contact with one surface of the semiconductor layer.

[0017] In addition, the above bonding step can bond one surface of the semiconductor layer on which a surface roughness pattern is formed through the bonding layer to a support substrate.

[0018] Additionally, the bonding layer can be in ohmic contact with one surface of the semiconductor layer.

[0019] In addition, the bonding step may form a separation layer on the support substrate and then bond one surface of the semiconductor layer to the separation layer.

[0020] In addition, the bonding step can form a separation layer on the temporary substrate and then bond the ohmic contact electrode to the separation layer through the bonding layer.

[0021] In addition, the bonding step can form a protective layer on the ohmic contact electrode and then bond the protective layer to the temporary substrate through the adhesive layer.

[0022] According to the present invention, in the manufacture of lateral chips, flip chips, and vertical chips for micro LED displays using a chip on wafer method, an undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, uAlGaInN, uGaP, uInGaP, uAlGaP, or uAlGaInP) can be formed to a desired thickness without damaging the chip, thereby manufacturing a high-quality, high-brightness micro LED display chip of 3㎛ or less, and the problem of gallium (Ga) droplets remaining on the surface of the semiconductor layer can be fundamentally prevented, so that light extraction efficiency can be significantly improved.

[0023] In addition, according to the present invention, after growing a semiconductor layer, an ohmic contact electrode is formed through high-temperature heat treatment in a state where other layers are not laminated, and then the remaining necessary layers, such as a reflective layer, are laminated on one side of the semiconductor layer, so that the problem of the laminated chip being damaged by high-temperature heat treatment during the formation of the ohmic contact electrode can be fundamentally prevented.

[0024] Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within a range obvious to those skilled in the art from the contents described below.

[0025] Figures 1 and 2 illustrate the overall process of manufacturing a chip-on-wafer according to the method for manufacturing a chip-on-wafer for a micro LED display of the present invention.

[0026] FIG. 3 is a flowchart of a method for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention.

[0027] FIG. 4 illustrates a process of manufacturing a chip-on-wafer according to a method for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention.

[0028] FIG. 5 is a flowchart of a method for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention.

[0029] FIG. 6 illustrates a process of manufacturing a chip-on-wafer according to a method for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention.

[0030] FIG. 7 is a flowchart of a method for manufacturing a chip-on-wafer for a micro LED display according to a third embodiment of the present invention.

[0031] FIG. 8 illustrates a process of manufacturing a chip-on-wafer according to a method for manufacturing a chip-on-wafer for a micro LED display according to a third embodiment of the present invention.

[0032] FIG. 9 is a flowchart of a method for manufacturing a chip-on-wafer for a micro LED display according to a fourth embodiment of the present invention.

[0033] FIG. 10 illustrates a process of manufacturing a chip-on-wafer according to a method for manufacturing a chip-on-wafer for a micro LED display according to a fourth embodiment of the present invention.

[0034] FIG. 11 illustrates a lateral chip manufactured using a chip-on-wafer manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention.

[0035] FIG. 12 illustrates a flip chip manufactured using a chip-on-wafer manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display according to the fourth embodiment of the present invention.

[0036] FIG. 13 illustrates a vertical chip manufactured using a chip-on-wafer manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention.

[0037] FIG. 14 illustrates a vertical chip manufactured using a chip-on-wafer manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display according to a third embodiment of the present invention.

[0038] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings.

[0039] In addition, when describing an embodiment of the present invention, if a detailed description of a related known configuration or function is judged to hinder understanding of the embodiment of the present invention, the detailed description is omitted.

[0040] Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0041]

[0042] From now on, with reference to the attached drawings, a method (S100) for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention will be described in detail.

[0043] FIG. 1 and FIG. 2 are overall diagrams illustrating a process of manufacturing a chip-on-wafer according to a method for manufacturing a chip-on-wafer for a micro LED display of the present invention, FIG. 3 is a flowchart of a method (S100) for manufacturing a chip-on-wafer for a micro LED display according to a first embodiment of the present invention, and FIG. 4 is a diagram illustrating a process of manufacturing a chip-on-wafer according to a method (S100) for manufacturing a chip-on-wafer for a micro LED display according to a first embodiment of the present invention.

[0044] As illustrated in FIGS. 1 to 4, a method (S100) for manufacturing a chip-on-wafer for a micro LED display according to a first embodiment of the present invention manufactures a chip-on-wafer through a two-time bonding method, and includes a growth step (S110), an electrode formation step (S120), an adhesion step (S130), an exposure step (S140), a molding step (S150), a pattern formation step (S160), a reflective layer formation step (S170), a bonding step (S180), and a removal step (S190).

[0045] The growth stage (S110) is a stage in which the first growth substrate (110) is prepared and a semiconductor layer (120) is epitaxially grown on the first growth substrate (110).

[0046] In the case where the semiconductor layer (120) emits blue or green light, when the laser lift off (LLO) process is used to remove the first growth substrate (110), the substrate may be made of a sapphire (α-phase Al2O3) substrate that is optically transparent and has high-temperature heat resistance and through which a laser beam (single wavelength light) can be transmitted 100% (theoretically) without absorption, and when the chemical lift off (CLO) process is used to remove the first growth substrate (110), the substrate may be made of a Si substrate having a (111), (110), or (100) crystal plane that can be removed by wet etching.

[0047] Meanwhile, in the case where the first growth substrate (110) is prepared as a sapphire substrate, it is also desirable for the first growth substrate (110) to have a protrusion shape that is patterned regularly or irregularly in various dimensions (size and shape) in microscale or nanoscale in order to minimize crystal defects within the group III nitride semiconductor thin film grown on top (patterned sapphire substrate, PSS).

[0048] In addition, when the semiconductor layer (120) emits red light, the initial growth substrate (110) may be prepared as a GaAs substrate that can be removed by wet etching using a chemical lift off (CLO) process. Furthermore, when the semiconductor layer (120) emits red light through a high-quality InGaN active region having a high In composition of 30% or more, the initial growth substrate (110) may be prepared as a sapphire or Si substrate, similarly to when the semiconductor layer (120) emits blue or green light.

[0049] The semiconductor layer (120) generates light and includes a third semiconductor region, a second semiconductor region, an active region, and a first semiconductor region.

[0050] In the present invention, the semiconductor layer (120) can emit blue, green, or red light. When the semiconductor layer (120) emits blue or green light, a binary, ternary, or quaternary compound such as InN, InGaN, GaN, AlGaN, AlN, or AlGaInN, which is a group 3 (Al, Ga, In) nitride semiconductor among group 3-5 compound semiconductors, can be epitaxially grown by arranging it in an appropriate position and order on the initial growth substrate (110).

[0051] In particular, a high-quality group III nitride semiconductor such as InGaN with a high In composition to emit blue or green light should be preferentially formed on top (active region) of a group III nitride semiconductor composed of GaN, AlGaN, AlN or AlGaInN, but is not limited thereto.

[0052] In addition, in the present invention, when the semiconductor layer (120) emits red light, a binary, ternary, or quaternary compound such as InP, InGaP, GaP, AlInP, AlGaP, AlP, or AlGaInP, which is a group 3 (Al, Ga, In) phosphide semiconductor among group 3-5 compound semiconductors, can be epitaxially grown by being placed in an appropriate position and order on the initial growth substrate (110).

[0053] In particular, in order to emit red light, a high-quality group III phosphide semiconductor such as InGaP having a high In composition should be preferentially formed on top of a group III phosphide semiconductor composed of GaP, AlInP, AlGaP, AlP or AlGaInP, but is not limited thereto, and for convenience of explanation, the group III nitride semiconductor will be used as a basis for the following description.

[0054] Furthermore, in recent years, in order to further improve the value of display panel products and the development of equipment and process technology, in the case of emitting red light, in addition to group III phosphide semiconductors, high-quality group III nitride semiconductors such as InGaN with a high In composition of 30% or more can be preferentially formed on top (active region) of group III nitride semiconductors composed of GaN, AlGaN, AlN or AlGaInN. Specifically, the active region is In x Ga 1-xWhen composed of N, x, that is, when the composition of indium is 16 to 20%, it emits blue light in the wavelength band of 450 nm to 470 nm, when the composition of indium is 22 to 28%, it emits green light in the wavelength band of 525 nm to 540 nm, and when the composition of indium is 30 to 35% (preferably 33%), it emits red light in the wavelength band of 625 nm to 635 nm.

[0055] In more detail, the growth step (S110) may sequentially epitaxially grow a third semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN) which is an undoped semiconductor region, a second semiconductor region (e.g., nGaN, nInGaN, nAlGaN, or nAlGaInN) which is an n-type semiconductor region, an active region (MQWs) of a multi-quantum well structure, and a first semiconductor region (e.g., pGaN, pInGaN, pAlGaN, or nAlGaInN) which is a p-type semiconductor region on the initial growth substrate (110), and may ultimately have an overall thickness of typically about 5.0 μm to 7.0 μm including multiple multi-layers of group III nitrides, but is not limited thereto.

[0056] The third semiconductor region is an undoped semiconductor region, and specifically, the third semiconductor region is a region that acts as a buffer to relieve stress and improve film quality of the epitaxially grown second semiconductor region, active region, and first semiconductor region before epitaxially growing the second semiconductor region, active region, and first semiconductor region on top of the first growth substrate (110).

[0057] This third semiconductor region may include a nucleation layer (NL) and may be formed to a thickness of typically 2.5 μm to 3 μm. In addition, when the initial growth substrate (110) is removed using a laser lift-off (LLO) technique, a sacrificial layer (SL) may be provided between the nucleation layer and the third semiconductor region, and the nucleation layer may also function as the sacrificial layer.

[0058] The second semiconductor region has n-type conductivity and is formed on the third semiconductor region. This second semiconductor region may have a thickness of 2.0 to 2.5 μm, and its lower surface has nitrogen polarity (N-polarity).

[0059] The active region, which has a multi-quantum well structure and generates light through the recombination of electrons and holes, is formed on top of the second semiconductor region. This active region can have a thickness of approximately 50 nm in multiple layers.

[0060] The first semiconductor region has p-type conductivity and is formed over the active region. This first semiconductor region may have a thickness of 0.5 μm or less in multiple layers, and its upper surface has gallium polarity (Ga-polarity).

[0061] That is, the active region is interposed between the second semiconductor region and the first semiconductor region, and when electrons in the second semiconductor region, which is an n-type semiconductor region, and holes in the first semiconductor region, which is a p-type semiconductor region, recombine in the active region, light is generated.

[0062] The electrode formation step (S120) is a step of forming an ohmic contact electrode (130) on a semiconductor layer (120).

[0063] According to the conventional chip-on-wafer method, since the stacked structure of the chip (including horizontal chips, flip chips, and vertical chips) is completed using only the initial growth substrate (110), the p-type ohmic contact electrode (130) must be formed in the back-end process. In this case, in order to form the p-type ohmic contact electrode (130), heat treatment must be performed at a temperature of 450°C or higher, so there is a problem that the chip, on which multiple layers have already been stacked, is damaged by the high temperature.

[0064] Accordingly, in the present invention, after the semiconductor layer (120) is grown, a p-type ohmic contact electrode (130) is formed through high-temperature heat treatment in a state where other layers are not laminated (i.e., in a state where the structure of the chip is not completed), and then the remaining necessary layers, such as a reflective layer (170), are laminated on one surface of the semiconductor layer (120), so that the problem of the laminated chip being damaged by the high-temperature heat treatment for forming the p-type ohmic contact electrode (130) can be fundamentally prevented.

[0065] More specifically, in the present invention, the ohmic contact electrode (130) is formed to contact the first semiconductor region, which is a p-type semiconductor, and is formed as a p-type ohmic contact electrode (130). Since the present embodiment is used in a vertical chip structure, the p-type ohmic contact electrode (130) is formed of a material having transparent conductivity so that light from the bottom can be transmitted to the top. In this case, the ohmic contact electrode (130) material may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, or IGZO.

[0066] Meanwhile, in the present invention, the p-type ohmic contact electrode (130) may have a single-layer structure, and may have a multi-layer structure in which a thin p-type ohmic contact electrode (130) is first formed on a gallium polarity (Ga-polarity) surface, and then a p-type electrode is formed thereon with a material that is the same as or different from the p-type ohmic contact electrode (130) and is electrically connected.

[0067] The bonding step (S130) is a step of bonding the ohmic contact electrode (130) to the intermediate temporary substrate (150) through the bonding layer (140).

[0068] Here, the intermediate temporary substrate (150) preferably has a coefficient of thermal expansion (CTE) that is equal to or similar to that of the initial growth substrate (110) and the final support substrate (190). In the case where a laser lift off (LLO) process is used to remove the intermediate temporary substrate (150), the intermediate temporary substrate (150) may be formed of a sapphire (α-phase Al2O3) substrate that is optically transparent and has high temperature resistance and through which a laser beam (single wavelength light) can be transmitted 100% (theoretically) without absorption, glass whose coefficient of thermal expansion (CTE) is adjusted to have a difference of 2 ppm or less from that of the support substrate (190), and in the case where a chemical lift off (CLO) process is used to remove the intermediate temporary substrate (150), the intermediate temporary substrate (150) may be formed of a Si substrate having a (111), (110), or (100) crystal plane that can be removed by wet etching.

[0069] In addition, in the present embodiment, the adhesive layer (140) may be formed of a metal or alloy, ceramic, or resin material. In particular, it is preferable to preferentially select a material that performs metallic bonding (eutectic bonding, diffusion bonding, direct bonding, etc.) as the adhesive layer (140), and the adhesive layer (140) may include a metallic bonding material that can be soldered at a temperature of 300°C or lower, such as In, Sn, Ga, Zn, Au, Ag, Cu, Pd, Ni, Ti, Cr, Al, or Si. In addition, a ceramic material that can be directly bonded at a temperature of 100°C or lower, such as SiO2, SOG (spin on glass), FOx (flowable oxides), SiN x , Al2O3, AlN, SiCN, ITO, IZO or ZnO, and may include resin materials such as epoxy, BCB (benzocyclobutene) or PI (polyimide) as organic adhesives capable of indirect bonding at a temperature of 100℃ or lower.

[0070] Meanwhile, the bonding step (S130) may form a separation layer (S) on an intermediate temporary substrate (150), and then bond the ohmic contact electrode (130) to the separation layer (S) through the adhesive layer (140). This separation layer (S) is a layer that is sacrificed and separated when the intermediate temporary substrate (150) is removed, and its material may vary depending on whether a laser lift off (LLO) process or a chemical lift off (CLO) process is used. Meanwhile, this separation layer (S) may be located on the upper or lower side of the adhesive layer (140) depending on the purpose, and if the adhesive layer (140) performs the function of the separation layer (S), the separation layer (S) may be omitted.

[0071] In addition, the bonding step (S130) can form a protective layer (P) on the ohmic contact electrode (130), and then bond the protective layer (P) to the temporary substrate (150) through the adhesive layer (140). This protective layer (P) serves to protect the elements below the ohmic contact electrode (130) when the adhesive layer (140) is removed in a subsequent process, and representative materials of the protective layer (P) include SiO2 and SiN. x , or AlN, but is not limited thereto, and various materials may be used depending on the method of removing the adhesive layer (140) (for example, when removing the adhesive layer (140) with hydrochloric acid, a SiO2 protective layer (P) is used). Furthermore, if the removal of the adhesive layer (140) does not affect the device, the protective layer (P) may be omitted.

[0072] Furthermore, the bonding step (S130) may form a separation layer (S) on an intermediate temporary substrate (150) and a protective layer (P) on an ohmic contact electrode (130), and then bond the protective layer (P) to the separation layer (S) through an adhesive layer (140).

[0073] The exposure step (S140) is a step of removing the growth substrate (110) to expose one side of the semiconductor layer (120).

[0074] In more detail, the exposure step (S140) can expose the third semiconductor region, which is an undoped semiconductor region, to the outside by removing the first growth substrate (110) using a laser lift off (LLO) process or a chemical lift off (CLO) process.

[0075] The forming step (S150) is a step of forming the semiconductor layer (120) to a preset thickness by selectively etching one surface of the exposed semiconductor layer (120).

[0076] According to the conventional chip-on-wafer method, since the stacked structure of the chip (including horizontal chips, flip chips, and vertical chips) is completed using only the initial growth substrate (110), the thickness of the undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN) or the n-type semiconductor region (e.g., nGaN, nInGaN, nAlGaN, or nAlGaInN) cannot be controlled, making it impossible to manufacture a high-quality, high-brightness micro LED having a thickness of 5 μm or less. In addition, there is also a disadvantage that the light extraction efficiency is lowered by such a thick undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN).

[0077] Meanwhile, in the conventional chip-on-wafer method, a completed chip is attached to TFT Glass, an interposer, etc., and then the initial growth substrate (110) on the opposite side is removed to expose an undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN). However, even if the undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN) is etched, there is a problem in that the completed chip is damaged by the high temperature generated during etching and the gas injected.

[0078] Furthermore, when the initial growth substrate (110) is removed by the laser lift off (LLO) process, a large number of gallium (Ga) droplets (solid, powder) that interfere with the scattering of the generated light are generated on the surface of the semiconductor layer (120) from which the initial growth substrate (110) was removed. Currently, the gallium (Ga) droplets are removed by hydrochloric acid vapor or taping. However, when hydrochloric acid vapor is used, there is a problem that the process cost is excessive, and the chip may be damaged during the gallium (Ga) droplet removal process. In addition, when taping is used, there is a problem that the gallium (Ga) droplets cannot be completely removed. However, when the growth substrate for Si (blue, green, and red nitride) and GaAs (red phosphide) micro LEDs is removed by the chemical lift off (CLO) process, there is no gallium (Ga) droplet issue.

[0079] Accordingly, in the present invention, the ohmic contact electrode (130) on the semiconductor layer (120) is bonded to the intermediate temporary substrate (150), and then the first growth substrate (110) is removed while other layers are not stacked (i.e., the chip structure is not completed), and the exposed undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN) is etched to form it to a predetermined thickness, so that the undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN) can be formed to a desired thickness without damaging the chip, thereby manufacturing a high-quality, high-brightness micro LED display chip of 3 ㎛ or less. In addition, the problem of gallium (Ga) droplets remaining on the surface of the semiconductor layer (120) can be fundamentally prevented, so that the light extraction efficiency can be significantly improved.

[0080] In more detail, the forming step (S150) forms the semiconductor layer (120) to a predetermined thickness by etching the third semiconductor region, which is an undoped semiconductor region exposed by removing the growth substrate (110). This forming step (S150) can etch the third semiconductor region, which is 2.5 μm to 3 μm, to a desired thickness or etch and remove the entire third semiconductor region by using a dry process using a known gas (Cl2, BCl3, Ar) plasma. In this case, in the present invention, even if a high temperature is generated during the etching of the third semiconductor region, since only the semiconductor layer (120) and the ohmic contact electrode (130) are formed and the chip structure is not yet complete, the thickness of the chip can be adjusted as desired without damage to the chip, and there is an advantage in that gallium (Ga) droplets can be completely removed by etching.

[0081] The pattern formation step (S160) is a step of forming a surface roughness (T) (surface texture) pattern on one surface of a semiconductor layer (120) that has already been formed to a set thickness.

[0082] In more detail, the pattern formation step (S160) forms a regular or irregular surface roughness (T) (surface texture) pattern on one surface of a semiconductor layer (120) having a nitrogen polarity (N-polarity) surface using a wet process using a basic solution (including OH, NaOH, KOH) or a dry process using a known gas (Cl2, BCl3, Ar) plasma, in order to increase the light extraction efficiency through light scattering.

[0083] The reflective layer formation step (S170) is a step of forming a reflective layer (170) on one surface of a semiconductor layer (120) on which a surface roughness (T) pattern is formed.

[0084] This reflective layer (170) may be formed of Ag, Al, Au, Pd, Pt, Ni, Mo, Cu, Cr, Ti, TiW, ITO, IZO, ZnO, TiN, DBR (distributed Bragg reflector), ODR (omni-directional reflector) or a combination thereof, and in this embodiment, the reflective layer (170) may be formed on one surface of the semiconductor layer (120), i.e., the nitrogen polarity (N-polarity) surface.

[0085] Meanwhile, the reflective layer (170) may have a single-layer structure and may be an n-type ohmic contact electrode in itself, or a thin n-type ohmic contact electrode may be first formed on the nitrogen polarity (N-polarity) surface of the semiconductor layer (120), and then a reflective layer (170) may be formed thereon with a material that is the same as or different from the n-type ohmic contact electrode, so as to have a multi-layer structure that is electrically connected.

[0086] Meanwhile, in the present invention, the reflective layer (170) may be formed entirely on the nitrogen polarity (N-polarity) surface of the semiconductor layer (120) or may be formed separately in chip units. As shown in FIG. 4, in order to prevent re-deposition from occurring in advance when etching is performed to separate into chip units on a chip-on-wafer, it is preferable that the reflective layer (170) be formed separately in chip units using photoresist (PR).

[0087] The bonding step (S180) is a step of bonding one surface of a semiconductor layer (120) on which a reflective layer (170) is formed to a final support substrate (190) through a bonding layer (180).

[0088] Here, the final support substrate (190) is a substrate that supports the structure of a chip that has gone through each step of the manufacturing method (S100) of a chip-on-wafer for a micro LED display according to the first embodiment of the present invention, and this support substrate (190) can be made of a sapphire (α-phase Al2O3) substrate or glass with a controlled coefficient of thermal expansion (CTE).

[0089] In this embodiment, the bonding layer (180) may be formed of a ceramic, resin, metal or alloy material. In particular, it is preferable to preferentially select a ceramic or resin material for the bonding layer (180), and the bonding layer (180) may be a ceramic material capable of direct bonding at a temperature of 100°C or lower, such as SiO2, SOG (spin on glass), FOx (flowable oxides), SiN x , Al2O3, AlN, SiCN, ITO, IZO or ZnO, and may include resin materials such as epoxy, BCB (benzocyclobutene) or PI (polyimide) as organic adhesives that can be indirectly bonded at a temperature of 100°C or lower. In addition, may include materials such as In, Sn, Ga, Zn, Au, Ag, Cu, Pd, Ni, Ti, Cr, Al or Si as metallic bonding materials that can be soldered at a temperature of 300°C or lower. Furthermore, when the reflective layer (170) is formed separately in chip units, the bonding layer (180) is formed to surround the reflective layer (170) so that one surface of the semiconductor layer (120) on which the reflective layer (170) is formed can be bonded to the support substrate (190). Here, the bonding layer (180) does not make an ohmic contact with the semiconductor layer (120).

[0090] Meanwhile, the bonding step (S180) may form a separation layer (S) on a support substrate (190), and then bond one surface of the semiconductor layer (120) to the separation layer (S). This separation layer (S) is a layer that is sacrificed and separated when the final support substrate (190) is removed, and a material according to a laser lift off (LLO) process may be used. Meanwhile, this separation layer (S) may be located on the upper or lower side of the bonding layer (180) depending on the purpose, and if the bonding layer (180) performs the function of the separation layer (S), the separation layer (S) may be omitted.

[0091] The removal step (S190) is a step of removing the intermediate temporary substrate (150) and the adhesive layer (140).

[0092] In more detail, the removal step (S190) removes the intermediate temporary substrate (150) and the adhesive layer (140) using a laser lift off (LLO) process or a chemical lift off (CLO) process, and when a separation layer (S) and a protective layer (P) are formed, the separation layer (S) and the protective layer (P) are also removed together.

[0093] A chip-on-wafer manufactured according to the method for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention as described above (S100) has a structure in which a final support substrate (190), a separation layer (S), a bonding layer (180), a reflective layer (170), a semiconductor layer (120), and an ohmic contact electrode (130) are sequentially laminated.

[0094] FIG. 13 illustrates a vertical chip manufactured using a chip-on-wafer manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display (S100) according to the first embodiment of the present invention.

[0095] As shown in FIG. 13, when a fabrication (Fab) process is performed on a chip-on-wafer manufactured according to the method (S100) for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention, which has a structure in which a final support substrate (190), a separation layer (S), a bonding layer (180), a reflective layer (170), a semiconductor layer (120), and an ohmic contact electrode (130) are sequentially laminated, a vertical chip having a p-type ohmic contact electrode (130) provided on the upper side and a reflective layer (170) functioning as an n-type ohmic contact electrode provided on the lower side can be manufactured on the wafer.

[0096] Afterwards, when the chip is transferred to a panel, interposer, etc. to finally manufacture a display, it is transferred selectively through a single bonding or double bonding method depending on the position where the layer (or electrode) that functions as a reflector, such as a reflective layer (170), is arranged. Since the chip manufactured through this embodiment has a vertical chip structure in which a p-type ohmic contact electrode (130) is provided on the upper side and a reflective layer (170) that functions as an n-type ohmic contact electrode is provided on the lower side, the final support substrate (190) is removed through a double bonding method using another temporary substrate, and then the panel is positioned on the surface from which the final support substrate (190) was removed.

[0097]

[0098] From now on, with reference to the attached drawings, a method for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention (S200) will be described in detail.

[0099] FIG. 5 is a flowchart of a method (S200) for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention, and FIG. 6 illustrates a process for manufacturing a chip-on-wafer according to a method (S200) for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention.

[0100] As illustrated in FIGS. 5 and 6, a method (S200) for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention manufactures a chip-on-wafer through a two-time bonding method, and includes a growth step (S210), an electrode formation step (S220), an adhesion step (S230), an exposure step (S240), a molding step (S250), a pattern formation step (S260), a reflective layer formation step (S270), a bonding step (S280), and a removal step (S290).

[0101] Here, the growth step (S210) is the same as the manufacturing method (S100) of the chip-on-wafer for micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0102] The electrode formation step (S220) is a step of forming an ohmic contact electrode (130) on a semiconductor layer (120).

[0103] More specifically, in the present invention, the ohmic contact electrode (130) is formed to be in contact with the first semiconductor region, which is a p-type semiconductor, and is formed as a p-type ohmic contact electrode (130). Since the present embodiment is used in a lateral chip structure, the ohmic contact electrode (130) is formed of a material having transparent conductivity so that light from the bottom can be transmitted to the top. In this case, the ohmic contact electrode (130) material may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, or IGZO.

[0104] The bonding step (S230) to the pattern forming step (S260) are the same as the manufacturing method (S100) of the chip-on-wafer for micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0105] The reflective layer formation step (S270) is a step of forming a reflective layer (171) on one surface of a semiconductor layer (120) on which a surface roughness (T) pattern is formed.

[0106] This reflective layer (171) may be formed of Ag, Al, Au, Pd, Pt, Ni, Mo, Cu, Cr, Ti, TiW, ITO, IZO, ZnO, TiN, DBR (distributed Bragg reflector), ODR (omni-directional reflector) or a combination thereof, and in the present embodiment, the reflective layer (171) may be formed on one surface of the semiconductor layer (120) which is an n-type semiconductor, i.e., the nitrogen polarity (N-polarity) surface. Meanwhile, in the present embodiment, the reflective layer (171) does not make ohmic contact with the semiconductor layer (120), and a separate n-type ohmic contact electrode does not exist in the chip-on-wafer manufactured according to the present embodiment.

[0107] Meanwhile, in the present invention, the reflective layer (170) may be formed entirely on the nitrogen polarity (N-polarity) surface of the semiconductor layer (120) or may be formed separately in chip units. As shown in FIG. 4, in order to prevent re-deposition from occurring in advance when etching is performed to separate into chip units on a chip-on-wafer, it is preferable that the reflective layer (170) be formed separately in chip units using photoresist (PR).

[0108] The bonding step (S280) to the removal step (S290) are the same as the manufacturing method (S100) of the chip-on-wafer for micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0109] A chip-on-wafer manufactured according to the method for manufacturing a chip-on-wafer for a micro LED display according to the second embodiment of the present invention as described above (S200) has a structure in which a final support substrate (190), a separation layer (S), a bonding layer (180), a reflective layer (171), a semiconductor layer (120), and an ohmic contact electrode (130) are sequentially laminated.

[0110] FIG. 11 illustrates a lateral chip manufactured using a chip-on-wafer manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display (S200) according to a second embodiment of the present invention.

[0111] As shown in FIG. 11, when a fabrication (Fab) process is performed on a chip-on-wafer manufactured according to a method (S200) for manufacturing a chip-on-wafer for a micro LED display according to the second embodiment of the present invention, which has a structure in which a final support substrate (190), a separation layer (S), a bonding layer (180), a reflective layer (171), a semiconductor layer (120), and an ohmic contact electrode (130) are sequentially laminated, a part of the semiconductor layer (120) is mesa etched to form an n-type ohmic contact electrode (N) in a second semiconductor region which is an n-type semiconductor, thereby enabling a lateral chip having a p-type ohmic contact electrode (130) and an n-type ohmic contact electrode (N) provided thereon to be manufactured on the wafer.

[0112] Afterwards, when the chip is transferred to a panel, interposer, etc. to finally manufacture a display, it is transferred selectively through a single bonding or double bonding method depending on the position where the layer (or electrode) that functions as a reflector, such as a reflective layer (170), is arranged. Since the chip manufactured through this embodiment has a horizontal chip structure with a p-type ohmic contact electrode (130) and an n-type ohmic contact electrode (N) provided on the upper side, the final support substrate (190) is removed through a double bonding method using another temporary substrate, and then the panel is positioned on the surface from which the final support substrate (190) was removed.

[0113]

[0114] From now on, with reference to the attached drawings, a method for manufacturing a chip-on-wafer for a micro LED display according to a third embodiment of the present invention (S300) will be described in detail.

[0115] FIG. 7 is a flowchart of a method (S300) for manufacturing a chip-on-wafer for a micro LED display according to a third embodiment of the present invention, and FIG. 8 illustrates a process for manufacturing a chip-on-wafer according to a method (S300) for manufacturing a chip-on-wafer for a micro LED display according to a third embodiment of the present invention.

[0116] As illustrated in FIGS. 7 and 8, a method (S300) for manufacturing a chip-on-wafer for a micro LED display according to a third embodiment of the present invention manufactures a chip-on-wafer through a two-time bonding method, and includes a growth step (S310), an electrode formation step (S320), an adhesion step (S330), an exposure step (S340), a molding step (S350), a pattern formation step (S360), a bonding step (S370), and a removal step (S380).

[0117] Here, the growth step (S310) is the same as the manufacturing method (S100) of the chip-on-wafer for micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0118] The electrode formation step (S320) is a step of forming an ohmic contact electrode (130) on a semiconductor layer (120).

[0119] More specifically, in the present invention, the ohmic contact electrode (130) is formed to contact the first semiconductor region, which is a p-type semiconductor, and is formed as a p-type ohmic contact electrode (130). Since the present embodiment is used in a vertical chip structure, the p-type ohmic contact electrode (130) is formed of a material having transparent conductivity so that light from the bottom can be transmitted to the top. In this case, the ohmic contact electrode (130) material may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0120] The bonding step (S330) to the pattern forming step (S360) are the same as the manufacturing method (S100) of the chip-on-wafer for micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0121] The bonding step (S370) is a step of bonding one side of the semiconductor layer (120), i.e., the nitrogen polarity (N-polarity) surface, to the final support substrate (190) through the bonding layer (180).

[0122] Here, the final support substrate (190) is a substrate that supports the structure of a chip that has gone through each step of the manufacturing method (S300) of a chip-on-wafer for a micro LED display according to the third embodiment of the present invention, and this support substrate (190) can be made of a sapphire (α-phase Al2O3) substrate or glass with a controlled coefficient of thermal expansion (CTE).

[0123] In addition, in the present embodiment, the bonding layer (180) may be formed of a metal material, and may include materials such as In, Sn, Ga, Zn, Au, Ag, Cu, Pd, Ni, Ti, Cr, Al, and Si as a metallic bonding material that can be soldered at a temperature of 300°C or lower. In the present embodiment, the bonding layer (180) may be in n-ohmic contact with one surface of the semiconductor layer (120), which is an n-type semiconductor, and at the same time, performs the function of a reflector.

[0124] Meanwhile, the bonding step (S370) may form a separation layer (S) on a support substrate (190), and then bond one surface of the semiconductor layer (120) to the separation layer (S). This separation layer (S) is a layer that is sacrificed and separated when the final support substrate (190) is removed, and a material according to a laser lift off (LLO) process may be used. Meanwhile, this separation layer (S) may be located on the upper or lower side of the bonding layer (180) depending on the purpose, and if the bonding layer (180) performs the function of the separation layer (S), the separation layer (S) may be omitted.

[0125] The removal step (S380) is the same as the manufacturing method (S100) of a chip-on-wafer for a micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0126] A chip-on-wafer manufactured according to the method for manufacturing a chip-on-wafer for a micro LED display according to the third embodiment of the present invention as described above (S300) has a structure in which a final support substrate (190), a separation layer (S), a bonding layer (180), a semiconductor layer (120), and an ohmic contact electrode (130) are sequentially laminated.

[0127] FIG. 14 illustrates a vertical chip manufactured using a chip-on-wafer manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display (S300) according to a third embodiment of the present invention.

[0128] As shown in FIG. 14, when a fabrication (Fab) process is performed on a chip-on-wafer manufactured according to a method (S300) for manufacturing a chip-on-wafer for a micro LED display according to the third embodiment of the present invention, which has a structure in which a final support substrate (190), a separation layer (S), a bonding layer (180), a semiconductor layer (120), and an ohmic contact electrode (130) are sequentially laminated, a vertical chip having a p-type ohmic contact electrode (130) provided on the upper side and a bonding layer (180) functioning as an n-type ohmic contact electrode provided on the lower side can be manufactured on the wafer.

[0129] Afterwards, when the chip is transferred to a panel, interposer, etc. to finally manufacture a display, it is transferred selectively through a single bonding or double bonding method depending on the position where the layer (or electrode) that functions as a reflector, such as a reflective layer (170), is arranged. Since the chip manufactured through this embodiment has a vertical chip structure in which a p-type ohmic contact electrode (130) is provided on the upper side and a bonding layer (180) that functions as an n-type ohmic contact electrode is provided on the lower side, the final support substrate (190) is removed through a double bonding method using another temporary substrate, and then the panel is positioned on the surface from which the final support substrate (190) was removed.

[0130]

[0131] From now on, with reference to the attached drawings, a method for manufacturing a chip-on-wafer for a micro LED display according to the fourth embodiment of the present invention (S400) will be described in detail.

[0132] FIG. 9 is a flowchart of a method (S400) for manufacturing a chip-on-wafer for a micro LED display according to a fourth embodiment of the present invention, and FIG. 10 illustrates a process for manufacturing a chip-on-wafer according to a method (S400) for manufacturing a chip-on-wafer for a micro LED display according to a fourth embodiment of the present invention.

[0133] As illustrated in FIGS. 9 and 10, a method (S400) for manufacturing a chip-on-wafer for a micro LED display according to a fourth embodiment of the present invention manufactures a chip-on-wafer through a two-time bonding method, and includes a growth step (S410), an electrode formation step (S420), an adhesion step (S430), an exposure step (S440), a molding step (S450), a pattern formation step (S460), a bonding step (S470), and a removal step (S480).

[0134] Here, the growth step (S410) is the same as the manufacturing method (S100) of the chip-on-wafer for micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0135] The electrode formation step (S420) is a step of forming an ohmic contact electrode (131) on a semiconductor layer (120).

[0136] In more detail, in the present invention, the ohmic contact electrode (131) is formed to be in contact with the first semiconductor region, which is a p-type semiconductor, and is formed as a p-type ohmic contact electrode (131). Since the present embodiment is used in a flip chip structure, the ohmic contact electrode (131) is formed of a metallic material so as to reflect the generated light. In this case, the ohmic contact electrode (131) material may include Ag, Al, Au, Pt, Ni, Mo, Cu, Cr, Ti, etc. (However, Ag is not directly in ohmic contact, and a thin p-type ohmic contact electrode (130) made of another material may be first formed on the gallium polarity (Ga-polarity) surface and then formed thereon).

[0137] Meanwhile, in the present embodiment, the ohmic contact electrode (131) may be formed of a transparent conductive material. In this case, the ohmic contact electrode (130) material may include TiW, ITO, IZO, etc., and although not shown in the drawing, a reflector may be separately provided on the ohmic contact electrode (131) having transparent conductivity so as to reflect the generated light.

[0138] The bonding step (S430) to the pattern forming step (S460) are the same as the manufacturing method (S100) of the chip-on-wafer for micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0139] The bonding step (S470) is a step of bonding one surface of the semiconductor layer (120) to the final support substrate (190) through the bonding layer (181).

[0140] Here, the final support substrate (190) is a substrate that supports the structure of a chip that has gone through each step of the manufacturing method (S400) of a chip-on-wafer for a micro LED display according to the fourth embodiment of the present invention, and this support substrate (190) can be made of a sapphire (α-phase Al2O3) substrate or glass with a controlled coefficient of thermal expansion (CTE).

[0141] In addition, in this embodiment, the bonding layer (181) is made of SiO2, SiN so that the generated light can be transmitted. x , SiCN, AlN, Al2O3, SOG (spin on glass, liquid SiO2), HSQ (hydrogen silsesquioxane), etc., and in this embodiment, the bonding layer (181) is formed on one surface of the semiconductor layer (120) which is an n-type semiconductor, but does not form an ohmic contact.

[0142] Meanwhile, the bonding step (S470) may form a separation layer (S) on a support substrate (190), and then bond one surface of the semiconductor layer (120) to the separation layer (S). This separation layer (S) is a layer that is sacrificed and separated when the final support substrate (190) is removed, and a material according to a laser lift off (LLO) process may be used. Meanwhile, this separation layer (S) may be located on the upper or lower side of the bonding layer (181) depending on the purpose, and if the bonding layer (181) performs the function of the separation layer (S), the separation layer (S) may be omitted.

[0143] The removal step (S480) is the same as the manufacturing method (S100) of a chip-on-wafer for a micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0144] A chip-on-wafer manufactured according to the method for manufacturing a chip-on-wafer for a micro LED display according to the fourth embodiment of the present invention as described above (S400) has a structure in which a final support substrate (190), a separation layer (S), a bonding layer (181), a semiconductor layer (120), and an ohmic contact electrode (131) are sequentially laminated.

[0145] FIG. 12 illustrates a flip chip manufactured using a chip-on-wafer manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display (S400) according to the fourth embodiment of the present invention.

[0146] As shown in FIG. 12, when a fabrication (Fab) process is performed on a chip-on-wafer manufactured according to a method (S400) for manufacturing a chip-on-wafer for a micro LED display according to the fourth embodiment of the present invention, which has a structure in which a final support substrate (190), a separation layer (S), a bonding layer (181), a semiconductor layer (120), and an ohmic contact electrode (131) are sequentially laminated, a part of the semiconductor layer (120) is mesa-etched, and then an n-type ohmic contact electrode (not shown) and a passivation layer (L) are formed, and then a plurality of through holes are formed in the passivation layer (L) to form a first extension electrode (E1) electrically connected to the p-type ohmic contact electrode (131), and a second extension electrode (E2) electrically connected to the n-type ohmic contact electrode (not shown) of the mesa-etched portion are formed, thereby manufacturing a flip chip on the wafer. Here, the n-type ohmic contact electrode can be formed without heat treatment, and the n-type ohmic contact electrode can be omitted and then the second extension electrode (E2) can be directly connected to the semiconductor layer (120) of the mesa-etched portion.

[0147] Afterwards, when the chip is transferred to a panel, interposer, etc. to finally manufacture a display, it is transferred selectively through a one-time bonding or two-time bonding method depending on the position where the layer (or electrode) that functions as a reflector, such as the reflective layer (170), is arranged. However, since the chip manufactured through this embodiment has no reflective layer (170) and has a flip chip structure in which the p-type ohmic contact electrode (130) performs the function of a reflector (or a reflector arranged on a transparent conductive p-type ohmic contact electrode (130) performs the function), the first extension electrode (E1) and the second extension electrode (E2) are bonded to the panel through a one-time bonding method, and then the final support substrate (190) is removed.

[0148]

[0149] Although all components constituting the embodiments of the present invention have been described as being combined or operating in combination as one, the present invention is not necessarily limited to such embodiments. That is, within the scope of the present invention, all of the components may be selectively combined and operated in one or more combinations.

[0150] Furthermore, terms such as "include," "comprise," or "have" described above, unless specifically stated otherwise, imply that the corresponding component may be present, and therefore should be interpreted to include other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in dictionaries, should be interpreted to be consistent with the contextual meaning of the relevant technology, and shall not be interpreted in an ideal or overly formal sense, unless explicitly defined in the present invention.

[0151] The above description is merely an example of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention.

[0152] Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical concepts within the scope equivalent thereto should be construed as being included within the scope of the present invention.

Claims

1. A method for manufacturing a chip-on-wafer for a micro LED display, A growth step in which a semiconductor layer is grown epitaxially on a growth substrate; An electrode forming step of forming an ohmic contact electrode on the semiconductor layer; A bonding step of bonding the above-mentioned ohmic contact electrode to a temporary substrate through an adhesive layer; An exposure step of removing the growth substrate to expose one side of the semiconductor layer; A pattern forming step for forming a surface texture pattern on one surface of the exposed semiconductor layer; A bonding step of bonding one surface of the exposed semiconductor layer to a support substrate; and A method for manufacturing a chip-on-wafer for a micro LED display, comprising a removal step of removing the temporary substrate and the adhesive layer.

2. In claim 1, It further includes a forming step of forming the semiconductor layer to a preset thickness by etching one side of the exposed semiconductor layer, The above pattern formation step is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized by forming a surface roughness pattern on one surface of the semiconductor layer formed to a preset thickness.

3. In claim 2, The above growth stages are, The third semiconductor region, the second semiconductor region, the active region, and the first semiconductor region are sequentially epitaxially grown, The above forming step is, Etching the exposed third semiconductor region to form the semiconductor layer to a preset thickness, The third semiconductor region is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that it is an un-doped semiconductor region.

4. In claim 1, It further includes a reflective layer forming step of forming a reflective layer on one surface of the semiconductor layer on which a surface roughness pattern is formed, The above bonding step is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that one surface of the semiconductor layer on which the reflective layer is formed is bonded to the support substrate through a bonding layer.

5. In claim 4, The above reflective layer is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that an ohmic contact is formed on one surface of the semiconductor layer.

6. In claim 1, The above bonding step is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that one surface of the semiconductor layer having a surface roughness pattern formed thereon is bonded to a support substrate through a bonding layer.

7. In claim 6, The above bonding layer is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that an ohmic contact is formed on one surface of the semiconductor layer.

8. In claim 1, The above bonding step is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that a separation layer is formed on the support substrate and then one surface of the semiconductor layer is bonded to the separation layer.

9. In claim 1, The above bonding step is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that a separation layer is formed on the temporary substrate and then the ohmic contact electrode is bonded to the separation layer through the adhesive layer.

10. In claim 1, The above bonding step is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that a protective layer is formed on the above-mentioned ohmic contact electrode and then the protective layer is bonded to the temporary substrate through the adhesive layer.

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