Capacitor

Abstract

A capacitor according to one embodiment of the present invention comprises: a base including a through-hole penetrating from a first surface to a second surface opposite the first surface; a first electrode layer disposed on the first surface, the second surface, and an inner wall surface of the through-hole of the base; a first dielectric layer disposed on the first electrode layer on the first surface, the second surface, and the inner wall surface of the through-hole of the base; and a second electrode layer disposed on the first dielectric layer on the first surface, the second surface, and the inner wall surface of the through-hole of the base, wherein the base includes silicon, and the surface roughness of the inner wall surface of the through-hole is 1 nm to 50 nm.

Description

capacitor

[0001] An embodiment of the present invention relates to a capacitor.

[0002] Semiconductor packages are used in a variety of fields, including automobiles, communications, and computers. They typically include printed circuit boards (PCBs), semiconductor chips positioned on the PCBs, and passive components positioned on the PCBs. Passive components may include, for example, resistors, inductors, and capacitors.

[0003] As semiconductor packaging becomes more sophisticated, the demand for high-performance, highly reliable, and ultra-small capacitors is increasing. To meet these demands, silicon-based capacitors and anodic aluminum oxide (AAO)-based capacitors have been proposed. Silicon-based capacitors include electrode layers, dielectric layers, and electrode layers sequentially stacked on a silicon base, while AAO-based capacitors include electrode layers, dielectric layers, and electrode layers sequentially stacked on an AAO base.

[0004] As the need for reducing the signal path of semiconductor packages and the size of semiconductor packages increases, high-capacity capacitors that can be mounted inside or at the bottom of semiconductor packages are required.

[0005] The technical problem to be achieved by the present invention is to provide an ultra-small and high-capacity capacitor.

[0006] According to one embodiment of the present invention, a capacitor includes a base including a through hole penetrating from a first surface to a second surface opposite the first surface, a first electrode layer disposed on the first surface, the second surface of the base, and an inner wall surface of the through hole, a first dielectric layer disposed on the first electrode layer on the first surface, the second surface of the base, and the inner wall surface of the through hole, and a second electrode layer disposed on the first dielectric layer on the first surface, the second surface of the base, and the inner wall surface of the through hole, wherein the base includes silicon, and a surface roughness of the inner wall surface of the through hole is 1 nm to 50 nm.

[0007] The surface roughness of the inner wall of the above through hole may be 10 nm to 30 nm.

[0008] At least one of the first side and the second side may include a porous region.

[0009] The surface roughness of at least one of the first surface and the second surface may be different from the surface roughness of the inner wall surface of the through hole.

[0010] The surface roughness of the first surface may be different from the surface roughness of the second surface.

[0011] When the above through hole is divided into an upper region, a middle region, and a lower region with equal heights from the first surface of the base to the second surface, the surface roughness of the inner wall surface of the middle region may be 0.9 to 1.1 times the surface roughness of the inner wall surface of the upper region, and may be 0.9 to 1.1 times the surface roughness of the inner wall surface of the lower region.

[0012] When the above through hole is divided into an upper region, a middle region, and a lower region with equal heights from the first surface of the base to the second surface, the diameter of the middle region may be 0.9 to 1.1 times the diameter of the upper region, and may be 0.9 to 1.1 times the diameter of the lower region.

[0013] The first electrode layer and the second electrode layer may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, and copper (Cu).

[0014] It further includes a passivation layer disposed on the second electrode layer, and the passivation layer may include SiO2.

[0015] The length of the plurality of through holes in the direction from the first surface to the second surface may be 3.5 μm or more and 175 μm or less.

[0016] According to one embodiment of the present invention, a silicon substrate includes a base including a through hole penetrating from a first surface to a second surface opposite the first surface, wherein the base includes silicon, and the surface roughness of an inner wall surface of the through hole is 1 nm to 50 nm, and when the through hole is divided into an upper region, a middle region, and a lower region at equal heights from the first surface to the second surface of the base, the surface roughness of the inner wall surface of the middle region may be 0.9 to 1.1 times the surface roughness of the inner wall surface of the upper region, and may be 0.9 to 1.1 times the surface roughness of the inner wall surface of the lower region.

[0017] According to another embodiment of the present invention, a silicon substrate includes a base including a through hole penetrating from a first surface to a second surface opposite the first surface, wherein the base includes silicon, and the surface roughness of an inner wall surface of the through hole is 1 nm to 50 nm, and when the through hole is divided into an upper region, a middle region, and a lower region at equal heights from the first surface to the second surface of the base, the diameter of the middle region may be 0.9 to 1.1 times the diameter of the upper region, and may be 0.9 to 1.1 times the diameter of the lower region.

[0018] According to embodiments of the present invention, an ultra-small, high-capacity capacitor can be provided. Furthermore, according to embodiments of the present invention, a capacitor having a simple manufacturing process, low cost, and high reliability can be provided.

[0019] Figure 1 is a perspective view of a capacitor according to an embodiment of the present invention.

[0020] FIG. 2 is a perspective view of a base included in a capacitor according to an embodiment of the present invention.

[0021] FIG. 3 is a cross-sectional view of a base included in a capacitor according to an embodiment of the present invention.

[0022] Figures 4 to 7 are cross-sectional views of capacitors according to embodiments of the present invention.

[0023] Figure 8 shows a method for forming a through hole in a base according to an embodiment of the present invention.

[0024] FIGS. 9 and 10 are drawings for explaining an etching mechanism in a process for forming a through hole of a base according to an embodiment of the present invention.

[0025] Figures 11 to 13 are SEM images of structures manufactured according to embodiments of the present invention.

[0026] Figures 14 and 15 are cross-sectional views of a capacitor according to another embodiment of the present invention.

[0027] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0028] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0029] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0030] Additionally, the terms used in the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention.

[0031] In this specification, the singular may also include the plural unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C”, it may include one or more of all combinations that can be combined with A, B, C.

[0032] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0033] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0034] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0035] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it can include the meaning of a downward direction as well as an upward direction based on one component.

[0036] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0037] FIG. 1 is a perspective view of a capacitor according to an embodiment of the present invention, FIG. 2 is a perspective view of a base included in a capacitor according to an embodiment of the present invention, FIG. 3 is a cross-sectional view of a base included in a capacitor according to an embodiment of the present invention, and FIGS. 4 to 7 are cross-sectional views of capacitors according to embodiments of the present invention.

[0038] Referring to FIGS. 1 to 7, the capacitor (100) includes a base (110), a first electrode layer (120), a first dielectric layer (130), and a second electrode layer (140).

[0039] As illustrated in FIGS. 2 and 3, the base (110) includes a first surface (111), a second surface (112) opposite the first surface (111), and a third surface (113) disposed between the first surface (111) and the second surface (112). The first surface (111), the second surface (112), and the third surface (113) may be referred to as a top surface, a bottom surface, and a side surface, respectively. The base (110) is illustrated as having a hexahedral shape, but is not limited thereto. The base (110) may be a cylinder, an elliptical cylinder, a prism, or the like.

[0040] The base (110) may include a semiconductor material or an insulator material. For example, the base (110) may be a silicon (Si) substrate. For example, the base (110) may be a doped silicon substrate. For example, the base (110) may be an n-type doped silicon substrate or a p-type doped silicon substrate. Accordingly, the base (110) according to an embodiment of the present invention may also be referred to as a silicon substrate.

[0041] According to an embodiment of the present invention, the base (110) includes a plurality of through holes (TH) penetrating from the first surface (111) to the second surface (112). That is, the plurality of through holes (TH) extend from the first surface (111) to the second surface (112) of the base (110). At this time, at least some of the plurality of through holes (TH) may be parallel to each other. For example, a virtual line connecting the center of the bottom surface of one of the plurality of through holes (TH) to the center of the upper surface may be parallel to a virtual line connecting the center of the top surface of another of the plurality of through holes (TH) to the center of the upper surface. Accordingly, since an electrode layer can be easily deposited with a uniform thickness on the inner wall surfaces of the plurality of through holes (TH), a highly reliable capacitor can be obtained. The plurality of through holes (TH) may be formed by a method of etching a silicon substrate. The plurality of through holes (TH) may have the same shape or a regular shape, and the spacing between the plurality of through holes (TH) may be the same, or may have a pattern of regularly increasing or regularly decreasing.

[0042] According to an embodiment of the present invention, the average diameter (D1) of the plurality of through holes (TH) may be 1.5 μm to 3.5 μm, preferably 2 μm to 3 μm. Alternatively, the average shortest distance (D2) between two adjacent through holes (TH) may be 1.5 μm to 3.5 μm, preferably 2 μm to 3 μm. Accordingly, while having a sufficient specific surface area for implementing a capacitor, the possibility of damage to the base (110) may be minimized and durability may be increased.

[0043] At this time, the average height (H) of the plurality of through holes (TH) based on the second surface (112) of the base (110) may be 3.5 ㎛ or more and 175 ㎛ or less, preferably 30 ㎛ or more and 120 ㎛ or less, and more preferably 40 ㎛ or more and 60 ㎛ or less. Here, the height (H) of each through hole (TH) may be the height from the second surface (112) of the base (110). Accordingly, the base (110) may be easily manufactured while having a sufficient specific surface area for implementing a capacitor.

[0044] Accordingly, the ratio (H / D1) of the average height (H) of the plurality of through holes (TH) based on the second surface (112) of the base (110) to the average diameter (D1) of the plurality of through holes (TH) may be 1 to 50, preferably 15 to 40, more preferably 20 to 30. Alternatively, the ratio (H / D2) of the average height (H) of the plurality of through holes (TH) based on the second surface (112) of the base (110) to the average shortest distance (D2) between two adjacent through holes (TH) may be 1 to 50, preferably 15 to 40, more preferably 20 to 30. Accordingly, the base (110) may be easily manufactured while having a sufficient specific surface area for implementing a capacitor.

[0045] According to an embodiment of the present invention, as illustrated in FIGS. 4 to 7, the first electrode layer (120) is disposed on the first surface (111), the second surface (112) of the base (110) and the inner wall surfaces of the plurality of through holes (TH), the first dielectric layer (130) is disposed on the first electrode layer (120) on the first surface (111), the second surface (112) of the base (110) and the inner wall surfaces of the plurality of through holes (TH), the second electrode layer (140) is disposed on the first dielectric layer (130) on the first surface (111), the second surface (112) of the base (110) and the inner wall surfaces of the plurality of through holes (TH), the first electrode pad (150) is connected to the first electrode layer (120), and the second electrode pad (160) is connected to the second electrode layer (140).

[0046] The capacitance of a capacitor can be calculated according to the following mathematical formula 1.

[0047]

[0048] Here, C is the capacitance, ε is the permittivity, S is the area of ​​the electrode layer, and d is the distance between the electrode layers. According to this, it can be seen that the larger the area of ​​the electrode layer, the greater the capacitance.

[0049] At this time, the first electrode layer (120) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium-tin. For example, the first electrode layer (120) may include TiN, TiO2, MoO x , WO x , may include at least one of ITO and ITGO, wherein x is a positive integer.

[0050] In this way, when the first electrode layer (120) is arranged on the first surface (111), the second surface (112) of the base (110) and the inner wall surface of the through hole (TH), the specific surface area of ​​the capacitor increases, so that a high electrostatic capacitance can be obtained. In addition, since gas can flow through the through hole (TH) during the deposition process of the first electrode layer (120), easy and uniform deposition is possible.

[0051] Next, the first dielectric layer (130) is made of SiO2, Si3N3, SiN4, ZAZ, HfO2, ZrO2, Hf x Zr y O z and may include at least one of Al2O3, wherein x, y, and z are positive integers. When the material of the first dielectric layer (130) satisfies these conditions, it is easy to deposit the first dielectric layer (130) on the first electrode layer (120) with a uniform thickness.

[0052] Next, the second electrode layer (140) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, copper (Cu), and aluminum (Al). For example, the second electrode layer (140) may include TiN, TiO2, MoO x , WO x , may include at least one of ITO, ITGO, Cu and Al, wherein x is a positive integer.

[0053] The material of the second electrode layer (140) may be the same as the material of the first electrode layer (120), but is not limited thereto. That is, the material of the second electrode layer (140) may be different from the material of the first electrode layer (120). For example, the first electrode layer (120) may be deposited using at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium-tin, and the second electrode layer (140) may be plated using Cu or Al.

[0054] As illustrated in FIG. 5, the space between the second electrode layers (140) in the plurality of through holes (TH) may be filled with a filler (400). Here, the filler (400) may be a material having insulating properties and a lower thermal expansion coefficient than the second electrode layer (140). For example, the filler (400) may include Al2O3. Accordingly, even if the temperature of the capacitor (100) increases, the plurality of through holes (TH) do not undergo thermal expansion, so that a capacitor (100) having high reliability can be obtained. Alternatively, the filler (400) may include SiO2. Accordingly, the filler (400) may play a role of passivation.

[0055] Unlike the embodiments of FIGS. 4 and 5 in which the second electrode layer (140) is deposited according to the shape of the first dielectric layer (130), referring to FIG. 6, the second electrode layer (140) may be arranged to fill a plurality of through holes (TH). Accordingly, the overall resistance of the capacitor (100) can be reduced, thereby obtaining a capacitor with a fast response speed.

[0056] Meanwhile, the above description focuses on an example in which a first electrode layer (120), a first dielectric layer (130), and a second electrode layer (140) are sequentially laminated on a base (110), but is not limited thereto. According to an embodiment of the present invention, a dielectric layer and an electrode layer may be further alternately arranged on the second electrode layer (140).

[0057] Referring to FIG. 7, the second dielectric layer (180) is placed on the second electrode layer (140).

[0058] At this time, the second dielectric layer (180) is SiO2, Si3N3, SiN4, ZAZ, HfO2, ZrO2, Hf x Zr y O zand may include at least one of Al2O3, wherein x, y, and z are positive integers. When the material of the second dielectric layer (180) satisfies these conditions, it is easy to deposit the second dielectric layer (140) on the second electrode layer (140) with a uniform thickness.

[0059] Next, the third electrode layer (190) is placed on the second dielectric layer (180).

[0060] At this time, the third electrode layer (190) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, copper (Cu), and aluminum (Al). For example, the third electrode layer (190) may include TiN, TiO2, MoO x , WO x , may include at least one of ITO, ITGO, Cu and Al, wherein x is a positive integer.

[0061] The material of the third electrode layer (190) may be the same as the material of the first electrode layer (120) and the second electrode layer (140), but is not limited thereto. That is, the material of the third electrode layer (190) may be different from the materials of the first electrode layer (120) and the second electrode layer (140). For example, the first electrode layer (120) and the second electrode layer (140) may include titanium (Ti), molybdenum (Mo), tungsten (W), and indium-tin, and the third electrode layer (190) may include Cu or Al. Unlike the embodiment of FIG. 7 in which the third electrode layer (190) is deposited according to the shape of the second dielectric layer (180), the third electrode layer (190) may be arranged to fill a plurality of through holes (TH). According to this, the overall resistance of the capacitor (100) can be reduced, so a capacitor with a fast response speed can be obtained.

[0062] Referring again to FIGS. 2 and 3, according to an embodiment of the present invention, the inner wall surface of the through hole (TH) has a surface structure in the form of fine irregularities or protrusions. According to an embodiment of the present invention, the protrusions on the inner wall surface of the through hole (TH) may have a height (h1) of 1 nm to 50 nm, preferably 10 nm to 30 nm, and more preferably 15 nm to 25 nm. Here, the height (h1) of the protrusion refers to the vertical distance between the highest point and the lowest point of the protrusion, and may refer to the average height of the protrusions formed on the inner wall surface of the through hole (TH). In the present specification, the height of the protrusions may be expressed as surface roughness. Here, the surface roughness may be measured using a surface roughness measuring device, and may also be referred to as surface roughness. The surface roughness measuring device measures a cross-sectional curve using a probe, and may calculate the surface roughness using the peak line, the valley line, the average line, and the reference length of the cross-sectional curve. In this specification, surface roughness may refer to the arithmetic mean roughness (Ra) calculated by the centerline average calculation method. That is, in this specification, the arithmetic mean roughness (Ra) may refer to the average of the absolute values ​​of the lengths from the centerline of the rough surface to the cross-sectional curve within the reference length L. The arithmetic mean roughness (Ra) may be obtained through the following mathematical formula 2.

[0063]

[0064] That is, when the cross-sectional curve obtained using the probe of a surface roughness measuring device is extracted by a reference length L and expressed as a function (f(x)) with the mean line direction as the x-axis and the height direction as the y-axis, the value obtained by mathematical expression 2 can be expressed.

[0065] In this specification, surface roughness may also mean the ten-point average roughness (Rz). The ten-point average roughness (Rz) is obtained by taking a cross-sectional curve as a reference length L and measuring the distance between the fifth highest peak and the fifth deepest valley along a straight line that does not cut the cross-sectional curve horizontally parallel to the mean line of that portion, and expressing the difference in averages.

[0066] According to an embodiment of the present invention, the surface roughness (Ra) of the inner wall surface of the through hole (TH) may be 1 nm to 50 nm, preferably 10 nm to 30 nm, and more preferably 15 nm to 25 nm. If the surface roughness (Ra) of the inner wall surface of the through hole (TH) is within this numerical range, the specific surface area of ​​the inner wall surface of the through hole (TH) increases, so that the bonding force between the inner wall surface of the through hole (TH) and the first electrode layer (120) may increase when the first electrode layer (120) is deposited or plated. However, if the surface roughness (Ra) of the inner wall surface of the through hole (TH) exceeds this numerical range, for example, if a protrusion structure having a height of 100 nm or more is formed on the inner wall surface of the through hole (TH), the leakage current of the capacitor may be concentrated on this protrusion structure, which may deteriorate the quality of the capacitor.

[0067] According to an embodiment of the present invention, at least one of the first surface (111) and the second surface (112) of the base (110) may include a porous region. Here, porosity means a form having a large number of small pores. That at least one of the first surface (111) and the second surface (112) of the base (110) includes a porous region may mean that the porosity of at least one of the first surface (111) and the second surface (112) of the base (110) is greater than the porosity of an intermediate region between the first surface (111) and the second surface (112) of the base (110).

[0068] According to an embodiment of the present invention, the porous region may have the same material as the base (110), but may be porous. For example, the porous region may be a porous silicon region. That is, the porous region may be a silicon layer having a large number of fine pores. Accordingly, the specific surface area of ​​at least one of the first surface (111) and the second surface (112) of the base (110) may be increased. As described above, the first electrode layer (120) is in direct contact with the first surface (111) and the second surface (112) of the base (110). At this time, if at least one of the first surface (111) and the second surface (112) of the base (110) includes a porous region, the bonding force between the porous region and the first electrode layer (120) may be increased.

[0069] The porosity of at least one of the first surface (111) and the second surface (112) of the base (110) may be expressed by surface roughness. According to an embodiment of the present invention, the surface roughness of at least one of the first surface (111) and the second surface (112) of the base (110) may be greater than the surface roughness of the inner wall surface of the through hole (TH). The thickness of the first electrode layer (120) deposited or plated on at least one of the first surface (111) and the second surface (112) of the base (110) may be thicker than the thickness of the first electrode layer (120) deposited on the inner wall surface of the through hole (TH). When the surface roughness of at least one of the first surface (111) and the second surface (112) of the base (110) is greater than the surface roughness of the inner wall surface of the through hole (TH), the first electrode layer (120) can be flatly deposited or plated on at least one of the first surface (111) and the second surface (112) of the base (110).

[0070] According to an embodiment of the present invention, the surface roughness of the first surface (111) of the base (110) may be different from the surface roughness of the second surface (112) of the base (110). For example, the surface roughness of the first surface (111) of the base (110) may be greater than the surface roughness of the second surface (112) of the base (110). When the surface roughness of the first surface (111) of the base (110) is greater than the surface roughness of the second surface (112) of the base (110), the first electrode layer (120) can be flatly deposited or plated on the first surface (111) of the base (110), and it is easy to arrange the first electrode pad (150) and the second electrode pad (160) on the first surface (111) of the base (110). Alternatively, the surface roughness of the first surface (111) of the base (110) may be smaller than the surface roughness of the second surface (112) of the base (110).

[0071] According to an embodiment of the present invention, when the through hole (TH) is divided into an upper region (T), a middle region (M), and a lower region (B) at the same height from the first surface (111) to the second surface (112) of the base (110), the surface roughness of the inner wall surface of the middle region (M) may be 0.9 to 1.1 times, preferably 0.95 to 1.05 times, and more preferably 0.99 to 1.01 times, the surface roughness of the inner wall surface of the upper region (T), and the surface roughness of the inner wall surface of the middle region (M) may be 0.9 to 1.1 times, preferably 0.95 to 1.05 times, and more preferably 0.99 to 1.01 times, the surface roughness of the inner wall surface of the lower region (B). According to this, since the surface roughness of the inner wall surface of the through hole (TH) is uniform from the first surface (111) to the second surface (112), the resistance of the first electrode layer (120) can be maintained uniformly, and a uniform capacitance can be obtained.

[0072] According to an embodiment of the present invention, when the through hole (TH) is divided into an upper region (T), a middle region (M), and a lower region (B) at the same height from the first surface (111) to the second surface (112) of the base (110), the diameter of the middle region (M) may be 0.9 to 1.1 times, preferably 0.95 to 1.05 times, and more preferably 0.99 to 1.01 times, the diameter of the upper region (T), and the diameter of the middle region (M) may be 0.9 to 1.1 times, preferably 0.95 to 1.05 times, and more preferably 0.99 to 1.01 times, the diameter of the lower region (B). According to this, the resistance of the first electrode layer (120) deposited or plated on the inner wall surface of the through hole (TH) can be maintained uniformly, a uniform capacitance can be obtained, and the aspect ratio of the through hole (TH) can be increased to increase the capacity of the capacitor.

[0073] FIG. 8 shows a method for forming a through hole of a base according to an embodiment of the present invention, and FIGS. 9 and 10 are drawings for explaining an etching mechanism in a process for forming a through hole of a base according to an embodiment of the present invention.

[0074] Referring to Fig. 8(a), a silicon substrate is prepared. Here, the silicon substrate may contain silicon at 90% or more, preferably 99% or more, and more preferably 99.999% or more.

[0075] Referring to Fig. 8(b), a metal catalyst is placed on the upper surface of a silicon substrate. Here, the metal catalyst may include at least one of gold (Au), silver (Ag), titanium (Ti), and tungsten (W). The metal catalyst may be ring-shaped. That is, the metal catalyst may be a ring-shaped metal plate having an inner diameter and an outer diameter. Here, a circular ring shape is illustrated, but is not limited thereto, and may be a polygonal ring shape having an outer diameter and an inner diameter, such as a square ring shape or a hexagonal ring shape. To this end, a ring-shaped metal catalyst may be deposited on the silicon substrate through a photoresist process and a lift-off process, but is not limited thereto.

[0076] Referring to Fig. 8(c), a silicon substrate is etched to form a plurality of through holes penetrating the upper and lower surfaces of the base (110). The etching can be performed by a chemical reaction of silicon. For example, when a metal catalyst including at least one of gold (Au), silver (Ag), titanium (Ti), and tungsten (W) is deposited on the upper surface of the silicon substrate and wet etching is performed in an HF and H2O2 environment, etching is performed by an electrochemical reaction of the metal catalyst, silicon, HF, and H2O2. For example, the etching can be performed by the following chemical reaction.

[0077] [Reaction Formula 1]

[0078] 3H2O2+6H + →6H2O+6h +

[0079] [Reaction Formula 2]

[0080] 6h + +2Si+12HF→2H2SiF6+6H + +H2

[0081] That is, 6h generated by reaction scheme 1 on a metal catalyst + can oxidize Si.

[0082] The overall reaction equation can be expressed as shown in the following reaction equation 3.

[0083] [Reaction Formula 3]

[0084] 2Si+12HF+3H2O2→2H2SiF6+6H2O+H2

[0085] Referring to Figure 9, the hole (h) according to reaction formula 1 + ) can oxidize and etch the silicon substrate under the metal catalyst. Accordingly, a porous layer can be formed under the metal catalyst. Referring to Fig. 10 for more detail, when reaction formulas 1 to 3 proceed while the metal catalyst is deposited on the silicon substrate as in Fig. 10(a), the etching starts from the silicon substrate on the lower side of the metal catalyst as in Fig. 10(b), and the etching continues up to the silicon substrate below the metal catalyst as in Fig. 10(c), and a porous layer can be formed on the silicon substrate below the metal catalyst as in Fig. 10(d).

[0086] Referring again to Fig. 8(c), through this process, the silicon substrate is etched according to the ring shape of the metal catalyst, and the area arranged on the inner diameter of the metal catalyst is separated from the silicon substrate in the shape of a cylinder.

[0087] In this way, when a ring-shaped metal catalyst is used, the reaction area is small, so that the electrochemical reaction of the metal catalyst, silicon, HF, and H2O2 proceeds at a high speed, thereby reducing the possibility of formation of protrusions having a height of 100 nm or more on the inner wall of the through-hole, and the inner wall of the through-hole having a surface roughness of 1 to 50 nm can be obtained. In addition, when a ring-shaped metal catalyst is used, the reaction area is small, so that the electrochemical reaction of the metal catalyst, silicon, HF, and H2O2 proceeds at a high speed, thereby reducing the possibility of deformation of the shape of the metal catalyst or changes in the etching condition even when the etching depth increases, and accordingly, the difference between the diameters of the through-holes in the upper region and the lower region may not be large. In addition, when a ring-shaped metal catalyst is used, the problem of the metal catalyst being removed during the etching process can be prevented, and since the metal catalyst is automatically removed after etching, a separate metal catalyst removal process is not required.

[0088] As described with reference to FIGS. 8 to 10, after forming a through hole (TH) in the base (110), deposition of the first electrode layer (120), the dielectric layer (130), and the second electrode layer (130) may be sequentially performed. The first electrode layer (120) may be deposited, for example, using an atomic layer deposition (ALD) process. Using the ALD process, the material of the first electrode layer (120) may be conformally deposited on the first surface (111) of the base (110), the second surface (112) of the base (110), and the inner wall surface of the through hole (TH) in atomic units. Accordingly, the first electrode layer (120) may be uniformly deposited on the first surface (111) of the base (110), the second surface (112) of the base (110), and the inner wall surface of the through hole (TH).

[0089] The first dielectric layer (130) can be deposited, for example, using an ALD process. According to this, the material of the first dielectric layer (130) can be uniformly and conformally deposited on an atomic level on the surface of the first electrode layer (120).

[0090] The second electrode layer (140) can be deposited, for example, using an ALD process. According to this, the material of the second electrode layer (140) can be conformally deposited on the surface of the first dielectric layer (130) at an atomic level. Alternatively, the second electrode layer (140) can be formed on the first dielectric layer (130) by an electrolytic plating process. At this time, the second electrode layer (140) can include Al. When the second electrode layer (140) includes Al, contamination within the chamber can be prevented due to the low silicon diffusion coefficient of Al.

[0091] However, the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) can be deposited by various processes other than the ALD process.

[0092] Next, a first electrode pad (150) is connected on the first electrode layer (120), and a second electrode pad (160) is connected on the second electrode layer (140). In order to connect the first electrode pad (150) to the first electrode layer (120), the second electrode layer (140) and the first dielectric layer (130) may be etched. In addition, the first electrode pad (150) and the second electrode pad (160) may be deposited by sputtering.

[0093] Figures 11 to 13 are SEM images of structures manufactured according to embodiments of the present invention. Figure 11(a) is an SEM image of an upper region of a through hole, Figure 11(b) is an SEM image of a middle region of a through hole, Figure 11(c) is an SEM image of a lower region of a through hole, Figures 12(a) to 12(c) are enlarged SEM images of Figures 11(a) to 11(c), respectively, and Figures 13(a) to 13(c) are enlarged SEM images of Figures 12(a) to 12(c), respectively.

[0094] Referring to FIGS. 11 to 13, it can be seen that a fine protrusion structure having a height of 1 to 50 nm can be obtained on the inner wall surface of a through hole according to an embodiment of the present invention.

[0095] Figures 14 and 15 are cross-sectional views of a capacitor according to another embodiment of the present invention. Duplicate descriptions of the same content as described with reference to Figures 1 to 13 will be omitted.

[0096] Referring to FIG. 14, the capacitor (100) includes a base (110), a first electrode layer (120) disposed on the base (110), a first dielectric layer (130) disposed on the first electrode layer (120), a second electrode layer (140) disposed on the first dielectric layer (130), a first electrode pad (150) connected to the first electrode layer (120), and a second electrode pad (160) connected to the second electrode layer (140).

[0097] In order to place the first electrode pad (150) and the second electrode pad (160), according to an embodiment of the present invention, an insulating layer (200) is further placed on the second electrode layer (140) on the first surface (111) of the base (110). As illustrated, the insulating layer (200) may extend into the through hole (TH) and serve as a filler (400).

[0098] On the second electrode layer (140) of the first surface (111) of the base (110), the insulating layer (200) includes a first opening (200C1) and a second opening (200C2). A first electrode pad (150) may be arranged in the first opening (200C1), and a second electrode pad (160) may be arranged in the second opening (200C2). Accordingly, the second electrode pad (160) arranged in the second opening (200C2) may be connected to the second electrode layer (140). In order to connect the first electrode pad (150) positioned in the first opening (200C1) with the first electrode layer (120), the insulating layer (200) extends along the edge of the first opening (200C1) to the first dielectric layer (130), and the first dielectric layer (130) may include a first hole (130C1) corresponding to the first opening (200C1). Accordingly, the first electrode pad (150) may be connected with the first electrode layer (120).

[0099] When the first electrode pad (150) and the second electrode pad (160) are arranged in this structure, the upper surfaces of the first electrode pad (150) and the second electrode pad (160) can be arranged to have the same height. Accordingly, when the capacitor (100) according to the embodiment of the present invention is mounted on a printed circuit board, there is no need to separately adjust the heights of the first electrode pad (150) and the second electrode pad (160), so the assembly process can be improved, and the bonding strength between the first electrode pad (150) and the second electrode pad (160) and the printed circuit board can be improved.

[0100] Referring to FIG. 15, the capacitor (100) includes a base (110), a first electrode layer (120) disposed on the base (110), a first dielectric layer (130) disposed on the first electrode layer (120), a second electrode layer (140) disposed on the first dielectric layer (130), a second dielectric layer (180) disposed on the second electrode layer (140), a third electrode layer (190) disposed on the second dielectric layer (180), a first electrode pad (150) connected to the first electrode layer (120), a second electrode pad (160) connected to the second electrode layer (140), and a third electrode pad (165) connected to the third electrode layer (190).

[0101] In order to place the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165), according to an embodiment of the present invention, an insulating layer (200) is further placed on the third electrode layer (190) on the first surface (111) of the base (110). As illustrated, the insulating layer (200) may extend into the through hole (TH) to serve as a filler (400).

[0102] On the third electrode layer (190) of the first surface (111) of the base (110), the insulating layer (200) includes a first opening (200C1), a second opening (200C2), and a third opening (200C3). A first electrode pad (150) may be arranged in the first opening (200C1), a second electrode pad (160) may be arranged in the second opening (200C2), and a third electrode pad (165) may be arranged in the third opening (200C3). Accordingly, the third electrode pad (165) arranged in the third opening (200C3) may be connected to the third electrode layer (190).

[0103] In order to connect the first electrode pad (150) disposed in the first opening (200C1) with the first electrode layer (120), the insulating layer (200) may extend along the edge of the first opening (200C1) to the second dielectric layer (180), and the second dielectric layer (180) may include a first hole (180C1) corresponding to the first opening (200C1). In addition, the second dielectric layer (180) may extend along the edge of the first hole (180C1) to the first dielectric layer (130), and the first dielectric layer (130) may include a second hole (130C1) corresponding to the first hole (180C1). Accordingly, the first electrode pad (150) may be connected to the first electrode layer (120).

[0104] In order to connect the second electrode pad (160) positioned in the second opening (200C2) with the second electrode layer (140), the insulating layer (200) extends along the edge of the second opening (200C2) to the second dielectric layer (180), and the second dielectric layer (180) may include a third hole (180C2) corresponding to the second opening (200C2). Accordingly, the second electrode pad (160) may be connected with the second electrode layer (140).

[0105] When the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165) are arranged in this structure, the upper surfaces of the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165) can be arranged to have the same height. Accordingly, when the capacitor (100) according to the embodiment of the present invention is mounted on a printed circuit board, there is no need to separately adjust the heights of the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165), so that the assembly process can be improved, and the bonding strength between the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165) and the printed circuit board can be improved.

[0106] Although the silicon substrate according to the embodiment of the present invention has been described primarily as being applied to a capacitor, it is not limited thereto. The silicon substrate according to the embodiment of the present invention can also be applied to an interposer or MEMS TSV.

[0107] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. A base including a through hole extending from the first side to the second side, which is the opposite side of the first side; A first electrode layer disposed on the first surface, the second surface, and the inner wall surface of the through hole of the base; A first dielectric layer disposed on the first electrode layer on the first surface, the second surface and the inner wall surface of the through hole of the base, and A second electrode layer is disposed on the first dielectric layer on the first surface of the base, the second surface, and the inner wall surface of the through hole, The above base contains silicone, A capacitor having a surface roughness of the inner wall of the above through hole of 1 nm to 50 nm.

2. In paragraph 1, A capacitor wherein at least one of the first surface and the second surface includes a porous region.

3. In paragraph 1, A capacitor in which the surface roughness of at least one of the first surface and the second surface is different from the surface roughness of the inner wall surface of the through hole.

4. In paragraph 3, A capacitor in which the surface roughness of the first surface is different from the surface roughness of the second surface.

5. In paragraph 1, A capacitor in which, when the through hole is divided into an upper region, a middle region, and a lower region at equal heights from the first surface of the base to the second surface, the surface roughness of the inner wall surface of the middle region is 0.9 to 1.1 times the surface roughness of the inner wall surface of the upper region, and is 0.9 to 1.1 times the surface roughness of the inner wall surface of the lower region.

6. In paragraph 1, A capacitor in which, when the through hole is divided into an upper region, a middle region, and a lower region with equal heights from the first surface of the base to the second surface, the diameter of the middle region is 0.9 to 1.1 times the diameter of the upper region, and the diameter of the lower region is 0.9 to 1.1 times the diameter of the lower region.

7. In paragraph 1, A capacitor wherein the first electrode layer and the second electrode layer include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, and copper (Cu).

8. In paragraph 7, A capacitor further comprising a passivation layer disposed on the second electrode layer, wherein the passivation layer comprises SiO2.

9. Including a base including a through hole extending from the first side to the second side, which is the opposite side of the first side; The above base contains silicone, The surface roughness of the inner wall of the above through hole is 1 nm to 50 nm, A silicon substrate in which, when the through hole is divided into an upper region, a middle region, and a lower region at equal heights from the first surface of the base to the second surface, the surface roughness of the inner wall surface of the middle region is 0.9 to 1.1 times the surface roughness of the inner wall surface of the upper region, and is 0.9 to 1.1 times the surface roughness of the inner wall surface of the lower region.

10. Including a base including a through hole penetrating from the first side to the second side which is the opposite side of the first side, The above base contains silicone, The surface roughness of the inner wall of the above through hole is 1 nm to 50 nm, A silicon substrate in which, when the through hole is divided into an upper region, a middle region, and a lower region with equal heights from the first surface of the base to the second surface, the diameter of the middle region is 0.9 to 1.1 times the diameter of the upper region, and is 0.9 to 1.1 times the diameter of the lower region.

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