Display panel and manufacturing method for display panel

Abstract

Disclosed in the application are a display panel and a manufacturing method for a display panel. The display panel comprises an edge portion and a non-edge portion at least partially surrounded by the edge portion. The display panel comprises: a substrate, an array composite layer arranged on the substrate, a plurality of light-emitting diodes (LEDs) arranged on the array composite layer, and an encapsulation layer arranged on the LEDs. At the edge portion, the array composite layer is exposed out of the substrate, and the encapsulation layer is arranged in contact with the substrate. According to the present application, the service life and reliability of the display panel are improved.

Description

Display panel and method for manufacturing the same Technical Field

[0001] The present application relates to the field of display, and in particular to a display panel and a method for manufacturing the display panel. Background Art

[0002] With the development of display technology, display panels have become widely used in our daily lives, such as in mobile phones, computers, and television screens. Micro-LED (Min-LED, Micro-LED, etc.) display panels have been developed. These panels offer generational advantages in brightness, resolution, energy consumption, lifespan, response speed, and thermal stability, and are internationally recognized as the future of display technology.

[0003] However, current micro-LED display panels have the problem of water vapor or oxygen entering the interior from the side, resulting in a reduced lifespan and failure of the micro-LED display panels. Summary of the Invention

[0004] The embodiments of the present application provide a display panel and a method for manufacturing the display panel, which can solve the problem of water vapor or oxygen entering the interior of the current micro-LED display panel from the side, resulting in a reduced lifespan and failure of the micro-LED display panel.

[0005] The present application provides a display panel, comprising an edge portion and a non-edge portion at least partially surrounded by the edge portion, the display panel comprising:

[0006] substrate;

[0007] an array composite layer, disposed on the substrate;

[0008] A plurality of light emitting diodes are arranged on the array composite layer;

[0009] an encapsulation layer, disposed on the light-emitting diode;

[0010] Wherein, at the edge portion, the array composite layer is exposed from the substrate, and the packaging layer is arranged in contact with the substrate.

[0011] Optionally, in some embodiments of the present application, the encapsulation layer includes a cover layer and an optical adhesive layer, the optical adhesive layer is arranged between the cover layer and the light-emitting diode, and at the edge portion, the optical adhesive layer connects the substrate and the cover layer.

[0012] Optionally, in some embodiments of the present application, the display panel includes a frame portion and a display portion at least partially surrounded by the frame portion;

[0013] The edge portion includes a first edge portion, the non-edge portion includes a first non-edge portion, the first edge portion corresponds to the frame portion, and the first non-edge portion corresponds to the display portion.

[0014] Optionally, in some embodiments of the present application, the display panel includes a frame portion and a display portion at least partially surrounded by the frame portion;

[0015] The display portion includes a plurality of light emitting diodes, and at least one opening is provided between at least some adjacent two light emitting diodes;

[0016] The edge portion includes a second edge portion, the non-edge portion includes a second non-edge portion, the second edge portion corresponds to the opening, and the second non-edge portion corresponds to the light emitting diode on one side of the opening.

[0017] Optionally, in some embodiments of the present application, the array composite layer forms a first slope at the boundary between the edge portion and the non-edge portion, the optical adhesive layer covers the first slope, and the angle between the first slope and the base of the edge portion is an obtuse angle.

[0018] Optionally, in some embodiments of the present application, the array composite layer includes a conductive metal oxide layer and a thin film transistor layer, the thin film transistor layer forms a second slope corresponding to the first slope, the metal oxide layer includes a first sub-protection portion, the first sub-protection portion covers the second slope and extends to the edge portion to contact the substrate, and the optical adhesive layer covers the first sub-protection portion.

[0019] Optionally, in some embodiments of the present application, an angle between the second slope and the base at the edge portion is in a range of 110 degrees to 140 degrees.

[0020] Optionally, in some embodiments of the present application, the array composite layer further includes a first insulating layer disposed between the thin film transistor layer and the metal oxide layer, the metal oxide layer includes a second sub-protection portion located in the non-edge portion, and the entire surface of the second sub-protection portion is disposed on the first insulating layer.

[0021] Optionally, in some embodiments of the present application, the first insulating layer is a planar layer of an organic material.

[0022] Optionally, in some embodiments of the present application, the layer structure of the thin film transistor layer includes:

[0023] A plurality of thin film transistors are provided on the substrate, wherein the thin film transistors at least include a semiconductor layer, a gate insulating layer, a gate, a source electrode, and a drain electrode;

[0024] The first insulating layer is provided on a side of the plurality of thin film transistors facing away from the substrate;

[0025] a plurality of first through holes, at least penetrating the first insulating layer;

[0026] The first metal layer is arranged on a side of the first insulating layer away from the substrate. The first metal layer includes a plurality of pads. At least some of the pads are connected to the drain electrodes of the corresponding thin film transistors through the first through holes.

[0027] Optionally, in some embodiments of the present application, the metal oxide layer further includes a third sub-protection portion, and the third sub-protection portion covers the first metal layer.

[0028] Optionally, in some embodiments of the present application, the third sub-protection portion includes a plurality of protection members, the protection members cover the corresponding pads, and the light-emitting diodes are connected to the corresponding pads through the protection members.

[0029] Optionally, in some embodiments of the present application, the thin film transistor layer further includes:

[0030] The second insulating layer is disposed between the plurality of thin film transistors and the first insulating layer. The second insulating layer is made of an inorganic material, the first insulating layer is made of an organic material, and the first through hole also penetrates the second insulating layer.

[0031] Accordingly, an embodiment of the present application further provides a method for manufacturing a display panel, which includes the following steps:

[0032] providing a substrate;

[0033] forming an array composite layer on the substrate, wherein the array composite layer exposes the substrate and forms a first slope, wherein the first slope divides the display panel into an edge portion and a non-edge portion at least partially surrounded by the edge portion;

[0034] transferring a plurality of light emitting diodes onto the array composite layer;

[0035] A packaging layer is manufactured on the light emitting diode, and the packaging layer is arranged in contact with the substrate at the edge portion.

[0036] Optionally, in some embodiments of the present application, the manufacturing of the encapsulation layer on the light-emitting diode includes: providing a cover layer and an optical adhesive layer on the light-emitting diode;

[0037] The optical adhesive layer is disposed between the cover layer and the light-emitting diode. At the edge portion, the optical adhesive layer contacts the substrate and connects the substrate and the cover layer.

[0038] Optionally, in some embodiments of the present application, the forming of the array composite layer includes the following steps:

[0039] forming a thin film transistor layer on the substrate, and forming a first insulating layer on the thin film transistor layer, wherein the thin film transistor layer includes a plurality of thin film transistors disposed on the substrate and a second insulating layer disposed on the plurality of thin film transistors, wherein the second insulating layer is an inorganic material and the first insulating layer is an organic material, and the thin film transistors include at least a semiconductor layer, a gate insulating layer, a gate, a source electrode, and a drain electrode;

[0040] Opening a first through hole in the first insulating layer, and removing the first insulating layer at the edge portion;

[0041] Opening a hole in the second insulating layer so that the first through hole also penetrates the second insulating layer, and simultaneously removing the second insulating layer and other film layers in the array composite layer at the edge portion;

[0042] The first insulating layer, the second insulating layer and other film layers in the array composite layer form a second slope at the edge portion.

[0043] Optionally, in some embodiments of the present application, when forming the array composite layer, the following steps are further included after opening the holes in the second insulating layer:

[0044] A first metal layer is formed on the first insulating layer. The first metal layer is patterned to form a plurality of pads. At least some of the pads are electrically connected to the drain electrode through the first through-hole.

[0045] Optionally, in some embodiments of the present application, when forming the array composite layer, the following steps are further included after forming the first metal layer on the first insulating layer:

[0046] A metal oxide layer is formed on the first metal layer, and the metal oxide layer is patterned to form a first sub-protection portion, a second sub-protection portion, and a third sub-protection portion. The first sub-protection portion covers the second slope to form the first slope, and extends to the edge portion to contact the substrate. The entire surface of the second sub-protection portion is arranged on the first insulating layer. The third sub-protection portion covers the first metal layer. The third sub-protection portion includes a plurality of protective parts, and the protective parts cover the corresponding pads. Beneficial effects

[0047] In an embodiment of the present application, a display panel and a method for manufacturing the display panel are provided. The display panel includes an edge portion and a non-edge portion at least partially surrounded by the edge portion. The display panel includes: a substrate; an array composite layer disposed on the substrate; a plurality of light-emitting diodes disposed on the array composite layer; and an encapsulation layer disposed on the light-emitting diodes. In the edge portion, the array composite layer is exposed to the substrate, and the encapsulation layer is disposed in contact with the substrate. In the present application, in the edge portion, the array composite layer is exposed to the substrate, and the encapsulation layer is disposed in contact with the substrate, forming an encapsulation sealing structure of the encapsulation layer and the substrate. When the sealing structure is located between the frame portion and the display portion, it prevents the array composite layer from being exposed at the side end of the display panel, and can prevent water vapor or oxygen from diffusing or transmitting through the array composite layer to the interior of the display panel, thereby improving the life and reliability of the display panel. At the same time, when the sealing structure is located between two adjacent pixels or light-emitting diodes in the display portion, the sealing structure blocks the channel for water vapor or oxygen to diffuse or transmit, preventing the expansion of display defects, thereby improving the life and reliability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0049] FIG1 is a first plan view of a first display panel provided in Example 1 of the present application;

[0050] FIG2 is a second schematic plan view of the first display panel provided in Example 1 of the present application;

[0051] FIG3 is a schematic cross-sectional view of a partial structure of a first display panel provided in Example 1 of the present application;

[0052] FIG4 is a partial plan view of a second display panel provided in Example 1 of the present application;

[0053] FIG5 is a schematic cross-sectional view taken along the dashed line DD in FIG4 ;

[0054] FIG6 is a schematic diagram of the process steps of a method for manufacturing a display panel provided in Example 2 of the present application;

[0055] FIG7 is a schematic diagram of another process step of a method for manufacturing a display panel provided in Example 2 of the present application;

[0056] FIG8 is a schematic diagram of a first intermediate process of a method for manufacturing a display panel provided in Example 2 of the present application;

[0057] FIG9 is a schematic diagram of a second intermediate process of a method for manufacturing a display panel provided in Example 2 of the present application;

[0058] FIG10 is a schematic diagram of a third intermediate process of a method for manufacturing a display panel provided in Example 2 of the present application;

[0059] FIG11 is a schematic diagram of a fourth intermediate process of a method for manufacturing a display panel provided in Example 2 of the present application;

[0060] FIG12 is a schematic diagram of a fifth intermediate process of a method for manufacturing a display panel provided in the second embodiment of the present application. Modes for Carrying Out the Invention

[0061] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0062] An embodiment of the present application provides a display panel, comprising an edge portion and a non-edge portion at least partially surrounded by the edge portion, the display panel comprising: a substrate; an array composite layer disposed on the substrate; a plurality of light-emitting diodes disposed on the array composite layer; and an encapsulation layer disposed on the light-emitting diodes; wherein, at the edge portion, the array composite layer is exposed from the substrate, and the encapsulation layer is disposed in contact with the substrate.

[0063] The present application also provides a method for manufacturing the above-mentioned display panel. Detailed descriptions are given below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0064] Example 1

[0065] Please refer to Figures 1 to 5. Figure 1 is a first planar schematic diagram of the first display panel provided in Example 1 of the present application; Figure 2 is a second planar schematic diagram of the first display panel provided in Example 1 of the present application; Figure 3 is a cross-sectional schematic diagram of a partial structure of the first display panel provided in Example 1 of the present application; Figure 4 is a partial planar schematic diagram of the second display panel provided in Example 1 of the present application; and Figure 5 is a cross-sectional schematic diagram along the DD dotted line in Figure 4. Figures 1 to 3 illustrate the first display panel. Compared to Figure 1, Figure 2 illustrates the shape of the metal oxide layer. Figures 4 and 5 illustrate the second display panel. The embodiment features of the first display panel can be combined with the embodiment features of the second display panel.

[0066] An embodiment of the present application provides a display panel 100, which includes an edge portion 100B and a non-edge portion 100A at least partially surrounded by the edge portion 100B. The display panel 100 includes a substrate 11, an array composite layer 101Z, a plurality of light-emitting diodes 30, and an encapsulation layer 431; the array composite layer 101Z is arranged on the substrate 11; the plurality of light-emitting diodes 30 are arranged on the array composite layer 101Z; the encapsulation layer 431 is arranged on the light-emitting diodes 30; wherein, at the edge portion 100B, the array composite layer 101Z is exposed to the substrate 11, and the encapsulation layer 431 is arranged in contact with the substrate 11.

[0067] Specifically, the substrate 11 may be a glass substrate, but is not limited thereto.

[0068] In this embodiment, at the edge portion 100B, the array composite layer 101Z is exposed to the substrate 11, and the encapsulation layer 431 is arranged in contact with the substrate 11, forming an encapsulation sealing structure of the encapsulation layer 431 and the substrate 11. When this sealing structure is located between the frame portion BB and the display portion AA, it avoids the array composite layer 101Z from being exposed at the side end of the display panel 100, and can prevent water vapor or oxygen from diffusing or being transmitted to the interior of the display panel 100 through the array composite layer 101Z, thereby improving the life and reliability of the display panel 100; at the same time, when this sealing structure is located between two adjacent pixels or light-emitting diodes 30 in the display portion AA, the sealing structure blocks the channel for water vapor or oxygen to diffuse or be transmitted, thereby avoiding the expansion of display defects, thereby improving the life and reliability of the display panel.

[0069] In some embodiments, the encapsulation layer 431 includes a cover layer 40 and an optical adhesive layer 31 . The optical adhesive layer 31 is disposed between the cover layer 40 and the light-emitting diode 30 . At the edge portion 100B, the optical adhesive layer 31 connects the substrate 11 and the cover layer 40 .

[0070] Specifically, the optical adhesive layer 31 may be an optically clear adhesive (OCA) or an optically clear resin (OCR).

[0071] Specifically, the cover plate layer 40 may be a glass cover plate, a metal cover plate, or a ceramic cover plate, which is not limited here.

[0072] Specifically, at the edge portion 100B, the optical adhesive layer 31 connects the substrate 11 and the cover layer 40 to form a package sealing structure.

[0073] Referring to the first display panel in Figures 1 to 3, in some embodiments, the display panel 100 includes a frame portion BB and a display portion AA at least partially surrounded by the frame portion BB; the edge portion 100B includes a first edge portion 101B, and the non-edge portion 100A includes a first non-edge portion 101A, the first edge portion 101B corresponds to the frame portion BB, and the first non-edge portion 101A corresponds to the display portion AA.

[0074] Specifically, as shown in Figures 1 to 3, the first edge portion 101B corresponds to the frame portion BB, and the first non-edge portion 101A corresponds to the display portion AA, that is, in the edge portion 100B, the array composite layer 101Z is retracted relative to the substrate 11, and the encapsulation layer 431 is arranged in contact with the substrate 11.

[0075] Specifically, as shown in FIG1 , the display panel 100 includes an edge portion 100B (or a first edge portion 101B) and a non-edge portion 100A (or a first non-edge portion 101A). The edge portion 100B surrounds or partially surrounds the non-edge portion 100A. The boundary between the edge portion 100B and the non-edge portion 100A in FIG1 is the first slope 101 or / and the second slope 102 described in subsequent embodiments.

[0076] Specifically, the array composite layer 101Z may include structures such as a driving circuit and wiring for driving the micro-LEDs 30 to emit light.

[0077] Specifically, the display panel 100 includes a plurality of light emitting diodes 30 disposed on a substrate 11 . The light emitting diodes 30 may serve as light sources for the backlight of the display panel, or may serve as part of a sub-pixel for directly displaying an image on the display panel.

[0078] Specifically, as shown in FIG. 1 , the first edge portion 101B refers to a portion close to a side end of the display panel 100 . Usually, the first edge portion 101B is located in a non-display area or a frame portion BB.

[0079] Specifically, the non-edge portion 100A may include a display portion AA or a finger display portion AA.

[0080] Specifically, the first edge portion 101B partially surrounds the first non-edge portion 101A, or the first edge portion 101B surrounds the first non-edge portion 101A. Specifically, the array composite layer 101Z is retracted relative to the substrate 11, which means that on the plane of the display panel, the edge of the array composite layer 101Z does not overlap with the edge of the substrate 11, and the edge of the array composite layer 101Z is located on the side of the edge of the substrate 11 closer to the center of the substrate 11.

[0081] Specifically, the array composite layer 101Z is retracted relative to the substrate 11 , which means that on the plane of the display panel, the edge of the substrate 11 is located outside the edge of the array composite layer 101Z.

[0082] In this embodiment, at the edge portion 100B, the array composite layer 101Z is retracted relative to the substrate 11 so as to expose the substrate 11, and the encapsulation layer 431 is arranged in contact with the substrate 11, thereby preventing the array composite layer 101Z from being exposed at the side end of the display panel 100. This can prevent and isolate water vapor or oxygen from diffusing or being transmitted through the array composite layer 101Z to the interior of the display panel 100, thereby improving the life and reliability of the display panel.

[0083] Referring to Figures 4 and 5, in some embodiments, the display panel 100 includes a frame portion BB and a display portion AA at least partially surrounded by the frame portion BB; the display portion AA includes a plurality of light-emitting diodes 30, and at least one opening 301 is provided between at least partially adjacent two light-emitting diodes 30; the edge portion 100B includes a second edge portion 102B, and the non-edge portion 100A includes a second non-edge portion 102A, the second edge portion 102B corresponds to the opening 301, and the second non-edge portion 102A corresponds to the light-emitting diodes 30 on one side of the opening 301.

[0084] Specifically, at least one opening 301 is provided between at least two adjacent light emitting diodes 30 , that is, the display panel 100 includes at least one opening 301 .

[0085] Specifically, the second edge portion 102B corresponds to the opening 301, and the second non-edge portion 102A corresponds to the light-emitting diode 30 on one side of the opening 301. That is, in this embodiment, the edge portion 100B or the second edge portion 102B is arranged between two adjacent sub-pixels or two adjacent light-emitting diodes 30 in the display portion AA. Since the two adjacent light-emitting diodes 30 may need to be driven by the same scan line, the same data line, or the same routing, it is difficult to set the second edge portion 102B to completely surround the corresponding sub-pixels or light-emitting diodes 30. Therefore, it is necessary to form the second edge portion 102B by setting the opening 301.

[0086] Specifically, as shown in Figures 4 and 5, the display panel 100 includes an edge portion 100B (or a second edge portion 102B) and a non-edge portion 100A (or a second non-edge portion 102A). The edge portion 100B surrounds or partially surrounds the non-edge portion 100A. The boundary between the edge portion 100B and the non-edge portion 100A in Figure 4 is the first slope 101 and / or the second slope 102 introduced in subsequent embodiments. The boundary between the edge portion 100B and the non-edge portion 100A in Figure 4 is also the edge of the opening 301.

[0087] Specifically, as shown in Figures 4 and 5, at the edge portion 100B (or the second edge portion 102B), the array composite layer 101Z is exposed to the substrate 11, and the encapsulation layer 431 is arranged in contact with the substrate 11, forming an encapsulation sealing structure of the encapsulation layer 431 and the substrate 11. When this sealing structure is located between two adjacent pixels or light-emitting diodes 30 in the display portion AA, the sealing structure blocks the channel for the diffusion or transmission of water vapor or oxygen, avoiding the expansion of display defects, thereby improving the life and reliability of the display panel.

[0088] In this embodiment, the first display panel 100 shown in Figures 1 to 3 and the second display panel shown in Figures 4 and 5 are introduced, but the first edge portion 101B in the first display panel and the second edge portion 102B in the second display panel can be set in the same display panel. In this case, the beneficial effects of both are achieved at the same time.

[0089] Since the division between the first edge portion 101B and the first non-edge portion 101A in the above embodiment is the same as the division between the second edge portion 102B and the second non-edge portion 102A, in this embodiment, the structure is described in detail with reference to the edge portion 100B and the non-edge portion 100A.

[0090] In some embodiments, as shown in Figures 1 to 5, the array composite layer 101Z forms a first slope 101 at the boundary between the edge portion 100B and the non-edge portion 100A, the optical adhesive layer 31 covers the first slope 101, and the angle between the first slope 101 and the substrate 11 of the edge portion 100B is an obtuse angle.

[0091] Specifically, the array composite layer 101Z shrinks to form a first slope 101 , and the angle between the first slope 101 and the substrate 11 at the edge portion 100B is an obtuse angle, which can prevent air bubbles from forming between the optical adhesive layer 31 and the array composite layer 101Z when the optical adhesive layer 31 is attached.

[0092] Specifically, as shown in Figures 3 and 5, the first slope 101 or the extension line of the first slope 101 intersects with the base 11, and the angle between the first slope 101 and the edge portion 100B of the base 11 refers to the angle located at the edge portion 100B, or refers to the angle of the first slope 101 away from the non-edge portion 100A side.

[0093] 3 and 5 , the first slope 101 divides the display panel into an edge portion 100B and a non-edge portion 100A. On the plane of the display panel, the side of the first slope 101 close to the light emitting diode 30 is the non-edge portion 100A, and the side of the first slope 101 away from the light emitting diode 30 is the edge portion 100B.

[0094] In some embodiments, the array composite layer 101Z includes a conductive metal oxide layer 22 and a thin-film transistor layer 101Y. The thin-film transistor layer 101Y forms a second slope 102 corresponding to the first slope 101. The metal oxide layer 22 includes a first sub-protecting portion 221. The first sub-protecting portion 221 covers the second slope 102 and extends to the edge portion 100B to contact the substrate 11. The optical adhesive layer 31 covers the first sub-protecting portion 221. In addition, the optical adhesive layer 31 may further cover the portion of the substrate 11 that protrudes from the first sub-protecting portion 221 on the plane of the display panel.

[0095] Specifically, the portion of the substrate 11 that protrudes relative to the first sub-protecting portion 221 on the plane of the display panel means that on the plane of the display panel, the first sub-protecting portion 221 is retracted relative to the substrate 11, and the substrate 11 protrudes relative to the first sub-protecting portion 221. The protruding portion is the portion of the substrate 11 that protrudes relative to the first sub-protecting portion 221 on the plane of the display panel.

[0096] Specifically, the thin film transistor layer 101Y refers to a plurality of film layers between the metal oxide layer 22 and the substrate 11 , and the thin film transistor layer 101Y may include a plurality of thin film transistors 103 .

[0097] Specifically, the conductive metal oxide layer 22 may be indium tin oxide (ITO).

[0098] Specifically, as shown in FIG. 2 and FIG. 3 , in the first display panel, the metal oxide layer 22 is provided on the entire surface. The metal oxide layer 22 includes oxide openings 220 corresponding to the light-emitting diodes 30 or pads. The oxide openings 220 expose the pads connected to the light-emitting diodes 30 .

[0099] Specifically, the first sub-protection portion 221 covers the second slope 102 and extends to the edge portion 100B to contact the substrate 11. The first sub-protection portion 221 has good water vapor and oxygen blocking capabilities, which can prevent the thin film transistor layer 101Y from being exposed at the edge portion 100B or forming a barrier to block the propagation of water vapor and oxygen, preventing water vapor or oxygen from entering the interior of the display panel through the thin film transistor layer 101Y, or preventing water vapor or oxygen from being transmitted through the thin film transistor layer 101Y inside the display panel, thereby improving the life and reliability of the display panel.

[0100] Specifically, the first sub-protecting portion 221 covers the second slope 102 and extends to the edge portion 100B to contact the substrate 11 , thereby blocking the diffusion path of water vapor or oxygen and isolating water vapor or oxygen.

[0101] In some embodiments, the included angle between the second slope 102 and the base 11 of the edge portion 100B is in a range of 110 degrees to 140 degrees.

[0102] Specifically, the angle α between the second slope 102 and the substrate 11 of the edge portion 100B is in the range of 110 degrees to 140 degrees, which allows the first sub-protective portion 221 to well cover or adhere to the second slope 102 and extend to the edge portion 100B to contact the substrate 11, thereby improving the coverage and contact performance of the metal oxide layer 22 and avoiding the generation of cracks.

[0103] In some embodiments, the array composite layer 101Z further includes a first insulating layer 20 disposed between the thin film transistor layer 101Y and the metal oxide layer 22 , the metal oxide layer 22 includes a second sub-protection portion 222 located in the non-edge portion 100A, and the entire second sub-protection portion 222 is disposed on the first insulating layer 20 .

[0104] Specifically, the entire surface of the second sub-protection portion 222 is arranged on the first insulating layer 20, which can further block water vapor or oxygen. The second sub-protection portion 222 acts as a protective layer. Even if water vapor or oxygen enters the optical adhesive layer 31, the second sub-protection portion 222 can also block water vapor or oxygen from entering the thin film transistor 103.

[0105] In some embodiments, the first insulating layer 20 is a planar layer of organic material.

[0106] Specifically, the first insulating layer 20 is a planar layer of an organic material, which can play a planarization role, so that the metal oxide layer 22 is well attached to the thin film transistor layer 101Y without the occurrence of unexpected cracks.

[0107] In some embodiments, the layer structure of the thin film transistor layer 101Y includes multiple thin film transistors 103, a first insulating layer 20, multiple first through holes 201 and a first metal layer 21; multiple thin film transistors 103 are arranged on the substrate 11, and the thin film transistors 103 at least include a semiconductor layer 14, a gate insulating layer 15, a gate 16, a source 181 and a drain 182; the first insulating layer 20 is arranged on the side of the multiple thin film transistors 103 away from the substrate 11; the multiple first through holes 201 at least penetrate the first insulating layer 20; the first metal layer 21 is arranged on the side of the first insulating layer 20 away from the substrate 11, and the first metal layer 21 includes multiple pads, and at least some of the pads are connected to the drain 182 of the corresponding thin film transistor 103 through the first through hole 201.

[0108] Specifically, the plurality of pads include a first pad 211 and a second pad 212 , and two electrodes of the micro light emitting diode 30 are connected to the corresponding first pad 211 and the corresponding second pad 212 , respectively.

[0109] Specifically, the thin film transistor 103 drives the corresponding micro light emitting diode 30 to emit light.

[0110] In some embodiments, the metal oxide layer 22 further includes a third sub-protecting portion 223 , and the third sub-protecting portion 223 covers the first metal layer 21 .

[0111] Specifically, the metal oxide layer 22 has good electrical conductivity and water vapor or oxygen barrier properties. The third sub-protection portion 223 covers the first metal layer 21. The third sub-protection portion 223 plays the role of the first metal layer 21. Even if water vapor or oxygen enters the interior of the display panel, the third sub-protection portion 223 can prevent the first metal layer 21 from being oxidized or corroded.

[0112] In some embodiments, the thin film transistor layer 101Y also includes a second insulating layer 19, which is arranged between the multiple thin film transistors 103 and the first insulating layer 20. The second insulating layer 19 is an inorganic material, the first insulating layer 20 is an organic material, and the first through hole 201 also penetrates the second insulating layer 19.

[0113] Specifically, the first insulating layer 20 is an organic material, which provides a flat attachment surface for the metal oxide layer 22 and good flatness for the micro-LEDs 30 , thereby improving the transfer yield of the micro-LEDs.

[0114] Specifically, the second insulating layer 19 is made of an inorganic material and has good water vapor or oxygen barrier properties. Even if water vapor or oxygen enters the display panel, the second insulating layer 19 can prevent water vapor or oxygen from entering the thin film transistor 103 .

[0115] It should be noted that the layer structure of the display panel 100 shown in Figures 3 and 5 includes the following stacked in sequence: substrate 11, light shielding layer 12, buffer layer 13, semiconductor layer 14, gate insulating layer 15, gate 16, interlayer insulating layer 17, source / drain metal layer 18, second insulating layer 19, first insulating layer 20, first metal layer 21, metal oxide layer 22, micro-LEDs 30, optical adhesive layer 31, and cover layer 40. The source / drain metal layer 18 is patterned to form a source electrode 181 and a drain electrode 182.

[0116] Example 2

[0117] Please refer to Figures 6 to 11, Figure 6 is a schematic diagram of the process steps of a method for manufacturing a display panel provided in Example 2 of the present application; Figure 7 is a schematic diagram of another process step of a method for manufacturing a display panel provided in Example 2 of the present application; Figure 8 is a schematic diagram of a first intermediate process of a method for manufacturing a display panel provided in Example 2 of the present application; Figure 9 is a schematic diagram of a second intermediate process of a method for manufacturing a display panel provided in Example 2 of the present application; Figure 10 is a schematic diagram of a third intermediate process of a method for manufacturing a display panel provided in Example 2 of the present application; Figure 11 is a schematic diagram of a fourth intermediate process of a method for manufacturing a display panel provided in Example 2 of the present application; Figure 12 is a schematic diagram of a fifth intermediate process of a method for manufacturing a display panel provided in Example 2 of the present application.

[0118] The display panel 100 in any of the above embodiments can be manufactured using the display panel manufacturing method of this embodiment.

[0119] Specifically, as shown in FIG6 , this embodiment provides a method for manufacturing a display panel, including steps: S100 , S200 , S300 , and S400 .

[0120] S100, providing a substrate.

[0121] Specifically, a substrate 11 is provided.

[0122] S200 , forming an array composite layer on a substrate, wherein the array composite layer leaks out of the substrate and forms a first slope, wherein the first slope divides the display panel into an edge portion and a non-edge portion at least partially surrounded by the edge portion.

[0123] Specifically, an array composite layer 101Z is formed on the substrate 11 and is retracted relative to the substrate 11 to form a first slope 101 . The first slope 101 divides the display panel 100 into an edge portion 100B and a non-edge portion 100A at least partially surrounded by the edge portion 100B.

[0124] S300 , transferring a plurality of light emitting diodes onto the array composite layer.

[0125] Specifically, a plurality of light emitting diodes 30 are transferred onto the array composite layer 101Z.

[0126] S400 , manufacturing a packaging layer on the light emitting diode, wherein the packaging layer contacts the substrate at the edge.

[0127] Specifically, the encapsulation layer 431 is manufactured on the light emitting diode 30 , and the encapsulation layer 431 is disposed in contact with the substrate 11 at the edge portion 100B.

[0128] In some embodiments, manufacturing a packaging layer on a light-emitting diode includes: setting a cover layer 40 and an optical adhesive layer 31 on the light-emitting diode 30; wherein the optical adhesive layer 31 is set between the cover layer 40 and the light-emitting diode 30, and at the edge portion 100B, the optical adhesive layer 31 contacts the substrate and is connected to the substrate 11 and the cover layer 40.

[0129] In some embodiments, as shown in FIG. 7 , forming the array composite layer includes the following steps: S210 , S220 , and S230 .

[0130] S210, forming a thin film transistor layer on the substrate, and forming a first insulating layer on the thin film transistor layer, the thin film transistor layer includes a plurality of thin film transistors arranged on the substrate, and a second insulating layer arranged on the plurality of thin film transistors, the second insulating layer is an inorganic material, the first insulating layer is an organic material, and the thin film transistor includes at least a semiconductor layer, a gate insulating layer, a gate, a source electrode and a drain electrode.

[0131] Specifically, as shown in Figure 8, a thin film transistor layer 101Y is formed on the substrate 11, and a first insulating layer 20 is formed on the thin film transistor layer 101Y. The thin film transistor layer 101Y includes a plurality of thin film transistors 103 arranged on the substrate 11 and a second insulating layer 19 arranged on the plurality of thin film transistors 103. The second insulating layer 19 is an inorganic material, and the first insulating layer 20 is an organic material. The thin film transistor 103 includes at least a semiconductor layer 14, a gate insulating layer 15, a gate 16, a source electrode 181 and a drain electrode 182.

[0132] S220 , forming a first through hole 201 in the first insulating layer, and removing the first insulating layer at the edge portion 100B.

[0133] Specifically, as shown in FIG. 9 , a first through hole 201 is formed in the first insulating layer 20 , and the first insulating layer 20 is removed at the edge portion 100B.

[0134] S230, opening a hole in the second insulating layer so that the first through hole also penetrates the second insulating layer, and simultaneously removing the second insulating layer and other film layers in the array composite layer at the edge; wherein the first insulating layer, the second insulating layer and other film layers in the array composite layer form a second slope at the edge.

[0135] Specifically, as shown in Figure 10, a hole is opened on the second insulating layer 19 so that the first through hole 201 also penetrates the second insulating layer 19, and at the same time, the second insulating layer 19 and other film layers in the array composite layer 101Z are removed at the edge portion 100B; wherein, the first insulating layer 20, the second insulating layer 19 and other film layers in the array composite layer 101Z form a second slope 102 at the edge portion 100B.

[0136] In some embodiments, as shown in Figure 11, when forming the array composite layer 101Z, the following steps are also included after opening a hole in the second insulating layer 19: forming a first metal layer 21 on the first insulating layer 20, patterning the first metal layer 21 to form a plurality of pads 211, and at least some of the pads 211 are electrically connected to the drain 182 through the first through hole 201.

[0137] In some embodiments, as shown in Figure 12, when forming the array composite layer 101Z, it also includes the following steps after forming the first metal layer 21 on the first insulating layer 20: forming a metal oxide layer 22 on the first metal layer 21, and patterning the metal oxide layer 22 to form a first sub-protection portion 221, a second sub-protection portion 222 and a third sub-protection portion 223, the first sub-protection portion 221 covers the second slope 102 to form the first slope 101, and extends to the edge portion 100B to contact the substrate 11, the second sub-protection portion 222 is entirely arranged on the first insulating layer 20, the third sub-protection portion 223 covers the first metal layer 21, and the third sub-protection portion 223 includes a plurality of protective parts, and the protective parts cover the corresponding pads.

[0138] This embodiment has the same beneficial effects as the first embodiment, which will not be described in detail here.

[0139] The above is a detailed introduction to a display panel and a method for manufacturing a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, wherein: The display panel comprises an edge portion and a non-edge portion at least partially surrounded by the edge portion, and comprises: substrate; An array composite layer is disposed on the substrate; A plurality of light emitting diodes are arranged on the array composite layer; An encapsulation layer, disposed on the light emitting diode; Wherein, at the edge portion, the array composite layer is exposed from the substrate, and the packaging layer is arranged in contact with the substrate.

2. The display panel according to claim 1, wherein: The packaging layer includes a cover layer and an optical adhesive layer. The optical adhesive layer is arranged between the cover layer and the light-emitting diode. At the edge portion, the optical adhesive layer connects the substrate and the cover layer.

3. The display panel according to claim 2, wherein: The display panel comprises a frame portion and a display portion at least partially surrounded by the frame portion; The edge portion includes a first edge portion, the non-edge portion includes a first non-edge portion, the first edge portion corresponds to the frame portion, and the first non-edge portion corresponds to the display portion.

4. The display panel according to claim 2, wherein: The display panel comprises a frame portion and a display portion at least partially surrounded by the frame portion; The display portion includes a plurality of the light emitting diodes, and at least one opening is provided between at least two adjacent light emitting diodes; The edge portion includes a second edge portion, the non-edge portion includes a second non-edge portion, the second edge portion corresponds to the opening, and the second non-edge portion corresponds to the light emitting diode on one side of the opening.

5. The display panel according to claim 2, wherein: The array composite layer forms a first slope at the boundary between the edge portion and the non-edge portion, the optical adhesive layer covers the first slope, and the angle between the first slope and the base of the edge portion is an obtuse angle.

6. The display panel according to claim 5, wherein: The array composite layer includes a conductive metal oxide layer and a thin film transistor layer, the thin film transistor layer forms a second slope corresponding to the first slope, the metal oxide layer includes a first sub-protecting portion, the first sub-protecting portion covers the second slope and extends to the edge portion to contact the substrate, and the optical adhesive layer covers the first sub-protecting portion.

7. The display panel according to claim 6, wherein: An included angle between the second slope and the base at the edge portion is in a range of 110 degrees to 140 degrees.

8. The display panel according to claim 6, wherein: The array composite layer also includes a first insulating layer disposed between the thin film transistor layer and the metal oxide layer. The metal oxide layer includes a second sub-protection portion located at the non-edge portion. The second sub-protection portion is entirely disposed on the first insulating layer.

9. The display panel according to claim 8, wherein: The first insulating layer is a planar layer of organic material.

10. The display panel according to claim 8, wherein: The layer structure of the thin film transistor layer includes: A plurality of thin film transistors are disposed on the substrate, wherein the thin film transistors at least include a semiconductor layer, a gate insulating layer, a gate, a source electrode and a drain electrode; The first insulating layer is disposed on a side of the plurality of thin film transistors away from the substrate; a plurality of first through holes, at least penetrating the first insulating layer; The first metal layer is disposed on a side of the first insulating layer away from the substrate, and the first metal layer includes a plurality of pads, at least some of which are connected to the drain of the corresponding thin film transistor through the first through hole.

11. The display panel according to claim 10, wherein: The metal oxide layer further includes a third sub-protecting portion, and the third sub-protecting portion covers the first metal layer.

12. The display panel according to claim 11, wherein: The third sub-protection portion includes a plurality of protection members, the protection members cover the corresponding pads, and the light-emitting diodes are connected to the corresponding pads through the protection members.

13. The display panel according to claim 10, wherein: The thin film transistor layer further comprises: The second insulating layer is disposed between the plurality of thin film transistors and the first insulating layer. The second insulating layer is made of an inorganic material, the first insulating layer is made of an organic material, and the first through hole also penetrates the second insulating layer.

14. A method for manufacturing a display panel, wherein: The steps include: providing a substrate; forming an array composite layer on the substrate, wherein the array composite layer exposes the substrate and forms a first slope, wherein the first slope divides the display panel into an edge portion and a non-edge portion at least partially surrounded by the edge portion; transferring a plurality of light emitting diodes onto the array composite layer; A packaging layer is manufactured on the light emitting diode, and the packaging layer is arranged in contact with the substrate at the edge portion.

15. The method for manufacturing a display panel according to claim 14, wherein: The manufacturing of the encapsulation layer on the light emitting diode comprises: providing a cover layer and an optical adhesive layer on the light emitting diode; The optical adhesive layer is disposed between the cover layer and the light-emitting diode. At the edge portion, the optical adhesive layer contacts the substrate and connects the substrate and the cover layer.

16. The method for manufacturing a display panel according to claim 15, wherein: When forming the array composite layer, the following steps are included: forming a thin film transistor layer on the substrate, and forming a first insulating layer on the thin film transistor layer, wherein the thin film transistor layer comprises a plurality of thin film transistors arranged on the substrate, and a second insulating layer arranged on the plurality of thin film transistors, wherein the second insulating layer is an inorganic material, and the first insulating layer is an organic material, and the thin film transistor comprises at least a semiconductor layer, a gate insulating layer, a gate, a source electrode, and a drain electrode; Opening a hole in the first insulating layer to form a first through hole, and removing the first insulating layer at the edge portion; Opening a hole in the second insulating layer so that the first through hole also penetrates the second insulating layer, and simultaneously removing the second insulating layer and other film layers in the array composite layer at the edge portion; The first insulating layer, the second insulating layer and other film layers in the array composite layer form a second slope at the edge portion.

17. The method for manufacturing a display panel according to claim 16, wherein: When forming the array composite layer, the following steps are also included after opening a hole in the second insulating layer: A first metal layer is formed on the first insulating layer, and the first metal layer is patterned to form a plurality of pads, at least some of the pads are electrically connected to the drain electrode through the first through hole.

18. The method for manufacturing a display panel according to claim 17, wherein: When forming the array composite layer, the method further includes the following steps after forming the first metal layer on the first insulating layer: A metal oxide layer is formed on the first metal layer, and the metal oxide layer is patterned to form a first sub-protection portion, a second sub-protection portion and a third sub-protection portion, the first sub-protection portion covers the second slope to form the first slope, and extends to the edge portion to contact the substrate, the second sub-protection portion is entirely disposed on the first insulating layer, the third sub-protection portion covers the first metal layer, and the third sub-protection portion includes a plurality of protective members, and the protective members cover the corresponding pads.

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