NANO laminated dielectric film having high dielectric constant and preparation method therefor

Abstract

The present invention relates to the technical field of dielectric film materials. Disclosed are a nano laminated dielectric film having a high dielectric constant and a preparation method therefor. The nano laminated dielectric film structurally comprises a silicon substrate, a bottom electrode protection layer, a transition metal chalcogenide nanolaminate and a top electrode which are arranged from bottom to top, wherein the bottom electrode is arranged between the silicon substrate and the bottom electrode protection layer, the transition metal chalcogenide nanolaminate is arranged above the bottom electrode protection layer, and a top electrode protection layer is arranged between the transition metal chalcogenide nanolaminate and the top electrode; the transition metal chalcogenide nanolaminate is formed by stacking two or three transition metal chalcogenide compounds; and the top electrode protection layer and the bottom electrode protection layer are made of a silicon-aluminum mixture film, and the transition metal chalcogenide nanolaminate material is prepared by means of an atomic layer deposition method. The dielectric film provided in the present invention has the advantages of small size, high dielectric constant, etc.

Description

A nano-laminated dielectric film with high dielectric constant and its preparation method Technical Field

[0001] The present invention relates to the technical field of dielectric film materials, and in particular to a nano-laminated dielectric film with a high dielectric constant and a preparation method thereof. Background Art

[0002] In the past few decades, the rapid development of integrated circuit (IC) methods has greatly promoted the progress of the modern semiconductor industry. The application of metal-oxide-semiconductor (CMOS) methods has greatly improved the performance of integrated circuits and greatly reduced static power consumption, and has become the mainstream method of integrated circuit design.

[0003] Traditional MOSFET devices use thermally grown SiO2 as the dielectric material between the gate electrode and the conductive channel. However, as MOSFET device dimensions continue to shrink and integrated circuit process nodes advance, leakage current, primarily through direct tunneling, begins to appear in the SiO2 gate dielectric. This leakage current increases exponentially as the physical thickness of the SiO2 gate dielectric decreases. The physical thickness of traditional SiO2 gate dielectrics has shrunk to approximately 1.2 nm, just 3–4 atomic layers thick. This thickness has reached its limit, and to continue Moore's Law, new high-k materials are needed to replace SiO2.

[0004] Chinese patent literature discloses a nano-laminated dielectric film with a high dielectric constant and a preparation method thereof, with the authorization announcement number CN108588677B. By the method of ALD deposition, the process parameters of growth are controlled, two semiconductors and insulator materials with very low dielectric constants are combined in the form of nano-laminated layers, and the charge polarization effect at the interface is utilized to obtain a promotion of several dozen times of dielectric constant. Its theory is based on the Maxwell-Wagner effect (i.e., the Maxwell-Wagner effect), in which the movable charges in the semiconductor move to its interface under the action of an external electric field and polarize, generating an electric dipole moment. The multi-layer structure can provide a large number of interfaces for charge polarization, greatly improving the dielectric constant of the material. However, its laminated structure is limited by the properties of the metal oxide material, and the thickness of the sub-layer metal oxide cannot be less than 0.4nm, and the total thickness of the oxide laminate cannot be less than 80nm. Summary of the Invention

[0005] To address the problem that existing metal oxide laminated dielectric materials require a large thickness to achieve a dielectric constant increase of several dozen times, the present invention replaces metal oxides with transition metal chalcogenides. Transition metal chalcogenides are two-dimensional materials belonging to the post-Moore era. Compared with metal oxides, their thickness can be further reduced. A single layer of transition metal chalcogenides can break the 0.4nm limit and still provide charge polarization interfaces at a size less than 0.4nm. Compared with metal oxides, they can provide more charge polarization interfaces at the same thickness, thereby obtaining a small-sized nano-laminated dielectric thin film material with a high dielectric constant.

[0006] The solution adopted by the present invention is: a nano-laminated dielectric film with a high dielectric constant, whose structure includes a silicon substrate, a bottom electrode protection layer, a transition metal sulfide compound nano-laminate and a top electrode arranged from bottom to top, a bottom electrode is arranged between the silicon substrate and the bottom electrode protection layer, the transition metal sulfide compound nano-laminate is arranged above the bottom electrode protection layer, and a top electrode protection layer is arranged between the transition metal sulfide compound nano-laminate and the top electrode.

[0007] Preferably, the bottom electrode protection layer and the top electrode protection layer are both silicon-aluminum mixture films, and the thickness of the silicon-aluminum mixture film is 3-5 nm.

[0008] Preferably, the transition metal chalcogenide in the transition metal chalcogenide nanolaminate is composed of a two-dimensional material, and the two-dimensional material is a parent-child layer structure composed of any two or three of MoS2, La2S2, RuS2, SnS2, ReS2, HfS2, ZrS2, and TiS2.

[0009] Preferably, the structural formula of the transition metal sulfide in the transition metal sulfide nanolaminate is (a-MS2 / b-NS2); wherein a is the thickness of the sublayer material, b is the thickness of the parent layer material, and M and N represent metal elements respectively.

[0010] Preferably, the material of the bottom electrode and the top electrode is one of Au, Pt and Ti, and the thickness of the bottom electrode and the top electrode is 50-100 nm.

[0011] The present invention also provides a method for preparing a nano-laminated dielectric film with a high dielectric constant, comprising the following steps:

[0012] Step 1: Surface pretreatment of the silicon substrate;

[0013] Step 2: The silicon substrate after surface pretreatment is plated with a bottom electrode having a thickness of 50-100 nm by physical vapor deposition;

[0014] Step 3: Using atomic layer deposition to form a 3-5 nm thick silicon-aluminum mixture film on the bottom electrode as a bottom electrode protection layer;

[0015] Step 4: Using tetrakis(dimethylamine)zirconium as a source and di-tert-butyl disulfide as a reaction gas sulfur source, an atomic layer deposition method is used to form a 0.1-1 nm thick parent layer material on the bottom electrode protection layer;

[0016] Step 5: Using tetrakis(dimethylamine)zirconium as a source and di-tert-butyl disulfide as a reaction gas sulfur source, an atomic layer deposition method is used to form a sub-layer material with a thickness of 0.1~1nm on the parent layer material;

[0017] Step 6: Using tetrakis(dimethylamine)zirconium as a source and di-tert-butyl disulfide as a reaction gas sulfur source, an atomic layer deposition method is used to form a mother layer material with a thickness of 0.1-1 nm on the daughter layer material;

[0018] Step 7: Repeat the process from step 5 to step 6, and stack the layers n times to obtain a transition metal chalcogenide nanolayer with a composition of (a-HfS2 / b-ZrS2)n;

[0019] Step 8: Using atomic layer deposition, a top electrode protection layer with a thickness of 3 to 5 nm is formed on the transition metal chalcogenide nanolayer;

[0020] Step 9: Using physical vapor deposition, a 50-100 nm metal top electrode is formed on the top electrode protection layer to obtain a nano-laminated dielectric film with a high dielectric constant.

[0021] Preferably, in step 1, the surface of the silicon substrate is pretreated by ultrasonic treatment in acetone for 15 min, then ultrasonic treatment in ethanol for 15 min, and finally ultrasonic treatment in deionized water for 15 min, and finally drying with a nitrogen gun.

[0022] Preferably, in step 4, step 5 and step 6, the atomic layer deposition method is specifically as follows: tetrakis(dimethylamine)zirconium is used as the source, di-tert-butyl disulfide is used as the reaction gas sulfur source, the temperature is controlled at 200°C, the pulse time of the metal precursor is 0.1~1s, the purge time is 30~90s, the pulse time of di-tert-butyl disulfide is 0.5~1.8s, and n nanolayers are stacked, where n is a positive integer.

[0023] From the above description of the structure of the present invention, it can be seen that compared with the existing method, the present invention has the following advantages:

[0024] 1. The nano-laminated dielectric film prepared by the present invention has a high dielectric constant.

[0025] 2. The present invention uses two-dimensional materials of transition metal sulfides as stacking materials, and the minimum thickness can exceed 0.4nm. When the single layer thickness is less than 0.4nm, there is still a charge polarization interface, and when the total thickness of the stack is less than 80nm, there is still an increase in the dielectric constant by several dozen times.

[0026] 3. Compared with three-dimensional metal oxide material stacks, the transition metal sulfide of the present invention can provide a larger charge polarization area at the same thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0028] FIG1 is a schematic diagram of the structure of a nano-laminated dielectric film with a high dielectric constant prepared by the present invention;

[0029] FIG2 is a dielectric constant diagram of Example 1 of a nano-laminated dielectric film with a high dielectric constant prepared by the present invention;

[0030] FIG3 is a dielectric constant diagram of Example 2 of a nano-laminated dielectric film with a high dielectric constant prepared by the present invention;

[0031] FIG4 is a dielectric constant diagram of Example 3 of a nano-laminated dielectric film with a high dielectric constant prepared by the present invention;

[0032] FIG5 is a dielectric constant diagram of Example 4 of a nano-laminated dielectric film with a high dielectric constant prepared by the present invention;

[0033] FIG6 is a graph showing the loss factor of Example 1 of a nano-laminated dielectric film with a high dielectric constant prepared by the present invention;

[0034] FIG7 is a graph showing the loss factor of Example 2 of a nano-laminated dielectric film with a high dielectric constant prepared by the present invention;

[0035] FIG8 is a graph showing the loss factor of Example 3 of the nano-laminated dielectric film with a high dielectric constant prepared by the present invention;

[0036] FIG9 is a graph showing the loss factor of Example 4 of the nano-laminated dielectric film with a high dielectric constant prepared according to the present invention. DETAILED DESCRIPTION

[0037] It should be noted that, unless there is any conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the embodiments.

[0038] As shown in FIG1 , the present invention provides a high dielectric constant nano-laminated dielectric film, which comprises a silicon substrate 1, a bottom electrode protection layer 3, a transition metal sulfide compound nano-laminated layer 4, and a top electrode 6 arranged from bottom to top. A bottom electrode 2 is arranged between the silicon substrate 1 and the bottom electrode protection layer 3, the transition metal sulfide compound nano-laminated layer 4 is arranged above the bottom electrode protection layer 3, and a top electrode protection layer 5 is arranged between the transition metal sulfide compound nano-laminated layer 4 and the top electrode 6; the bottom electrode protection layer 3 and the top electrode protection layer 5 are both silicon-aluminum mixture films, and the thickness of the silicon-aluminum mixture film is 3 to 5 nm; the transition metal sulfide compound nano-laminated layer The transition metal sulfide in layer 4 is composed of a two-dimensional material, and the two-dimensional material has a parent-child layer structure composed of any two or three of MoS2, La2S2, RuS2, SnS2, ReS2, HfS2, ZrS2, and TiS2; the structural formula of the transition metal sulfide in the transition metal sulfide nanolayer 4 is (a-MS2 / b-NS2); wherein a is the thickness of the sub-layer material, b is the thickness of the parent layer material, and M and N represent metal elements respectively; the materials of the bottom electrode 2 and the top electrode 6 are both one of Au, Pt and Ti, and the thickness of the bottom electrode 2 and the top electrode 6 is 50~100nm.

[0039] Example 1

[0040] As shown in FIG2 and FIG6 , the method provided by the present invention is used to prepare a nano-laminated dielectric film (wherein HfS2 with a thickness of 0.1 nm is used as the sub-layer material and ZrS2 with a thickness of 0.2 nm is used as the parent layer material). The specific process steps are as follows:

[0041] Step 1: Surface pretreatment of the silicon substrate was performed by ultrasonic treatment in acetone for 15 min, ultrasonic treatment in ethanol for 15 min, and finally ultrasonic treatment in deionized water for 15 min, and finally drying with a nitrogen gun;

[0042] Step 2: using physical vapor deposition to deposit a 100 nm thick bottom electrode pt on the surface pretreated silicon substrate;

[0043] Step 3: Using an atomic layer deposition method, a 5 nm thick bottom electrode protection layer is grown on the bottom electrode, wherein the material of the bottom electrode protection layer is a silicon-aluminum mixture thin film;

[0044] Step 4: On the bottom electrode protection layer, an atomic layer deposition method is used, using tetrakis(dimethylamine)zirconium as a source and di-tert-butyl disulfide (TBDS) as a reaction gas sulfur source. At 200°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a parent layer material ZrS2 with a thickness of 0.2nm on the bottom electrode protection layer;

[0045] Step 5: On the parent layer material ZrS2, an atomic layer deposition method is used, using tetrakis(dimethylamine)hafnium as the source and di-tert-butyl disulfide (TBDS) as the reaction gas sulfur source. At 200°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a sub-layer material HfS2 with a thickness of 0.1nm on the parent layer material ZrS2;

[0046] Step 6: On the sub-layer material HfS2, an atomic layer deposition method is used, using tetrakis(dimethylamine)zirconium as a source and di-tert-butyl disulfide (TBDS) as a reaction gas sulfur source. At 200°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a mother layer material ZrS2 with a thickness of 0.2nm on the sub-layer material HfS2;

[0047] Step 7: Repeat steps 5 to 6 for 167 times to obtain a transition metal chalcogenide nanolayer with a thickness of about 50 nm.

[0048] Step 8: forming a top electrode protection layer with a thickness of 5 nm on the transition metal chalcogenide nano-laminate by atomic layer deposition, wherein the material of the top electrode protection layer is a silicon-aluminum mixture thin film;

[0049] Step nine: using a physical vapor deposition method to form a metal top electrode array with a thickness of 100 nm on the top electrode protection layer.

[0050] Example 2

[0051] As shown in FIG3 and FIG7 , the method provided by the present invention is used to prepare a nano-laminated dielectric film (wherein ReS2 with a thickness of 0.1 nm is used as the sub-layer material and MoS2 with a thickness of 0.2 nm is used as the mother layer material). The specific process steps are as follows:

[0052] Step 1: Surface pretreatment of the silicon substrate was performed by ultrasonic treatment in acetone for 15 min, ultrasonic treatment in ethanol for 15 min, and finally ultrasonic treatment in deionized water for 15 min, and finally drying with a nitrogen gun;

[0053] Step 2: Using physical vapor deposition method, a 100nm thick bottom electrode pt is plated on the silicon substrate after surface pretreatment;

[0054] Step 3: Using an atomic layer deposition method, a 5 nm thick bottom electrode protection layer is grown on the bottom electrode; wherein the material of the bottom electrode protection layer is a silicon-aluminum mixture thin film;

[0055] Step 4: On the bottom electrode protection layer, an atomic layer deposition method is used, using molybdenum hexacarbonyl (Mo(CO)6) as a source and di-tert-butyl disulfide (TBDS) as a reaction gas sulfur source. At 250°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a mother layer material MoS2 with a thickness of 0.2nm on the bottom electrode protection layer;

[0056] Step 5: On the mother layer material MoS2, an atomic layer deposition method is used, with ReCl5 as the source and di-tert-butyl disulfide (TBDS) as the reaction gas sulfur source. At 250°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a sub-layer material ReS2 with a thickness of 0.1nm on the mother layer material MoS2;

[0057] Step 6: On the sub-layer material ReS2, an atomic layer deposition method is used, using molybdenum hexacarbonyl (Mo(CO)6) as a source and di-tert-butyl disulfide (TBDS) as a reaction gas sulfur source. At 250°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a mother layer material MoS2 with a thickness of 0.2nm on the sub-layer material ReS2;

[0058] Step 7: Repeat steps 5 to 6 for 167 times to obtain a transition metal chalcogenide nanolayer with a thickness of about 50 nm.

[0059] Step 8: forming a top electrode protection layer with a thickness of 5 nm on the transition metal chalcogenide nano-laminate by atomic layer deposition, wherein the material of the top electrode protection layer is a silicon-aluminum mixture thin film;

[0060] Step nine: using a physical vapor deposition method to form a metal top electrode array with a thickness of 50-100 nm on the top electrode protection layer.

[0061] Example 3

[0062] As shown in FIG4 and FIG8, the method provided by the present invention is used to prepare a nano-laminated dielectric film (wherein HfS2 with a thickness of 0.5 nm is used as the sub-layer material and ZrS2 with a thickness of 0.7 nm is used as the mother layer material). The specific process steps are as follows:

[0063] Step 1: Surface pretreatment of the silicon substrate was performed by ultrasonic treatment in acetone for 15 min, ultrasonic treatment in ethanol for 15 min, and finally ultrasonic treatment in deionized water for 15 min, and then blown dry with a nitrogen gun;

[0064] Step 2: The silicon substrate after surface pretreatment is plated with a 100nm bottom electrode pt by physical vapor deposition;

[0065] Step 3: Using an atomic layer deposition method, a 5 nm thick bottom electrode protection layer is grown on the bottom electrode; wherein the material of the bottom electrode protection layer is a silicon-aluminum mixture thin film;

[0066] Step 4: On the bottom electrode protection layer, an atomic layer deposition method is used, using tetrakis(dimethylamine)zirconium as a source and di-tert-butyl disulfide (TBDS) as a sulfur source. At 200°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a parent layer material ZrS2 with a thickness of 0.7nm on the bottom electrode protection layer;

[0067] Step 5: On the parent layer material ZrS2, an atomic layer deposition method is used, using tetrakis(dimethylamine)hafnium as the source and di-tert-butyl disulfide (TBDS) as the sulfur source. At 200°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a sub-layer material HfS2 with a thickness of 0.5nm on the parent layer material ZrS2;

[0068] Step 6: On the sub-layer material HfS2, an atomic layer deposition method is used, using tetrakis(dimethylamine)zirconium as a source and di-tert-butyl disulfide (TBDS) as a sulfur source. At 200°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a mother layer material ZrS2 with a thickness of 0.7nm on the sub-layer material HfS2;

[0069] Step 7: Repeat steps 5 to 6 for 42 times to obtain a transition metal chalcogenide nanolayer with a thickness of about 50 nm.

[0070] Step 8: forming a top electrode protection layer with a thickness of 5 nm on the transition metal chalcogenide nano-laminate by atomic layer deposition; wherein the material of the top electrode protection layer is a silicon-aluminum mixture thin film;

[0071] Step nine: using a physical vapor deposition method to form a metal top electrode array with a thickness of 100 nm on the top electrode protection layer.

[0072] Example 4

[0073] As shown in FIG5 and FIG9, the method provided by the present invention is used to prepare a nano-laminated dielectric film (wherein, a 0.5 nm thick ReS 2 As the sub-layer material, 0.7nm thick MoS2 is used as the mother layer material). The specific process steps are as follows:

[0074] Step 1: Surface pretreatment of the silicon substrate was performed by ultrasonic treatment in acetone for 15 min, ultrasonic treatment in ethanol for 15 min, and finally ultrasonic treatment in deionized water for 15 min, and then blown dry with a nitrogen gun;

[0075] Step 2: Using physical vapor deposition method, a bottom electrode pt with a thickness of 100nm is plated on the silicon substrate after surface pretreatment;

[0076] Step 3: Using an atomic layer deposition method, a 5 nm thick bottom electrode protection layer is grown on the bottom electrode; wherein the material of the bottom electrode protection layer is a silicon-aluminum mixture thin film;

[0077] Step 4: On the bottom electrode protection layer, an atomic layer deposition method is used, using molybdenum hexacarbonyl (Mo(CO)6) as a source and di-tert-butyl disulfide (TBDS) as a reaction gas sulfur source. At 250°C, the metal precursor pulse time is 0.5 s, the purge time is 90 s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5 s. The above process is repeated to form a mother layer material MoS2 with a thickness of 0.5 nm on the bottom electrode protection layer;

[0078] Step 5: On the mother layer material MoS2, an atomic layer deposition method is used, using ReCl5 as a source and di-tert-butyl disulfide (TBDS) as a reaction gas sulfur source. At 250°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a sub-layer material ReS2 with a thickness of 0.5nm on the mother layer material MoS2;

[0079] Step 6: On the sub-layer material ReS2, an atomic layer deposition method is used, using molybdenum hexacarbonyl (Mo(CO)6) as a source and di-tert-butyl disulfide (TBDS) as a reaction gas sulfur source. At 250°C, the metal precursor pulse time is 0.5s, the purge time is 90s, and the di-tert-butyl disulfide (TBDS) reaction gas sulfur source pulse time is 0.5s. The above process is repeated to form a mother layer material MoS2 with a thickness of 0.7nm on the sub-layer material ReS2;

[0080] Step 7: Repeat steps 5 to 6 for 42 times to obtain a transition metal chalcogenide nanolayer with a thickness of about 50 nm.

[0081] Step 8: forming a top electrode protection layer with a thickness of 5 nm on the transition metal chalcogenide nano-laminate by atomic layer deposition; wherein the material of the top electrode protection layer is a silicon-aluminum mixture thin film;

[0082] Step nine: using a physical vapor deposition method to form a metal top electrode array with a thickness of 50-100 nm on the top electrode protection layer.

[0083] The dielectric constant test results at different frequencies are as follows:

[0084]

[0085] In summary, Examples 1 to 4 prepared by different processes, in which the dielectric constants of the mother layer materials ZrS2 and MoS2 are approximately 4.5 and 11.8, are tested on their nano-laminated dielectric films, and the results are shown in the table above. The test results of Examples 1 and 3 show that the thickness of the mother and child layers below 0.4 nm can improve the dielectric constant of the film and still provide a polarization interface for the charge, thereby achieving the effect of improving the dielectric constant.

[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A nano-laminated dielectric film with a high dielectric constant, characterized in that: Its structure includes a silicon substrate, a bottom electrode protection layer, a transition metal chalcogenide nano-layer and a top electrode arranged from bottom to top, a bottom electrode is arranged between the silicon substrate and the bottom electrode protection layer, the transition metal chalcogenide nano-layer is arranged above the bottom electrode protection layer, and a top electrode protection layer is arranged between the transition metal chalcogenide nano-layer and the top electrode; the transition metal chalcogenide in the transition metal chalcogenide nano-layer is composed of a two-dimensional material, and the two-dimensional material is a parent-child layer structure composed of any two or three of MoS2, La2S2, RuS2, SnS2, ReS2, HfS2, ZrS2, and TiS2.

2. The high dielectric constant nano-laminated dielectric film according to claim 1, characterized in that: The bottom electrode protection layer and the top electrode protection layer are both silicon-aluminum mixture films, and the thickness of the silicon-aluminum mixture film is 3-5 nm.

3. The nano-laminated dielectric film with a high dielectric constant according to claim 1, characterized in that: The structural formula of the transition metal sulfide in the transition metal sulfide nanolaminate is (a-MS2 / b-NS2); wherein a is the thickness of the sub-layer material, b is the thickness of the parent layer material, and M and N represent metal elements respectively.

4. The high dielectric constant nanolaminate dielectric film according to claim 1, characterized in that: The material of the bottom electrode and the top electrode is one of Au, Pt and Ti, and the thickness of the bottom electrode and the top electrode is 50-100 nm.

5. A method for preparing a nano-laminated dielectric film with a high dielectric constant, used to implement a nano-laminated dielectric film with a high dielectric constant as claimed in any one of claims 1 to 4, characterized in that: The following steps are involved: Step 1: Surface pretreatment of the silicon substrate; Step 2: The silicon substrate after surface pretreatment is plated with a bottom electrode having a thickness of 50-100 nm by physical vapor deposition; Step 3: using an atomic layer deposition method to form a 3-5 nm thick silicon-aluminum mixture film on the bottom electrode as a bottom electrode protection layer; Step 4: using tetrakis(dimethylamine)zirconium as a source and di-tert-butyl disulfide as a reaction gas sulfur source, an atomic layer deposition method is used to form a parent layer material with a thickness of 0.1-1 nm on the bottom electrode protection layer; Step 5: Using tetrakis(dimethylamine)hafnium as a source and di-tert-butyl disulfide as a reaction gas sulfur source, an atomic layer deposition method is used to form a sub-layer material with a thickness of 0.1-1 nm on the parent layer material; Step 6: Using tetrakis(dimethylamine)zirconium as a source and di-tert-butyl disulfide as a reaction gas sulfur source, an atomic layer deposition method is used to form a mother layer material with a thickness of 0.1-1 nm on the sub-layer material; Step 7: Repeat the process from step 5 to step 6, and after repeated lamination n times, obtain a transition metal chalcogenide nano-laminate; Step 8: using an atomic layer deposition method to form a top electrode protection layer with a thickness of 3 to 5 nm on the transition metal chalcogenide nanolayer; Step nine: using physical vapor deposition to form a 50-100 nm metal top electrode on the top electrode protection layer; obtaining a nano-laminated dielectric film with a high dielectric constant.

6. The method for preparing a nano-laminated dielectric film with a high dielectric constant according to claim 5, characterized in that: In step 1, the surface of the silicon substrate is pretreated in the following manner: first, ultrasonic treatment is performed in acetone for 15 min, then ultrasonic treatment is performed in ethanol for 15 min, and finally ultrasonic treatment is performed in deionized water for 15 min, and finally, the substrate is dried by a nitrogen gun.

7. The method for preparing a nano-laminated dielectric film with a high dielectric constant according to claim 6, characterized in that: In step 4, step 5 and step 6, the atomic layer deposition method is specifically used as follows: tetrakis(dimethylamine)zirconium or tetrakis(dimethylamine)hafnium is used as the source, di-tert-butyl disulfide is used as the reaction gas sulfur source, the temperature is controlled at 200°C, the pulse time of the metal precursor is 0.1~1s, the purge time is 30~90s, the pulse time of di-tert-butyl disulfide is 0.5~1.8s, and n nanolayers are stacked, where n is a positive integer.

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