Method for simultaneously growing polycrystalline silicon having different thicknesses on front and back surfaces of battery, and back contact battery

Abstract

The present invention belongs to the technical field of back contact battery preparation, and in particular relates to a method for simultaneously growing polycrystalline silicon having different thicknesses on front and back surfaces of a battery, and a back contact battery. The method comprises: S1, providing silicon wafers having a polished back surface and a textured front surface; S2, controlling the silicon wafers to be arranged in pairs and at intervals, front surfaces of paired silicon wafers being arranged face to face, a distance between the front surfaces of paired silicon wafers being S1, and a distance between the back surface of one paired silicon wafer and the back surface of an adjacent silicon wafer in a next pair being S2; simultaneously forming a tunneling oxide layer and intrinsic polycrystalline silicon on the front surface and the back surface of the silicon wafers, forming first intrinsic polycrystalline silicon having a thickness of L1 on the front surface, and forming second intrinsic polycrystalline silicon having a thickness of L2 on the back surface, wherein [S1 / (2×S2)]+0.1≤L1 / L2≤[S1 / (2×S2)]+0.3; S3, performing doping using a diffusion annealing process; and S4, cleaning. The present application can achieve simultaneous growth of polycrystalline silicon having different thicknesses on two sides, and can improve conductivity and battery conversion efficiency.

Description

Method for simultaneously growing polysilicon of different thicknesses on the front and back sides of a battery and back contact battery

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application requests the priority and rights of the Chinese patent application with patent application number 2023111834415 filed with the State Intellectual Property Office of China on September 14, 2023, and the invention name “Method for simultaneously growing polysilicon of different thicknesses on the front and back sides of a battery and a back-contact battery”, and incorporates the entire text of the patent application into this application by reference. Technical Field

[0003] The present application belongs to the technical field of back-contact cell preparation, and specifically relates to a method for simultaneously growing polysilicon of different thicknesses on the front and back sides of a cell and a back-contact cell. Background Art

[0004] The tunnel oxide layer and polysilicon structure, when used on the front side of the back-contact heterojunction solar cell, requires the use of thinner polysilicon to increase the battery current; while when used on the back side, thicker polysilicon is required to improve the conductivity.

[0005] Existing tunneling polycrystalline growth processes primarily use LPCVD to grow oxide and polysilicon layers, followed by high-temperature diffusion. For example, tunneling silicon oxide layers and N-type doped polysilicon layers are simultaneously formed on the front and back sides of a silicon wafer. After forming the tunneling silicon oxide layer on both sides, the process for forming the N-type doped polysilicon layer involves: first, using LPCVD to simultaneously deposit an undoped intrinsic silicon layer (30nm thick) on both sides of the tunneling silicon oxide layer; then, using PECVD, phosphorus-doped polysilicon is in-situ doped on the back side of the wafer. After completing these coating processes, the silicon wafer is placed in a high-temperature phosphorus diffusion furnace for phosphorus diffusion. During this phosphorus diffusion step, the wafers are evenly spaced to ensure that the same PSG glass layer (phosphosilicate glass) is formed on both sides, and the phosphorus diffusion process proceeds simultaneously. The PSG glass layer produced in these steps is then removed. Therefore, currently, thickening the backside polysilicon layer, resulting in a different thickness from the frontside polysilicon, is typically achieved through additional backside coating.

[0006] However, the existing LPCVD polysilicon deposition process cannot achieve the simultaneous growth of polycrystalline with different thicknesses on the front and back sides, and the existing high-temperature diffusion process cannot achieve the simultaneous diffusion of polycrystalline with different thicknesses and different doping concentrations on the front and back sides.

[0007] Summary of the Invention

[0008] The purpose of this application is to overcome the defect of the existing LPCVD polysilicon deposition process in the prior art that it is unable to achieve the simultaneous growth of polycrystalline silicon with different thicknesses on the front and back sides, and to provide a method for simultaneously growing polycrystalline silicon with different thicknesses on the front and back sides of a battery and a back-contact battery. This method can achieve the simultaneous growth of polycrystalline silicon with different thicknesses on both sides, and can improve the short-circuit current and fill factor of the battery while improving the conductivity, thereby improving the battery conversion efficiency; since the structure of tunnel oxide layer and polycrystalline silicon on both the front and back sides is formed at the same time, the equipment cost is significantly reduced.

[0009] To achieve the above objectives, in a first aspect, the present application provides a method for simultaneously growing polysilicon of different thicknesses on the front and back sides of a cell, comprising the following steps:

[0010] S1, provide silicon wafers with backside polishing and front side textured;

[0011] S2. Control the silicon wafers to be spaced apart in pairs and the front sides of the paired silicon wafers to be face to face, and the spacing between the front sides of the paired silicon wafers is S1, and the spacing between the back sides of the previous paired silicon wafer and the back sides of the adjacent next paired silicon wafer is S2, where S2 is greater than S1; then, a tunneling oxide layer is formed on the front and back sides of the silicon wafers at the same time, and then, intrinsic polysilicon is formed on the front and back sides at the same time, wherein a first intrinsic polysilicon is formed on the front side and the thickness of the first intrinsic polysilicon on the texturing front side is L1, and a second intrinsic polysilicon with a thickness of L2 is formed on the back side, and L1, L2, S1, and S2 satisfy: [S1 / (2×S2)]+0.1≤L1 / L2≤[S1 / (2×S2)]+0.3;

[0012] S3, using a diffusion annealing process to form corresponding doped polysilicon layers from the first intrinsic polysilicon and the second intrinsic polysilicon;

[0013] S4. Then, cleaning is performed.

[0014] In the present application, preferably, L1 is 15-70 nm, preferably 15-50 nm, and L2 is 100-300 nm.

[0015] In the present application, preferably, S1 is 1-5 mm, preferably 2-5 mm, and S2 is 10-15 mm.

[0016] In this application, preferably, S2 is greater than S1.

[0017] In some preferred embodiments of the present application, the thickness of the tunnel oxide layer is 1.2-2.0 nm.

[0018] In some preferred embodiments of the present application, the simultaneous formation of the tunnel oxide layer and the intrinsic polysilicon in S2 is performed in a tubular LPCVD device, and each silicon wafer is mounted on a quartz boat with a plurality of slots.

[0019] In some preferred embodiments of the present application, in S2, the conditions for forming the tunnel oxide layer include: thermal oxidation at 550-650°C.

[0020] In some preferred embodiments of the present application, the conditions for forming intrinsic polysilicon include: a growth temperature of 550-650° C. and a gas pressure of 5-10000 Pa.

[0021] In some preferred embodiments of the present application, the method further comprises the step of simultaneously forming polysilicon with different doping concentrations on the front and back surfaces:

[0022] In S3, a silicon dioxide barrier layer is first formed on the surface of the first intrinsic polysilicon obtained in S2, and then the diffusion annealing process is performed; the sheet resistance of the first doped polysilicon obtained in S3 is 400-600Ω, and the sheet resistance of the second doped polysilicon obtained is 40-150Ω, preferably 50-150Ω;

[0023] The silicon dioxide barrier layer is removed by cleaning in S4.

[0024] More preferably, the thickness of the silicon dioxide barrier layer is 1 / 3 to 1 times, preferably 1 / 2 to 1 times, the difference between the thicknesses of the first intrinsic polysilicon and the second intrinsic polysilicon.

[0025] More preferably, the silicon dioxide barrier layer is formed by using a tubular PECVD device or a plate PECVD device.

[0026] In some preferred embodiments of the present application, the formation conditions of the silicon dioxide barrier layer include: a growth temperature of 300-550°C, reaction gases of SiH4 and N2O, a reaction pressure of 500-5000 Pa, and a power of 1000-3000W.

[0027] In some preferred embodiments of the present application, the diffusion annealing process is high-temperature phosphorus diffusion, and the high-temperature phosphorus diffusion adopts the phosphorus oxychloride diffusion method, and the process includes: first performing phosphorus diffusion, the phosphorus diffusion temperature is 700-850°C, then performing high-temperature advancement, the high-temperature advancement temperature is 850-950°C; and subsequently performing a cooling annealing treatment, the temperature is reduced to 600-700°C.

[0028] More preferably, the phosphorus diffusion conditions include: introducing POCl3, O2, and N2, with a POCl3 gas flow rate of 50sccm-500sccm, an O2 gas flow rate of 100sccm-1000sccm, and an N2 gas flow rate of 100sccm-1000sccm; the furnace tube pressure is 50mbar-300mbar, and the phosphorus diffusion time is controlled within 5min-30min.

[0029] More preferably, the high-temperature advancement conditions include: introducing O2 and N2, with an O2 gas flow rate of 1000sccm-2000sccm and an N2 gas flow rate of 1000sccm-5000sccm; the furnace tube pressure is 100mbar-500mbar, and the high-temperature advancement time is controlled within 30min-60min.

[0030] More preferably, the cooling annealing conditions include: introducing N2 with a N2 gas flow rate of 1000 sccm-3000 sccm, and controlling the cooling annealing time to be 30 min-60 min.

[0031] In some preferred embodiments of the present application, the cleaning solution used in S4 is an HF acid solution, and the mass percentage of HF in the HF acid solution is 3%-8%.

[0032] Preferably, during the cleaning, the silicon wafer is treated in the HF acid solution for 2-8 minutes at a temperature of 15-25°C.

[0033] In some preferred embodiments of the present application, the process of providing a back-polished and front-textured silicon wafer in S1 includes:

[0034] S101, performing double-sided polishing on the front and back sides of the silicon wafer, and then cleaning;

[0035] S102, depositing a protective layer on the back side of the double-sided polished silicon wafer;

[0036] S103, performing single-sided texturing and cleaning on the front side of the silicon wafer obtained in S102 to form a pyramid texturing surface on the front side.

[0037] Preferably, the protective layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0038] More preferably, the texturing time is 8-40 minutes, and the texturing temperature is 65°C-85°C.

[0039] More preferably, the texturing liquid used for texturing is a mixture of potassium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide in the texturing liquid is 1%-5%, and the mass percentage of the texturing additive is 0.5%-1%.

[0040] In the second aspect, the present application provides a back-contact cell, which includes a silicon wafer, a tunneling oxide layer arranged on the front and back sides of the silicon wafer, a first doped polysilicon arranged on the front side of the silicon wafer, and a second doped polysilicon arranged on the back side of the silicon wafer. The back-contact cell is prepared by the method described in the first aspect, and the thickness of the first doped polysilicon and the second doped polysilicon are different, or the thickness and doping concentration of the first doped polysilicon and the second doped polysilicon are different. Beneficial effects:

[0041] The present application adopts the above-mentioned technical solution, especially by controlling the front-side face-to-face arrangement of silicon wafers with different spacings, and coordinating L1, L2, S1, and S2 to satisfy a specific relationship, and then simultaneously forming a tunnel oxide layer and intrinsic polysilicon, so as to achieve the simultaneous growth of polysilicon with different thicknesses on both sides, and can improve the short-circuit current and fill factor of the battery while improving the conductivity of the resulting battery, thereby improving the battery conversion efficiency; due to the structure of forming the tunnel oxide layer and polysilicon on both the front and back sides simultaneously, the equipment cost is significantly reduced. Among them, when the spacing between silicon wafers is larger, the gas freedom degree during the formation of the corresponding polysilicon is greater, the reaction rate is faster, and the polysilicon grown in the same time is thicker; when the spacing between silicon wafers is smaller, the gas freedom degree during the formation of the corresponding polysilicon is smaller, the gas is not easy to enter, the reaction rate is slower, and the polysilicon grown in the same time is thinner, thereby achieving the simultaneous growth of polysilicon with different thicknesses on both sides. Among them, this application specifically requires that L1, L2, S1, and S2 meet a specific relationship, which can reduce the light absorption of the front polycrystalline while ensuring the conductivity of the back polycrystalline, which is beneficial to improving the short-circuit current and fill factor of the battery, thereby improving the battery conversion efficiency. Under the same conditions, if this specific relationship is not met, such as L1 / L2>[S1 / (2×S2)]+0.3, the front polycrystalline will be too thick or the back polycrystalline will be too thin. The front polycrystalline will be too thick, resulting in severe light absorption and a significant decrease in current, while the back polycrystalline will be too thin, resulting in poor back conductivity. If [S1 / (2×S2)]+0.1>L1 / L2, the front polycrystalline will be too thin or the back polycrystalline will be too thick. The front polycrystalline will be too thin, which will damage the passivation during wet cleaning. The back polycrystalline will be too thick, which will be detrimental to the laser opening process during the subsequent HBC battery production, and will also affect the short-circuit current.

[0042] In the scheme of setting up a silicon dioxide barrier layer in the present application, the use of the silicon dioxide barrier layer can also simultaneously diffuse different doping concentrations according to the different polysilicon thicknesses on the front and back sides. This is because the diffusion coefficient of common impurities (boron, phosphorus, arsenic, etc.) in the oxide layer is much smaller than the diffusion coefficient in silicon. Therefore, the oxide layer has the ability to block the diffusion of impurities into the semiconductor. Therefore, in the preferred scheme of the present application, a layer of silicon dioxide barrier layer is deposited on the thinner polysilicon surface on the front side before the diffusion annealing process, which slows down the diffusion rate of phosphorus impurities during phosphorus diffusion and reduces the doping concentration of the front polysilicon. There is no silicon dioxide barrier layer on the back side, and the doping concentration is higher, thereby forming different doping concentrations on the front and back sides. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0044] FIG1 is a schematic diagram of the structure of the quartz boat and silicon wafer used in Example 1 of the present application;

[0045] FIG2 is a schematic structural diagram of a double-sided polished silicon wafer according to Example 1 of the present application;

[0046] FIG3 is a schematic structural diagram of a single-sided textured silicon wafer according to Example 1 of the present application;

[0047] FIG4 is a schematic diagram of the structure of the tunnel oxide layer and intrinsic polysilicon formed on the front and back sides of Example 1 of the present application;

[0048] FIG5 is a schematic structural diagram of a silicon dioxide barrier layer formed on the surface of the first intrinsic polysilicon in FIG4 ;

[0049] FIG6 is a schematic structural diagram of the coordination of a quartz boat and a silicon wafer in the prior art of Comparative Example 1. FIG.

[0050] Description of Reference Numerals

[0051] 1. Quartz boat, 2. Double-sided polished silicon wafer, 3. Single-sided textured silicon wafer, 4. First tunneling oxide layer, 5. Second tunneling oxide layer, 6. First intrinsic polysilicon, 7. Second intrinsic polysilicon, 8. Silicon dioxide barrier layer. DETAILED DESCRIPTION

[0052] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0053] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0054] In a first aspect, the present application provides a method for simultaneously growing polysilicon of different thicknesses on the front and back sides of a cell, comprising the following steps:

[0055] S1, provide silicon wafers with backside polishing and front side textured;

[0056] S2. Control the silicon wafers to be spaced apart in pairs and the front sides of the paired silicon wafers to be face to face, and the spacing between the front sides of the paired silicon wafers is S1, and the spacing between the back sides of the previous paired silicon wafer and the back sides of the adjacent next paired silicon wafer is S2, where S2 is greater than S1; then, a tunneling oxide layer is formed on the front and back sides of the silicon wafers at the same time, and then, intrinsic polysilicon is formed on the front and back sides at the same time, wherein a first intrinsic polysilicon is formed on the front side and the thickness of the first intrinsic polysilicon on the texturing front side is L1, and a second intrinsic polysilicon with a thickness of L2 is formed on the back side, and L1, L2, S1, and S2 satisfy: [S1 / (2×S2)]+0.1≤L1 / L2≤[S1 / (2×S2)]+0.3;

[0057] S3, using a diffusion annealing process to form corresponding doped polysilicon layers from the first intrinsic polysilicon and the second intrinsic polysilicon;

[0058] S4. Then, cleaning is performed.

[0059] Preferably, [S1 / (2×S2)]+0.1≤L1 / L2≤[S1 / (2×S2)]+0.2.

[0060] In this application, L1 is preferably 15-70nm, preferably 15-50nm, and L2 is 100-300nm. In this preferred solution, L1 and L2 are appropriately selected to reduce light absorption by the front polycrystalline while ensuring the conductivity of the back polycrystalline, which is beneficial to improving the short-circuit current and fill factor of the battery.

[0061] In this application, preferably, S1 is 1-5mm, preferably 2-5mm, and S2 is 10-15mm. In this preferred solution, S1 and S2 are appropriately set to ensure that both the front and back polycrystalline are at an appropriate thickness, which is more conducive to improving the short-circuit current and fill factor of the battery.

[0062] In some preferred embodiments of the present application, the thickness of the tunnel oxide layer is 1.2-2.0 nm. In this preferred embodiment, the thickness of the tunnel oxide layer is appropriately selected to ensure the passivation level and facilitate carrier tunneling.

[0063] In this application, those skilled in the art can use existing methods to prepare silicon wafers with polished backside and textured frontside. For example, in some specific embodiments of this application, the process of providing a silicon wafer with polished backside and textured frontside in S1 includes:

[0064] S101, performing double-sided polishing on the front and back sides of the silicon wafer, and then cleaning;

[0065] S102, depositing a protective layer on the back side of the double-sided polished silicon wafer;

[0066] S103: The front side of the silicon wafer obtained in S102 is subjected to single-sided texturing and cleaning to form a pyramid textured surface on the front side to reduce reflectivity. It is understood that the protective layer deposited in S102 will be removed in the cleaning step of S103, and the cleaning solution used for cleaning is, for example, hydrofluoric acid.

[0067] The polishing liquid for the double-sided polishing in S101 is an alkaline solution, which is used to remove the wire-cut damage layer on the surface of the silicon wafer. The remaining alkaline solution on the surface of the silicon wafer is subsequently removed by cleaning. The alkali in the alkaline solution can be, for example, potassium hydroxide, sodium hydroxide, or a mixture thereof, and the mass concentration of the alkali in the alkaline solution can be, for example, 2% to 10%.

[0068] Preferably, the conditions for the double-side polishing may include, for example: a reaction temperature of 65° C. to 90° C., a reaction time of 1 to 15 minutes, and a single-side removal thickness controlled to be 1 to 20 μm.

[0069] The protective layer in S102 has a strong resistance to alkaline solution corrosion and can resist alkaline corrosion in the texturing solution. The protective layer may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride. The protective layer may be formed using a thin film forming method such as sputtering or CVD, preferably using PECVD.

[0070] In S103, more preferably, the texturing time is 8-40 minutes, and the texturing temperature is 65°C-85°C.

[0071] More preferably, the texturing liquid used for texturing is a mixture of potassium hydroxide, a texturing additive and water, the mass percentage of potassium hydroxide in the texturing liquid is 1%-5%, the mass percentage of the texturing additive is 0.5%-1%, and the texturing additive can be any commercially available texturing additive in the field.

[0072] The silicon wafer in S1 is preferably an N-type single crystal silicon wafer.

[0073] In some preferred embodiments of the present application, the simultaneous formation of the tunnel oxide layer and intrinsic polysilicon in S2 is performed in a tubular LPCVD apparatus, with each silicon wafer mounted on a quartz boat having a plurality of slots. This preferred solution, utilizing a tubular LPCVD apparatus in conjunction with a quartz boat, enables the deposition of a denser tunnel oxide layer and intrinsic polysilicon, further improving passivation levels and making them less susceptible to damage from solutions during subsequent cleaning processes.

[0074] The control silicon wafers in S2 are arranged in pairs with spaced intervals, with the front faces of the paired silicon wafers facing each other and matching the spacing between S1 and S2. This can be achieved by snapping the silicon wafers into the slots of the quartz boat. The slots on the quartz boat can be arranged at unequal intervals, with the unequal intervals matching the spacing between S1 and S2 to snap the silicon wafers into place to meet the above arrangement. The slots can also be arranged at equal intervals, in which case the silicon wafers are snapped into some of the slots at different intervals between S1 and S2 to meet the above arrangement.

[0075] In some preferred embodiments of the present application, in S2, the conditions for forming the tunnel oxide layer include: thermal oxidation at 550-650° C. The thermal oxidation time can be determined according to the desired thickness of the tunnel oxide layer, for example, 10-30 minutes.

[0076] In some preferred embodiments of the present application, the conditions for forming intrinsic polysilicon include: a growth temperature of 550-650° C. and a pressure of 5-10000 Pa. The time for forming intrinsic polysilicon can be determined according to the required thickness of intrinsic polysilicon, for example, 20-40 minutes.

[0077] The cleaning step S4 of the present application is used to remove the double-sided PSG layer (ie, phosphorus silicon glass layer) generated during the diffusion annealing process.

[0078] In some preferred embodiments of the present application, the cleaning solution used in S4 is an HF acid solution, and the mass percentage of HF in the HF acid solution is 3%-8%.

[0079] Preferably, during the cleaning, the silicon wafer is treated in the HF acid solution for 2-8 minutes at a temperature of 15-25°C.

[0080] In some preferred embodiments of the present application, the method further includes the step of simultaneously forming polysilicon with different doping concentrations on the front and back sides: in S3, a silicon dioxide barrier layer is first formed on the surface of the first intrinsic polysilicon obtained in S2, and then the diffusion annealing process is performed; the first doped polysilicon obtained in S3 has a square resistance of 400-600Ω, and the second doped polysilicon obtained has a square resistance of 40-150Ω, preferably 50-150Ω; and the silicon dioxide barrier layer is removed by cleaning in S4. In this preferred embodiment, a silicon dioxide barrier layer is deposited on the thinner polysilicon surface on the front side before the diffusion annealing process to slow the diffusion rate of phosphorus impurities during phosphorus diffusion and reduce the doping concentration of the front polysilicon. However, the back side is not blocked by the silicon dioxide barrier layer and has a higher doping concentration, thereby forming different doping concentrations on the front and back sides, and forming doped polysilicon with different square resistances on the front and back sides, wherein the higher the doping concentration, the lower the square resistance.

[0081] More preferably, the thickness of the silicon dioxide barrier layer is 1 / 3 to 1 times the difference between the thickness of the first intrinsic polysilicon and the second intrinsic polysilicon.

[0082] Further preferably, the thickness of the silicon dioxide barrier layer is between 1 / 2 and 1 times the difference between the thicknesses of the first intrinsic polysilicon and the second intrinsic polysilicon. In this preferred embodiment, the thickness of the silicon dioxide barrier layer is appropriate, ensuring both passivation and the required doping concentration of the front polycrystalline, preventing over-doping or under-doping, and further improving the passivation level of the front polycrystalline.

[0083] More preferably, the silicon dioxide barrier layer is formed by using a tubular PECVD device or a plate PECVD device, and a tubular PECVD device is further preferred.

[0084] In some preferred embodiments of the present application, the formation conditions of the silicon dioxide barrier layer include: a growth temperature of 300-550°C, reaction gases of SiH4 and N2O, a reaction pressure of 500-5000 Pa, and a power of 1000-3000W.

[0085] The ratio of each gas in the reaction gas and the growth time described in the present application can be determined according to the amount of silicon dioxide barrier layer required to be generated. For example, in the reaction gas, the molar ratio of SiH4 and N2O can be 0.2-0.5:1, and the growth time can be 10-20 minutes.

[0086] In some preferred embodiments of the present application, the diffusion annealing process is high-temperature phosphorus diffusion, and the high-temperature phosphorus diffusion adopts the phosphorus oxychloride diffusion method, and the process includes: first performing phosphorus diffusion, the phosphorus diffusion temperature is 700-850°C, then performing high-temperature advancement, the high-temperature advancement temperature is 850-950°C; and subsequently performing a cooling annealing treatment, the temperature is reduced to 600-700°C.

[0087] More preferably, the phosphorus diffusion conditions include: introducing POCl3, O2, and N2, with a POCl3 gas flow rate of 50sccm-500sccm, an O2 gas flow rate of 100sccm-1000sccm, and an N2 gas flow rate of 100sccm-1000sccm; the furnace tube pressure is 50mbar-300mbar, and the phosphorus diffusion time is controlled within 5min-30min.

[0088] More preferably, the high-temperature advancement conditions include: introducing O2 and N2, with an O2 gas flow rate of 1000sccm-2000sccm and an N2 gas flow rate of 1000sccm-5000sccm; the furnace tube pressure is 100mbar-500mbar, and the high-temperature advancement time is controlled within 30min-60min.

[0089] More preferably, the cooling annealing conditions include: introducing N2 with a N2 gas flow rate of 1000 sccm-3000 sccm, and controlling the cooling annealing time to be 30 min-60 min.

[0090] In a second aspect, the present application provides a back-contact cell comprising a silicon wafer, a tunneling oxide layer disposed on both the front and back sides of the silicon wafer, a first doped polysilicon disposed on the front side of the silicon wafer, and a second doped polysilicon disposed on the back side of the silicon wafer. The back-contact cell is prepared by the method described in the first aspect, and the first doped polysilicon and the second doped polysilicon have different thicknesses, or the first doped polysilicon and the second doped polysilicon have different thicknesses and doping concentrations.

[0091] It should be noted that the tunnel oxide layer and the second doped polysilicon disposed on the back serve as the first semiconductor layer. Those skilled in the art can further configure conventional structural layers, such as the second semiconductor layer and metal electrodes, as required, which will not be described in detail here.

[0092] The back contact battery provided in this application combines excellent conductivity with high battery current and high battery conversion efficiency.

[0093] The embodiments of the present application are described in detail below. These embodiments are exemplary and are only used to explain the present application. They should not be construed as limiting the present application.

[0094] Example 1

[0095] A method for simultaneously growing polysilicon of different thicknesses and different doping concentrations on the front and back sides of a battery, comprising the following steps:

[0096] S1. Provide silicon wafers with backside polishing and front side textured. The process is as follows:

[0097] S101. As shown in FIG2 , the front and back sides of an N-type single crystal silicon wafer are double-sided polished, and an alkaline solution is used to remove the wire-cut damage layer on the surface of the silicon wafer to form a double-sided polished silicon wafer 2. The alkaline solution is a potassium hydroxide solution with a mass concentration of 5%. The reaction temperature is 70° C., the reaction time is 5 minutes, and the thickness removed on one side is controlled to be 10 μm. Then, a standard RCA cleaning is performed to remove the alkaline solution remaining on the surface of the silicon wafer.

[0098] S102. Depositing a silicon nitride protective layer on the back of the silicon wafer. The silicon nitride protective layer has a strong property of resisting corrosion by alkaline solutions and can resist alkaline corrosion in the texturing solution. The layer is deposited by using a PECVD method.

[0099] S103. As shown in FIG3 , the silicon wafer protected by silicon nitride is subjected to single-sided texturing and cleaning to form a pyramid texturing surface on the front side, reduce the reflectivity, and form a single-sided texturing silicon wafer 3. The texturing time is 20 minutes, and the texturing temperature is 75° C. The texturing solution is an alkaline mixed solution, specifically a mixture of potassium hydroxide, a texturing additive, and water, wherein the mass percentage of potassium hydroxide is 2%, the mass percentage of the texturing additive is 0.5%, and the balance is water. The texturing additive is a commercially available product (purchased from Changzhou Shichuang Energy Co., Ltd., brand TS series).

[0100] S2. As shown in FIG4 , LPCVD is used to simultaneously grow a first tunnel oxide layer 4, a second tunnel oxide layer 5, a first intrinsic polysilicon 6, and a second intrinsic polysilicon 7 on the single-sided textured silicon wafer 3. The first intrinsic polysilicon 6 is deposited to a thickness of L1 on the textured front surface, and the second intrinsic polysilicon 7 is deposited to a thickness of L2 on the polished back surface. The corresponding tunnel oxide layer and the corresponding polysilicon are grown in a tubular LPCVD apparatus using a quartz boat 1 that allows different spacing between the two sides of the silicon wafer. As shown in FIG1 , the silicon wafers are placed on the quartz boat 1 and arranged in pairs with the front surfaces of the paired silicon wafers facing each other. The spacing between the two textured front surfaces of the paired silicon wafers is S1, which is 2 mm, and the spacing between the two adjacent polished back surfaces is S2, which is 15 mm. L1 / L2 = [S1 / (2×S2)] + 0.2. The thickness L1 of the first intrinsic polysilicon is 40 nm, and the thickness L2 of the second intrinsic polysilicon is 150 nm. The formation process of the corresponding tunnel oxide layer is: thermal oxidation at 600°C for 30 minutes to form a tunnel oxide layer with a thickness of 1.5nm. The growth temperature of the corresponding intrinsic polysilicon is controlled at 600°C, the gas pressure is controlled at 50Pa, and the growth time is 20-40 minutes.

[0101] S3. As shown in FIG5 , a silicon dioxide barrier layer 8 is grown on the surface of the first intrinsic polycrystalline silicon 6. The silicon dioxide barrier layer 8 is grown using a tubular PECVD apparatus. The growth conditions for the silicon dioxide barrier layer 8 are: a growth temperature of 450° C., reactant gases of SiH 4 and N 2 O in a molar ratio of 0.3:1, a reaction pressure of 1000 Pa, a power of 2000 W, and a growth time of 10 minutes. The thickness of the silicon dioxide barrier layer is the difference between the thickness L1 of the first intrinsic polycrystalline silicon and the thickness L2 of the second intrinsic polycrystalline silicon.

[0102] The silicon wafer, on which the silicon dioxide barrier layer 8 had been grown, was subjected to high-temperature diffusion to phosphorus-dope the corresponding intrinsic polysilicon layers to form N-type doped polysilicon. Specifically, a phosphorus oxychloride diffusion method was employed. The process included: first, phosphorus diffusion, during which POCl3, O2, and N2 were introduced; the phosphorus diffusion temperature was 750°C, the phosphorus diffusion time was 10 minutes, the POCl3 gas flow rate was 100 sccm, the O2 gas flow rate was 200 sccm, the N2 gas flow rate was 100 sccm, and the furnace pressure was 100 mbar; then, a high-temperature diffusion process was performed, during which O2 and N2 were introduced; the high-temperature diffusion temperature was 900°C, the high-temperature diffusion time was 40 minutes, the O2 gas flow rate was 1000 sccm, the N2 gas flow rate was 2000 sccm, and the furnace pressure was 200 mbar. The resulting first doped polysilicon had a sheet resistance of 400Ω, and the second doped polysilicon had a sheet resistance of 60Ω.

[0103] Then, a cooling annealing treatment is performed, and the temperature is reduced to 600° C. During this period, N2 gas is introduced with a N2 gas flow rate of 1500 sccm, and the cooling annealing time is controlled at 40 minutes.

[0104] S4. Re-clean the diffused silicon wafer. In this embodiment, a silicon dioxide barrier layer and a phosphosilicate glass (PSG) layer formed by a high-temperature diffusion reaction exist on the surface of the N-type polysilicon layer. The cleaning solution used for the re-cleaning is an HF acid solution. The HF acid solution contains 5% by mass of HF and 95% by mass of deionized water. The silicon wafer is treated in the HF acid solution for 5 minutes at a temperature of 20°C.

[0105] Example 2

[0106] The method of Example 1 was followed, except that L1 was adjusted to 22.5 nm and S1 was adjusted to 1.5 mm, such that [S1 / (2×S2)]+0.1=L1 / L2. L2 and S2 remained unchanged. To meet L1, the process parameters were modified accordingly: the thickness of the front silicon dioxide barrier layer was changed to 127.5 nm, instead of the 110 nm thickness of Example 1.

[0107] Example 3

[0108] The method of Example 1 was followed, except that L1 was adjusted to 70 nm and S1 was adjusted to 5 nm so that [S1 / (2×S2)]+0.3=L1 / L2. In this case, L2 and S2 remained unchanged. To meet L1, the process parameters were changed accordingly: the thickness of the front oxidation barrier layer was changed to 80 nm, instead of the 110 nm thickness of Example 1.

[0109] Example 4

[0110] The method of Example 1 was followed, except that the silicon dioxide barrier layer was not formed.

[0111] The first doped polysilicon and the second doped polysilicon obtained in this embodiment have the same doping concentration, and both have a sheet resistance of 400Ω.

[0112] Example 5

[0113] The method of Example 1 is referred to, except that the thickness of the silicon dioxide barrier layer is 50 nm, which is less than 1 / 2 of the difference between the thickness of the first intrinsic polysilicon and the second intrinsic polysilicon.

[0114] The sheet resistance of the first doped polysilicon obtained in this embodiment is 200Ω; the sheet resistance of the second doped polysilicon is 60Ω.

[0115] Example 6

[0116] The method of Example 1 is referred to, except that the thickness of the silicon dioxide barrier layer is 130 nm, which is greater than the difference between the thickness of the first intrinsic polysilicon and the second intrinsic polysilicon.

[0117] The sheet resistance of the first doped polysilicon obtained in this embodiment is 500Ω; the sheet resistance of the second doped polysilicon is 60Ω.

[0118] Comparative Example 1

[0119] The method of Example 1 is referred to, except that in the tubular LPCVD equipment used in forming the corresponding tunnel oxide layer and intrinsic polysilicon, the silicon wafers are alternately arranged at equal intervals (spacing 15 mm) in the quartz boat, as shown in Figure 6, and the front side of the silicon wafer is arranged face to face with the back side of the adjacent silicon wafer.

[0120] The thickness of the first doped polysilicon obtained in this comparative example is 150 nm, and the sheet resistance is 600Ω; the thickness of the second doped polysilicon is 150 nm, and the sheet resistance is 60Ω.

[0121] Comparative Example 2

[0122] The method of Example 1 was followed, except that L1 was adjusted to 20 nm so that [S1 / (2×S2)]+0.1>L1 / L2. To meet this condition, the process parameters were changed accordingly: the thickness of the dioxide barrier layer was increased to 130 nm.

[0123] Comparative Example 3

[0124] The method of Example 1 is referred to, except that L2 is adjusted to 50nm so that [S1 / (2×S2)]+0.3<L1 / L2. To meet this condition, the process parameters are changed accordingly: the corresponding phosphorus diffusion time is changed to 66% of the corresponding phosphorus diffusion time of Example 1, and the square resistance of the second intrinsic polysilicon layer is 150Ω.

[0125] Test Case

[0126] Silicon wafers with tunneling oxide layers and doped polysilicon on both the front and back sides, obtained in the above examples and comparative examples, were uniformly configured with conventional layers (i.e., an antireflection layer was also provided on the front side, and a second semiconductor layer consisting of an intrinsic amorphous layer and a P-type doped microcrystalline silicon layer, as well as a mask layer, a conductive film layer, and a metal electrode were also provided on the back side. The back side structure was the same as that in the applicant's earlier patent CN115207137B) to form cells. The resulting cells were then uniformly tested for performance, with the test results shown in Table 1.

[0127] Table 1

[0128] From the above, it can be seen that compared with the comparative example, the embodiment of the present application can achieve the simultaneous growth of polysilicon with different thicknesses on both sides, and at the same time can improve the short-circuit current, fill factor and battery conversion efficiency while improving conductivity.

[0129] Furthermore, according to Examples 1 and 3 of the present application, it can be seen that by adopting the correspondence between L1, L2, S1, and S2 in the preferred specific range of the present application, a suitable thickness ratio is formed for the front and back polysilicon, which significantly reduces the short-circuit current affected by the excessive thickness of the back polysilicon, and minimizes the loss caused by the corresponding higher energy laser opening, thereby further improving the battery conversion efficiency.

[0130] Furthermore, according to Examples 1 and 4-6 of the present application, it can be seen that the preferred arrangement of the silicon dioxide barrier layer and its thickness according to the present application is more conducive to doping of the back polysilicon and improving the fill factor of the battery.

[0131] The preferred embodiments of the present application are described in detail above, but the present application is not limited thereto. Within the technical concept of the present application, various simple modifications can be made to the technical solution of the present application, including combining the various technical features in any other appropriate manner. These simple modifications and combinations should also be regarded as the contents disclosed in the present application and fall within the scope of protection of the present application. Industrial Applicability

[0132] This application overcomes the existing technical drawback of the existing LPCVD polysilicon deposition process, which is unable to achieve simultaneous growth of polysilicon with different thicknesses on the front and back sides. It provides a method for simultaneously growing polysilicon with different thicknesses on the front and back sides of a battery and a back-contact battery. This method can achieve simultaneous growth of polysilicon with different thicknesses on both sides, while also improving the battery's short-circuit current and fill factor while increasing conductivity, thereby improving battery conversion efficiency. Because a structure with tunnel oxide layers and polysilicon on both the front and back sides is simultaneously formed, equipment costs are significantly reduced. Therefore, it is conducive to industrial promotion and application.

Claims

1. A method for simultaneously growing polysilicon of different thicknesses on the front and back sides of a battery, characterized in that: The following steps are involved: S1, provide silicon wafers with backside polishing and front side textured; S2, control the silicon wafers to be arranged in pairs with intervals and the front sides of the paired silicon wafers to be arranged face to face, and the spacing between the front sides of the paired silicon wafers is S1, and the spacing between the back sides of the previous paired silicon wafer and the adjacent back side of the paired silicon wafer is S2, and S2 is greater than S1; then a tunneling oxide layer is formed on the front and back sides of the silicon wafers at the same time, and then intrinsic polysilicon is formed on the front and back sides at the same time, wherein a first intrinsic polysilicon is formed on the front side and the thickness of the first intrinsic polysilicon on the front side of the texturing is L1, and a second intrinsic polysilicon with a thickness of L2 is formed on the back side, and L1, L2, S1, and S2 satisfy: [S1 / (2×S2)]+0.1≤L1 / L2≤[S1 / (2×S2)]+0.3; S3, using a diffusion annealing process to form corresponding doped polysilicon layers from the first intrinsic polysilicon and the second intrinsic polysilicon; S4, and then wash.

2. The method according to claim 1, characterized in that: L1 is 15-70nm, L2 is 100-300nm, S1 is 1-5mm, S2 is 10-15mm; and / or, The thickness of the tunnel oxide layer is 1.2-2.0 nm.

3. The method according to any one of claims 1 to 2, characterized in that: The simultaneous formation of the tunnel oxide layer and the intrinsic polysilicon in S2 is carried out in a tubular LPCVD device, and each silicon wafer is mounted on a quartz boat with a plurality of slots.

4. The method according to any one of claims 1 to 3, characterized in that: In S2, the conditions for forming the tunnel oxide layer include: thermal oxidation at 550-650° C.; the conditions for forming the intrinsic polysilicon include: growth temperature of 550-650° C. and gas pressure of 5-10000Pa.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises the step of simultaneously forming polysilicon with different doping concentrations on the front and back sides: In S3, a silicon dioxide barrier layer is first formed on the surface of the first intrinsic polysilicon obtained in S2, and then the diffusion annealing process is performed, so that the sheet resistance of the first doped polysilicon obtained in S3 is 400-600Ω, and the sheet resistance of the second doped polysilicon obtained is 40-150Ω; The silicon dioxide barrier layer is removed by cleaning in S4.

6. The method according to claim 5, characterized in that The thickness of the silicon dioxide barrier layer is 1 / 3 to 1 times the difference between the thickness of the first intrinsic polysilicon and the thickness of the second intrinsic polysilicon.

7. The method according to claim 5, characterized in that The silicon dioxide barrier layer is formed by using a tubular PECVD device or a plate PECVD device; and / or, The formation conditions of the silicon dioxide barrier layer include: growth temperature of 300-550° C., reaction gases of SiH 4 and N 2 O, reaction pressure of 500-5000 Pa, and power of 1000-3000 W.

8. The method according to claim 5, characterized in that The diffusion annealing process is high-temperature phosphorus diffusion, and the high-temperature phosphorus diffusion adopts the phosphorus oxychloride diffusion method, and the process includes: firstly performing phosphorus diffusion, the phosphorus diffusion temperature is 700-850°C, then performing high-temperature advancement, the high-temperature advancement temperature is 850-950°C; and then performing a cooling annealing treatment, the temperature is reduced to 600-700°C; The phosphorus diffusion conditions include: introducing POCl3, O2, and N2, the POCl3 gas flow rate is 50sccm-500sccm, the O2 gas flow rate is 100sccm-1000sccm, and the N2 gas flow rate is 100sccm-1000sccm; the furnace tube pressure is 50mbar-300mbar, and the phosphorus diffusion time is controlled at 5min-30min; The conditions for high-temperature advancement include: introducing O2 and N2, with the O2 gas flow rate being 1000sccm-2000sccm, and the N2 gas flow rate being 1000sccm-5000sccm; the pressure of the furnace tube being 100mbar-500mbar, and the high-temperature advancement time being controlled at 30min-60min. The cooling annealing conditions include: introducing N2, the N2 gas flow rate is 1000sccm-3000sccm, and the cooling annealing time is controlled within 30min-60min.

9. The method according to any one of claims 1 to 8, characterized in that: The cleaning solution used in S4 is an HF acid solution, the HF mass percentage of the HF acid solution is 3%-8%, the treatment time of the silicon wafer in the HF acid solution during the cleaning is 2-8 minutes, and the treatment temperature is 15-25°C; and / or The process of providing backside polished and frontside textured silicon wafers in S1 includes: S101, performing double-sided polishing on the front and back sides of the silicon wafer, and then cleaning; S102, depositing a protective layer on the back side of the double-sided polished silicon wafer; S103. The front side of the silicon wafer obtained in S102 is subjected to single-sided texturing and cleaning to form a pyramid texturing surface on the front side, wherein the texturing time is 8-40 minutes, the texturing temperature is 65°C-85°C, and the texturing liquid used is a mixture of potassium hydroxide, a texturing additive and water. The mass percentage of potassium hydroxide in the texturing liquid is 1%-5%, and the mass percentage of the texturing additive is 0.5%-1%.

10. A back contact cell, comprising a silicon wafer, a tunnel oxide layer disposed on both the front and back sides of the silicon wafer, a first doped polysilicon disposed on the front side of the silicon wafer, and a second doped polysilicon disposed on the back side of the silicon wafer, characterized in that: The back contact cell is prepared by the method as described in any one of claims 1 to 9, and the thicknesses of the first doped polysilicon and the second doped polysilicon are different, or the thicknesses and doping concentrations of the first doped polysilicon and the second doped polysilicon are different.

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