Semiconductor structure, integrated circuit, and preparation method for semiconductor structure

Abstract

Provided in the embodiments of the present application are a semiconductor structure, an integrated circuit, and a preparation method for the semiconductor structure, relating to the technical field of semiconductors. The semiconductor structure has good quality and is stable. The semiconductor structure comprises a substrate, a nucleation layer, and an epitaxial layer which are arranged in a stacked manner. The substrate comprises a first region and a second region, wherein the nucleation layer on the first region and the nucleation layer on the second region are different in crystal orientation, and the polarization direction of the epitaxial layer on the first region is different from the polarization direction of the epitaxial layer on the second region.

Description

Semiconductor structure, integrated circuit, and method for preparing semiconductor structure This application claims the priority of the Chinese patent application filed with the State Intellectual Property Office on September 11, 2023, with application number 202311170776.3 and application name “Semiconductor structure, integrated circuit and method for preparing semiconductor structure”, all contents of which are incorporated by reference in this application. Technical Field The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, an integrated circuit, and a method for preparing the semiconductor structure. Background Art Electronic devices are used to process radio frequency signals through radio frequency devices provided therein. For example, the radio frequency signal power generated in the radio frequency modulation circuit of the electronic device is very small, and the radio frequency signal needs to be amplified by a radio frequency power amplifier to obtain sufficient radio frequency power before it can be fed to the antenna for radiation. At present, the radio frequency power amplifier generally includes a semiconductor structure, and the semiconductor structure can be a high electron mobility transistor (HEMT). Among them, the semiconductor structure includes a stacked substrate and an epitaxial layer. When the semiconductor structure is a high electron mobility transistor, in order to further improve the electron mobility of the high electron mobility transistor, the material of the epitaxial layer in the high electron mobility transistor is usually set to gallium nitride, because gallium nitride has a better two-dimensional electron gas limit threshold, lower ohmic contact resistance and stronger short channel effect suppression ability. However, the semiconductor structure whose epitaxial layer material is gallium nitride usually has problems such as poor quality and instability. Summary of the invention The embodiments of the present application provide a semiconductor structure, an integrated circuit, and a method for preparing a semiconductor structure. The quality of the semiconductor structure is good and relatively stable. In a first aspect, a semiconductor structure is provided, comprising: a stacked substrate, a nucleation layer, and an epitaxial layer; the substrate comprises a first region and a second region; the nucleation layer on the first region has a different crystal orientation from the nucleation layer on the second region; the polarization direction of the epitaxial layer on the first region is different from the polarization direction of the epitaxial layer on the second region. In the semiconductor structure, the polarization direction of the epitaxial layer on the first region is different from the polarization direction of the epitaxial layer on the second region, so that the epitaxial layer can maximize its advantages and avoid the disadvantages of the existence of a single polarization direction, thereby improving the stability of the semiconductor structure. In addition, in the semiconductor structure, the presence of the nucleation layer can reduce the defect density of the epitaxial layer, further improving the quality of the semiconductor structure. Optionally, in the stacking direction, the thickness of the nucleation layer on the first region is different from the thickness of the nucleation layer on the second region. Optionally, the substrate further includes a third region, the first region and the third region are respectively arranged on both sides of the second region; the crystal orientation of the nucleation layer on the third region is the same as that of the nucleation layer on the first region; the polarization direction of the epitaxial layer on the third region is the same as that of the epitaxial layer on the first region. In this example, the polarization direction of the epitaxial layer on the third region is the same as that of the epitaxial layer on the first region. In such a semiconductor structure, a region with a different polarization direction may be arranged between two regions with the same polarization direction, thereby improving the flexibility of the semiconductor structure. Optionally, the semiconductor structure further includes an electrode disposed on the epitaxial layer. Optionally, the semiconductor structure further includes a barrier layer disposed between the epitaxial layer and the electrode. Optionally, the material of the epitaxial layer includes one or more of the following: aluminum nitride, gallium nitride, indium nitride, and boron nitride. Optionally, the material of the substrate includes any one of the following: sapphire, silicon, silicon carbide, and gallium oxide. In a second aspect, an integrated circuit is provided, comprising a packaging structure and one or more semiconductor structures as described in any one of the first aspects above, wherein the semiconductor structure is packaged inside the packaging structure. According to a third aspect, an electronic device is provided, comprising a printed circuit board and the integrated circuit as described in the second aspect, wherein the integrated circuit is coupled to the printed circuit board. In a fourth aspect, a method for preparing a semiconductor structure is provided, comprising: producing a nucleation layer on a substrate, the substrate comprising a first region and a second region, the nucleation layer on the first region having a different crystal orientation from the nucleation layer on the second region; growing an epitaxial layer material on the nucleation layer by an epitaxial process to form an epitaxial layer, wherein the polarization direction of the epitaxial layer on the first region is different from the polarization direction of the epitaxial layer on the second region. Optionally, a nucleation layer is produced on a substrate, including: depositing a nucleation layer material on the substrate through a deposition process to form a first deposition structure, wherein the first deposition structure covers a first region and the first deposition structure does not cover a second region; and growing a nucleation layer material on the second region and the first deposition structure through one or more epitaxial processes to form a nucleation layer. Optionally, the substrate also includes a third region, and the first region and the third region are respectively arranged on both sides of the second region; the crystal orientation of the nucleation layer on the third region is the same as that of the nucleation layer on the first region; the polarization direction of the epitaxial layer on the third region is the same as that of the epitaxial layer on the first region; and the first deposition structure also covers the third region. Optionally, a nucleation layer material is deposited on a substrate by a deposition process to form a first deposition structure, including: making a mask covering the substrate; performing photolithography on the mask to form a first deposition structure window, wherein the first deposition structure window is located on the first region; depositing a nucleation layer material at the first deposition structure window by a deposition process to form a first deposition structure; and removing the mask to expose the second region. Optionally, a nucleation layer material is deposited on a substrate by a deposition process to form a first deposition structure, including: depositing a nucleation layer material on a substrate by a deposition process to form a second deposition structure, wherein the second deposition structure covers the substrate; making a mask covering the second deposition structure; photolithography the mask to form an etching window, wherein the etching window is located on the second region; etching the second deposition structure according to the etching window to form a first deposition structure; and removing the mask to expose the first deposition structure. Optionally, after growing an epitaxial layer material on the nucleation layer through an epitaxial process to form the epitaxial layer, the method further includes: manufacturing an electrode on the epitaxial layer. Optionally, before forming the electrode on the epitaxial layer, the method further includes: forming a barrier layer on the epitaxial layer. Optionally, the material of the epitaxial layer includes one or more of the following: aluminum nitride, gallium nitride, indium nitride, and boron nitride. Optionally, the material of the substrate includes any one of the following: sapphire, silicon, silicon carbide, and gallium oxide. Among them, the technical effects brought about by any possible implementation method of the second to fourth aspects can refer to the technical effects brought about by different implementation methods of the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS FIG1 is a schematic diagram of the structure of a terminal provided in an embodiment of the present application; FIG2 is a schematic diagram of the structure of a network device provided in an embodiment of the present application; FIG3 is a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application; FIG4 is a schematic diagram of the atomic structure of gallium nitride provided in an embodiment of the present application; FIG5 is a flow chart of the preparation of a semiconductor structure provided by the present application; FIG6 is a schematic structural diagram of a semiconductor structure provided by the present application; FIG7 is a schematic diagram of a semiconductor structure provided in an embodiment of the present application; FIG8 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present application; FIG9 is a schematic structural diagram of a semiconductor structure provided in yet another embodiment of the present application; FIG10 is a flow chart of a method for preparing a semiconductor structure provided in yet another embodiment of the present application; FIG11 is a schematic structural diagram of a semiconductor structure in a method for preparing a semiconductor structure provided in yet another embodiment of the present application; FIG12 is a schematic structural diagram of a semiconductor structure in a method for preparing a semiconductor structure provided in another embodiment of the present application; FIG13 is a schematic structural diagram of a semiconductor structure in a method for preparing a semiconductor structure provided in yet another embodiment of the present application; FIG. 14 is a schematic structural diagram of a semiconductor structure in a method for preparing a semiconductor structure provided in yet another embodiment of the present application. DETAILED DESCRIPTION The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Unless otherwise defined, all scientific and technological terms used herein have the same meaning as those known to those of ordinary skill in the art. In the embodiments of the present application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B, which may represent: A exists alone, A and B exist at the same time, and B exists alone, wherein A and B may be singular or plural. The character " / " generally indicates that the associated objects before and after are a kind of "or" relationship. "At least one of the following (individuals)" or its similar expressions refers to any combination of these items, including any combination of single items (individuals) or plural items (individuals). For example, at least one of a, b or c (individuals) may represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c may be single or multiple. In addition, in the embodiments of the present application, the words "first", "second" and the like do not limit the quantity and order. In addition, in the embodiments of the present application, directional terms such as "upper" and "lower" refer to the directions in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and may change accordingly according to the change of the orientation of the components in the drawings. In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way. The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The integrated circuit provided in the embodiments of the present application can be applied to various electronic devices, which can be different types of terminals such as computers, mobile phones, tablet computers, wearable devices, and vehicle-mounted devices, and can also be network devices such as base stations. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device. Referring to Figure 1, Figure 1 is a schematic diagram of the structure of a terminal 100 provided in an embodiment of the present application. The terminal 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, and a display screen 170, etc. It is to be understood that the structures illustrated in the embodiments of the present application do not constitute specific limitations on the terminal 100. In other embodiments of the present application, the terminal 100 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware. The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors. The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the processor. In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc. The charging management module 140 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger through the USB interface 130. In some wireless charging embodiments, the charging management module 140 may receive wireless charging input through a wireless charging coil of the terminal 100. While the charging management module 140 is charging the battery 142, it may also power the terminal 100 through the power management module 141. The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives the charging input of the battery 142 and / or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 170, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device. The wireless communication function of the terminal 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor. Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in terminal 100 can be used to cover a single or multiple Communication frequency band. Different antennas can also be reused to improve the utilization of the antenna. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch. The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G applied on the terminal 100. The mobile communication module 150 may include one or more filters, switches, power amplifiers, low noise amplifiers (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In other embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110. The modem processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to a speaker, a receiver, etc.), or displays an image or video through the display screen 170. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules. The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the terminal 100. The wireless communication module 160 can be one or more devices integrating one or more communication processing modules. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the frequency of the electromagnetic wave signal and performs filtering, and sends the processed signal to the processor 110. The wireless communication module 160 can also receive the radio frequency signal to be sent from the processor 110, modulate the frequency of it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2. In some embodiments, the antenna 1 of the terminal 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the terminal 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology, etc. The GNSS may include a global positioning system (GPS), a global navigation satellite system (GLONASS), a Beidou navigation satellite system (BDS), a quasi-zenith satellite system (QZSS) and / or a satellite based augmentation system (SBAS). The terminal 100 implements the display function through a GPU, a display screen 170, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 170 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information. The display screen 170 is used to display images, videos, etc. The display screen 170 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light emitting diode or an active-matrix organic light emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light emitting diode (QLED), etc. In some embodiments, the terminal 100 may include 1 or N display screens 170, where N is a positive integer greater than 1. The terminal 100 can implement a shooting function through an ISP, a camera, a video codec, a GPU, a display screen 170, and an application processor. The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the terminal 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function, such as storing files such as music and videos in the external memory card. The internal memory 121 may be used to store one or more computer programs, which include instructions. The processor 110 can enable the terminal 100 to perform various functional applications and data processing by running the above instructions stored in the internal memory 121. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system; the program storage area can also store one or more applications (such as a gallery, contacts, etc.). The data storage area can store data (such as photos, contacts, etc.) created during the use of the terminal 100. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, universal flash storage (UFS), etc. In other embodiments, the processor 110 enables the terminal 100 to perform various functional applications and data processing by running instructions stored in the internal memory 121, and / or instructions stored in a memory provided in the processor. In addition, the terminal 100 may also include one or more components such as an audio module, a speaker, a receiver, a microphone, an earphone interface, a sensor module, a display screen, a button, a motor, an indicator, and a subscriber identification module (SIM) card interface. Referring to FIG. 2, FIG. 2 is a schematic diagram of the structure of a network device 20 provided in an embodiment of the present application. The network device 20 takes a 5G base station as an example. The network device 20 can be divided into different architectures such as a baseband processing unit (BBU)-active antenna unit (AAU), a central unit-distribute unit (CU-DU)-AAU, a BBU-remote radio unit (RRU)-antenna, a CU-DU-RRU-Antenna, and an integrated 5G base station (5G node base station, gNB). Taking a base station with a BBU-RRU architecture as an example, as shown in FIG. 2, the network device 20 includes a BBU21, an RRU22, and an antenna 23; wherein the BBU21 and the RRU22 are connected by optical fiber, and the interface between the two is based on an open common public radio interface (CPRI) and an open base station architecture (OBSAI). Among them, the BBU21 processes the generated baseband signal through the RRU22 and sends it to the antenna 23 for transmission. RRU22 includes a digital intermediate frequency module 221, a transceiver module 222, a power amplifier 223 (PA) and a filter 224. The digital intermediate frequency module 221 realizes modulation and demodulation, digital up and down conversion, digital to analog converter (D / A) and other functions of the baseband signal transmitted by optical fiber to form an intermediate frequency signal; the transceiver module 222 completes the conversion of the intermediate frequency signal to the radio frequency signal; the power amplifier 223 is used to amplify the power of the low-power radio frequency signal; the filter 224 is used to filter the radio frequency signal and then transmit the radio frequency signal through the antenna 23. The integrated circuit provided by the embodiment of the present application can be applied to the terminal 100 shown in FIG. 1 or the network device 20 shown in FIG. 2. For example, the integrated circuit provided by the embodiment of the present application can be the processor 110, the external memory interface 120, the internal memory 121, the charging management module 140, the power management module 141, the mobile communication module 150, the wireless communication module 160, etc. in the terminal 100 shown in FIG. 1, or the integrated circuit provided by the embodiment of the present application can be the BBU 21, the digital intermediate frequency module 221, the transceiver module 222, the power amplifier 223, the filter 224, etc. in the network device 20 shown in FIG. 2. Of course, the specific application scenario is not limited to the terminal shown in FIG. 1 and the network device shown in FIG. 2. Referring to FIG. 3 , FIG. 3 is a schematic diagram of the structure of an integrated circuit provided by an embodiment of the present application, wherein the integrated circuit 30 includes a semiconductor structure 31 and a packaging structure 32, wherein the semiconductor structure 31 is packaged inside the packaging structure 32. As shown in FIG. 3 , the packaging structure 32 specifically includes: a heat dissipation substrate 321, wherein in order to improve the conductivity and heat dissipation of the heat dissipation substrate 321, the heat dissipation substrate 321 may adopt a composite material, such as a laminated structure formed by copper Cu / molybdenum Mo / copper Cu; the semiconductor structure 31 is bonded to the heat dissipation substrate 321 by sintering silver. When the semiconductor structure 31 includes electrodes, part of the electrodes of the semiconductor structure 31 shown in FIG. 3 are conductively connected to the heat dissipation substrate 321; in addition, part of the electrodes of the semiconductor structure 31 may also be connected to the pins by gold wire bonding, and the pins are arranged on an insulating layer (for example, insulating ceramic), and the insulating layer is bonded to the heat dissipation substrate 321 by an insulating adhesive. The packaging structure 32 includes a packaging shell 322 , which is bonded to a heat dissipation substrate 321 by an insulating adhesive, and one end of a pin is exposed from the packaging structure to connect to other circuits. The semiconductor structure 31 is disposed in a space surrounded by the packaging shell 322 and the heat dissipation substrate 321 . Exemplarily, when the semiconductor structure 31 includes electrodes, the semiconductor structure 31 may be a diode, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or other transistors. Exemplarily, when the semiconductor structure 31 is a diode, the electrodes in the semiconductor structure 31 are specifically an anode (+) and a cathode (-); when the semiconductor structure 31 is a BJT, the electrodes in the semiconductor structure 31 are specifically a collector electrode (C), a base electrode (B), and an emitter electrode (E); when the semiconductor structure 31 is a HEMT, the electrodes in the semiconductor structure 31 are specifically a source electrode (C). (source electrode, S), drain electrode (drain electrode, D) and gate electrode (gate electrode, G). In order to improve the performance of the device, an epitaxial layer is often provided in the semiconductor structure 31. The material of the epitaxial layer includes gallium nitride. There are two polar structures of gallium nitride, which are respectively called nitrogen-face gallium nitride and gallium-face gallium nitride. As shown in FIG4 , FIG4 (a) shows a schematic diagram of the structure of gallium-face gallium nitride. According to the placement of FIG4 , in gallium-face gallium nitride, each gallium nitride bond is gallium atom-nitrogen atom from top to bottom, and the polarization direction of gallium-face gallium nitride is

[0001] FIG4 (b) shows a schematic diagram of the structure of nitrogen-surface gallium nitride. According to the placement of FIG4 , in the nitrogen-surface gallium nitride, each gallium nitride bond is a nitrogen atom-gallium atom from top to bottom, and the polarization direction of the nitrogen-surface gallium nitride is [000-1]. At present, the material in the epitaxial layer in the semiconductor structure 31 is usually gallium-surface gallium nitride. Compared with gallium-surface gallium nitride, nitrogen-surface gallium nitride has better two-dimensional electron gas limit threshold, lower ohmic contact resistance and stronger short channel effect suppression ability. However, nitrogen-surface gallium nitride has disadvantages such as poor crystal quality and high background carrier concentration. In order to maximize the advantages of nitrogen-surface gallium nitride and avoid its defects, more and more epitaxial layers are made of mixed polarity gallium nitride, which includes nitrogen-surface gallium nitride and gallium-surface gallium nitride. Referring to FIG. 5 , FIG. 5 is a flow chart of preparing a semiconductor structure 50. The gallium nitride in the gallium nitride material layer in the semiconductor structure 50 prepared in FIG. 5 is mixed polarity gallium nitride. Referring to FIG. 5 (e), the semiconductor structure 50 shown in FIG. 5 includes a stacked substrate 51, a nucleation layer 52, and an epitaxial layer 53. The epitaxial layer 53 includes a gallium-face gallium nitride 531 and a nitrogen-face gallium nitride 532. In the stacking direction, the gallium-face gallium nitride 531 is in contact with the nucleation layer 52, the gallium-face gallium nitride 531 is not in contact with the substrate 51, and the nitrogen-face gallium nitride 532 is in contact with the substrate 51. Specifically, (a) in FIG. 5 is the first step of preparing the semiconductor structure 50, specifically, growing a nucleation layer material on a substrate 51 by pulsed laser molecular beam epitaxy (PLMBE), thereby forming a nucleation layer 52 covering the substrate 51. (b) in FIG. 5 is the second step of preparing the semiconductor structure 50, specifically, making a metal mask 501 covering the nucleation layer 52 on the nucleation layer 52, shielding the metal mask 501 by a light shield (mask), and then performing photolithography to form an etching window 502. (c) in FIG. 5 is the third step of preparing the semiconductor structure 50, etching the nucleation layer 52 below the etching window 502 by dry etching and / or wet etching, and stopping etching after etching to the substrate 51 to form an etching groove 503. (d) in FIG. 5 is the fourth step of preparing the semiconductor structure 50, specifically, removing the metal mask 501 to expose the nucleation layer 52 to the outside. (e) in Figure 5 is the fifth step of preparing the semiconductor structure 50, specifically, overgrowing gallium nitride material on the substrate 51 by PLMBE to form an epitaxial layer 53, wherein the gallium nitride in the epitaxial layer 53 is mixed polarity gallium nitride, and the epitaxial layer 53 includes gallium-face gallium nitride 531 and nitrogen-face gallium nitride 532. In the stacking direction, the gallium-face gallium nitride 531 is in contact with the nucleation layer 52, the gallium-face gallium nitride 531 is not in contact with the substrate 51, and the nitrogen-face gallium nitride 532 is in contact with the substrate 51. Among them, in the steps of preparing the semiconductor structure 50 shown in FIG. 5 , it is necessary to ensure that the etching reaches the substrate 51 during the third etching step, which results in a complex process and a high process cost. Referring to FIG6 , FIG6 is a schematic diagram of the structure of a semiconductor structure 60, wherein the gallium nitride in the gallium nitride material layer in the semiconductor structure 60 shown in FIG6 is mixed polarity gallium nitride. Referring to FIG6 , the semiconductor structure 60 includes a stacked substrate 61, a nucleation layer 62, and an epitaxial layer 63, wherein the epitaxial layer 63 includes a gallium-face gallium nitride 631 and a nitrogen-face gallium nitride 632, wherein the nitrogen-face gallium nitride 632 is disposed on a side of the gallium-face gallium nitride 631 away from the nucleation layer 62. Among them, in the semiconductor structure 60 shown in Figure 6, the manufacturing method of the epitaxial layer 63 is: epitaxially grow the gallium nitride material to form the epitaxial layer through an epitaxial process, and inject magnesium Mg ions into the side of the epitaxial layer away from the nucleation layer 62 through an ion implantation process to form nitrogen-face gallium nitride 632 and gallium-face gallium nitride 631, wherein the thickness of the nitrogen-face gallium nitride 632 and the thickness of the gallium-face gallium nitride 631 can be controlled by controlling the depth of ion implantation. In the semiconductor structure 60 shown in FIG. 6 , stacked nitrogen-faced gallium nitride and gallium-faced gallium nitride can only be fabricated in the stacking direction, while in an actual semiconductor structure, nitrogen-faced gallium nitride and gallium-faced gallium nitride need to be fabricated in a direction parallel to the substrate 61 . To this end, an embodiment of the present application provides a semiconductor structure in which the polarization direction of the epitaxial layer is different. Specifically, the polarization direction of the epitaxial layer changes in a direction parallel to the substrate. Referring to FIG. 7 , FIG. 7 is a schematic diagram of a semiconductor structure 31 provided in an embodiment of the present application, wherein the semiconductor structure 31 includes: a stacked substrate 311, a nucleation layer 312, and an epitaxial layer 313; the substrate 311 includes a first region 3111 and a second region 3112; the nucleation layer 312 on the first region 3111 and the nucleation layer 312 on the second region 3112 have different crystal orientations; the polarization direction of the epitaxial layer 313 on the first region 3111 and the polarization direction of the epitaxial layer 313 on the second region 3112 are different. In the semiconductor structure 31, the polarization direction of the epitaxial layer 313 on the first region 3111 and the polarization direction of the epitaxial layer 313 on the second region 3112 are different. The polarization directions of the epitaxial layer 313 are different, so that the epitaxial layer 313 can maximize its advantages and avoid the disadvantages of a single polarization direction, thereby improving the stability of the semiconductor structure 31. In addition, in the semiconductor structure 31, the presence of the nucleation layer 312 can reduce the defect density of the epitaxial layer 313, further improving the quality of the semiconductor structure 31. Exemplarily, in the stacking direction, the thickness of the nucleation layer 312 on the first region 3111 is different from the thickness of the nucleation layer 312 on the second region 3112. Specifically, as shown in FIG7 , the polarization direction of the epitaxial layer 313 on the first region 3111 is specifically

[0001] , the polarization direction of the epitaxial layer 313 on the second region 3112 is specifically [000-1], and the thickness of the nucleation layer 312 on the first region 3111 is greater than the thickness of the nucleation layer 312 on the second region 3112. In some embodiments, the polarization direction of the epitaxial layer 313 on the first region 3111 is specifically [000-1], and the polarization direction of the epitaxial layer 313 on the second region 3112 is specifically

[0001] , then the thickness of the nucleation layer 312 on the first region 3111 is less than the thickness of the nucleation layer 312 on the second region 3112. Exemplarily, the thickness of the nucleation layer 312 below the epitaxial layer 313 with a polarization direction of

[0001] is greater than the thickness of the nucleation layer 312 below the epitaxial layer 313 with a polarization direction of [000-1]. The material of the epitaxial layer 313 includes one or more of the following: aluminum nitride AlN, gallium nitride GaN, indium nitride InN, and boron nitride BN. When the material of the epitaxial layer is gallium nitride GaN, the epitaxial layer 313 with a polarization direction of

[0001] is also called gallium-face gallium nitride, and the epitaxial layer 313 with a polarization direction of [000-1] is also called nitrogen-face gallium nitride. Exemplarily, as shown in FIG. 7 , the material of the substrate 311 includes any of the following: sapphire, silicon, silicon carbide, and gallium oxide. In some embodiments, referring to Figure 8, based on the semiconductor structure 31 shown in Figure 7, in the semiconductor structure 31 shown in Figure 8, the substrate 311 also includes a third region 3113, wherein the first region 3111 and the third region 3113 are respectively arranged on both sides of the second region 3112, wherein the crystal orientation of the nucleation layer 312 on the third region 3113 is the same as the crystal orientation of the nucleation layer 312 on the first region 3111; the polarization direction of the epitaxial layer 313 on the third region 3113 is the same as the polarization direction of the epitaxial layer 313 on the first region 3111. Specifically, as shown in FIG8 , the polarization direction of the epitaxial layer 313 on the first region 3111 is specifically

[0001] , the polarization direction of the epitaxial layer 313 on the second region 3112 is specifically [000-1], the polarization direction of the epitaxial layer 313 on the third region 3113 is specifically

[0001] , the thickness of the nucleation layer 312 on the first region 3111 is greater than the thickness of the nucleation layer 312 on the second region 3112, and the thickness of the nucleation layer 312 on the third region 3113 is greater than the thickness of the nucleation layer 312 on the second region 3112. The thickness of the nucleation layer 312 on the third region 3113 may be equal to or different from the thickness of the nucleation layer 312 on the first region 3111. Exemplarily, electrodes may be further provided on the basis of the semiconductor structure 31 shown in FIG7 , and the electrodes may specifically be an anode (+) and a cathode (-) to form a diode. Alternatively, electrodes may be further provided on the basis of the semiconductor structure 31 shown in FIG8 , and the electrodes may specifically be an emitter E, a base B, and a collector C to form a BJT. Alternatively, electrodes may be further provided on the basis of the semiconductor structure 31 shown in FIG8 , and the electrodes may specifically be a source S, a drain D, and a gate G to form a HEMT. Exemplarily, referring to FIG. 9 , based on the semiconductor structure 31 shown in FIG. 8 , the semiconductor structure 31 shown in FIG. 9 further includes electrodes disposed on the epitaxial layer 313, and the electrodes are specifically a source S, a drain D, and a gate G. The semiconductor structure 31 shown in FIG. 9 is specifically a HEMT. As shown in FIG. 9 , the semiconductor structure 31 further includes a barrier layer 314 (for example, a Schottky barrier layer) disposed between the epitaxial layer 313 and the electrode; further includes an evaporation layer 315 disposed between the barrier layer 314 and the source S; and an evaporation layer 316 disposed between the barrier layer 314 and the drain D, wherein the evaporation layer 315 is not in contact with the evaporation layer 316, the gate G is in contact with the barrier layer 314, and the gate G is also located between the evaporation layer 315 and the evaporation layer 316. Exemplarily, the epitaxial layer 313 of the semiconductor structure 31 is specifically a channel layer of the HEMT, and an active region exists in the epitaxial layer 313, and the active region is a region in the epitaxial layer 313 directly below the gate G, wherein the active region is arranged on the second region 3112 of the substrate 311, the fusing layer 315 is arranged on the first region 3111 of the substrate 311, and the fusing layer 316 is arranged on the third region 3113 of the substrate 311, wherein the polarization direction of the epitaxial layer 313 on the first region 3111 is

[0001] , the polarization direction of the epitaxial layer 313 on the second region 3112 is [000-1], and the polarization direction of the epitaxial layer 313 on the third region 3113 is

[0001] . The working principle of the semiconductor structure 31 is to control the potential well depth of the heterojunction formed by the barrier layer 314 above the epitaxial layer 313 and the epitaxial layer 313 by applying a gate voltage to the gate G, so as to control the concentration of the two-dimensional electron gas generated above the barrier layer 314 (refer to the dotted line shown on the barrier layer 314 shown in FIG9 ), thereby controlling the working current of the device. In addition, in order to further improve the performance of the semiconductor structure 31 (for example, to increase the concentration of the two-dimensional electron gas, reduce the leakage current or increase the device response speed, etc.), other semiconductor material layers may be provided between the epitaxial layer 313 and the barrier layer 314, for example: one or more buffer layers, and doping layers may also be provided between the multiple buffer layers. As shown in FIG9 , a buffer layer 317, a doping layer 318 and a buffer layer 319 are provided from bottom to top between the epitaxial layer 313 and the barrier layer 314. Of course, the above description only describes a typical layer structure of a HEMT. In order to improve the performance of the device in other embodiments, the semiconductor structure 31 shown in FIG. 9 may also include more material layers or fewer material layers. 10 , an embodiment of the present application provides a method for preparing a semiconductor structure 31 , wherein the method for preparing the semiconductor structure 31 comprises the following steps: S101, forming a nucleation layer on a substrate. Exemplarily, as shown in FIG11 , a substrate 311 required for manufacturing a semiconductor structure 31 is prepared first, wherein the material of the substrate 311 includes any of the following: sapphire, silicon, silicon carbide, gallium oxide, wherein no dopant may be provided in the substrate 311, or dopant may be provided in the substrate 311. The substrate 311 includes a first region 3111 and a second region 3112. After the substrate 311 is prepared, a nucleation layer 312 may be fabricated on the substrate 311 , wherein the nucleation layer 312 on the first region 3111 and the nucleation layer 312 on the second region 3112 have different crystal orientations. Specifically, forming a nucleation layer 312 on a substrate 311 includes the following steps: S1011 , depositing a nucleation layer material on a substrate through a deposition process to form a first deposition structure. As shown in FIG. 11 , the first deposition structure 1003 covers the first region 3111 , and the first deposition structure does not cover the second region 3112 . Illustratively, the embodiments of the present application provide two steps for making the first deposition structure, as shown in FIG. 12 and FIG. 13 . Referring to FIG. 12 , FIG. 12 is a diagram showing the steps of manufacturing the first deposition structure. In FIG. 12 , manufacturing the first deposition structure comprises the following four steps: The first step is shown in (a) of FIG. 12 , and specifically involves making a mask 1001 covering the substrate 311 . The second step is as shown in (b) of FIG12, specifically, the mask 1001 is photolithographically processed to form the first deposition structure window 1002. As shown in (b) of FIG12, the mask 1001 is shielded by a light shielding plate, the light shielding plate includes a light-transmitting area and a light-impermeable area, and then light is irradiated. After the light is irradiated, the mask 1001 corresponding to the light-transmitting area of ​​the light shielding plate will be activated, and the activated mask 1001 will be easily removed. The mask 1001 corresponding to the light-impermeable area of ​​the light shielding plate will not be activated, and the unactivated mask 1001 will not be removed. Specifically, the light-transmitting area of ​​the light shielding plate is aligned with the first area 3111, and the light-impermeable area of ​​the light shielding plate is aligned with the second area 3112, and then light is irradiated to form the first deposition structure window 1002. The first deposition structure window 1002 is located on the first area 3111. The third step is shown in (c) of FIG. 12 , specifically, a nucleation layer material is deposited at the first deposition structure window 1002 by a deposition process to form a first deposition structure 1003. Referring to (c) of FIG. 12 , the nucleation layer material is deposited by any deposition process of metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The nucleation layer material can be deposited on the first region 3111 corresponding to the first deposition structure window 1002, and the nucleation layer material cannot be deposited on the mask 1001, thereby forming the first deposition structure 1003, the first deposition structure 1003 covers the first region 3111 of the substrate 311, and the first deposition structure 1003 does not cover the mask 1001 and the second region 3112 under the mask 1001. Exemplarily, the nucleation layer material includes aluminum nitride AlN. The fourth step is shown in (d) of FIG12, specifically, removing the mask 1001 to expose the second region 3112 of the substrate 311. The mask 1001 may be directly photolithographically activated to remove the mask 1001, and then the mask 1001 is removed to form the structure shown in (d) of FIG12. Referring to FIG. 13 , FIG. 13 is a diagram showing the steps of manufacturing the first deposition structure in the second method. In FIG. 13 , manufacturing the first deposition structure comprises the following five steps: The first step is shown in (a) of FIG. 13 , specifically, a nucleation layer material is deposited on the substrate 311 by a deposition process to form a second deposition structure 1004, wherein the second deposition structure 1004 covers the substrate 311. Referring to (a) of FIG. 13 , a nucleation layer material is deposited on the substrate 311 by any deposition process of MOCVD, PVD, and ALD to form a second deposition structure 1004 covering the substrate 311. The second step is shown in (b) of FIG. 13 , and specifically involves making a mask 1005 covering the second deposition structure 1004 . The third step is shown in (c) of FIG. 13 , specifically, photolithography is performed on the mask 1005 to form an etched window 1006. As shown in (c) of FIG. 13 , the mask 1005 is shielded by a light shielding plate, the light-transmitting area of ​​the light shielding plate is aligned with the second area 3112, and the light-impermeable area of ​​the light shielding plate is aligned with the first area 3111, and then light is irradiated to form an etched window 1006, and the etched window 1006 exposes the second deposition structure 1004 on the second area 3112. The fourth step is shown in (d) of FIG. 13 , which is to form a second deposited film on the second region 3112 according to the etching window 1006. The second deposition structure 1004 is etched to form the first deposition structure 1003. As shown in (d) of FIG. 13 , dry etching and / or wet etching can be used to etch away the second deposition structure 1004 on the second region 3112 according to the etching window 1006 to form the first deposition structure 1003, wherein the etching needs to be stopped after the substrate 311 is etched. The fifth step is to remove the mask 1005 to expose the first deposition structure 1003. The mask 1001 may be directly photolithographically processed to activate the mask 1001, and then the mask 1001 is removed to form a structure such as that shown in (d) in FIG. 12 . After executing the four steps shown in FIG. 12 or the five steps shown in FIG. 13 , the first deposition structure 1003 can be manufactured on the substrate 311 , and the first deposition structure 1003 covers the first region 3111 of the substrate 311 , but does not cover the second region 3112 of the substrate 311 . S1012, epitaxially growing a nucleation layer material on the second region and the first deposition structure through one or more epitaxial processes to form a nucleation layer. Exemplarily, specifically, on the structure shown in (d) of FIG. 12 , a nucleation layer material is epitaxially grown through one or more epitaxial processes, and the epitaxial processes include any one of MOCVD, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), and PVD, thereby forming the nucleation layer 312 shown in FIG. 11 , and the nucleation layer 312 on the first region 3111 has a different crystal orientation from the nucleation layer 312 on the second region 3112. Exemplarily, when a nucleation layer 312 of a required thickness can be formed through a single epitaxial process, the nucleation layer material can be epitaxially grown through a single epitaxial process to thereby form the nucleation layer 312; Exemplarily, when the thickness of the nucleation layer 312 formed through a single epitaxial process is less than the required thickness of the nucleation layer 312, the nucleation layer material can be epitaxially grown through multiple epitaxial processes to thereby form the nucleation layer 312. Exemplarily, between step S1011 and step S1012, it also includes: performing high-temperature nitridation treatment on the second region 3112 and the upper surface of the first deposition structure 1003, and in step S1012, when epitaxially growing the nucleation layer material (specifically aluminum nitride AlN) in the epitaxial process, the reaction gas sources introduced are trimethylaluminum (C3H9Al) and ammonia (NH3), and the molar ratio of trimethylaluminum to ammonia is relatively high, for example, the molar ratio of trimethylaluminum to ammonia can be greater than 200, that is, V / III>200, so that the epitaxial nucleation layer material grows on the first deposition structure 1003 in the same crystal direction as that of the first deposition structure 1003, and the nucleation layer material on the second region 3112 of the substrate 311 grows in a crystal direction different from that of the first deposition structure 1003, thereby forming a nucleation layer 312. At this point, the nucleation layer 312 is completed. S102 , growing an epitaxial layer material on the nucleation layer through an epitaxial process to form an epitaxial layer. The polarization direction of the epitaxial layer 313 on the first region 3111 is different from the polarization direction of the epitaxial layer 313 on the second region 3112 . Specifically, the epitaxial layer material may be epitaxially grown on the nucleation layer 312 shown in FIG11 by any epitaxial process of MOCVD, MBE, HVPE, and PVD to form the epitaxial layer 313 shown in FIG7 . The epitaxial epitaxial layer material grows on the nucleation layer 312 on the second region in the same crystal direction as the nucleation layer 312 on the second region 3112, and the polarization direction is easily reversed to [000-1], and grows on the nucleation layer 312 on the first region in the same crystal direction as the nucleation layer 312 on the first region 3111, and the polarization direction is not easily reversed, and the polarization direction remains

[0001] , thereby forming the epitaxial layer 313. Exemplarily, the thickness of the nucleation layer 312 on the first region 3111 is different from the thickness of the nucleation layer 312 on the second region 3112. Specifically, the thickness of the nucleation layer 312 below the epitaxial layer 313 with a polarization direction of [000-1] is less than the thickness of the nucleation layer 312 below the epitaxial layer 313 with a polarization direction of

[0001] because when the nucleation layer is manufactured, the nucleation layer 312 below the epitaxial layer 313 with a polarization direction of

[0001] includes the first deposition structure 1003 shown in FIG. 11, and the nucleation layer 312 below the epitaxial layer 313 with a polarization direction of [000-1] does not include the first deposition structure 1003 shown in FIG. 11. Exemplarily, when it is necessary to manufacture the semiconductor structure 31 shown in FIG8 , a nucleation layer is manufactured on a substrate. Referring to FIG14 , the substrate 311 includes a first region 3111, a second region 3112, and a third region 3113, wherein the first region 3111 and the third region 3113 are respectively arranged on both sides of the second region 3112. When manufacturing the nucleation layer 312, firstly, a nucleation layer material is deposited on the substrate 311 by a deposition process to form a first deposition structure 1003, wherein the first deposition structure 1003 covers the first region 3111 and the third region 3113, and the first deposition structure 1003 does not cover the second region 3112, and then, on the second region 3112 and the first deposition structure 1003, a nucleation layer material is grown by one or more epitaxial processes to form the nucleation layer 312. The specific steps are shown in the above step S101, which will not be described in detail here. After the nucleation layer 312 is fabricated, the above step S102 is performed to grow an epitaxial layer material on the nucleation layer by an epitaxial process to form an epitaxial layer 313. Finally, the semiconductor structure 31 shown in FIG. 8 is obtained. For example, after the semiconductor structure 31 shown in FIG. 8 is manufactured, in some embodiments, the epitaxial layer 313 needs to be Chemical mechanical polishing (CMP) is performed to make the upper surface of the epitaxial layer 313 flat, and then electrodes are formed on the epitaxial layer 313, which electrodes may be, for example, a source electrode S, a drain electrode D, and a gate electrode G, to form the semiconductor structure 31 shown in FIG9 . Exemplarily, a barrier layer 314 needs to be formed on the epitaxial layer 313 first, and then an evaporating layer 315 and an evaporating layer 316 are formed on the barrier layer 314, and the evaporating layer 315 and the evaporating layer 316 are not in contact with each other, and then a source electrode S is formed on the evaporating layer 315, a gate electrode G is formed on the barrier layer 314, and a drain electrode D is formed on the evaporating layer 316, wherein the gate electrode G is also located between the evaporating layer 315 and the evaporating layer 316. Among them, the capping layer 315 is arranged on the first area 3111 of the substrate 311, the capping layer 316 is arranged on the third area 3113 of the substrate 311, and the active area corresponding to the gate G is arranged on the second area 3112 of the substrate 311, wherein the polarization direction of the epitaxial layer 313 on the first area 3111 is

[0001] , the polarization direction of the epitaxial layer 313 on the second area 3112 is [000-1], and the polarization direction of the epitaxial layer 313 on the third area 3113 is

[0001] . In some embodiments, in order to further improve the performance of the semiconductor structure 31 (for example, to increase the concentration of the two-dimensional electron gas, to reduce leakage current, or to increase the device response speed, etc.), other semiconductor material layers may be arranged between the epitaxial layer 313 and the barrier layer 314. For example, after chemical mechanical polishing (CMP) of the epitaxial layer 313, before forming the barrier layer 314 on the epitaxial layer 313, it is necessary to first form a buffer layer 317 on the epitaxial layer 313, and then form a doping layer 318 on the buffer layer 317, and then form a buffer layer 319 on the doping layer 318, and finally form a barrier layer 314 on the buffer layer 319. It should be noted that the masks mentioned in the specific implementation of the embodiments of the present application are all positive masks, that is, the mask can be activated after illumination, and then the activated mask is removed. Of course, in actual operations, negative masks can also be used. It should be noted that the negative mask will not be activated after illumination, but will be activated without illumination. Therefore, when using a negative mask, the light-transmitting area and the light-opaque area of ​​the shading plate in the figure need to be swapped, that is, the original light-transmitting area becomes the light-opaque area, and the original light-opaque area becomes the light-transmitting area, and other steps are not changed. Whether using a positive mask or a negative mask, it belongs to the protection scope of the present invention. Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, a nucleation layer and an epitaxial layer are stacked; The substrate comprises a first region and a second region; The nucleation layer on the first region has a different crystal orientation from the nucleation layer on the second region; A polarization direction of the epitaxial layer on the first region is different from a polarization direction of the epitaxial layer on the second region.

2. The semiconductor structure according to claim 1, characterized in that: In a stacking direction, a thickness of the nucleation layer on the first region is different from a thickness of the nucleation layer on the second region.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The substrate further includes a third region, wherein the first region and the third region are respectively arranged on both sides of the second region; The crystal orientation of the nucleation layer on the third region is the same as that of the nucleation layer on the first region; A polarization direction of the epitaxial layer on the third region is the same as a polarization direction of the epitaxial layer on the first region.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure also includes an electrode disposed on the epitaxial layer.

5. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further includes a barrier layer disposed between the epitaxial layer and the electrode.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The material of the epitaxial layer includes one or more of the following: aluminum nitride, gallium nitride, indium nitride, and boron nitride.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The material of the substrate includes any one of the following: sapphire, silicon, silicon carbide, and gallium oxide.

8. An integrated circuit, characterized in that: The integrated circuit comprises a packaging structure and one or more semiconductor structures according to any one of claims 1 to 7, wherein the semiconductor structure is packaged inside the packaging structure.

9. An electronic device, characterized in that: A method comprising: providing a printed circuit board and the integrated circuit of claim 8, the integrated circuit being coupled to the printed circuit board.

10. A method for preparing a semiconductor structure, characterized in that: include: Fabricating a nucleation layer on the substrate, wherein the substrate comprises a first region and a second region, and the nucleation layer on the first region has a different crystal orientation from the nucleation layer on the second region; An epitaxial layer material is grown on the nucleation layer by an epitaxial process to form an epitaxial layer, wherein a polarization direction of the epitaxial layer on the first region is different from a polarization direction of the epitaxial layer on the second region.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The step of forming a nucleation layer on the substrate comprises: Depositing a nucleation layer material on the substrate by a deposition process to form a first deposition structure, wherein the first deposition structure covers the first region and does not cover the second region; The nucleation layer material is grown on the second region and the first deposition structure through one or more epitaxial processes to form the nucleation layer.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: The substrate further includes a third region, wherein the first region and the third region are respectively arranged on both sides of the second region; The crystal orientation of the nucleation layer on the third region is the same as that of the nucleation layer on the first region; the polarization direction of the epitaxial layer on the third region is the same as that of the epitaxial layer on the first region; The first deposition structure also covers the third region.

13. The method for preparing a semiconductor structure according to claim 11 or 12, characterized in that: The step of depositing a nucleation layer material on the substrate by a deposition process to form a first deposition structure comprises: making a mask covering the substrate; Performing photolithography on the mask to form a first deposition structure window, wherein the first deposition structure window is located on the first region; Depositing the nucleation layer material at the opening of the first deposition structure by a deposition process to form the first deposition structure; The mask is removed to expose the second region.

14. The method for preparing a semiconductor structure according to claim 11 or 12, characterized in that: The step of depositing a nucleation layer material on the substrate by a deposition process to form a first deposition structure comprises: Depositing the nucleation layer material on the substrate by a deposition process to form a second deposition structure, wherein the second deposition structure covers the substrate; making a mask covering the second deposition structure; Performing photolithography on the mask to form an etched window, wherein the etched window is located on the second region; Etching the second deposition structure according to the etching window to form the first deposition structure; The mask is removed to expose the first deposition structure.

15. The method for preparing a semiconductor structure according to any one of claims 10 to 14, characterized in that: After the epitaxial layer material is grown on the nucleation layer by an epitaxial process to form the epitaxial layer, the method further comprises: Electrodes are fabricated on the epitaxial layer.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that: Before forming the electrode on the epitaxial layer, the method further comprises: A barrier layer is formed on the epitaxial layer.

17. The method for preparing a semiconductor structure according to any one of claims 10 to 16, characterized in that: The material of the epitaxial layer includes one or more of the following: aluminum nitride, gallium nitride, indium nitride, and boron nitride.

18. The method for preparing a semiconductor structure according to any one of claims 10 to 17, characterized in that: The material of the substrate includes any one of the following: sapphire, silicon, silicon carbide, and gallium oxide.

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