Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device (10) is provided with: a silicon carbide semiconductor substrate (11) that has a first conductivity type; a first semiconductor layer (12) that has the first conductivity type; a second semiconductor layer (13) that has a second conductivity type; a first semiconductor region (14) that has the first conductivity type; a second semiconductor region (15) that has the second conductivity type; a trench (16); a gate insulating film (17); a gate electrode (18); a high-concentration region (21) that has the second conductivity type and is positioned so as to face the trench (16) in the depth direction; and a connection region (23) that has the second conductivity type and is selectively provided so as to be in contact with the high-concentration region (21) and the second semiconductor layer (13) at a position that is closer to the second semiconductor layer (13) than the high-concentration region (21) and is closer to the silicon carbide semiconductor substrate (11) than the second semiconductor layer (13). The second semiconductor region (15) is periodically disposed in the longitudinal direction of the trench (16), and the connection region (23) is periodically disposed in the longitudinal direction of the trench (16) in a region where the connection region (23) does not overlap the second semiconductor region (15) in a plan view.

Description

Silicon carbide semiconductor device

[0001] This disclosure relates to silicon carbide semiconductor devices.

[0002] Conventionally, a semiconductor device has been known which includes a carrier transport layer of a first conductivity type, an injection control region of a second conductivity type provided on the upper surface of the carrier transport layer, an upper buried region of the second conductivity type in contact with the lower surface of the injection control region, and a lower buried region of the second conductivity type in contact with the lower surface of the upper buried region and the bottom surface of the trench, and in which the lower buried regions are separated from each other between the trenches via the carrier transport layer (see, for example, Patent Document 1 below).

[0003] International Publication No. 2022 / 137789

[0004] However, in conventional semiconductor device structures, the large number of structures per cell makes it difficult to shorten the cell pitch. This makes it particularly difficult to reduce resistance in SiC, which has low channel mobility. Furthermore, shortening the cell pitch in a complex structure narrows the p-type region of the pn junction, which increases the likelihood of electric field concentration and reduces breakdown voltage.

[0005] The object of this disclosure is to provide a silicon carbide semiconductor device that can achieve high breakdown voltage and low resistance by shortening the cell pitch in order to solve the problems of the prior art described above.

[0006] In order to solve the above-described problems and achieve the object of the present disclosure, a silicon carbide semiconductor device according to this disclosure has the following features: a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type; a second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a first semiconductor region of the first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate; a second semiconductor region of the second conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate, in contact with the first semiconductor region and the second semiconductor layer; a trench is provided penetrating the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer; a gate electrode is provided within the trench via a gate insulating film; and a high-concentration region of the second conductivity type is provided within the first semiconductor layer at a position facing the trench in a depth direction. A second conductivity type connection region is selectively provided within the first semiconductor layer, on the second semiconductor layer side of the high concentration region and on the silicon carbide semiconductor substrate side of the second semiconductor layer, in contact with the high concentration region and the second semiconductor layer. First electrodes are provided on surfaces of the first semiconductor region and the second semiconductor region. A second electrode is provided on a back surface of the silicon carbide semiconductor substrate. The second semiconductor regions are periodically arranged in the longitudinal direction of the trench, and the connection region is periodically arranged in a region that does not overlap with the second semiconductor region in a plan view.

[0007] According to the above disclosure, the p + The p-type region (high concentration region) is shallower than the p-type region and deeper than the p-type base region (second semiconductor layer). + A type connection region (connection region) is provided. + Type domain and p ++ The area of ​​connection with the contact region can be increased, the fluctuation of the feedback capacitance can be suppressed, and the SW loss can be reduced. +The region of the p-type base region exposed to the drain electrode is reduced by the type connection region, making it difficult for a high voltage to be applied to the p-type base region, and making it possible to increase the breakdown voltage.

[0008] According to the silicon carbide semiconductor device according to the present disclosure, the cell pitch can be shortened, and high breakdown voltage and low resistance can be achieved.

[0009] FIG. 1 is a perspective view showing a structure of a silicon carbide semiconductor device according to a first embodiment. FIG. 2A is a cross-sectional view taken along line A-A' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2C is a cross-sectional view taken along line C-C' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3A is a plan view of a surface D of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3B is a plan view of a depth E of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3C is a plan view of a depth F of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a perspective view (part 1) showing a portion of a silicon carbide semiconductor device according to a comparative example. FIG. 5 is a perspective view (part 2) showing a portion of a silicon carbide semiconductor device according to the comparative example. FIG. 6 is a perspective view (part 1) showing a portion of a silicon carbide semiconductor device according to the first embodiment. FIG. 7 is a perspective view (part 2) showing a portion of the silicon carbide semiconductor device according to the first embodiment. FIG. 8 is a perspective view showing current density of a silicon carbide semiconductor device according to a comparative example. FIG. 9 is a perspective view showing current density of a silicon carbide semiconductor device according to the first embodiment. FIG. 10 is a perspective view (part 1) showing a depletion region of a silicon carbide semiconductor device according to a comparative example. FIG. 11 is a perspective view (part 2) showing a depletion region of a silicon carbide semiconductor device according to a comparative example. FIG. 12 is a perspective view (part 1) showing a depletion region of a silicon carbide semiconductor device according to the first embodiment. FIG. 13 is a perspective view (part 2) showing a depletion region of a silicon carbide semiconductor device according to the first embodiment. FIG. 14 is a graph showing feedback capacitance versus drain voltage for a silicon carbide semiconductor device according to the first embodiment and a silicon carbide semiconductor device according to a comparative example. FIG. 15 is a perspective view showing a structure of a silicon carbide semiconductor device according to a second embodiment. FIG. 16 is a cross-sectional view taken along the line CC' of FIG. 15 showing the structure of the silicon carbide semiconductor device according to the second embodiment. FIG. 17 is a plan view of the surface D of FIG. 16 showing the structure of the silicon carbide semiconductor device according to the second embodiment. Fig. 18 is a perspective view showing the structure of a silicon carbide semiconductor device according to embodiment 3. Fig. 19 is a cross-sectional view taken along line AA' of Fig. 18 showing the structure of the silicon carbide semiconductor device according to embodiment 3.FIG. 20 is a depth E plan view of FIG. 19 showing the structure of the silicon carbide semiconductor device according to the third embodiment. FIG. 21A is an A-A' cross-sectional view of FIG. 22A showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. FIG. 21B is a CC' cross-sectional view of FIG. 22A showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. FIG. 22A is a surface D plan view of FIGS. 21A and 21B showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. FIG. 22B is a depth E plan view of FIGS. 21A and 21B showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. FIG. 23A is an A-A' cross-sectional view of FIG. 24A showing the structure of the silicon carbide semiconductor device according to the fifth embodiment. FIG. 23B is a CC' cross-sectional view of FIG. 24A showing the structure of the silicon carbide semiconductor device according to the fifth embodiment. FIG. 24A is a surface D plan view of FIGS. 23A and 23B showing the structure of the silicon carbide semiconductor device according to the fifth embodiment. Fig. 24B is a plan view at depth E of Figs. 23A and 23B showing the structure of the silicon carbide semiconductor device according to embodiment 5. Fig. 25 is a cross-sectional view taken along line A-A' in Fig. 27 showing the structure of a silicon carbide semiconductor device of a comparative example. Fig. 26 is a cross-sectional view taken along line B-B' in Fig. 27 showing the structure of a silicon carbide semiconductor device of a comparative example. Fig. 27 is a perspective view showing the structure of a silicon carbide semiconductor device of a comparative example.

[0010] Overview of Embodiments of the Present Disclosure In order to solve the above-described problems and achieve the object of the present disclosure, a silicon carbide semiconductor device according to the present disclosure has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of the first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A second semiconductor region of the second conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate, in contact with the first semiconductor region and the second semiconductor layer. A trench is provided penetrating the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. A high-concentration region of a second conductivity type is provided within the first semiconductor layer at a position facing the trench in the depth direction. A connection region of a second conductivity type is selectively provided within the first semiconductor layer, on the second semiconductor layer side of the high-concentration region and on the silicon carbide semiconductor substrate side of the second semiconductor layer, in contact with the high-concentration region and the second semiconductor layer. First electrodes are provided on surfaces of the first semiconductor region and the second semiconductor region. A second electrode is provided on a back surface of the silicon carbide semiconductor substrate. The second semiconductor regions are periodically arranged in the longitudinal direction of the trench, and the connection region is periodically arranged in a region that does not overlap with the second semiconductor region in a plan view.

[0011] According to the above disclosure, the p + The p-type region (high concentration region) is shallower than the p-type region and deeper than the p-type base region (second semiconductor layer). + A type connection region (connection region) is provided. + Type domain and p ++ The area of ​​connection with the contact region can be increased, the fluctuation of the feedback capacitance can be suppressed, and the SW loss can be reduced. +The region of the p-type base region exposed to the drain electrode is reduced by the type connection region, making it difficult for a high voltage to be applied to the p-type base region, and making it possible to increase the breakdown voltage.

[0012] Furthermore, the silicon carbide semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the width of the connection region in a direction perpendicular to the longitudinal direction of the trench is wider than the width of the second semiconductor region in a direction perpendicular to the longitudinal direction of the trench.

[0013] According to the above disclosure, the contact area between the connection region and the high concentration region below the trench increases, thereby improving the breakdown voltage.

[0014] Moreover, in the silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the connection regions are provided in a dot shape between the trenches in a plan view so as not to contact the trenches.

[0015] According to the disclosure above, the channel region is wider than when provided in a stripe shape, and the resistance can be reduced.

[0016] Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the connection regions are provided in a stripe pattern that is in contact with the trenches and is perpendicular to the longitudinal direction of the trenches in a planar view, and are located between the trenches.

[0017] According to the above disclosure, the contact area between the connection region and the high concentration region below the trench increases, thereby improving the breakdown voltage.

[0018] Moreover, in the silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the second semiconductor regions are provided in a dot shape between the trenches in a plan view so as not to contact the trenches.

[0019] According to the disclosure above, by forming the second semiconductor region in a dotted shape, it is possible to improve the characteristics of the silicon carbide semiconductor device.

[0020] Furthermore, in the silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the second semiconductor regions are provided in a stripe pattern that is in contact with the trenches between the trenches in a planar view and perpendicular to the longitudinal direction of the trenches.

[0021] According to the disclosure above, misalignment of the second semiconductor regions does not occur, and manufacturing costs can be reduced compared to when the second semiconductor regions are provided in a dot pattern.

[0022] In addition, in the silicon carbide semiconductor device disclosed above, the connection region has an impurity concentration higher than the impurity concentration of the second semiconductor layer and lower than the impurity concentration of the high concentration region.

[0023] Further, in the silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the impurity concentrations of the second semiconductor layer, the connection region and the high concentration region are 1×10 17 / cm 3 The present invention is characterized in that:

[0024] <Findings underlying the present disclosure> First, the problems with the semiconductor device of the comparative example will be described. Silicon carbide (SiC) is expected to be a next-generation semiconductor material to replace silicon (Si). A semiconductor element using silicon carbide as a semiconductor material (hereinafter referred to as a silicon carbide semiconductor device) has various advantages compared to conventional semiconductor elements using silicon as a semiconductor material, such as the ability to reduce the resistance of the element in the on-state to one-hundredth of that of conventional semiconductor elements using silicon as a semiconductor material, and the ability to be used in higher temperature environments (200°C or higher). This is due to the characteristics of the material itself, namely, the band gap of silicon is about three times larger than that of silicon, and the dielectric breakdown field strength is nearly one order of magnitude greater than that of silicon.

[0025] To date, commercially available silicon carbide semiconductor devices include Schottky barrier diodes (SBDs) and vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) having a planar gate structure or a trench gate structure.

[0026] The planar gate structure is a MOS gate structure in which a flat MOS gate is provided on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. This allows for a higher density of unit cells (element constituent units) per unit area and a higher current density per unit area compared to a planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, which is advantageous in terms of cost.

[0027] FIG. 25 is a cross-sectional view taken along line AA' in FIG. 27 showing the structure of a silicon carbide semiconductor device of a comparative example. FIG. 26 is a cross-sectional view taken along line BB' in FIG. 27 showing the structure of a silicon carbide semiconductor device of a comparative example. FIG. 27 is a perspective view showing the structure of a silicon carbide semiconductor device of a comparative example. Semiconductor device 110 of the comparative example shown in FIGS. 25 to 27 is a vertical MOSFET having a trench gate structure on a semiconductor substrate (semiconductor chip) 140 made of silicon carbide. In FIGS. 25 to 27, only the active region is shown, and the edge termination region is omitted.

[0028] The semiconductor substrate 140 is made of silicon carbide. + On the front surface of the starting substrate 141, - n-type drift region 112 - The semiconductor substrate 140 is formed by epitaxially growing an n-type silicon carbide layer 142. - The main surface on the side of the silicon carbide layer 142 is the front surface, and + The main surface on the mold starting substrate 141 side is referred to as the back surface. + A drain electrode 145 is provided over the entire area of ​​the back surface of the starting substrate 141. + The starting substrate 141 is n + The gate electrode 111 is a gate-type drain region.

[0029] n - n type drift region 112 +An n-type current diffusion region 120 is provided on the surface opposite to the silicon carbide substrate 111. In addition, a p-type current diffusion region 120 is provided in the n-type current diffusion region 120 at a position facing the bottom of the trench 116 in the depth direction. + The MOS gate of the trench gate structure has a p-type base region 113, an n-type base region 121, and a n-type base region 122. + type source region 114, p ++ The semiconductor device is composed of a contact region 115, a trench 116, a gate insulating film 117, and a gate electrode 118. ++ The p-type contact region 115 + A mold area 122 is optionally provided.

[0030] An interlayer insulating film 119 is provided on the gate electrode 118, and an n-type insulating film is formed in an opening of the interlayer insulating film 119. + type source region 114 and p ++ An ohmic electrode 143 is provided in contact with the type contact region 115. A barrier metal 138 that prevents diffusion of metal atoms toward the gate electrode 118 is provided on the ohmic electrode 143 and the interlayer insulating film 119. A source electrode 144 is provided on the barrier metal 138.

[0031] p + The n-type regions 121 and 122 are fixed to the potential of the source electrode 144, and have the function of depleting (or depleting the n-type current diffusion region 120, or both) when the MOSFET (silicon carbide semiconductor device 110) is turned off, thereby mitigating the electric field applied to the gate insulating film 117. + The p-type region 121 is provided apart from the p-type base region 113 and faces the bottom surface of the trench 116 in the depth direction. + The mold region 121 is p + The p-type region 122 is partially connected to the source electrode 144. + 26 shows a cross section of a portion where the mold region 122 is not provided. + A mold region 122 is provided, and p + The mold region 122 and p + 1 shows a cross section of the portion where the mold region 121 is connected.

[0032] In this way, p+ The p between the trenches 116 provided at the same depth as the mold region 121 + The type region is eliminated, and the JFET structure per cell (the structure of the portion where the current flows between the trenches 116) is unified. + Type region 121 and p ++ The connection to the contact region 115 is made by a deep p-type contact in the center between the trenches 116. + This is achieved by creating a mold area 122 .

[0033] This simplifies the structure per cell, thereby shortening the cell pitch, and shortening the cell pitch makes it possible to reduce the resistance of a SiC MOSFET with low channel mobility. + The width of the mold region 121 can be increased, and the flat portion of the pn junction becomes wider, thereby alleviating electric field concentration and increasing the breakdown voltage.

[0034] However, in this structure, the p + Type region 121 and p ++ p under the contact region 115 + The connection portion of the p-type region 122 becomes thinner. Therefore, when a high voltage is applied to the drain electrode 145 and the depletion region expands, + Type region 121 and p + The neutral region of the type region 122 separates, and p + The p-type region 121 is electrically floating, causing a sudden change in feedback capacitance, which in turn increases switching loss. + The electrically floating of the p-type region 121 causes problems such as application of a high voltage to the gate insulating film 117. In addition, since the area of ​​the p-type base region 113, which is the channel region, exposed to the drain electrode 145 is large, a high voltage is applied to the channel, causing a problem of a decrease in breakdown voltage.

[0035] Preferred embodiments of the silicon carbide semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. It is preferable that the terms "same" or "equivalent" be used to include variations within 5% in consideration of variations in manufacturing.

[0036] First Embodiment A structure of a silicon carbide semiconductor device according to a first embodiment will be described. FIG. 1 is a perspective view showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2A is a cross-sectional view taken along line A-A' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2C is a cross-sectional view taken along line C-C' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3A is a plan view at a depth D of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3B is a plan view at a depth E of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3C is a plan view at a depth F of FIGS. 2A to 2C showing the structure of the silicon carbide semiconductor device according to the first embodiment. A silicon carbide semiconductor device 10 according to the first embodiment shown in FIGS. 1 to 3C is a vertical MOSFET having a trench gate structure in a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC).

[0037] 1 to 3C show only the active region through which current flows in the on-state, and omit the edge termination region, which is surrounded by a substantially rectangular shape around the active region and has a breakdown voltage structure. The breakdown voltage structure functions to maintain a breakdown voltage by mitigating the electric field near the boundary between the active region and the edge termination region. The breakdown voltage is the maximum voltage at which the semiconductor device does not malfunction or break down.

[0038] A plurality of unit cells (functional units of an element) of the same structure (element structure) of the MOSFET are arranged adjacent to each other in parallel on the semiconductor substrate 40. The semiconductor substrate 40 is made of n-type silicon carbide. + On the front surface of a starting substrate (a silicon carbide semiconductor substrate of a first conductivity type) 41, - n-type drift region (first semiconductor layer of the first conductivity type) 12 - The semiconductor substrate 40 is formed by epitaxially growing an n-type silicon carbide layer 42. - The main surface on the silicon carbide layer 42 side is the front surface (first main surface), and + The main surface on the mold starting substrate 41 side is referred to as the back surface (second main surface).

[0039] n + The starting substrate 41 is n + The semiconductor substrate 40 is formed with n-type drain regions 11 to form the active regions. + On the starting substrate 41, - n-type drift region 12 - The n-type silicon carbide layer 42 is epitaxially grown in multiple stages. - The n-type drift region 12 - This is a portion of the silicon carbide layer 42 where no diffusion region is formed by ion implantation and the impurity concentration remains the same as during epitaxial growth. - The n-type drift region 12 + The substrate 41 is in contact with the active region and extends from the edge of the chip. - The silicon carbide layer 42 is formed by one-stage epitaxial growth, and the p-type base region 13 and the n-type + type source region 14, p ++ type contact region 15, n-type current diffusion region 20, p + Type region 21 and p + The mold connection region 23 may be formed by ion implantation.

[0040] The active region of the first embodiment is provided with a trench gate structure. The trench gate structure includes a p-type base region (second semiconductor layer of the second conductivity type) 13, an n + p-type source region (first semiconductor region of the first conductivity type) 14, ++The p-type base region 13, the n-type contact region 15, the n-type semiconductor region 16, the n-type gate insulating film 17, and the n-type gate electrode 18 are formed. + type source region 14 and p ++ The contact region 15 is an n - The p-type base region 13 is a diffusion region formed by ion implantation inside the n-type silicon carbide layer 42. - It is provided over the entire area between the mold drift region 12 and the substrate.

[0041] n + type source region 14 and p ++ The n-type contact regions 15 are selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 13, and are in contact with the p-type base region 13 at their bottoms (lower surfaces: rear surface side edges of the semiconductor substrate 40). + The source region 14 is p ++ The n-type contact region 15 is provided in contact with the n-type contact region 15. + type source region 14 and p ++ The mold contact region 15 is in ohmic contact with the ohmic electrode 43 on the upper surface (the end portion on the front surface side of the semiconductor substrate 40 ).

[0042] n - Between the n-type drift region 12 and the p-type base region 13, + The n-type current diffusion region 20 and the p-type current diffusion region 21 are formed at a deep position on the side of the n-type drain region 11 (the back surface side of the semiconductor substrate 40). + A p-type region (high concentration region of the second conductivity type) 21 is selectively provided on the p-type base region 13 side of the bottom surface of the trench 16. + The n-type current diffusion region 20, the p-type connection region (second conductivity type connection region) 23 are selectively provided. + Type region 21 and p + The n-type connection region 23 - The n-type current diffusion region 20 is a diffusion region formed by ion implantation inside the p-type silicon carbide layer 42. + n than the mold region 21 + It is preferable that the ion implantation reaches a deep position on the side of the mold drain region 11 .

[0043] The n-type current diffusion region 20 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. + Type region 21 and p + The n-type current diffusion region 20 contacts the p-type base region 13 at the top and the n-type current diffusion region 21 at the bottom. - It contacts the mold drift region 12 .

[0044] The n-type current diffusion region 20 may not be provided. When the n-type current diffusion region 20 is not provided, the n-type current diffusion region 20 may be replaced by - The p-type drift region 12 reaches the p-type base region 13, + Type region 21 and p + The n - The mold drift region 12 contacts the gate insulating film 17 on a part of the sidewall of the trench 16 .

[0045] p + Type region 21 and p + The n-type connection region 23 is fixed to the potential of the source electrode 44 described later, and has the function of depleting (or depleting the n-type current diffusion region 20, or both) when the MOSFET (silicon carbide semiconductor device 10) is turned off, thereby mitigating the electric field applied to the gate insulating film 17. + The p-type region 21 is provided apart from the p-type base region 13 and faces the bottom surface of the trench 16 in the depth direction. + The type region 21 is p + The p-type connection region 23 is partially connected to the source electrode 44. + A type connection region 23 is provided, and p + Type region 21 and p + 2B and 2C show cross sections of the portion where the p + 1 shows a cross section of a portion where the mold connection region 23 is not provided.

[0046] p +The mold region 21 may be in contact with the gate insulating film 17 at the bottom of the trench 16, or may be spaced apart from the bottom of the trench 16. + The width of the mold region 21 is the same as or wider than the width of the trench 16. For example, p + The width of the mold region 21 is preferably at least twice as wide as the width of the trench 16. + By making the width of the mold region 21 wider than the width of the trench 16, p + The mold region 21 also faces the bottom corner portion (boundary between the sidewall and the bottom) of the trench 16 in the depth direction. + The effect of the type region 21 in alleviating the electric field near the bottom of the trench 16 is further enhanced. + The mold regions 21 are arranged in a stripe pattern in the longitudinal direction of the trench 16 in a plan view.

[0047] p + As shown in FIG. 2A, the type connection region 23 is + The p-type region 21 and the p-type base region 13 are connected to each other. + shallower than the p-type base region 21 (on the p-type base region 13 side), and deeper than the p-type base region 13 (on the n-type base region 13 side). + As shown in FIG. 3B, + The mold connection regions 23 are arranged in a stripe pattern between the trenches 16 in a direction perpendicular to the longitudinal direction of the trenches 16 (the lateral direction of the trenches 16) in a plan view, and are in contact with the trenches 16. By arranging the mold connection regions 23 in a stripe pattern between the trenches 16, + The p-type connection region 23 and the p-type connection region 24 under the trench 16 + The area of ​​contact with the mold region 21 increases, and the breakdown voltage can be improved. ++ The mold contact regions 15 are periodically arranged in a dot pattern between the trenches 16 in the longitudinal direction of the trenches 16 in a plan view, and are not in contact with the trenches 16. ++ By forming contact region 15 in a dot shape, the characteristics of silicon carbide semiconductor device 10 can be improved.

[0048] Also, p + The impurity concentration of the p-type connection region 23 is higher than the impurity concentration of the p-type base region 13. +It is preferable that the impurity concentration is lower than that of the impurity concentration of the type region 21. ++ The impurity concentration of the p-type contact region 15 is + The type connection region 23 and p + The impurity concentration of the p-type base region 13 is higher than that of the p-type region 21. + The type connection region 23 and p + The impurity concentration of the mold region 21 is 1×10 17 / cm 3 It is preferable that this is equal to or greater than this.

[0049] Also, as shown in FIGS. 3A and 3B, p + The connecting region 23 is p ++ The contact region 15 is disposed in a region that does not overlap with the contact region 15. + A type connection region 23 is provided, and p ++ The region where the contact region 15 is not provided, as shown in FIG. + The type connection region 23 and p ++ The region where the contact region 15 is not provided, as shown in FIG. ++ A p-type contact region 15 is provided. + Regions where no mold connection region 23 is provided are periodically arranged in the longitudinal direction of the trench 16 .

[0050] Also, in plan view, + The width of the mold connection region 23 in the direction perpendicular to the longitudinal direction of the trench 16 is p ++ It is preferable that the width of the contact region 15 is wider than the width of the trench 16 in the direction perpendicular to the longitudinal direction. + The p-type connection region 23 and the p-type connection region 24 under the trench 16 + The area of ​​contact with the mold region 21 increases, and the pressure resistance can be improved.

[0051] In this way, the p + The p-type region 21 is shallower than the p-type base region 13. + By providing the mold connection region 23, + Type region 21 and p ++The area of ​​connection with the contact region 15 can be increased. This makes it possible to suppress the fluctuation of the feedback capacitance and reduce the SW loss. + The region of the p-type base region 13 exposed to the drain electrode 45 is reduced by the type connection region 23, making it difficult for a high voltage to be applied to the p-type base region 13, and making it possible to increase the breakdown voltage.

[0052] Here, Figures 4 and 5 are perspective views showing a portion of a silicon carbide semiconductor device of a comparative example. Figure 4 is a perspective view of a region S101 surrounded by a dotted line in Figure 27, and Figure 5 is a perspective view seen in the opposite direction with the side wall of the trench in Figure 4 as the center. Figures 6 and 7 are perspective views showing a portion of a silicon carbide semiconductor device according to the first embodiment. Figure 6 is a perspective view of a region S1 surrounded by a dotted line in Figure 1, and Figure 7 is a perspective view seen in the opposite direction with the side wall of the trench in Figure 6 as the center.

[0053] 4, in the comparative example, the width L101 of the JFET region below the p-type base region 113, which is the channel region, is large. On the other hand, as shown in FIG. 6, in the first embodiment, the width L1 of the JFET region below the p-type base region 13, which is the channel region, is small.

[0054] FIG. 8 is a perspective view showing the current density of a silicon carbide semiconductor device of a comparative example. FIG. 9 is a perspective view showing the current density of a silicon carbide semiconductor device according to the first embodiment. FIG. 8 shows the results of a simulation in which the drain voltage was set to about 1000 V, and FIG. 9 shows the results of a simulation in which the drain voltage was set to about 1500 V, with a thicker hash indicating a higher current density. As shown in FIG. 8, if the width L101 of the JFET region below the p-type base region 113, which is the channel region, is wide, punch-through is more likely to occur in the thin p-type base region 113 directly above, resulting in a decrease in breakdown voltage. On the other hand, in the first embodiment, the p + The p-type region 21 is shallower than the p-type base region 13. + The connecting region 23 is p ++In the first embodiment, the width L1 of the JFET region below the p-type base region 13, which is the channel region, is narrowed, and the breakdown voltage increases until avalanche occurs at the pn junction. In this way, in the first embodiment, the width of the JFET region below the channel region can be narrowed, and the breakdown voltage can be increased compared to the comparative example.

[0055] In addition, as shown in FIG. 5, in the comparative example, p + The mold region 122 and p ++ On the other hand, as shown in FIG. 6, in the first embodiment, the region S102 where the p + The type connection region 23 and p ++ In this manner, in the first embodiment, the region S2 where the p-type contact region 15 is connected to the p-type contact region 15 is wide. + The region S2 connected to the mold region 21 becomes wider, and when a high voltage is applied to the drain side, the fluctuation in feedback capacitance is small, and the switching speed becomes faster.

[0056] 10 and 11 are perspective views showing the depletion region of a silicon carbide semiconductor device of a comparative example. FIGS. 12 and 13 are perspective views showing the depletion region of a silicon carbide semiconductor device according to the first embodiment. FIGS. 10 to 13 show simulation results when the drain voltage is set to about 1000 V, and the area surrounded by the dotted line LW is the depletion region. As shown in FIGS. 10 and 11, in the comparative example, when a high voltage is applied to the drain electrode, the depletion region spreads into the p-type region, and the p-type region under trench 116 + Type region 121 and p ++ 12 and 13, in the first embodiment, even if a high voltage is applied to the drain electrode, the neutral region is divided (L102 in FIG. 11) between the two contact regions 122, and a sudden change in the feedback capacitance occurs. ++ The p-type contact region 15 under the trench 16 + The neutral region is not divided and the fluctuation of the feedback capacitance is small.

[0057] 14 is a graph showing feedback capacitance versus drain voltage for the silicon carbide semiconductor device according to the first embodiment and the silicon carbide semiconductor device of the comparative example. In Fig. 14, the horizontal axis represents drain voltage Vds in V, and the vertical axis represents feedback capacitance Crss in F / cm 2 14 shows the results of calculation of the feedback capacitance when a high voltage is applied to the drain electrode in a simulation. As shown in FIG. 14 , in the silicon carbide semiconductor device of the comparative example, the feedback capacitance fluctuates suddenly and significantly when the drain voltage exceeds 200 V, whereas in the silicon carbide semiconductor device according to the first embodiment, the feedback capacitance remains almost constant even when the drain voltage exceeds 200 V and reaches 1000 V, and it can be seen that fluctuations are suppressed.

[0058] Returning to the description of the structure of silicon carbide semiconductor device 10, trench 16 has an n-type + The n-type current diffusion region 20 (or the n-type current diffusion region 20 if the n-type current diffusion region 20 is not provided) penetrates the p-type source region 14 and the p-type base region 13. - The trench 16 extends to the p-type drift region 12. + The trench 16 may terminate within the mold region 21. The trench 16 extends, for example, in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 40 and reaches the outer periphery (not shown) of the active region. A gate electrode 18 is provided within the trench 16 with a gate insulating film 17 interposed therebetween.

[0059] The interlayer insulating film 19 is provided on the front surface of the semiconductor substrate 40, and in particular covers the gate electrode 18. The ohmic electrode (first electrode) 43 is provided on a portion of the front surface of the semiconductor substrate 40 that is exposed through the contact hole of the interlayer insulating film 19. The ohmic electrode 43 is connected to the n-type ohmic electrode 43 on the front surface of the semiconductor substrate 40 through the contact hole of the interlayer insulating film 19. + type source region 14 and p ++ The ohmic electrode 43 is in ohmic contact with the contact region 15. The ohmic electrode 43 is, for example, a nickel silicide (NixSiy, where x and y are any integers) film.

[0060] The source electrode (first electrode) 44 is provided over the interlayer insulating film 19 so as to fill the contact hole in the interlayer insulating film 19. The source electrode 44 is provided over substantially the entire area of ​​the center of the active region. The source electrode 44 is connected to the n-type ohmic electrode 43 via the ohmic electrode 43. + type source region 14, p ++ p-type contact region 15, p-type base region 13, p + Type region 21 and p + It is electrically connected to the mold connection region 23 .

[0061] A barrier metal 38 that prevents diffusion of metal atoms toward the gate electrode 18 may be provided on the ohmic electrode 43 and the interlayer insulating film 19. The barrier metal 38 is made of, for example, titanium (Ti) or titanium nitride (TiN). The barrier metal 38 may have a two-layer structure of Ti and TiN, with the Ti layer facing the semiconductor substrate 40. In this case, a source electrode 44 is provided on the barrier metal 38.

[0062] The drain electrode (second electrode) 45 is formed on the back surface (n + The back surface of the starting substrate 41 is provided with n + type drain region 11 (n + ohmic contact with the starting substrate 41), + The gate electrode 12 is electrically connected to the drain region 11 .

[0063] (Method for manufacturing a silicon carbide semiconductor device according to the first embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to the first embodiment will be described. The silicon carbide semiconductor device according to the first embodiment is manufactured in the same manner as the method for manufacturing a silicon carbide semiconductor device of the comparative example. For example, it is manufactured as follows. First, n + Starting substrate (n + On the front surface of the mold starting wafer 41, n - The first n-th region that becomes the type drift region 12 - Next, a first n-type silicon carbide layer is epitaxially grown by ion implantation of n-type impurities. - The lower portion of the n-type current diffusion region 20 is formed in the silicon carbide layer. Next, a first n-type current diffusion region 20 is formed by photolithography and ion implantation of p-type impurities. -The surface region of the silicon carbide layer is + A mold region 21 is selectively formed.

[0064] Next, a second n-type current diffusion region 20 is formed on the lower portion of the n-type current diffusion region 20. - Next, a second n-type silicon carbide layer is epitaxially grown by ion implantation of n-type impurities. - The upper portion of the n-type current diffusion region 20 is formed in the silicon carbide layer. - a third n-type silicon carbide layer on the silicon carbide layer; - The n-type silicon carbide layer is then epitaxially grown. + On the starting substrate 41 - In this manufacturing method, a semiconductor substrate (semiconductor wafer) 40 having a predetermined thickness is completed by laminating the first silicon carbide layer 42. - a second n-type silicon carbide layer on a surface region of the silicon carbide layer; - type silicon carbide layer and the 3n - Each region was formed by epitaxial growth and ion implantation of multiple silicon carbide layers. - Each region may be formed in the surface region of the silicon carbide layer by photolithography and ion implantation.

[0065] Next, a third n-type impurity is formed by photolithography and ion implantation of p-type impurities. - The p-type base region 13 is formed inside the silicon carbide layer. Next, a third n-type base region 13 is formed by photolithography and ion implantation of n-type impurities. - The surface region of the silicon carbide layer is + A type source region 14 is selectively formed.

[0066] Next, by photolithography and ion implantation of p-type impurities, a second n - The silicon carbide layer has a p-type silicon carbide layer on the bottom surface. + The upper surface of the p-type semiconductor layer 11 is in contact with the p-type base region 13. + Next, a third n-type connection region 23 is formed by photolithography and ion implantation of p-type impurities. - The surface region of the silicon carbide layer is ++ A mold contact region 15 is selectively formed.

[0067] n -The portion of the silicon carbide layer 42 that is not ion-implanted and remains at the same impurity concentration as during epitaxial growth is n - This forms the n-type drift region 12. - A heat treatment is performed to activate the impurities ion-implanted into the silicon carbide layer 42. The heat treatment for activating the impurities is performed in the first to third n-th steps. - This may be done each time impurity ions are implanted into the silicon carbide layer, or may be done all at once. Next, trenches 16, gate insulating films 17, and gate electrodes 18 are formed by a general method.

[0068] Next, an interlayer insulating film 19 is formed on the front surface of the semiconductor substrate 40. Next, a source electrode 44, a gate pad (not shown), a passivation film (surface protection film: not shown), and a drain electrode 45 are formed by a typical method. The portion of the source electrode 44 exposed in the opening of the passivation film becomes the source pad. Thereafter, the semiconductor wafer is diced (cut) into individual chips, thereby completing the silicon carbide semiconductor device 10 shown in FIGS. 1 to 3C.

[0069] As described above, according to the silicon carbide semiconductor device of the first embodiment, the p + shallower than the p-type region and deeper than the p-type base region + A type connection region is provided. + Type domain and p ++ The area of ​​connection with the contact region can be increased, the fluctuation of the feedback capacitance can be suppressed, and the SW loss can be reduced. + The region of the p-type base region exposed to the drain electrode is reduced by the type connection region, making it difficult for a high voltage to be applied to the p-type base region, and making it possible to increase the breakdown voltage.

[0070] Second Embodiment Next, a structure of a silicon carbide semiconductor device according to the second embodiment will be described. FIG. 15 is a perspective view showing the structure of the silicon carbide semiconductor device according to the second embodiment. FIG. 16 is a CC' cross-sectional view of FIG. 15 showing the structure of the silicon carbide semiconductor device according to the second embodiment. FIG. 17 is a depth D plan view of FIG. 16 showing the structure of the silicon carbide semiconductor device according to the second embodiment. The A-A' cross-sectional view and the B-B' cross-sectional view of FIG. 15 are the same as the A-A' cross-sectional view and the B-B' cross-sectional view of FIG. 1, respectively. The depth E plan view and the depth F plan view of FIG. 16 are the same as the depth E plan view and the depth F plan view of FIGS. 2A to 2C, respectively, and therefore are not shown here.

[0071] Silicon carbide semiconductor device 10 according to the second embodiment differs from silicon carbide semiconductor device 10 according to the first embodiment in that p ++ The p-type contact region 15 is provided in a stripe shape between the trenches 16. As shown in FIGS. ++ The mold contact regions 15 are periodically arranged in stripes between the trenches 16 in the longitudinal direction of the trenches 16 in a plan view, and are in contact with the trenches 16 .

[0072] In this way, p ++ By providing the contact regions 15 in a stripe shape between the trenches 16, p ++ There is no misalignment of the mold contact regions 15, and the manufacturing cost can be reduced compared to the first embodiment in which the mold contact regions 15 are provided in a dot pattern.

[0073] As described above, according to the silicon carbide semiconductor device of the second embodiment, similarly to the first embodiment, p + This makes it possible to suppress the fluctuation of the feedback capacitance, reduce the SW loss, and increase the breakdown voltage, as in the first embodiment. ++ By providing the contact region in a stripe shape between the trenches, ++ There is no misalignment of the mold contact region, and the manufacturing cost can be reduced compared to the first embodiment.

[0074] Third Embodiment Next, a structure of a silicon carbide semiconductor device according to a third embodiment will be described. FIG. 18 is a perspective view showing the structure of the silicon carbide semiconductor device according to the third embodiment. FIG. 19 is an A-A' cross-sectional view of FIG. 18 showing the structure of the silicon carbide semiconductor device according to the third embodiment. FIG. 20 is a depth E plan view of FIG. 18 showing the structure of the silicon carbide semiconductor device according to the third embodiment. The B-B' cross-sectional view and the C-C' cross-sectional view of FIG. 18 are the same as the B-B' cross-sectional view and the C-C' cross-sectional view of FIG. 1, respectively. The depth D plan view and the depth F plan view of FIG. 19 are the same as the depth D plan view and the depth F plan view of FIGS. 2A to 2C, respectively, and therefore are not shown here.

[0075] Silicon carbide semiconductor device 10 according to the third embodiment differs from silicon carbide semiconductor device 10 according to the first embodiment in that p + 18 to 20, the p + The mold connection regions 23 are arranged in a dot pattern in a direction perpendicular to the longitudinal direction of the trenches 16 in a plan view, and are spaced apart from the trenches 16. + By providing the die connection regions 23 in a dot pattern, the channel region becomes wider and the resistance can be reduced compared to the first embodiment in which the die connection regions 23 are provided in a stripe pattern between the trenches 16 .

[0076] As described above, according to the silicon carbide semiconductor device of the third embodiment, similarly to the first embodiment, p + This makes it possible to suppress the fluctuation of the feedback capacitance, reduce the SW loss, and increase the breakdown voltage, as in the first embodiment. + By providing the die connection regions in a dot pattern, the channel region becomes wider, and the resistance can be reduced more than in the first embodiment.

[0077] Fourth Embodiment Next, a structure of a silicon carbide semiconductor device according to a fourth embodiment will be described. In the fourth embodiment, perspective views are omitted. FIG. 21A is an A-A' cross-sectional view of FIG. 22A showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. FIG. 21B is a CC' cross-sectional view of FIG. 22A showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. FIG. 22A is a depth D plan view of FIGS. 21A and 21B showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. FIG. 22B is a depth E plan view of FIGS. 21A and 21B showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. The B-B' cross-sectional view of FIG. 22A is the same as the B-B' cross-sectional view of FIG. 1, and the depth F plan views of FIGS. 21A and 21B are the same as the depth F plan views of FIGS. 2A to 2C, and therefore are not shown.

[0078] Silicon carbide semiconductor device 10 according to the fourth embodiment differs from silicon carbide semiconductor device 10 according to the first embodiment in that p + The type connection region 23 and p ++ The difference is the arrangement position of the contact region 15. As shown in FIGS. + The type connection regions 23 are periodically arranged in the longitudinal direction of the trenches 16, but between adjacent trenches 16, p + The mold connection region 23 is not arranged, and ++ The p contact region 15 is also arranged. ++ The contact regions 15 are periodically arranged in the longitudinal direction of the trenches 16, but between adjacent trenches 16, p ++ The contact region 15 is not disposed, and the p + A mold connection area 23 is arranged.

[0079] As described above, according to the silicon carbide semiconductor device of the fourth embodiment, p + The type connection region is p between adjacent trenches. + No type connection region is arranged, and p ++ Even if the mold contact region is arranged, the same effect as in the first embodiment can be obtained.

[0080] Fifth Embodiment Next, a structure of a silicon carbide semiconductor device according to a fifth embodiment will be described. In the fifth embodiment, perspective views are omitted. FIG. 23A is an A-A' cross-sectional view of FIG. 24A showing the structure of a silicon carbide semiconductor device according to the fifth embodiment. FIG. 23B is a CC' cross-sectional view of FIG. 24A showing the structure of a silicon carbide semiconductor device according to the fifth embodiment. FIG. 24A is a depth D plan view of FIGS. 23A and 23B showing the structure of a silicon carbide semiconductor device according to the fifth embodiment. FIG. 24B is a depth E plan view of FIGS. 23A and 23B showing the structure of a silicon carbide semiconductor device according to the fifth embodiment. The B-B' cross-sectional view of FIG. 24A is the same as the B-B' cross-sectional view of FIG. 1, and the depth F plan views of FIGS. 23A and 23B are the same as the depth F plan views of FIGS. 2A to 2C, and therefore are not shown.

[0081] The silicon carbide semiconductor device according to the fifth embodiment differs from the silicon carbide semiconductor device according to the fourth embodiment in that p + The difference is that the mold connection regions 23 are provided in a dot pattern. + The mold connection regions 23 are arranged in a dot pattern in a direction perpendicular to the longitudinal direction of the trenches 16 in a plan view, and are spaced apart from the trenches 16. + By providing the die connection regions 23 in a dot pattern, the channel region becomes wider and the resistance can be reduced compared to the fourth embodiment in which the die connection regions 23 are provided in a stripe pattern between the trenches 16 .

[0082] As described above, according to the silicon carbide semiconductor device of the fifth embodiment, p + The type connection region is formed between adjacent trenches as p + No type connection region is arranged, and p ++ Even if the p-type contact region is arranged, the same effect as in the first embodiment can be obtained. + By providing the die connection regions in a dot pattern, the channel region becomes wider, and the resistance can be reduced more than in the fourth embodiment.

[0083] Also, p + The type connection region 23 and p ++ In the embodiment in which the contact regions 15 are aligned in a direction perpendicular to the longitudinal direction of the trench 16, in addition to the first to third embodiments,+ The connecting region 23 is formed in a dot pattern. ++ The mold contact regions 15 may be formed in stripes between the trenches 16 .

[0084] Also, p + The type connection region 23 and p ++ In a configuration in which the contact regions 15 are alternately arranged in a row in a direction perpendicular to the longitudinal direction of the trenches 16, in addition to the fourth and fifth embodiments, + The connecting region 23 is formed in a stripe pattern. ++ The p-type contact region 15 is striped. + The connecting region 23 is formed in a dot pattern. ++ The mold contact region 15 may be formed in a stripe shape.

[0085] The present disclosure can be modified in various ways without departing from the spirit of the present disclosure, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, etc. are variously set according to the required specifications, etc. Furthermore, each of the above-described embodiments has been described using a MOSFET having a trench structure as an example, but the present disclosure can also be applied to other semiconductor devices having a trench structure, such as IGBTs.

[0086] INDUSTRIAL APPLICABILITY As described above, silicon carbide semiconductor devices according to the present disclosure are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automobile igniters, and the like.

[0087] 10, 110 Silicon carbide semiconductor device 11, 111 n + type drain region (n + Silicon carbide substrate) 12, 112 n - n-type drift region 13, 113 p-type base region 14, 114 + Type source region 15, 115 p ++ 1. N-type contact region 16, 116: trench 17, 117: gate insulating film 18, 118: gate electrode 19, 119: interlayer insulating film 20, 120: n-type current diffusion region 21, 121: p-type current diffusion region under the trench + Type area 23p +Type connection region 38, 138 Barrier metal 40, 140 Semiconductor substrate 41, 141 n + Starting substrate 42, 142 n - Silicon carbide layer 43, 143 Ohmic electrode 44, 144 Source electrode 45, 145 Drain electrode 122 p ++ p under the contact region + type area

Claims

a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate; a second semiconductor region of a second conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate, in contact with the first semiconductor region and the second semiconductor layer; a trench penetrating the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer; a gate electrode provided inside the trench via a gate insulating film; and a high concentration region of a second conductivity type provided inside the first semiconductor layer at a position facing the trench in a depth direction. a connection region of a second conductivity type selectively provided inside the first semiconductor layer, on the second semiconductor layer side of the high concentration region and on the silicon carbide semiconductor substrate side of the second semiconductor layer, in contact with the high concentration region and the second semiconductor layer; a first electrode provided on surfaces of the first semiconductor region and the second semiconductor region; and a second electrode provided on a back surface of the silicon carbide semiconductor substrate, wherein the second semiconductor region is periodically arranged in a longitudinal direction of the trench, and the connection region is periodically arranged in a region not overlapping with the second semiconductor region in a planar view.

2. The silicon carbide semiconductor device according to claim 1, wherein the width of said connection region in a direction perpendicular to the longitudinal direction of said trench is wider than the width of said second semiconductor region in a direction perpendicular to the longitudinal direction of said trench.

3. The silicon carbide semiconductor device according to claim 1, wherein the connection regions are provided in a dot shape between the trenches in a plan view so as not to contact the trenches.

4. The silicon carbide semiconductor device according to claim 1, wherein the connection regions are provided in a stripe shape perpendicular to the longitudinal direction of the trenches and in contact with the trenches when viewed from above.

5. The silicon carbide semiconductor device according to claim 3 or 4, wherein the second semiconductor region is provided in a dot shape between the trenches in a plan view so as not to contact the trenches.

6. A silicon carbide semiconductor device according to claim 3 or 4, characterized in that the second semiconductor regions are provided in a stripe pattern perpendicular to the longitudinal direction of the trenches and in contact with the trenches between the trenches in a plan view.

7. The silicon carbide semiconductor device according to claim 1, wherein the impurity concentration of said connection region is higher than the impurity concentration of said second semiconductor layer and lower than the impurity concentration of said high concentration region.

8. The impurity concentration of the second semiconductor layer, the connection region and the high concentration region is 1×10 17 / cm 3 2. The silicon carbide semiconductor device according to claim 1, wherein:

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