Capacitor

Abstract

A capacitor according to one embodiment of the present invention comprises: a base substrate including a plurality of through-holes penetrating from a first surface to a second surface opposite to the first surface; a base electrode disposed on the first surface so as to cover at least two adjacent through-holes among the plurality of through-holes; a first electrode layer disposed on the upper surface edge and side surface of the base electrode; a dielectric layer disposed on the first electrode layer; a second electrode layer disposed on the dielectric layer; an insulating layer disposed on the second electrode layer; and a first electrode pad disposed on the upper surface of the base electrode, wherein the insulating layer extends from the upper surface of the second electrode layer along the side surface of the second electrode layer, the side surface of the dielectric layer, and the side surface of the first electrode layer to the upper surface of the base electrode, and is disposed between the side surface of the first electrode pad and the side surface of the first electrode layer, the side surface of the dielectric layer, and the side surface of the second electrode layer.

Description

capacitor

[0001] An embodiment of the present invention relates to a capacitor.

[0002] Semiconductor packages are used in a variety of fields, including automobiles, communications, and computers. They typically include printed circuit boards (PCBs), semiconductor chips positioned on the PCBs, and passive components positioned on the PCBs. Passive components may include, for example, resistors, inductors, and capacitors.

[0003] As semiconductor packaging becomes more sophisticated, the demand for high-performance, highly reliable, and ultra-small capacitors is increasing. To meet these demands, silicon-based capacitors and anodic aluminum oxide (AAO)-based capacitors have been proposed. Silicon-based capacitors include electrode layers, dielectric layers, and electrode layers sequentially stacked on a silicon base, while AAO-based capacitors include electrode layers, dielectric layers, and electrode layers sequentially stacked on an AAO base.

[0004] The AAO base may be a porous substrate manufactured using a metal anodic oxidation process. Because the porous substrate has a large surface area, it can increase the capacity of the capacitor. However, the difficulty of arranging electrode pads on the porous substrate is a problem.

[0005] The technical problem to be achieved by the present invention is to provide an ultra-small and high-capacity capacitor.

[0006] According to one embodiment of the present invention, a capacitor comprises a base substrate including a plurality of through holes penetrating from a first surface to a second surface opposite the first surface, a base electrode disposed on the first surface so as to cover at least two adjacent through holes among the plurality of through holes, a first electrode layer disposed on an upper edge and a side surface of the base electrode, a dielectric layer disposed on the first electrode layer, a second electrode layer disposed on the dielectric layer, an insulating layer disposed on the second electrode layer, and a first electrode pad disposed on an upper surface of the base electrode, wherein the insulating layer extends from an upper surface of the second electrode layer along a side surface of the second electrode layer, a side surface of the dielectric layer, and a side surface of the first electrode layer to an upper surface of the base electrode, and is disposed between the side surface of the first electrode layer, the side surface of the dielectric layer, the side surface of the second electrode layer, and the side surface of the first electrode pad.

[0007] The side of the base electrode may be arranged to be inclined with respect to the first surface, and the first electrode layer arranged on the side of the base electrode may be arranged to be inclined with respect to the first surface.

[0008] The side surface of the base electrode includes a concave region, and the first electrode layer can be arranged along the concave region on the side surface of the base electrode.

[0009] The lower surface of the base electrode may include a protrusion protruding in a direction from the first surface toward the second surface within the at least two through holes.

[0010] The at least two through holes arranged at the lower portion of the base electrode may be empty.

[0011] Among the plurality of through holes, the remaining through holes, excluding the at least two through holes, can be filled by the first electrode layer, the dielectric layer, the electrode layer, and the insulating layer.

[0012] The first electrode layer, the dielectric layer, the second electrode layer, and the insulating layer may be sequentially arranged on the inner wall surface of the remaining through holes, excluding at least two of the through holes among the plurality of through holes.

[0013] The first electrode layer, the dielectric layer, and the second electrode layer may be sequentially arranged on the first surface of the base substrate in a second region around the first region where the base electrode is arranged, and may further include a second electrode pad arranged on the second electrode layer in the second region.

[0014] The thickness of the base electrode may be 0.9 to 1.1 times the thickness of the first electrode layer, the dielectric layer, and the second electrode layer arranged in the second region.

[0015] The thickness of the above base electrode may be 10 nm to 100 μm.

[0016] The diameter of each of the plurality of through holes may be 10 nm to 500 nm, the shortest distance between two through holes may be 10 nm to 500 nm, and the aspect ratio of each through hole may be 20 or more.

[0017] The above base substrate may be an anodized substrate of at least one of aluminum (Al), magnesium (Mg), zinc (Zn), titanium (Ti), tantalum (Ta), hafnium (Hf), and niobium (Nb).

[0018] According to embodiments of the present invention, an ultra-small, high-capacity capacitor can be provided. Furthermore, according to embodiments of the present invention, a capacitor with a simple manufacturing process, low cost, and high reliability can be provided. In particular, according to embodiments of the present invention, a capacitor with a simple process for connecting electrode pads can be provided.

[0019] Figure 1 is a perspective view of a capacitor according to an embodiment of the present invention.

[0020] FIG. 2 is a perspective view of a base substrate included in a capacitor according to an embodiment of the present invention.

[0021] FIG. 3 is a top view of a base substrate included in a capacitor according to an embodiment of the present invention.

[0022] FIG. 4 is a cross-sectional view of a base substrate included in a capacitor according to an embodiment of the present invention.

[0023] FIG. 5 is a top view of a base substrate and a base electrode included in a capacitor according to an embodiment of the present invention.

[0024] FIG. 6 is a cross-sectional view of a base substrate and a base electrode included in a capacitor according to an embodiment of the present invention.

[0025] Figures 7 to 12 are cross-sectional views of capacitors according to embodiments of the present invention.

[0026] Fig. 13 is an example of a method for manufacturing a base substrate according to an embodiment of the present invention.

[0027] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0028] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0029] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0030] Additionally, the terms used in the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention.

[0031] In this specification, the singular may also include the plural unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C”, it may include one or more of all combinations that can be combined with A, B, C.

[0032] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0033] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0034] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0035] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it can include the meaning of a downward direction as well as an upward direction based on one component.

[0036] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0037] FIG. 1 is a perspective view of a capacitor according to an embodiment of the present invention, FIG. 2 is a perspective view of a base substrate included in a capacitor according to an embodiment of the present invention, FIG. 3 is a top view of a base substrate included in a capacitor according to an embodiment of the present invention, FIG. 4 is a cross-sectional view of a base substrate included in a capacitor according to an embodiment of the present invention, FIG. 5 is a top view of a base substrate and a base electrode included in a capacitor according to an embodiment of the present invention, FIG. 6 is a cross-sectional view of a base substrate and a base electrode included in a capacitor according to an embodiment of the present invention, and FIGS. 7 to 12 are cross-sectional views of capacitors according to embodiments of the present invention.

[0038] Referring to FIGS. 1 to 12, the capacitor (100) includes a base substrate (110), a first electrode layer (120), a first dielectric layer (130), and a second electrode layer (140).

[0039] As illustrated in FIGS. 2 to 4, the base substrate (110) includes a first surface (111), a second surface (112) opposite the first surface (111), and a third surface (113) disposed between the first surface (111) and the second surface (112). The first surface (111), the second surface (112), and the third surface (113) may be referred to as a top surface, a bottom surface, and a side surface, respectively. The base substrate (110) is illustrated as having a hexahedral shape, but is not limited thereto. The base substrate (110) may be a cylinder, an elliptical cylinder, a prism, or the like.

[0040] The base substrate (110) may include a semiconductor material or an insulator material. For example, the base substrate (110) may include an anodized metal. For example, the base substrate (110) may be an anodized substrate of at least one of aluminum (Al), magnesium (Mg), zinc (Zn), titanium (Ti), tantalum (Ta), hafnium (Hf), and niobium (Nb). For example, the base substrate (110) may include anodic aluminum oxide (AAO). Alternatively, the base substrate (110) may be a silicon (Si) substrate. For example, the base substrate (110) may be a doped silicon substrate. For example, the base substrate (110) may be an n-type doped silicon substrate or a p-type doped silicon substrate.

[0041] According to an embodiment of the present invention, the base (110) includes a plurality of through holes (TH) penetrating from the first surface (111) to the second surface (112). That is, the plurality of through holes (TH) extend from the first surface (111) to the second surface (112) of the base (110). At this time, at least some of the plurality of through holes (TH) may be parallel to each other. For example, an imaginary line connecting the center of the bottom surface of one of the plurality of through holes (TH) to the center of the upper surface may be parallel to an imaginary line connecting the center of the top surface of another of the plurality of through holes (TH) to the center of the upper surface. Accordingly, since an electrode layer can be easily deposited with a uniform thickness on the inner wall surfaces of the plurality of through holes (TH), a highly reliable capacitor can be obtained. The plurality of through holes (TH) may be regularly arranged. For example, as illustrated in FIG. 3, the distance from the center point (P1) of a through hole to the center points (P2 to P7) of six through holes arranged to surround it is constant, and the center points (P2 to P7) of the six through holes can be virtually connected to form a hexagonal shape. At this time, the deviation of the diameters (d1) of the plurality of through holes (TH) can be within 25%. Alternatively, the deviation of the distance (d2) between the center points of neighboring through holes among the plurality of through holes (TH) can be within 25%. Here, the deviation can mean the deviation between the minimum value and the maximum value. That is, the maximum value of the diameter or the distance between the center points of the through hole can mean that it is 1.25 times or less of the minimum value of the diameter or the distance between the center points of the through hole. Alternatively, the deviation can mean the deviation from the average value. That is, it can mean that the diameter of the through-hole or the distance between the center points is within 75% to 125% of the average value of the diameter of the through-hole or the distance between the center points. In this way, when a plurality of through-holes (TH) are regularly arranged, the surface area of ​​the base substrate (110) is maintained constant, so that a capacitor of uniform quality can be obtained.

[0042] According to an embodiment of the present invention, the average diameter (d1) of the plurality of through holes (TH) may be 1 nm to 1 μm, preferably 10 nm to 500 nm, and more preferably 50 nm to 300 nm. Alternatively, the average shortest distance (d3) between two adjacent through holes (TH) may be 1 nm to 1 μm, preferably 10 nm to 500 nm, and more preferably 50 nm to 300 nm. Accordingly, while having a sufficient specific surface area for implementing a capacitor, the possibility of damage to the base substrate (110) may be minimized and durability may be increased.

[0043] At this time, each through hole (TH) may have an aspect ratio of 20 or more, preferably 40 or more, more preferably 60 or more, and even more preferably 80 or more. Here, the aspect ratio may mean the ratio of the height (H) of the through hole (TH) based on the second surface (112) of the base substrate (110) to the diameter (d1) of the through hole (TH). Accordingly, a capacitor having a high capacity can be obtained by maximizing the surface area of ​​the base substrate (110).

[0044] Meanwhile, as illustrated in FIGS. 5 and 6, the capacitor (100) according to an embodiment of the present invention further includes a base electrode (600). The base electrode (600) is disposed on the first surface (111) of the base substrate (110) so as to cover at least two adjacent through holes among the plurality of through holes (TH). Accordingly, it is possible to easily connect an external electrode even on the first surface (111) of the base substrate (110) where through holes are formed with a diameter in nm units or a distance between center points in nm units.

[0045] More specifically, as illustrated in FIGS. 7 to 12, according to an embodiment of the present invention, the first electrode layer (120) is disposed on the first surface (111), the second surface (112) of the base (110) and the inner wall surfaces of the plurality of through holes (TH2), the first dielectric layer (130) is disposed on the first electrode layer (120) on the first surface (111), the second surface (112) of the base (110) and the inner wall surfaces of the plurality of through holes (TH2), the second electrode layer (140) is disposed on the first dielectric layer (130) on the first surface (111), the second surface (112) of the base (110) and the inner wall surfaces of the plurality of through holes (TH2), the first electrode pad (150) is connected to the first electrode layer (120), and the second electrode pad (160) is connected to the second electrode layer (140).

[0046] The capacitance of a capacitor can be calculated according to the following mathematical formula 1.

[0047]

[0048] Here, C is the capacitance, ε is the permittivity, S is the area of ​​the electrode layer, and d is the distance between the electrode layers. According to this, it can be seen that the larger the area of ​​the electrode layer, the greater the capacitance.

[0049] At this time, the first electrode layer (120) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium-tin. For example, the first electrode layer (120) may include TiN, TiO2, MoO x , WO x , may include at least one of ITO and ITGO, wherein x is a positive integer.

[0050] In this way, when the first electrode layer (120) is arranged on the first surface (111), the second surface (112) of the base (110) and the inner wall surface of the through hole (TH2), the specific surface area of ​​the capacitor increases, so that a high electrostatic capacitance can be obtained. In addition, since gas can flow through the through hole (TH2) during the deposition process of the first electrode layer (120), easy and uniform deposition is possible.

[0051] Next, the first dielectric layer (130) is made of SiO2, Si3N3, SiN4, ZAZ, HfO2, ZrO2, Hf x Zr y O z and may include at least one of Al2O3, wherein x, y, and z are positive integers. When the material of the first dielectric layer (130) satisfies these conditions, it is easy to deposit the first dielectric layer (130) on the first electrode layer (120) with a uniform thickness.

[0052] Next, the second electrode layer (140) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, copper (Cu), and aluminum (Al). For example, the second electrode layer (140) may include TiN, TiO2, MoO x , WO x , may include at least one of ITO, ITGO, Cu and Al, wherein x is a positive integer.

[0053] The material of the second electrode layer (140) may be the same as the material of the first electrode layer (120), but is not limited thereto. That is, the material of the second electrode layer (140) may be different from the material of the first electrode layer (120). For example, the first electrode layer (120) may be deposited using at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium-tin, and the second electrode layer (140) may be plated using Cu or Al.

[0054] At this time, the first electrode layer (120) is disposed on the edge and side surface (630) of the upper surface (610) of the base electrode (600), the first dielectric layer (130) is disposed on the first electrode layer (120), and the second electrode layer (140) is disposed on the first dielectric layer (130). Here, the first electrode layer (120) is in direct contact with the edge and side surface (630) of the upper surface (610) of the base electrode (600), and the first electrode pad (150) is disposed on the upper surface (610) of the base electrode (600). According to this, it is possible to easily place a first electrode pad (150) on a first surface (111) of a base substrate (110) in which a through hole is formed with a diameter in nm units or a distance between center points in nm units without a complicated process, and the first electrode layer (120) can be directly electrically connected to the first electrode pad (150) through the base electrode (600).

[0055] Here, the base electrode (600) may include the same material as the first electrode layer (120) or may include a different material. For example, the base electrode (600) may include at least one of chromium (Cr), copper (Cu), titanium (Ti), aluminum (Al), silver (Ag), and gold (Au), and may be disposed on the first surface (111) of the base substrate (110) by a deposition method. The base electrode (600) may be deposited on the first surface (111) of the base substrate (110) by a PVD (physical vapor deposition) method or a CVD (chemical vapor deposition) method.

[0056] According to an embodiment of the present invention, the capacitor (100) further includes an insulating layer (400) disposed on the second electrode layer (140), and the insulating layer (400) extends from the upper surface of the second electrode layer (140) along the side surface of the second electrode layer (140), the side surface of the first dielectric layer (130), and the side surface of the first electrode layer (120) to the upper surface (610) of the base electrode (600), and is disposed between the side surface of the first electrode layer (120), the side surface of the first dielectric layer (130), the side surface of the second electrode layer (140), and the side surface of the first electrode pad (150). Accordingly, the first electrode layer (120) is electrically connected to the first electrode pad (150) through the base electrode (600), but the second electrode layer (140) can be electrically insulated from the first electrode pad (150) by the insulating layer (400).

[0057] Meanwhile, according to an embodiment of the present invention, the capacitor (100) further includes a second electrode pad (160) disposed on the second electrode layer (140) and electrically connected to the second electrode layer (140). When the region of the first surface (111) of the base substrate (110) where the base electrode (600) is disposed is referred to as the first region (111A), the region of the first surface (111) of the base substrate (110) excluding the first region, that is, the region around the first region, may be referred to as the second region. That is, when the region of the first surface (111) of the base substrate (110) where the base electrode (600) is disposed is referred to as the first region, the region of the first surface (111) of the base substrate (110) where the base electrode (600) is not disposed may be referred to as the second region. According to an embodiment of the present invention, a second electrode pad (160) is disposed on a first electrode layer (120), a first dielectric layer (130), and a second electrode layer (140) sequentially disposed in a second region. As described above, an insulating layer (400) is disposed on the second electrode layer (140). In order for the second electrode layer (140) and the second electrode pad (160) to be electrically connected, an opening may be formed in the insulating layer (400) disposed in the second region, and the second electrode pad (160) may be disposed in the opening to be in direct contact with the second electrode layer (140).

[0058] According to an embodiment of the present invention, the thickness of the base electrode (600) may be 0.9 to 1.1 times, preferably 0.95 to 1.05 times, and more preferably 0.975 to 1.025 times, the sum of the thicknesses of the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) arranged in the second region. Accordingly, the first electrode pad (150) and the second electrode pad (160) may be arranged to have the same height with respect to the first surface (111) of the base substrate (110). Accordingly, when mounting a capacitor (100) according to an embodiment of the present invention on a printed circuit board, there is no need to separately adjust the heights of the first electrode pad (150) and the second electrode pad (160), so the assembly process can be improved, and the bonding strength between the first electrode pad (150) and the second electrode pad (160) and the printed circuit board can be improved.

[0059] To this end, the thickness of the base electrode (600) may be 10 nm to 100 μm, preferably 10 nm to 50 μm, and more preferably 10 nm to 10 μm. Accordingly, when the capacitor (100) is mounted on a printed circuit board while stably supporting the first electrode pad (150) disposed on the base electrode (600), the bonding strength with the printed circuit board can be maintained at a high level.

[0060] According to an embodiment of the present invention, in a state where the base electrode (600) is disposed on the first surface (111) of the base substrate (110), the material of the first electrode layer (120) can be deposited so that the first electrode layer (120) is disposed on the upper surface and side surfaces of the base electrode (600), the surface of the base substrate (110), and the inner wall surface of the through hole (TH2). The first electrode layer (120) can be deposited, for example, using an atomic layer deposition (ALD) process. Using the ALD process, the material of the first electrode layer (120) can be conformally deposited on the upper surface and side surfaces of the base electrode (600), the surface of the base substrate (110), and the inner wall surface of the through hole (TH2) in atomic units. Accordingly, the first electrode layer (120) can be uniformly deposited on the upper surface and side surfaces of the base electrode (600), the surface of the base substrate (110), and the inner wall surface of the through hole (TH2).

[0061] Likewise, the first dielectric layer (130) can be deposited, for example, using an ALD process. According to this, the material of the first dielectric layer (130) can be conformally and uniformly deposited on the surface of the first electrode layer (120) at an atomic level.

[0062] In addition, the second electrode layer (140) can be deposited, for example, using an ALD process. According to this, the material of the second electrode layer (140) can be conformally deposited on the surface of the first dielectric layer (130) at an atomic level. Alternatively, the second electrode layer (140) can be formed on the first dielectric layer (130) by an electrolytic plating process. In this case, the second electrode layer (140) can include Cu or Al.

[0063] And, the insulating layer (400) can be placed on the second electrode layer (140).

[0064] As described above, since the first electrode layer (120), the first dielectric layer (130), the second electrode layer (130), and the insulating layer (400) are arranged in a state where the base electrode (600) is arranged on the first surface (111) of the base substrate (110), the through hole (TH1) arranged at the bottom of the base electrode (600) is empty, and the remaining through holes (TH2) except for the through hole (TH1) arranged at the bottom of the base electrode (600) can be filled with the first electrode layer (120), the first dielectric layer (130), the second electrode layer (130), and the insulating layer (400). For example, the first electrode layer (120), the first dielectric layer (130), the second electrode layer (130), and the insulating layer (400) can be sequentially arranged on the inner wall surface of the remaining through holes (TH2) except for the through hole (TH1) arranged at the bottom of the base electrode (600).

[0065] In this way, when the insulating layer (400) is disposed on the second electrode layer (130), the thickness of the second electrode layer (130) can be maintained constant, so that a capacitor having uniform electrical characteristics can be obtained. In addition, when the insulating layer (400) is disposed on the second electrode layer (130) and fills the inside of the through hole (TH2), even if the temperature of the capacitor (100) increases, the plurality of through holes (TH2) do not thermally expand, so that a capacitor (100) having high reliability can be obtained. Alternatively, the insulating layer (400) can serve as a passivation. For this purpose, the insulating layer (400) can include Al2O3 or SiO2, or a resin composition having insulating and electrical insulating properties.

[0066] According to an embodiment of the present invention, as illustrated in FIG. 8, the lower surface (620) of the base electrode (600) may include a protrusion (622) protruding in a direction from the first surface (111) toward the second surface (112) within the through hole (TH) in which the base electrode (600) is arranged. Accordingly, since the base electrode (600) is stably fixed to the base substrate (110), high reliability can be maintained even when the capacitor (100) is applied to an environment with frequent shaking or vibration. At least one of the shape and thickness of the protrusion (622) may vary depending on the conditions of the deposition process of the PVD method or the CVD method or the deposition material.

[0067] According to an embodiment of the present invention, as illustrated in FIG. 9, the side surface (630) of the base electrode (600) may be arranged to be inclined with respect to the first surface (111) of the base substrate (110). Here, being arranged to be inclined with respect to the first surface (111) of the base substrate (110) may mean that the angle between the first surface (111) of the base substrate (110) and the side surface (630) of the base electrode (600) is greater than 90 degrees and less than 180 degrees. For example, the angle between the first surface (111) of the base substrate (110) and the side surface (630) of the base electrode (600) may be greater than 90 degrees and less than 180 degrees, greater than or equal to 100 degrees and less than or equal to 150 degrees, or greater than or equal to 110 degrees and less than or equal to 130 degrees. The angle between the first surface (111) of the base substrate (110) and the side surface (630) of the base electrode (600) may vary depending on the conditions or deposition materials of the PVD or CVD deposition process for the base electrode (600). Accordingly, the first electrode layer (120) disposed on the side surface (630) of the base electrode (600) may also be disposed to be inclined with respect to the first surface (111) of the base substrate (110). Similarly, the first dielectric layer (130) and the second electrode layer (140) disposed on the side surface (630) of the base electrode (600) may also be disposed to be inclined with respect to the first surface (111) of the base substrate (110). Accordingly, since the area of ​​the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) arranged on the side surface (630) of the base electrode (600) increases, the electrostatic capacitance can be increased, and the bonding force between the side surface (630) of the base electrode (600) and the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) can be increased. In addition, the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) can be deposited with a uniform thickness at the boundary between the upper surface (610) and the side surface (630) of the base electrode (600) and the boundary between the side surface (630) of the base electrode (600) and the first surface (111) of the base substrate (110).When the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) are deposited with uniform thickness, the resistance of the first electrode layer (120) and the second electrode layer (140) can be maintained uniformly, and a uniform capacitance can be obtained.

[0068] According to an embodiment of the present invention, as illustrated in FIG. 10, the side surface (630) of the base electrode (600) may include a concave region. The shape of the side surface (630) of the base electrode (600) may vary depending on the conditions or deposition materials of a PVD or CVD deposition process for the base electrode (600). Accordingly, the first electrode layer (120) disposed on the side surface (630) of the base electrode (600) may also be disposed along the concave region of the side surface (630) of the base electrode (600). Similarly, the first dielectric layer (130) and the second electrode layer (140) disposed on the side surface (630) of the base electrode (600) may also be disposed along the concave region of the side surface (630) of the base electrode (600). Accordingly, since the area of ​​the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) arranged on the side surface (630) of the base electrode (600) increases, the electrostatic capacitance can be increased, and the bonding force between the side surface (630) of the base electrode (600) and the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) can be increased. In addition, the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) can be deposited with a uniform thickness at the boundary between the upper surface (610) and the side surface (630) of the base electrode (600) and the boundary between the side surface (630) of the base electrode (600) and the first surface (111) of the base substrate (110).

[0069] According to an embodiment of the present invention, as illustrated in FIG. 11, the side surface (630) of the base electrode (600) may include a concave region, and the lower surface (620) of the base electrode (600) may include a protrusion (622) protruding from the first surface (111) toward the second surface (112) at the through hole (TH1). Although not illustrated, the side surface (630) of the base electrode (600) may be arranged to be inclined with respect to the first surface (111) of the base substrate (110), and the lower surface (620) of the base electrode (600) may include a protrusion (622) protruding from the first surface (111) toward the second surface (112) at the through hole (TH1).

[0070] According to an embodiment of the present invention, as illustrated in FIG. 12, a dielectric layer and an electrode layer may be further alternately arranged on the second electrode layer (140). The second dielectric layer (180) is arranged on the second electrode layer (140).

[0071] At this time, the second dielectric layer (180) is SiO2, Si3N3, SiN4, ZAZ, HfO2, ZrO2, Hf x Zr y O z and may include at least one of Al2O3, wherein x, y, and z are positive integers. When the material of the second dielectric layer (180) satisfies these conditions, it is easy to deposit the second dielectric layer (140) on the second electrode layer (140) with a uniform thickness.

[0072] Next, the third electrode layer (190) is placed on the second dielectric layer (180).

[0073] At this time, the third electrode layer (190) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, copper (Cu), and aluminum (Al). For example, the third electrode layer (190) may include TiN, TiO2, MoO x , WO x, may include at least one of ITO, ITGO, Cu and Al, wherein x is a positive integer.

[0074] The material of the third electrode layer (190) may be the same as the material of the first electrode layer (120) and the second electrode layer (140), but is not limited thereto. That is, the material of the third electrode layer (190) may be different from the materials of the first electrode layer (120) and the second electrode layer (140). For example, the first electrode layer (120) and the second electrode layer (140) may include titanium (Ti), molybdenum (Mo), tungsten (W), and indium-tin, and the third electrode layer (190) may include Cu or Al.

[0075] Fig. 13 is an example of a method for manufacturing a base substrate according to an embodiment of the present invention.

[0076] Referring to Fig. 13(a), an aluminum substrate is prepared. Here, the aluminum substrate may be an aluminum substrate containing 90% or more, preferably 99% or more, and more preferably 99.999% or more aluminum. At this time, the aluminum substrate may have a rough surface.

[0077] Referring to Fig. 13(b), the surface of the aluminum substrate is electrochemically polished. Accordingly, the surface of the aluminum substrate can be planarized.

[0078] Referring to Fig. 13(c), a first anodic oxidation process is performed on the surface of a planarized aluminum substrate. Accordingly, AAO can be grown on the aluminum substrate. At this time, AAO can be grown through a wet process. Accordingly, AAO having pores of a predetermined width can be grown on the aluminum substrate. At this time, AAO grown through the first anodic oxidation process may not be uniform.

[0079] Referring to Fig. 13(d), AAO on an aluminum substrate is removed through wet etching.

[0080] Referring to Fig. 13(e), a second anodizing process is performed on an aluminum substrate from which AAO grown by the first anodizing process has been removed. Accordingly, AAO can be grown more uniformly on the aluminum substrate than AAO grown during the first anodizing process. At this time, by controlling the solvent, temperature, time, and voltage of the second anodizing process, the pore size and length of AAO can be adjusted.

[0081] Referring to Fig. 13(f), the aluminum substrate is removed through wet etching.

[0082] Referring to Fig. 13(g), the lower part of the AAO, i.e., the area in contact with the aluminum substrate, is removed through wet etching.

[0083] Accordingly, a base substrate (110) including a plurality of through holes (TH) penetrating from the first surface (111) to the second surface (112) can be obtained.

[0084] Afterwards, a base electrode (600) is placed on the first surface (111) of the base substrate (110), a first electrode layer (120), a first dielectric layer (130), and a second electrode layer (140) are sequentially deposited, an insulating layer (400) is placed, a first electrode pad (150) is connected on the base electrode (600) electrically connected to the first electrode layer (120), and a second electrode pad (160) is connected on the second electrode layer (140).

[0085] Here, a method for manufacturing a capacitor including an AAO base is mainly described, but embodiments of the present invention are not limited thereto. A capacitor according to an embodiment of the present invention may be a silicon-based capacitor including a silicon base.

[0086] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. A base substrate including a plurality of through holes extending from a first surface to a second surface opposite to the first surface; A base electrode disposed on the first surface so as to cover at least two adjacent through holes among the plurality of through holes; A first electrode layer arranged on the upper edge and side of the base electrode; A dielectric layer disposed on the first electrode layer, A second electrode layer disposed on the dielectric layer, An insulating layer disposed on the second electrode layer, and including a first electrode pad disposed on the upper surface of the base electrode; A capacitor in which the insulating layer extends from the upper surface of the second electrode layer along the side surface of the second electrode layer, the side surface of the dielectric layer, and the side surface of the first electrode layer to the upper surface of the base electrode, and is disposed between the side surface of the first electrode layer, the side surface of the dielectric layer, the side surface of the second electrode layer, and the side surface of the first electrode pad.

2. In paragraph 1, The side of the base electrode is arranged to be inclined with respect to the first surface, A capacitor in which the first electrode layer disposed on the side of the base electrode is disposed to be inclined with respect to the first surface.

3. In paragraph 1, The side of the above base electrode includes a concave area, A capacitor in which the first electrode layer is arranged along the concave area on the side of the base electrode.

4. In paragraph 1, A capacitor in which the lower surface of the base electrode includes a protrusion protruding from the first surface toward the second surface within the at least two through holes.

5. In paragraph 1, A capacitor wherein at least two through holes disposed at the lower portion of the base electrode are empty.

6. In paragraph 5, A capacitor in which the remaining through holes, excluding the at least two through holes among the plurality of through holes, are filled by the first electrode layer, the dielectric layer, the electrode layer, and the insulating layer.

7. In paragraph 6, A capacitor in which the first electrode layer, the dielectric layer, the second electrode layer, and the insulating layer are sequentially arranged on the inner wall surfaces of the remaining through holes, excluding at least two of the through holes among the plurality of through holes.

8. In paragraph 1, The first electrode layer, the dielectric layer, and the second electrode layer are sequentially arranged on the first surface of the base substrate in a second region around the first region where the base electrode is arranged, A capacitor further comprising a second electrode pad disposed on the second electrode layer of the second region.

9. In paragraph 8, A capacitor in which the thickness of the base electrode is 0.9 to 1.1 times the thickness of the first electrode layer, the dielectric layer, and the second electrode layer arranged in the second region.

10. In paragraph 1, A capacitor in which the above base substrate is an anodic oxide substrate of at least one of aluminum (Al), magnesium (Mg), zinc (Zn), titanium (Ti), tantalum (Ta), hafnium (Hf), and niobium (Nb).

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