Pulse distortion compensation for pulse-width-modulation based converters

Abstract

Circuits and methods for elimination of narrow pulses and compensation thereof, as well as compensation of dead time and non-idealities in a converter including voltage drops across switches and busbars, pulse distortions caused by delays, unequal rising and falling times, and DC-bus voltage drops are disclosed. The methods can be used with converters having two complementary switches. Circuit embodiments include three sections. The first calculates deviation from reference voltage using dead-time. The second section includes a controller that adds compensatory value based on the difference between converter output and a reference voltage. The third section cancels narrow pulses and compensates for the cancellation using an integrator to accumulate differences between the reference and the output signals and uses a quantizer to add a compensatory value, without introducing new narrow pulses. The disclosed system eliminates narrow pulses to reduce losses, increase lifetime, reduce EMI, and enhance output power quality.

Description

PULSE DISTORTION COMPENSATION FOR PULSE-WIDTH-MODULATION BASED CONVERTERSFIELD OF THE INVENTION

[0001] This disclosure relates to a method of compensating for pulse distortion in converters with pulse-width modulation (PWM).BACKGROUND OF THE DISCLOSURE

[0002] Power converters play an important role in various aspects of our lives such as transportation, entertainment, energy and food chains in applications including, but not limited to, electrical drives, electric vehicles (EVs), renewable energy harvesting, power conditioning, and robotics. A power converter is a device that includes a control section which is implemented by electronics parts like microcontroller, op-amps, and other parts which control a structure of power semiconductor switches (power section) by commanding ON / OFF signals to gate drivers of the power switches. A power converter can be considered an analog to digital (A / D) converter which creates a string of discrete values from an analog waveform. For example, FIG. 1 shows a two-level pole, which is a building-block of two- level AC / DC, DC / AC or some DC / DC converters, generates a string of VDC / 2 and -VDC / 2 relative to DC-link middle point at the output, VO, which digitally can be considered "1" and "0" to synthesize an analog reference signal. FIGS. 2A-2C show ideal and non-ideal output waveforms of this pole. SI is referred to as high-side switch, and S2 as low-side switch.

[0003] The switches of the pole cannot be ON at the same time; otherwise, a short circuit between positive (+) and negative (-) rails would occur. However, with instantaneous switching of the high-side and low-side switches, there is a high possibility of overlapping ON states because of delays and non-idealities of the components. To avoid this situation, a deliberate dead-time in which none of the switches is ON is inserted between switching transitions of the high-side and low-side switches. This intentional OFF time introduces distortion to the output voltage waveform. Voltage drops on switches and busbars along with nonidealities of electronic components like delays, different skew rate, different rising and falling rates also cause distortion on the output waveform and reduce the power quality.

[0004] Another source of distortion is elimination of narrow pulses, which occurs in low and / or high modulation indices to reduce losses and to protect of the power switches. This task also causes distortion on the output waveform in high modulation index (MI) region and sometimes in low MI region depending on the modulation method.

[0005] Since in converters with high-switching frequency, the distortion is a considerable portion of the whole switching period and creates considerable deviation in the output waveform, compensating the pulse distortion is important. To generate an output waveform that precisely matches a desired reference signal, these distortions should be accounted for and compensated.

[0006] Methods for compensating these errors have been proposed in the existing literature. For example, United States patent number 6,714,424 to Deng et al. ("Deng") proposed adding a constant voltage considering current direction to reference voltage to compensate the voltage error due to dead-time. Deng's proposed method delays PWM pulses by a quarter of the switching period and generates four pulses of which two are chosen to fire switches of a leg of the converter. In addition to a large computation burden, a high number of peripheral modules of the microcontroller are needed for this method. Moreover, this method does not consider actual voltage drop on switches and diodes which introduce error into output voltage waveform. In another example of United States patent number 8,901,864 to Chi et al. ("Chi"), a dead-time compensation method proposed for v / f-controlled drives adds a smoothed value based on the sensed current and the deadtime. However, in Chi's method, dead-time is a predetermined value and the system cannot function properly in the systems with variable dead-time like auxiliary-resonant commutated pole (ARCP) circuits. In any event, Chi's method cannot compensate for other deviations due to factors such as, but not limited to, non-idealities of components, and minimum-pulse width.

[0007] The advent of fast switches such as silicon carbide (SiC) and Gallium nitride (GaN) devices have enabled manufacturers to design converters with high switching frequency. However, in such converters, a small deviation in PWM pulses can lead to considerable abnormally on the output voltage waveform and power quality.

[0008] It is desirable to mitigate the above-noted problems and to have reference waveform be synthesized a minimum of distortion at converter output, by compensating errors introduced, such as added dead-time, eliminated narrow pulses, and system nonlinearities and non-idealities.BRIEF DESCRIPTIONS OF THE DRAWINGS

[0009] For a better understanding of the embodiment(s) described herein and to show more clearly how the embodiment(s) may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings in which:

[0010] FIG. 1 depicts a prior art single-pole structure of a conventional AC-DC / DC-AC and some DC-DC converters;

[0011] FIG. 2A depicts a waveform for an ideal transition for switch transition in a pole;

[0012] FIG. 2B depicts a waveform for an ideal transition for switch transition in a pole depicting dead-time;

[0013] FIG. 20 depicts a waveform for non-ideal transition for switch transition in a pole depicting dead-time, delays, and rising and falling times;

[0014] FIG. 3A depicts a universal compensation architecture in accordance with a first embodiment showing dead-time and non-idealities compensation (DTNIC) block;

[0015] FIG. 3B depicts a universal compensation architecture in accordance with a second embodiment depicting a narrow pulse elimination and compensation (NPEC) block;

[0016] FIG. 30 depicts a universal compensation architecture in accordance with a third embodiment that includes both DTNIC and NPEC blocks;

[0017] FIG. 4 is a flowchart that depicts an algorithm for dead-time and other physical errors compensation method in accordance with an embodiment of the present disclosure;

[0018] FIG. 5A depicts the block diagram of an embodiment of NPEC that takes detection and compensation actions directly on pulse widths; and

[0019] FIG. 5B depicts the block diagram of an embodiment of NPEC that takes detection and compensation actions on reference voltages.

[0020] Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale.BRIEF SUMMARY OF THE INVENTION

[0021] In accordance with one aspect of the present disclosure, there is provided a system for elimination of narrow pulses from a power converter, compensating for effects of said elimination and outputting a desired voltage. The system includes: a sensor section for sensing electrical characteristics of a structure comprising two semiconductor devices arranged to switch in complementary mode; a control section comprising a modulator, the control section in electrical communication with the sensor section and the structure, synthesizing a reference waveform (Vref) based on one or more of dead-time, minimum acceptable pulse width (MAPW), and a required pulse width; and a compensation section to compensate the reference waveform Vref for deviations from the desired voltage Vo, by adding to or subtracting from Vref, to output a compensated voltage that is equivalent to the desired voltage Vo.

[0022] In accordance with one aspect of the present disclosure, there is provided a method for elimination of narrow pulses generated in a converter. The method includes: receiving a reference minimum acceptable pulse width (MAPW); using a narrow pulse width detector to detect narrow pulses having a width narrower than the MAPW; eliminating the narrow pulses; using an accumulator to accumulate values of the eliminated narrow pulses; and using a quantizer to modify pulses in an output waveform of the converter based on the accumulated values in the accumulator, to compensate for the eliminated pulses, wherein width of each pulse of the output waveform is greater or equal to the MAPW.

[0023] In accordance with one aspect of the present disclosure, there is provided a method of compensating for dead-time in a converter, using a controller. The method includes: receiving a dead-time value, load current, and current direction, from a structure comprising two semiconductor devices arranged to switch in complementary mode in the converter; computing compensatory voltage based on one or more of the dead-time value,the load current, and the current direction; and modifying a reference voltage based on calculated compensatory voltage.

[0024] These and other features, aspects, and advantages of the present invention will become more apparent to those skilled in the art through the following drawing and description.DETAILED DESCRIPTION

[0025] This disclosure relates to circuits and methods for compensation of the effect of eliminating narrow pulses in a converter. Particular embodiments of the disclosed method can also compensate for dead-time and non-idealities including, but not limited to, voltage drop on the switches and busbars, pulse distortion because of delays and non-equal rising and falling times, and DC-bus voltage drop. The method may be applied to any converter that has two complementary switches in its structure. Embodiments of the present disclosure include three main sections. The first section calculates voltage deviation from reference voltage using dead-time value determined in control and load current and adds appropriate compensatory value to the reference signal. The second section has a controller, which could be of Proportional-Integrator (PI), Integral (I), or other error accumulator, and based on the difference between the actual voltage at the converter output and the reference voltage adds compensatory value to the reference waveform. This section compensates output deviation because of DC bus voltage oscillation, voltage drop on the switches and busbars, and other source of the deviation like switch delays and distorted PWM pulses. If a specific converter does not have a sensor at output, this section can use an approximate model of the system to calculate compensatory value. The third section is responsible for narrow pulse cancellation and compensation for those cancelled pulses. The third section uses an integrator to accumulate a difference between reference signal and the output signal after narrow pulse cancellation. A quantizer adds appropriate value to the waveform after minimum pulse cancellation to compensate for the canceled pulses without creating pulses with widths less than an acceptable value. This disclosure allows elimination pulses with short widths and compensates for the effect of elimination of these pulses and other non-idealities like dead-time, delays, pulse distortion, voltage drop on switches and busbars, and DC-link voltage oscillation, which helps to reduce losses, increase lifetime, reduce EMI, and enhance output power quality.

[0026] Dead-time and narrow pulse elimination (NPE) cause distortion in the output voltage waveform and low power quality of a converter. This is especially true in converters with high switching frequency and / or with large dead-time interval, such as but not limited to converters with wide-band gap devices and ARCP-based converters. To have a precise synthesized voltage waveform and high-power quality at output of a converter, these distortions along with other distortions caused by non-linearities and non-idealities should be compensated.

[0027] Described herein is a compensation method for narrow pulse elimination. Such method can lower losses, lower noises, and lower stress on the power switches while maintaining the required output voltage. This method can lead to higher utilization of the DC-link, can make reaching to higher modulation indices feasible and can reduce output voltage distortions.

[0028] In some embodiments of the present disclosure herein, there is provided a compensation method for dead-time which can perform in systems or circuits with constant or variable dead-time.

[0029] With proper sensors on the converter output or a model of the system, the method described herein can additionally compensate for the deviation on output waveform with origin of system non-idealities and / or non-linearities including but not limited to voltage drop on switches and different rise / fall time of the switches.

[0030] For clarity of illustration, and where considered appropriate, reference numerals may be repeated among the Figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiment or embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein may be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the embodiments described herein. It should be understood at the outset that, although exemplary embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques, whethercurrently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described below.

[0031] Various terms used throughout the present description may be read and understood as follows, unless the context indicates otherwise: "or" as used throughout is inclusive, as though written "and / or"; singular articles and pronouns as used throughout include their plural forms, and vice versa; similarly, gendered pronouns include their counterpart pronouns so that pronouns should not be understood as limiting anything described herein to use, implementation, performance, etc. by a single gender; "exemplary" should be understood as "illustrative" or "exemplifying" and not necessarily as "preferred" over other embodiments. Further definitions for terms may be set out herein; these may apply to prior and subsequent instances of those terms, as will be understood from a reading of the present description. It will also be noted that the use of the term "a" or "an" will be understood to denote "at least one" in all instances unless explicitly stated otherwise or unless it would be understood to be obvious that it must mean "one".

[0032] Modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, "each" refers to each member of a set or each member of a subset of a set.

[0033] FIG. 3A, 3B and 3C depict block diagrams of different configurations of the systems and methods disclosed herein. As shown in FIG. 3A, FIG. 3B and FIG. 3C, the embodiments may include one or more compensators such as the DTNIC and / or NPEC blocks.

[0034] In FIG. 3A, system 300a includes an application-level control system 340a, a control section 330a, a sensor section 320a, a power section 310a and a gate driver section 350a. The control section 330a includes DTNIC 331a and modulator 333a.

[0035] In FIG. 3B, system 300b includes an application-level control system 340b, a control section 330b, a sensor section 320b, a power section 310b and a gate driver section 350b. The control section 330b includes NPEC 332b and modulator 333b.

[0036] In FIG. 3C, system 300c includes an application-level control system 340c, a control section 330c, a sensor section 320c, a power section 310c and a gate driver section 350c. The control section 330c includes DTNIC 331c, NPEC 332c, and modulator 333c.

[0037] In FIGS. 3A, 3B and 3C, similar elements are identified with similar reference numerals. System 300a, 300b, 300c may be referred to individually and collectively as "system 300". Application-level control system 340a, 340b, 340c may be referred to individually and collectively as "control system 340". Control sections 330a, 330b, 330c may be referred to individually and collectively as "control section 330". Sensor section 320a, 320b, 320c, may be referred to individually and collectively as "sensor section 320". Power section 310a, 310b, 310c may be referred to individually and collectively as "power section 310", and a gate driver sections 350a, 350b, 350c may be referred to individually and collectively as "gate driver section 350". DTNIC 331a, 331c, may be referred to individually and collectively as "DTNIC 331". NPEC 332b, 332c, may be referred to individually and collectively as "NPEC 332". Modulator 333a, 333b, 333c may be referred to individually and collectively as "modulator 333".

[0038] Power section 310 which in its structure uses switches in complementary states which can be one or multiple switch pole(s) which is shown in FIG. 1, structures with extra switches like auxiliary resonant commutated pole (ARCP), or structures that have multiple switches in complementary mode on a phase like multilevel inverters. Sensor section 320 measures required parameters and after applying filtering to the measured parameters, provides required feedback to the depicted control systems. Control section 330 uses the reference signal provided by application-level control system 340 and modulates it on the power switch gates after applying protection and compensatory measures by gate driver sections 350. If required signals are already used in the application-level control system 340, there is no need for separate sensor section and this section can be eliminated.

[0039] In some embodiments, such as the embodiment of FIG. 3C, the control section 330 comprises DTNIC 331c, NPEC section 332c, and modulator 333c. In otherembodiments, such as the embodiment of FIG. 3A, the control section 330 comprises DTNIC 331a and modulator 333a. In yet other embodiments, such as the embodiment of FIG. 3B, the control section 330b comprises NPEC section 332b and modulator 333b. Modulator 333 performs a modulation method based on pulse-width modulation including but not limited to sinusoidal pulse width modulation (SPWM) and space vector modulation (SVM) which converts the input analog waveform (from e.g. motor control algorithm) to equivalent digital gating waveform to control the power switches of the converter. For clarity, the order of the elements forming a part of control section 330 is interchangeable.

[0040] FIG. 4 shows a block diagram of an embodiment of the dead-time compensation system 400 and associated method. At block 410, the mean voltage deviation is calculated for the next PWM cycle according to load current direction. In a two-level pole (as shown in FIG. 1), this calculation is determined by current direction. When the load current is directed toward a converter in the dead-time interval, the high-side diode conducts. Therefore, if a transition occurs from low-side switch ON to high-side switch ON, dead-time has no effect on the output waveform and mean deviation is zero. On the transition from upper switch to lower switch, since the upper switch is conducting and dead-time is inserted by delaying the gate pulse of the switch is going to be turned ON, therefore for dead-time duration +VDC / 2 on the output is present while desired value is -VDC / 2, and mean voltage deviation is +VDC. In other converter structures, the mechanics of block 410 should be modified accordingly. For example, although for a soft-switching converter like auxiliary resonant commutated pole voltage does not have two-level shape of a hard-switching converter, and voltage change in the dead-time is continuous, the mean voltage deviation can be calculated using current value and system parameters or using feed-back signal of the closed-loop control as described in US application serial number 63 / 524,976 filed July 5, 2023, the contents of which are incorporated herein by reference.

[0041] In another embodiment, a model-based estimator can substitute block 410. The method then calculates a volt-second quantity considering the dead-time duration which can be variable or constant at block 420 and subtract appropriate amount from reference value by considering switching period at block 430. Adder block 440 adds compensatory voltage to the reference voltage waveform. By adding block 450 to this control section, deviation caused by DC-link voltage oscillation can be compensated. In a multilevel inverter, this section should be modified to take the corrective measures based on internalparameters like clamped-point or cell voltages. Afterwards, the signal will pass to block 460. In this embodiment, block 460 contemplates input to the NPEC; in other embodiments, block 460 can be a pulse generator.

[0042] FIG. 5A shows a block diagram of a system 500 and associated method in which the elimination and compensation can be implemented after the modulator in which case the elimination and the compensation are based on the actual width of the pulses. In this embodiment, the duty cycle values are in per-unit with base value of full-duty cycle which means full duty cycle is 1 time unit. In this case, in block 510 narrow pulses smaller than Minimum Allowable Pulse Width (MAPW) are eliminated. Since switches of one leg are in complementary mode, reference pulses with width more than (1 - MAPW) also will be saturated to the width values equal to (1 - MAPW). This eliminates narrow pulses both on low-side and high-side switches.

[0043] Afterwards, in block 520 the difference between the actual width of the reference pulse and the modified pulse is calculated. Block 570 calculates the difference between output of 520 and the feedback of the output of 540 to produce an error signal. In block 530 this error is accumulated. In block 540 the accumulated error is quantized to the two values that adding them to the modified pulse does not cause shorter pulses than permitted value on neither high-side nor low-side switch. These values are 0 or MAPW, when accumulated error is positive, and 0 or (-MAPW), when accumulated error is negative. Adding these compensatory values (output of the quantizer at block 540) by block 550 to the modified reference pulse clips the output voltage to one of the DC-link rails for the whole switching period and causes the error between actual reference pulse and the modified reference pulse to be compensated in a period of time depending on modulation index. If the compensatory value is added to the output, negative feedback deducts it from the error accumulator in block 560. Eventually, the compensated value is used to generate firing pulses in controller's PWM module.

[0044] FIG. 5B shows another embodiment of NPEC system 500b. Considering some Average Voltage caused by MAPW (AV_MAPW), in block 510b, the reference waveform is saturated from top and bottom to eliminate occurrence of the narrow pulses on high-side and low-side switches. Depending on modulation method, the regions where narrow pulses occur can be different, for example SVM does not have narrow pulses at low modulationindices while Discontinuous PWM (DPWM) has narrow pulses both on low and high modulation indices. Therefore, block 510b may be modified based on modulation method and the region that narrow pulses occur. Afterwards, in block 520b the difference between the actual reference signal and the modified reference signal is calculated. Block 570b calculates the difference between output of 520b and the feedback of the output of 540b to produce an error signal. In block 530b this error is accumulated. In block 540b the accumulated error is quantized according to its sign to the two values such that adding them to the modified reference voltage does not cause shorter pulses than the permitted value. For example, these values are 0 or +AV_MAPW, when accumulated error is positive, and 0 or -AV_MAPW, when accumulated error is negative. By adding this compensatory signal (output of the quantizer in block 540b) in block 550b to the modified reference waveform (output of block 510b), the error between actual reference signal and the modified reference signal can be compensated in a period of time depending on modulation index. Then, negative feedback deducts the compensatory signal from the error accumulator 570b. Eventually, the compensated value is used in a modulator algorithm 560b, e.g. SVM.

[0045] Increasing or reducing voltage of all phases simultaneously has no effect on the load. This fact can also be used to eliminate narrow pulses without affecting the output waveform quality by eliminating the narrow pulses and adding same duration to the other phases' pulses. However, this is not possible in all circumstances. Therefore, in another embodiment, two-stage narrow pulse elimination can be used. If the other phases have the pulse widths that increasing them in amount of the pulse width of the phase with narrow pulse does not cause narrow pulses on those phases or duty cycle more than 100%, narrow pulse elimination is done by simply eliminating pulse with smallest pulse width and reducing same duration from the pulse widths of the other phases; Otherwise, algorithm shown in FIG. 5 will be run to eliminate and compensate narrow pulse.

[0046] The method disclosed herein can improve converter performance and reliability by compensated elimination of the narrow pulses and compensating for dead-time, DC-link voltage oscillation, voltage drop on the power switches and the busbars. Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. It is contemplated that any part of any aspect or embodiment discussed in this specification may be implemented or combined with any part of any other aspect or embodiment discussed in this specification. While particularembodiments have been described in the foregoing, it is to be understood that other embodiments are possible and are intended to be included herein. It will be clear to any person skilled in the art that modification of and adjustment to the foregoing embodiments, not shown, is possible.

[0047] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as is commonly understood by one of ordinary skill in the art to which the subject matter disclosed herein belongs. In addition, any citation of references herein is not to be construed nor considered as an admission that such references are prior art to the subject matter disclosed herein.

[0048] Persons skilled in the art will appreciate that there are yet more alternative implementations and modifications possible, and that the above examples are only illustrations of one or more implementations. The scope of the claims should not be limited by the example embodiments set forth herein but should be given the broadest interpretation consistent with the description as a whole.

Claims

WHAT IS CLAIMED IS:

1. A system for eliminating narrow pulses from a power converter, and for compensating for effects of eliminating the narrow pulses from the power converter and for outputting a desired voltage, the system comprising: a sensor section for sensing electrical characteristics of a structure comprising two semiconductor devices arranged to switch in complementary mode; a control section comprising a modulator, the control section in electrical communication with the sensor section and the structure, that can synthesize a reference waveform (Vref) based on one or more of dead-time, minimum acceptable pulse width (MAPW), and a required pulse width; and a compensation section to compensate the reference waveform Vref for deviations from the desired voltage Vo, by adding to or subtracting from Vref, to output a compensated voltage that is equivalent to the desired voltage Vo.

2. The system of claim 1, wherein the electrical characteristics comprises one or more of load current, phase voltage, and DC-link voltage.

3. The system of claim 1, wherein the control section comprises at least one of: dead-time and non-idealities compensation (DTNIC) block, and a narrow pulse elimination and compensation (NPEC) block.

4. The system of claim 3, wherein the control section comprises the dead-time and nonidealities compensation (DTNIC) block.

5. The system of claim 3, wherein the control section comprises the narrow pulse elimination and compensation (NPEC) block.

6. The system of claim 1, wherein the control section sends one or more commands to a gate driver in electrical communication with one or more gates of the semiconductor devices.

7. A method for eliminating narrow pulses generated in a converter, the method comprising: receiving a reference minimum acceptable pulse width (MAPW); using a narrow pulse width detector to detect narrow pulses having a width narrower than the MAPW; eliminating the narrow pulses; using an accumulator to accumulate values of the eliminated narrow pulses; and using a quantizer to modify pulses in an output waveform of the converter based on the accumulated values in the accumulator, to compensate for the eliminated pulses, wherein a width of each pulse of the output waveform is greater or equal to the MAPW.

8. The method of claim 7, wherein the output waveform is fed to a pulse generator.

9. The method of claim 7, wherein the output waveform is fed to a narrow pulse elimination and compensation (NPEC) block.

10. The method of claim 7, wherein the narrow pulse detector detects the narrow pulses directly from a reference voltage waveform.

11. A method of compensating for dead-time in a converter, the method comprising: receiving a dead-time value, load current, and current direction, from a structure comprising two semiconductor devices arranged to switch in complementary mode in the converter; computing compensatory voltage based on one or more of the dead-time value, the load current, and the current direction; and modifying a reference voltage based on the compensatory voltage.

12. The method of claim 11, wherein said computing compensatory voltage comprises using a mean voltage deviation computed in a previous cycle.

13. The method of claim 11, wherein said computing compensatory voltage comprises using a model-based estimator.

14. The method of claim 11, wherein said modifying the reference voltage comprises using an adder to add the compensatory voltage to the reference voltage.

15. A two-stage narrow pulse elimination and compensation method comprising: a first stage for eliminating a narrow pulse having a duration W that is narrower than a minimum acceptable pulse width (MAPW) and for reducing the same duration W from pulse widths of other phases; and a second stage comprising the method of claim 7; wherein upon determining that said eliminating the narrow pulse having a duration W, does not cause narrow pulses on said phases or result in a duty cycle of more than 100%, utilizing the first stage; but otherwise utilizing the second stage.

16. A zero-voltage switching converter comprising: the system according to any one of claims 1 to 6; the structure comprising two semiconductor devices arranged to switch in complementary mode; and an auxiliary circuit in electrical communication with the structure to permit zerovoltage switching.

Images