Semiconductor structure and manufacturing method therefor, and memory

Abstract

Provided in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor, and a memory. The semiconductor structure comprises: a lower group of electrically-conductive layers and an upper group of electrically-conductive layers located on the lower group of electrically-conductive layers, wherein the two groups of electrically-conductive layers have the same number of layers, and each electrically-conductive layer is provided with a common connecting area and a storage unit area located on at least one side of the common connecting area; a plurality of through holes, which are provided in the common connecting area and are arranged at intervals in the extending direction of the common connecting area, wherein the through holes penetrate the plurality of electrically-conductive layers, and the number of through holes is equal to the number of layers of the lower group of electrically-conductive layers; a plurality of electrically-conductive posts, wherein one electrically-conductive post is correspondingly arranged in one through hole, the electrically-conductive post comprises a lower electrically-conductive section and an upper electrically-conductive section, which are separated from each other by an insulating section, one lower electrically-conductive section is correspondingly electrically connected to one electrically-conductive layer of the lower group of electrically-conductive layers, and one upper electrically-conductive section is correspondingly electrically connected to one electrically-conductive layer of the upper group of electrically-conductive layers.

Description

Semiconductor structure and manufacturing method thereof, and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 21, 2023, with application number 202311228372.5 and invention name “Semiconductor structure, manufacturing method thereof, and memory”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a semiconductor structure, a manufacturing method thereof, and a memory. Background Art

[0003] As 3D memory increases storage density through multi-layer stacking, the number of sense amplifiers (SAs) and sub-word line drivers (SWDs) in the peripheral circuits will also increase accordingly. Currently, in common-bitline memory device structures, a large number of SAs must be placed on the bonding chip. However, as the number of 3D stacking layers increases, the number of SAs also increases, placing higher requirements on the placement and integration of SAs and SWDs on the bonding chip.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in accordance with the embodiments of the present disclosure. This overview is not intended to limit the scope of the claims.

[0006] In one aspect, exemplary embodiments of the present disclosure provide a semiconductor structure comprising:

[0007] a lower set of conductive layers comprising a plurality of conductive layers stacked vertically in a spaced relationship;

[0008] an upper conductive layer group located above the lower conductive layer group and comprising a plurality of conductive layers stacked vertically and spaced apart from each other, the upper conductive layer group and the lower conductive layer group having the same number of layers, each conductive layer having a common connection region and a memory cell region located on at least one side of the common connection region;

[0009] a plurality of through holes, which are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes passing through the upper conductive layer and the lower conductive layer, and the number of the through holes is equal to the number of layers of the lower conductive layer;

[0010] Multiple conductive pillars, one of the conductive pillars is correspondingly arranged in one of the through holes, each conductive pillar includes a lower conductive segment and an upper conductive segment separated by an insulating segment, a lower conductive segment is electrically connected to a conductive layer in the lower group of conductive layers, and an upper conductive segment is electrically connected to a conductive layer in the upper group of conductive layers.

[0011] In an exemplary embodiment, it also includes multiple lower insulating rings and multiple upper insulating rings, one lower insulating ring is correspondingly arranged in a through hole and surrounds the corresponding lower conductive segment, the height of the lower insulating ring is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and is greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; one upper insulating ring is correspondingly arranged in a through hole and surrounds the corresponding upper conductive segment, and one end of the upper insulating ring close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer.

[0012] In an exemplary embodiment, along the extension direction of the common connection area, the height of the lower conductive segment in the through hole gradually increases, while the height of the upper conductive segment gradually decreases; or, the height of the lower conductive segment in the through hole gradually decreases, while the height of the upper conductive segment gradually increases.

[0013] In an exemplary embodiment, distances between adjacent through holes are the same along an extension direction of the common connection region.

[0014] In another aspect, an exemplary embodiment of the present disclosure provides a memory, comprising:

[0015] a substrate on which a plurality of first devices are disposed;

[0016] a lower conductive layer group located on the substrate and comprising a plurality of conductive layers stacked vertically in a spaced relationship;

[0017] an upper conductive layer group located above the lower conductive layer group and comprising a plurality of conductive layers stacked vertically and spaced apart from each other, wherein the upper conductive layer group and the lower conductive layer group have the same number of conductive layers, and each conductive layer has a common connection region and a memory cell region located on at least one side of the common connection region;

[0018] a bonding chip, which is located on the upper conductive layer and is provided with a plurality of second devices;

[0019] a plurality of through holes, which are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes passing through the plurality of conductive layers, and the number of the through holes is equal to the number of layers of the lower group of conductive layers;

[0020] A plurality of conductive pillars are provided, one conductive pillar is correspondingly arranged in one through hole, each conductive pillar includes a lower conductive segment and an upper conductive segment separated by an insulating segment, one end of a lower conductive segment away from the substrate is electrically connected to a conductive layer in the lower group of conductive layers, and one end close to the substrate is electrically connected to a first device; one end of an upper conductive segment away from the binding chip is electrically connected to a conductive layer in the upper group of conductive layers, and one end close to the binding chip is electrically connected to a second device.

[0021] In an exemplary embodiment, the common connection region is a common bit line region and the first device and the second device are both sense amplifiers, or the common connection region is a common word line region and the first device and the second device are both sub-word line drivers.

[0022] In an exemplary embodiment, it also includes multiple lower insulating rings and multiple upper insulating rings, one lower insulating ring is correspondingly arranged in a through hole and surrounds the corresponding lower conductive segment, the height of the lower insulating ring is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and is greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; one upper insulating ring is correspondingly arranged in a through hole and surrounds the corresponding upper conductive segment, one end of the upper insulating ring close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent previous conductive layer; the height of the lower conductive segment is greater than the height of the conductive layer to which it is electrically connected and less than the height of the previous conductive layer adjacent to the conductive layer electrically connected; the end of the upper conductive segment close to the substrate is located between the conductive layer to which it is electrically connected and the adjacent next conductive layer.

[0023] In yet another aspect, exemplary embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, comprising:

[0024] forming a stacked structure on a substrate, the stacked structure comprising a lower group of sacrificial layers and an upper group of sacrificial layers located above the lower group of sacrificial layers, the lower group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers and the lower group of sacrificial layers having the same number of layers, each sacrificial layer having a preset common connection region and a preset storage cell region located on at least one side of the preset common connection region;

[0025] forming a plurality of through holes arranged at intervals in the preset common connection area and along an extension direction of the preset common connection area, wherein the through holes penetrate the stacked structure, and the number of the through holes is equal to the number of layers of the lower group of sacrificial layers;

[0026] forming a conductive pillar and an insulating ring surrounding the conductive pillar in the through hole;

[0027] Patterning the stacked structure so that the predetermined common connection region forms a common connection region and the predetermined memory cell region forms a memory cell region;

[0028] replacing the materials of the plurality of sacrificial layers with conductive materials to form corresponding lower and upper conductive layers;

[0029] forming conductive pillars and insulating rings with different heights in each through hole to form lower conductive segments and lower insulating rings, and one lower conductive segment is electrically connected to a corresponding conductive layer in the lower group of conductive layers;

[0030] forming the insulating segment above the lower conductive segment;

[0031] Conductive columns and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and one upper conductive segment is electrically connected to one conductive layer in the upper conductive layer group.

[0032] In an exemplary embodiment,

[0033] Conductive pillars and insulating rings with different heights are formed in each through hole to form lower conductive segments and lower insulating rings, and one lower conductive segment is electrically connected to one conductive layer in the lower group of conductive layers, comprising:

[0034] Depositing an insulating layer film on the inner sidewall and bottom surface of each through hole;

[0035] removing the insulating film on the bottom surface of the through hole to form an insulating ring located on the inner side wall of the through hole;

[0036] depositing a conductive material in the through hole to form a conductive pillar;

[0037] Removing part of the material of the insulating ring and the conductive pillar in the through hole to the same height, so that the height of the insulating ring and the conductive pillar in the through hole is less than the height of the conductive layer to be electrically connected to the lower conductive segment and higher than the height of the next conductive layer adjacent to the conductive layer to be electrically connected to the lower conductive segment, so as to form the lower insulating ring and the preset lower conductive segment, and forming empty grooves of different heights in the through hole;

[0038] Depositing a conductive material into the empty groove until the empty groove is filled;

[0039] Part of the conductive material in the empty groove is removed so that the height of the preset lower conductive segment is greater than the height of the conductive layer to be electrically connected and less than the height of the upper conductive layer adjacent to the electrically connected conductive layer, so as to form the lower conductive segment, and one lower conductive segment is electrically connected to one conductive layer in the lower group of conductive layers.

[0040] In an exemplary embodiment, conductive pillars and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and one upper conductive segment is electrically connected to a corresponding conductive layer in the upper group of conductive layers, comprising:

[0041] Depositing an insulating film above the insulating segment in the through hole and removing the insulating film on top of the insulating segment to form the upper insulating ring; wherein an end of the insulating ring close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer;

[0042] removing a portion of the insulating segment in the through hole so that an end of the insulating segment away from the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent next conductive layer;

[0043] Conductive material is deposited in the empty groove to form the upper conductive segments, and one upper conductive segment is electrically connected to a corresponding conductive layer in the upper group of conductive layers.

[0044] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the solutions described in the description and the drawings.

[0045] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0046] Summary of the Figures

[0047] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0048] FIG1A is a schematic perspective view of a semiconductor structure provided in accordance with an exemplary embodiment of the present disclosure;

[0049] FIG1B is a schematic vertical cross-sectional view of the structure shown in FIG1A taken along a plane parallel to the first direction;

[0050] 2 is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a plane parallel to a first direction;

[0051] 3A is a horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a sacrificial layer;

[0052] FIG3B is a schematic vertical cross-sectional view of the intermediate product shown in FIG3A taken along a plane parallel to the first direction;

[0053] 4 is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a plane parallel to a first direction;

[0054] FIG5 is a horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a sacrificial layer;

[0055] 6A is a horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a conductive layer;

[0056] FIG6B is a schematic vertical cross-sectional view of the intermediate product shown in FIG6A taken along a plane parallel to the first direction;

[0057] 7 is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a plane parallel to a first direction;

[0058] 8 is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a plane parallel to a first direction;

[0059] 9 is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a plane parallel to a first direction;

[0060] 10 is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a plane parallel to a first direction;

[0061] 11 is a schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a plane parallel to a first direction;

[0062] FIG12 is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, taken along a plane parallel to a first direction; and

[0063] 13 is a schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure, taken along a plane parallel to a first direction.

[0064] Details

[0065] To make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0066] The embodiments herein can be implemented in a variety of different forms. A person skilled in the art can easily understand that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0067] The scales of the figures in this disclosure are intended to serve as a reference for actual processes, but are not intended to be limiting. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing between them can be adjusted based on actual needs. The figures described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0068] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0069] In this specification, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0070] In the description of the present disclosure, ordinal numbers such as “first” and “second” are provided to avoid confusion among constituent elements, rather than to limit the quantity.

[0071] In this specification, "film" and "layer" can be interchanged. For example, "metal layer" can sometimes be replaced with "metal film".

[0072] Sense amplifiers (SAs) are typically coupled to columns of memory cells (e.g., bit lines) to detect the current or voltage flowing through the memory cells as part of a read operation. A large number of SAs are placed on a bonded chip, and the number of SAs increases as the number of stacked layers increases, placing higher demands on the placement and integration of SAs and SWDs on the bonded chip. However, the inventors of the present disclosure discovered that, in order to increase the integration of memory cells, the SAs are placed in a shunt arrangement, that is, below the transistor array, so that the bit lines are located above the SAs, making it impossible to connect the SAs to the bit lines.

[0073] Therefore, an embodiment of the present disclosure provides a semiconductor structure, comprising a lower conductive layer, which comprises a plurality of conductive layers stacked vertically at intervals; an upper conductive layer, which is located above the lower conductive layer and comprises a plurality of conductive layers stacked vertically at intervals, the upper conductive layer and the lower conductive layer having the same number of layers, each conductive layer having a common connection area and a storage cell area located on at least one side of the common connection area; a plurality of through holes, which are arranged in the common connection area and are arranged at intervals along the extension direction of the common connection area, the through holes passing through the upper conductive layer and the lower conductive layer, the number of the through holes being equal to the number of layers of the lower conductive layer; a plurality of conductive pillars, one conductive pillar being correspondingly arranged in one through hole, each conductive pillar comprising a lower conductive segment and an upper conductive segment separated by an insulating segment, a lower conductive segment being electrically connected to a corresponding conductive layer in the lower conductive layer, and an upper conductive segment being electrically connected to a corresponding conductive layer in the upper conductive layer.

[0074] The semiconductor structure provided by the exemplary embodiments of the present disclosure may include a lower group of conductive layers and an upper group of conductive layers located above the lower group of conductive layers. Each group of conductive layers may include a plurality of conductive layers stacked vertically at intervals, and the upper group of conductive layers and the lower group of conductive layers have the same number of layers.

[0075] As used in this disclosure, the term "first direction" X is defined as a direction parallel to the through-hole arrangement direction; the term "second direction" Y is defined as a direction intersecting the first direction X; and the term "third direction" Z is defined as a direction perpendicular to the plane of the substrate. The plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be shown in Figure 1A, etc.

[0076] As shown in FIG1A and FIG1B , the lower conductive layer group may include a first lower conductive layer 61, a second lower conductive layer 62, a third lower conductive layer 63, a fourth lower conductive layer 64, and a fifth lower conductive layer 65, for a total of five layers. The upper conductive layer group may include a first upper conductive layer 71, a second upper conductive layer 72, a third upper conductive layer 73, a fourth upper conductive layer 74, and a fifth upper conductive layer 75, for a total of five layers. In other words, the lower conductive layer group and the upper conductive layer group have the same number of layers.

[0077] Each conductive layer may have a common bit line extending along a first direction X and at least two memory cells located on both sides of the common bit line and extending along a second direction Y. For 1T1C and 2T0C memory cells, the drain of each memory cell may be connected to the common bit line.

[0078] Continuing with FIG. 1B , the semiconductor structure provided by the present disclosure may include five through-holes disposed in the common bit line region and arranged sequentially along the extension direction of the common connection region, each through-hole penetrating the lower conductive layer and the upper conductive layer. The number of through-holes is the same as the number of layers of the lower conductive layer and the upper conductive layer.

[0079] Each through-hole may include a conductive pillar, each conductive pillar including a lower conductive segment and an upper conductive segment separated by an insulating segment. FIG1B shows that the first through-hole may include a first lower conductive segment 21, a first insulating segment 31, and a first upper conductive segment 41; the second through-hole may include a second lower conductive segment 22, a second insulating segment 32, and a second upper conductive segment 42; the third through-hole may include a third lower conductive segment 23, a third insulating segment 33, and a third upper conductive segment 43; the fourth through-hole may include a fourth lower conductive segment 24, a fourth insulating segment 34, and a fourth upper conductive segment 44; and the fifth through-hole may include a fifth lower conductive segment 25, a fifth insulating segment 35, and a fifth upper conductive segment 45.

[0080] Figure 1B also shows that the first lower conductive segment 21 is electrically connected only to the first lower conductive layer 61; the second lower conductive segment 22 is electrically connected only to the second lower conductive layer 62; the third lower conductive segment 23 is electrically connected only to the third lower conductive layer 63; the fourth lower conductive segment 24 is electrically connected only to the fourth lower conductive layer 64; and the fifth lower conductive segment 25 is electrically connected only to the fifth lower conductive layer 65. That is, the lower conductive segments in each through hole are electrically connected only to one lower conductive layer and are electrically insulated from the other lower conductive layers by their respective lower insulating rings.

[0081] 1B also shows that the first upper conductive segment 41 is electrically connected only to the first upper conductive layer 71 , the second upper conductive segment 42 is electrically connected only to the second upper conductive layer 72 , the third upper conductive segment 43 is electrically connected only to the third upper conductive layer 73 , the fourth upper conductive segment 44 is electrically connected only to the fourth upper conductive layer 74 , and the fifth upper conductive segment 45 is electrically connected only to the fifth upper conductive layer 75 . That is, the upper conductive segments in each through hole are electrically connected only to one upper conductive layer and are electrically insulated from the other upper conductive layers by their respective upper insulating rings.

[0082] 1B also shows that the height of the first lower conductive segment 21 is greater than the height of the first conductive layer 61 to which it is electrically connected and less than the height of the upper conductive layer 62 adjacent to the conductive layer 61 to which it is electrically connected; the height of the second lower conductive segment 22 is greater than the height of the second conductive layer 62 to which it is electrically connected and less than the height of the upper conductive layer 63 adjacent to the conductive layer 62 to which it is electrically connected; the height of the third lower conductive segment 23 is greater than the height of the third conductive layer 63 to which it is electrically connected and less than the height of the upper conductive layer 64 adjacent to the conductive layer 63 to which it is electrically connected; the height of the fourth lower conductive segment 24 is greater than the height of the fourth conductive layer 64 to which it is electrically connected and less than the height of the upper conductive layer 65 adjacent to the conductive layer 64 to which it is electrically connected; and the height of the fifth lower conductive segment 25 is greater than the height of the fifth conductive layer 65 to which it is electrically connected and the height of the first upper conductive layer 71.

[0083] Taking the bonded chip as the height reference plane, FIG1B also shows that the height of the first upper conductive segment 41 is greater than the height of the upper conductive layer 71 to which it is electrically connected and less than the height of the lower conductive layer 65 adjacent to the upper conductive layer 71 to which it is electrically connected; the height of the second upper conductive segment 42 is greater than the height of the upper conductive layer 72 to which it is electrically connected and less than the height of the upper conductive layer 71 adjacent to the upper conductive layer 72 to which it is electrically connected; the height of the third upper conductive segment 43 is greater than the height of the upper conductive layer 73 to which it is electrically connected and less than the height of the upper conductive layer 72 adjacent to the upper conductive layer 73 to which it is electrically connected; the height of the fourth upper conductive segment 44 is greater than the height of the upper conductive layer 74 to which it is electrically connected and less than the height of the upper conductive layer 73 adjacent to the upper conductive layer 74 to which it is electrically connected; and the height of the fifth upper conductive segment 45 is greater than the height of the upper conductive layer 75 to which it is electrically connected and less than the height of the upper conductive layer 74 adjacent to the upper conductive layer 75 to which it is electrically connected.

[0084] As used in this disclosure, when referring to lower conductive segments and lower insulating rings, the term "height" refers to the distance between the side of each lower conductive segment facing away from the substrate and the side of each lower insulating ring facing away from the substrate and the top surface of the substrate. When referring to upper conductive segments and upper insulating rings, the term "height" refers to the distance between the side of each upper conductive segment facing closer to the substrate and the side of each upper insulating ring facing closer to the substrate and the top surface of the stacked structure (i.e., the side where the chip is bonded).

[0085] FIG1B also shows that the heights of the first through fifth lower conductive segments gradually increase, while the heights of the first through fifth upper conductive segments gradually decrease, along the first direction X. However, in other exemplary embodiments, the heights of the first through fifth lower conductive segments may gradually decrease, while the heights of the first through fifth upper conductive segments may gradually increase, along the first direction X.

[0086] In an exemplary embodiment, the common connection region may be a common bit line region or a common word line region.

[0087] In an exemplary embodiment, the memory cell may be a 1T1C memory cell, a 2T0C memory cell, or a 2T1C memory cell.

[0088] The semiconductor structure provided by this application is particularly suitable for the device structure of the planar annular channel (PCAA) of three-dimensional DRAM.

[0089] Therefore, the present disclosure is particularly suitable for connecting the common bit lines of each layer of a 3D memory to both the device below the 3D memory (such as a memory chip) and the corresponding sense amplifiers in the device above the 3D memory (such as a bonding chip).

[0090] The semiconductor structure provided in the exemplary embodiment of the present disclosure is described above, assuming that the upper conductive layer group includes five conductive layers, the lower conductive layer group includes five conductive layers, and the number of through holes is five. However, it should be understood that in other exemplary embodiments of the present disclosure, the upper conductive layer group and the lower conductive layer group may also include more or fewer conductive layers.

[0091] The following further illustrates the technical solution of the present disclosure through the fabrication process of a semiconductor structure according to an exemplary embodiment of the present disclosure. The "patterning process" referred to in this exemplary embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this exemplary embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations herein. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film of a certain material formed on a substrate using a deposition or coating process. If the "thin film" does not require a patterning or photolithography process during the entire fabrication process, the "thin film" can also be referred to as a "layer." If the "thin film" also requires a patterning or photolithography process during the entire fabrication process, the "thin film" before the patterning process is referred to as a "thin film" and the "layer" after the patterning process is referred to as a "layer." The "layer" after the patterning or photolithography process contains at least one "pattern."

[0092] The manufacturing method of the present disclosure is explained below by taking a manufacturing process of a semiconductor structure for connecting a bit line of a three-dimensional memory to sense amplifiers (SA) disposed below and above the bit line as an example.

[0093] This exemplary manufacturing method may include the following steps:

[0094] S100: A stacked structure is formed on a substrate, wherein the stacked structure includes, stacked in sequence from bottom to top, a first lower insulating layer and a first lower sacrificial layer; a second lower insulating layer and a second lower sacrificial layer; ...; an nth lower insulating layer and an nth lower sacrificial layer; an isolation insulating layer; a first upper insulating layer and a first upper sacrificial layer; a second upper insulating layer and a second upper sacrificial layer; ...; and an nth upper insulating layer and an nth upper sacrificial layer, where n is a positive integer; the stacked structure has a preset common connection area and a preset storage unit area located on at least one side of the preset common connection area.

[0095] An exemplary step may include: alternately depositing insulating layer films and sacrificial layer films on a substrate 2 to form a stacked structure 1, the stacked structure 1 including, from bottom to top, a first lower insulating layer 101 and a first lower sacrificial layer 121, a second lower insulating layer 102 and a second lower sacrificial layer 122, a third lower insulating layer 103 and a third lower sacrificial layer 123, a fourth lower insulating layer 104 and a fourth lower sacrificial layer 124, a fifth lower insulating layer 105 and a fifth lower sacrificial layer 125, an isolation insulating layer 106, and a heat-insulating layer 107. 06, the first upper insulating layer 107 and the first upper sacrificial layer 126, the second upper insulating layer 108 and the second upper sacrificial layer 127, the third upper insulating layer 109 and the third upper sacrificial layer 128, the fourth upper insulating layer 110 and the fourth upper sacrificial layer 129, and the fifth upper insulating layer 111 and the fifth upper sacrificial layer 130; the stacked structure 1 has a preset common bit line area 100 and preset memory cell areas 200 and 300 located on both sides of the preset common bit line area 100, as shown in Figure 2.

[0096] In an exemplary embodiment, each insulating layer film and the sacrificial layer film may be deposited by using a chemical vapor deposition method, plasma enhanced chemical vapor deposition, atomic layer deposition (ALD), or the like.

[0097] In an exemplary embodiment, each insulating layer may be formed of an oxide insulating material, such as silicon dioxide (eg, SiO 2 ), which is convenient for large-area deposition.

[0098] In an exemplary embodiment, each sacrificial layer may be made of a nitride material, such as silicon nitride (SiN).

[0099] S200: forming a through hole.

[0100] An exemplary step may include: in the preset common bit line area 100, forming five equally spaced through holes along the extension direction Y of the preset common bit line area by photolithography and etching, namely the first through hole K1, the second through hole K2, the third through hole K3, the fourth through hole K4 and the fifth through hole K5, wherein the number of through holes is the same as the number of layers of the upper conductive layer or the lower conductive layer formed subsequently, as shown in Figures 3A and 3B.

[0101] In an exemplary embodiment, the orthographic projection of each through hole on a plane parallel to the substrate 2 may be in a shape such as a circle, an ellipse, a square, or a rectangle.

[0102] S300: forming a conductive column and an insulating ring.

[0103] Exemplary steps may include: depositing an insulating layer film around the inner sidewalls and bottom of each of the through holes by atomic layer deposition, anisotropically etching the insulating layer at the bottom and retaining only the insulating layer on the inner sidewalls of the through holes; continuing to deposit metal in each through hole by ALD; and finally leveling the upper surface of the stacked structure by CMP to form five conductive pillars 10 and five insulating rings 20, as shown in FIG4 .

[0104] In an exemplary embodiment, each conductive pillar may be made of a metal material such as tungsten.

[0105] In an exemplary embodiment, each insulating ring may be made of materials such as HfO 2 or Al 2 O 3 .

[0106] S400: Patterning a stacked structure, forming a second sub-stacked structure extending along the second direction in the preset common bit line area, forming a plurality of first sub-stacked structures extending along the first direction and terminating at the second sub-stacked structure in the preset memory cell area, and the plurality of first sub-stacked structures are arranged at intervals in the second direction.

[0107] Exemplary steps may include: etching the stacked structure by photolithography to form a second sub-stacked structure 1000 extending along the second direction Y in the preset common bit line area 100, and forming a plurality of first sub-stacked structures 2000 and 3000 extending along the first direction X and terminating at the second sub-stacked structure 1000 in the preset memory cell areas 200 and 300, wherein the plurality of first sub-stacked structures 2000 and 3000 are arranged at intervals in the second direction Y, as shown in FIG. 5 .

[0108] S500: replacing the material of each sacrificial layer in the stacked structure with a conductive material to form n conductive layers, so as to form a memory cell region of each layer in the first sub-stacked structure and a common bit line region of each layer in the second sub-stacked structure;

[0109] Exemplary steps may include: removing each sacrificial layer by etching to form a plurality of grooves; depositing metal conductive material into the plurality of grooves, etching away the metal on the side walls of the insulating layer, leaving only the metal between adjacent insulating layers, completing the replacement of the sacrificial layer material, and forming 10 conductive layers, namely, a first lower conductive layer 61, a second lower conductive layer 62, a third lower conductive layer 63, a fourth lower conductive layer 64, and a fifth lower conductive layer 65; a first upper conductive layer 71, a second upper conductive layer 72, a third upper conductive layer 73, a fourth upper conductive layer 74, and a fifth upper conductive layer 75, as shown in Figures 6A and 6B.

[0110] S600: removing a portion of each of the conductive pillars and each of the insulating rings.

[0111] Exemplary steps may include: removing a portion of the material of the conductive pillar and the insulating ring by etching, so that the conductive pillar and the insulating ring in each through hole have the same height, but the conductive pillars and the insulating rings in different through holes have different heights, the heights of the conductive pillars and the insulating rings in through hole K1 to through hole K5 gradually increase, and the upper part of the conductive pillar and the insulating ring in each through hole is empty, as shown in Figure 7.

[0112] S700: An exemplary step may include: depositing the same material as the conductive pillar into each through hole through an ALD process, and then leveling the upper surface of the stacked structure through a CMP process, as shown in FIG8 .

[0113] S800: forming lower insulating rings and lower conductive segments.

[0114] Exemplary steps may include: etching the conductive pillars in each through hole to different heights through a staircase process, so that the first lower insulating ring 11 in the through hole K1 has a height T1 and the first lower conductive segment 21 has a height H1; and similarly, the second lower insulating ring 12 in the through hole K2 has a height T2 and the second lower conductive segment 22 has a height H2; the third lower insulating ring 13 in the through hole K3 has a height T3 and the third lower conductive segment 23 has a height H3; the fourth lower insulating ring 14 in the through hole K4 has a height T4 and the fourth lower conductive segment 24 has a height H4; and the fifth lower insulating ring 15 in the through hole K5 has a height T5 and the fifth lower conductive segment 25 has a height H5, as shown in FIG. 9 .

[0115] Figure 9 shows that heights H1 to H5 gradually increase, and heights T1 to T5 gradually increase. However, in other exemplary embodiments, heights H1 to H5 may gradually decrease, and heights T1 to T5 may also gradually decrease; or, height H3 is the largest and gradually decreases toward both sides, i.e., H3 gradually decreases toward H1 and H3 gradually decreases toward H5; similarly, T3 gradually decreases toward T1 and T3 gradually decreases toward T5.

[0116] 9 also shows that the first lower conductive segment 21 is electrically connected only to the first lower conductive layer 61 , the second lower conductive segment 22 is electrically connected only to the second lower conductive layer 62 , the third lower conductive segment 23 is electrically connected only to the third lower conductive layer 63 , the fourth lower conductive segment 24 is electrically connected only to the fourth lower conductive layer 64 , and the fifth lower conductive segment 25 is electrically connected only to the fifth lower conductive layer 65 . That is, the lower conductive segments in each through hole are electrically connected only to one lower conductive layer and are electrically insulated from the other lower conductive layers by their respective lower insulating rings, thereby achieving electrical connection between the common bit lines of each layer and the corresponding sense amplifiers below.

[0117] S900: An exemplary step may include: depositing an insulating material film to fill each through-hole, and then leveling the upper surface of the stacked structure through a CMP process, as shown in FIG10 .

[0118] In an exemplary embodiment, each insulating material may be HfO 2 or Al 2 O 3 .

[0119] S1000: forming each insulating segment.

[0120] Exemplary steps may include: using a step process to etch the insulating layer in each through hole to different depths to form a first insulating segment 31 , a second insulating segment 32 , a third insulating segment 33 , a fourth insulating segment 34 and a fifth insulating segment 35 , as shown in FIG. 11 .

[0121] S1100: forming upper insulating rings.

[0122] Exemplary steps may include: depositing an insulating layer film around the inner sidewalls and bottom of each of the through holes by the ALD method, anisotropically etching the insulating layer at the bottom and retaining only the insulating layer on the inner sidewalls of the through holes; etching the insulating layer to expose the metal cross-section that needs to be connected, forming a first upper insulating ring 51, a second upper insulating ring 52, a third upper insulating ring 53, a fourth upper insulating ring 54 and a fifth upper insulating ring 55, as shown in Figure 12.

[0123] S1200: forming upper conductive segments.

[0124] An exemplary step may include: continuing to deposit metal conductive material on the metal cross-sections exposed in each through-hole in the aforementioned step, and leveling the upper surface of the stacked structure through a CMP process to form a first upper conductive segment 41, a second upper conductive segment 42, a third upper conductive segment 43, a fourth upper conductive segment 44, and a fifth upper conductive segment 45, as shown in FIG13 .

[0125] Figure 13 shows that the first upper conductive segment 41 is electrically connected only to the first upper conductive layer 71, the second upper conductive segment 42 is electrically connected only to the second upper conductive layer 72, the third upper conductive segment 43 is electrically connected only to the third upper conductive layer 73, the fourth upper conductive segment 44 is electrically connected only to the fourth upper conductive layer 74, and the fifth upper conductive segment 45 is electrically connected only to the fifth upper conductive layer 75. That is, the upper conductive segments in each through hole are electrically connected to only one upper conductive layer and are electrically insulated from the other upper conductive layers by their respective upper insulating rings, thereby achieving electrical connection between the common bit line of each layer and the corresponding sense amplifier above the bit line.

[0126] The method of the embodiment of the present disclosure can enable the common bit line in the memory cell array to be connected to the device located below the memory cell array, such as the SA on the memory array chip, and to be connected to the device located above the memory cell array, such as the SA in the binding chip.

[0127] In the embodiment of the present disclosure, lower conductive segment structures of different heights are formed on the side of the substrate below the memory array in a through-hole structure located in the common connection area of ​​the memory array, so that each lower conductive segment structure is electrically connected to each lower conductive layer of the corresponding memory array; at the same time, upper conductive segment structures of different heights are formed on the side of the chip above the memory array, so that each upper conductive segment structure is electrically connected to each upper conductive layer of the corresponding memory array, thereby being able to connect downward to the devices (such as the sense amplifier SA or the sub-word line driver SWD) located on the substrate below the memory array, and being able to connect upward to the devices (such as the sense amplifier SA or the sub-word line driver SWD) located on the bonding chip above the memory array. Such as sense amplifier SA or sub-word line driver SWD), it can also connect storage cells located on both sides of the common connection area, thereby enabling multiple SA and SWD devices to be placed in a distributed manner, and enabling these devices to be placed more evenly on the chip below the memory array or on the bound chip above the memory array, alleviating the pressure on the bound chip and significantly reducing the manufacturing difficulty and process cost of the three-dimensional device; or it can also reasonably allocate the number of peripheral devices placed on the chip below the memory array or on the bound chip above the memory array as needed, making the manufacturing process more flexible and enhancing the design flexibility and adaptability of the three-dimensional device product.

[0128] The exemplary embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising the following steps:

[0129] S1000: forming a stacked structure on a substrate, the stacked structure comprising a lower group of sacrificial layers and an upper group of sacrificial layers located above the lower group of sacrificial layers, the lower group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers and the lower group of sacrificial layers having the same number of layers, each sacrificial layer having a preset common connection region and a preset storage unit region located on at least one side of the preset common connection region;

[0130] S1100: forming a plurality of through holes arranged at intervals in the preset common connection area and along an extension direction of the preset common connection area, wherein the through holes penetrate the stacked structure, and the number of the through holes is equal to the number of layers of the lower group of sacrificial layers;

[0131] S1200: forming a conductive pillar and an insulating ring surrounding the conductive pillar in the through hole;

[0132] S1300: patterning the stacked structure so that the preset common connection region forms a common connection region and the preset memory cell region forms a memory cell region;

[0133] S1400: replacing the materials of the plurality of sacrificial layers with conductive materials to form corresponding lower and upper conductive layers;

[0134] S1500: forming conductive pillars and insulating rings with different heights in each through hole to form lower conductive segments and lower insulating rings, wherein one lower conductive segment is electrically connected to one conductive layer in the lower group of conductive layers;

[0135] S1600: forming the insulating segment on the lower conductive segment;

[0136] S1700: Conductive pillars and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and one upper conductive segment is electrically connected to one conductive layer in the upper group of conductive layers.

[0137] In an exemplary embodiment, step S1500 may include:

[0138] S1510: Depositing an insulating layer film on the inner sidewall and bottom surface of each through hole;

[0139] S1520: removing the insulating film on the bottom surface of the through hole to form an insulating ring located on the inner sidewall of the through hole;

[0140] S1530: depositing a conductive material in the through hole to form a conductive pillar;

[0141] S1540: removing part of the material of the insulating ring and the conductive pillar in the through hole to the same height, so that the height of the insulating ring and the conductive pillar in the through hole is less than the height of the conductive layer to be electrically connected to the lower conductive segment and is higher than the height of the next conductive layer adjacent to the conductive layer to be electrically connected to the lower conductive segment, so as to form the lower insulating ring and the preset lower conductive segment, and forming empty grooves of different heights in the through hole;

[0142] S1550: depositing a conductive material into the empty groove until the empty groove is filled;

[0143] S1560: Remove part of the conductive material in the empty groove so that the height of the preset lower conductive segment is greater than the height of the conductive layer to be electrically connected and less than the height of the upper conductive layer adjacent to the electrically connected conductive layer, so as to form the lower conductive segment, and one lower conductive segment is electrically connected to one conductive layer in the lower group of conductive layers.

[0144] In an exemplary embodiment, step S1700 may include:

[0145] S1710: Depositing an insulating layer film above the insulating segment in each through hole, and removing the insulating layer film on top of the insulating segment to form the upper insulating ring; wherein an end of the insulating ring close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer;

[0146] S1720: removing a portion of the insulating segment in the through hole so that an end of the insulating segment away from the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent next conductive layer;

[0147] S1730: Depositing a conductive material in the empty groove to form the upper conductive segment, and one upper conductive segment is electrically connected to one conductive layer in the upper group of conductive layers.

[0148] An exemplary embodiment of the present disclosure further provides a memory, comprising:

[0149] a substrate on which a plurality of first devices are disposed;

[0150] a lower conductive layer group located on the substrate and comprising a plurality of conductive layers stacked vertically in a spaced relationship;

[0151] an upper conductive layer group located above the lower conductive layer group and comprising a plurality of conductive layers stacked vertically and spaced apart from each other, wherein the upper conductive layer group and the lower conductive layer group have the same number of conductive layers, and each conductive layer has a common connection region and a memory cell region located on at least one side of the common connection region;

[0152] a bonding chip, which is located on the upper conductive layer and is provided with a plurality of second devices;

[0153] a plurality of through holes, which are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes passing through the plurality of conductive layers, and the number of the through holes is equal to the number of layers of the lower group of conductive layers;

[0154] A plurality of conductive pillars are provided, one conductive pillar is correspondingly arranged in one through hole, each conductive pillar includes a lower conductive segment and an upper conductive segment separated by an insulating segment, an end of a lower conductive segment away from the substrate is electrically connected to a conductive layer in the lower group of conductive layers, and an end close to the substrate is electrically connected to a first device; an end of an upper conductive segment away from the binding chip is electrically connected to a conductive layer in the upper group of conductive layers, and an end close to the binding chip is electrically connected to a second device.

[0155] In an exemplary embodiment, the common connection region is a common bit line region and the first device and the second device are both sense amplifiers, or the common connection region is a common word line region and the first device and the second device are both sub-word line drivers.

[0156] In an exemplary embodiment, the memory further includes a plurality of lower insulating rings and a plurality of upper insulating rings, wherein a lower insulating ring is correspondingly arranged in a through hole and surrounds the corresponding lower conductive segment, and a height of the lower insulating ring is less than a height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than a height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; an upper insulating ring is correspondingly arranged in a through hole and surrounds the corresponding upper conductive segment, and an end of the upper insulating ring close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer; the height of the lower conductive segment is greater than a height of the conductive layer to which it is electrically connected and less than a height of the previous conductive layer adjacent to the conductive layer to which it is electrically connected; and an end of the upper conductive segment close to the substrate is located between the conductive layer to which it is electrically connected and the adjacent next conductive layer.

[0157] Although the embodiments disclosed in the present disclosure are as described above, the above contents are merely examples or implementations adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a lower set of conductive layers, comprising a plurality of conductive layers stacked vertically in an interspaced relationship; An upper conductive layer group, which is located above the lower conductive layer group and includes a plurality of conductive layers stacked vertically and spaced apart from each other, the upper conductive layer group and the lower conductive layer group have the same number of layers, and each conductive layer has a common connection area and a storage cell area located at least on one side of the common connection area; A plurality of through holes are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes penetrate the upper conductive layer and the lower conductive layer, and the number of the through holes is equal to the number of layers of the lower conductive layer; A plurality of conductive pillars, one of the conductive pillars is correspondingly arranged in one of the through holes, each conductive pillar comprises a lower conductive segment and an upper conductive segment separated by an insulating segment, a lower conductive segment is correspondingly electrically connected to one of the conductive layers in the lower group of conductive layers, and an upper conductive segment is correspondingly electrically connected to one of the conductive layers in the upper group of conductive layers.

2. The semiconductor structure according to claim 1 further includes a plurality of lower insulating rings and a plurality of upper insulating rings, wherein a lower insulating ring is correspondingly arranged in a through hole and surrounds the corresponding lower conductive segment, and a height of the lower insulating ring is less than a height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than a height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; an upper insulating ring is correspondingly arranged in a through hole and surrounds the corresponding upper conductive segment, and an end of the upper insulating ring close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer.

3. The semiconductor structure according to claim 1, wherein: Along the extension direction of the common connection area, the height of the lower conductive segment in the through hole gradually increases, while the height of the upper conductive segment gradually decreases; or, the height of the lower conductive segment in the through hole gradually decreases, while the height of the upper conductive segment gradually increases.

4. The semiconductor structure according to claim 1, wherein: Along the extension direction of the common connection area, the distances between adjacent through holes are the same.

5. A memory comprising: a substrate on which a plurality of first devices are disposed; a lower conductive layer group located on the substrate and comprising a plurality of conductive layers stacked vertically in an interspaced relationship; an upper conductive layer group, which is located above the lower conductive layer group and includes a plurality of conductive layers stacked vertically and spaced apart from each other, wherein the upper conductive layer group and the lower conductive layer group have the same number of conductive layers, and each conductive layer has a common connection area and a storage cell area located at least on one side of the common connection area; A binding chip, which is located on the upper conductive layer and is provided with a plurality of second devices; A plurality of through holes, which are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes penetrate the plurality of conductive layers, and the number of the through holes is equal to the number of layers of the lower group of conductive layers; A plurality of conductive pillars, one conductive pillar is correspondingly arranged in one through hole, each conductive pillar comprises a lower conductive segment and an upper conductive segment separated by an insulating segment, one end of a lower conductive segment away from the substrate is electrically connected to a conductive layer in the lower conductive layer group and one end close to the substrate is electrically connected to a first device; one end of an upper conductive segment away from the binding chip is electrically connected to a conductive layer in the upper conductive layer group and one end close to the binding chip is electrically connected to a second device.

6. The memory according to claim 5, wherein: The common connection region is a common bit line region and the first device and the second device are both sense amplifiers, or the common connection region is a common word line region and the first device and the second device are both sub word line drivers.

7. The memory according to claim 5 further comprises a plurality of lower insulating rings and a plurality of upper insulating rings, wherein a lower insulating ring is correspondingly arranged in a through hole and surrounds the corresponding lower conductive segment, and a height of the lower insulating ring is less than a height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than a height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; an upper insulating ring is correspondingly arranged in a through hole and surrounds the corresponding upper conductive segment, and an end of the upper insulating ring close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent previous conductive layer; the height of the lower conductive segment is greater than a height of the conductive layer electrically connected to it and less than a height of the previous conductive layer adjacent to the conductive layer electrically connected to it; and an end of the upper conductive segment close to the substrate is located between the conductive layer electrically connected to it and the adjacent next conductive layer.

8. A method for manufacturing a semiconductor structure, comprising: Forming a stacked structure on a substrate, the stacked structure comprising a lower group of sacrificial layers and an upper group of sacrificial layers located above the lower group of sacrificial layers, the lower group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers and the lower group of sacrificial layers having the same number of layers, each sacrificial layer having a preset common connection area and a preset storage unit area located at least on one side of the preset common connection area; A plurality of through holes are formed in the preset common connection area and along the extension direction of the preset common connection area. The through holes penetrate the stacked structure, and the number of the through holes is equal to the number of layers of the lower group of sacrificial layers. forming a conductive column and an insulating ring surrounding the conductive column in the through hole; Patterning the stacked structure so that the preset common connection region forms a common connection region and the preset memory cell region forms a memory cell region; Replacing the materials of the plurality of sacrificial layers with conductive materials to form corresponding lower and upper conductive layers; Forming conductive pillars and insulating rings with different heights in each through hole to form lower conductive segments and lower insulating rings, and one lower conductive segment is electrically connected to one conductive layer in the lower conductive layer group; forming the insulating segment above the lower conductive segment; Conductive columns and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and one upper conductive segment is electrically connected to one conductive layer in the upper group of conductive layers.

9. The manufacturing method according to claim 8, wherein: Conductive columns and insulating rings with different heights are formed in each through hole to form lower conductive segments and lower insulating rings, and one lower conductive segment is electrically connected to one conductive layer in the lower conductive layer group, including: Depositing an insulating layer film on the inner sidewall and bottom surface of each through hole; Removing the insulating film on the bottom surface of the through hole to form an insulating ring located on the inner side wall of the through hole; depositing a conductive material in the through hole to form a conductive column; Removing part of the material of the insulating ring and the conductive pillar in the through hole to the same height, so that the height of the insulating ring and the conductive pillar in the through hole is less than the height of the conductive layer to be electrically connected to the lower conductive segment and is higher than the height of the next conductive layer adjacent to the conductive layer to be electrically connected to the lower conductive segment, so as to form the lower insulating ring and the preset lower conductive segment, and form empty grooves of different heights in the through hole; Depositing a conductive material into the empty groove until the empty groove is filled; Part of the conductive material in the empty groove is removed so that the height of the preset lower conductive segment is greater than the height of the conductive layer to be electrically connected and less than the height of the upper conductive layer adjacent to the electrically connected conductive layer, so as to form the lower conductive segment, and one lower conductive segment is electrically connected to one conductive layer in the lower group of conductive layers.

10. The manufacturing method according to claim 9, wherein: Conductive columns and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and one upper conductive segment is electrically connected to one conductive layer in the upper conductive layer group, including: Depositing an insulating layer film above the insulating segment in each through hole, and removing the insulating layer film on the top of the insulating segment to form the upper insulating ring; wherein one end of the insulating ring close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer; Removing part of the insulating segment in the through hole so that an end of the insulating segment away from the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent next conductive layer; Conductive material is deposited in the empty groove to form the upper conductive segments, and one upper conductive segment is electrically connected to one conductive layer in the upper group of conductive layers.

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