Level shift circuit, driving circuit and half-bridge circuit

Abstract

Disclosed in the present application are a level shift circuit, a driving circuit and a half-bridge circuit. The level shift circuit comprises: a first voltage-current conversion circuit, which is used for generating a set current signal on the basis of an input signal; a second voltage-current conversion circuit, which is used for generating a reset current signal on the basis of an inverted signal of the input signal; and a latch misoperation protection circuit, which is used for generating a set driving signal and a reset driving signal in a second voltage domain on the basis of the set current signal and the reset current signal, and providing the set driving signal and the reset driving signal to a latch circuit, wherein the latch misoperation protection circuit is further used for pulling up the set driving signal and the reset driving signal when common-mode noise has occurred, and quickly pulling down one of a set end and a reset end of the latch circuit on the basis of the state of an output signal, such that the output of the latch circuit remains in an original state, and thus noise and interference in the circuit can be suppressed when the common-mode noise has occurred, thereby avoiding false triggering of the latch circuit and improving the performance and reliability of the circuit.

Description

Level shift circuit, driver circuit and half-bridge circuit

[0001] This application claims priority to a Chinese invention application filed on September 20, 2023, with application number 2023112145068 and titled “Level shift circuit, drive circuit and half-bridge circuit”, and incorporates the entire specification, claims, drawings and abstract of the above-mentioned Chinese invention application into this application by reference. Technical Field

[0002] The present invention relates to the technical field of integrated circuits, and more particularly to a level shift circuit, a drive circuit and a half-bridge circuit. Background Art

[0003] With the rapid development of electronic power technology, especially the increasing use of high-frequency, self-shutoff components such as IGBTs and MOSFETs, driver circuit design has become crucial, especially for high-voltage integrated circuits (HVICs). A well-designed driver circuit ensures high-performance HVIC chips, including excellent system reliability and efficiency. HVICs are widely used in various consumer and industrial applications, including variable-frequency motor drives, switching power supplies, and electronic ballasts.

[0004] As a core component of driver chips, high-voltage level shifting circuits face significant performance challenges due to their transmission delay and reliability. In driver chips, level shifting is implemented using high-voltage LDMOS devices, which have a large parasitic capacitance (Cpar) between the drain and substrate. When common-mode noise (dV / dt) occurs, the presence of Cpar causes the output nodes of the level shifting circuit to fail to keep up with the transient transitions of the high-side floating power rail, resulting in glitches. High dV / dt levels can easily cause false triggering of subsequent circuits, resulting in erroneous outputs. This indicates that the level shifting circuit's common-mode transient immunity (CMTI) is insufficient. To improve the CMTI capability of the level shifting circuit, glitches caused by dV / dt noise need to be filtered out. Traditionally, this solution involves adding an RC filter circuit after the high-voltage level shifting circuit. However, this sacrifices the operating frequency of the driver chip, making it unsuitable for half-bridge driver chips.

[0005] In summary, traditional high-voltage level shift circuits have a contradictory and restrictive relationship among transmission delay, CMTI capability, and power consumption, making them unsuitable for use in high-speed, high-reliability half-bridge driver chips. Therefore, it is necessary to design a high-voltage level shift circuit that combines high speed, high reliability, and low power consumption. Summary of the Invention

[0006] In view of the above problems, the object of the present invention is to provide a level shift circuit, a driving circuit and a half-bridge circuit, which can suppress noise and interference in the circuit when common-mode noise occurs, avoid false triggering of the latch circuit, and improve the circuit's resistance to noise, thereby improving the performance and reliability of the circuit.

[0007] According to one aspect of the present invention, a level shift circuit is provided for converting an input signal in a first voltage domain into an output signal in a second voltage domain, comprising: a first voltage-to-current conversion circuit for receiving the input signal and generating a set current signal based on the input signal; a second voltage-to-current conversion circuit for receiving an inverted signal of the input signal and generating a reset current signal based on the inverted signal of the input signal; a latch malfunction protection circuit for receiving the set current signal through a first signal line and the reset current signal through a second signal line, and generating a set drive signal and a reset drive signal in the second voltage domain based on the set current signal and the reset current signal; a latch circuit having a set end for receiving the set drive signal and a reset end for receiving the reset drive signal, the latch circuit being configured to output a corresponding logic level when the set drive signal and the reset drive signal have different levels; and a shaping output circuit for providing the output signal according to the output of the latch circuit, wherein the latch malfunction protection circuit is further configured to set the set drive signal and the reset drive signal to the same level when common mode noise occurs, and then quickly pull down one of the set end and the reset end of the latch circuit according to the state of the output signal, so that the output of the latch circuit remains in its original state.

[0008] Optionally, the level shifting circuit also includes: a pulse generating circuit for generating a set pulse signal for controlling the on and off of the first voltage-to-current conversion circuit at the first edge of the input signal, and generating a reset pulse signal for controlling the on and off of the second voltage-to-current conversion circuit at the second edge of the input signal.

[0009] Optionally, the level shift circuit also includes: a current generating circuit for generating a current representing the initial state of the level shift circuit, wherein the first voltage-to-current conversion circuit includes: a first transistor, a first resistor, a first high-voltage transistor, a second transistor and a third transistor connected in series between the second power supply voltage of the second voltage domain and the first ground of the first voltage domain, the control end of the first high-voltage transistor is connected to the first power supply voltage of the first voltage domain, the control end of the second transistor is connected to the input signal, the second end of the second transistor is used to receive the set pulse signal, and the third transistor obtains the current of the current generating circuit by mirroring; and a fourth transistor, connected between the second power supply voltage and the first signal line, the fourth transistor and the first transistor constitute a current mirror to generate the set current signal by mirroring the current in the first transistor.

[0010] Optionally, the second voltage-to-current conversion circuit includes: a fifth transistor, a second resistor, a second high-voltage transistor, a sixth transistor and a seventh transistor connected in series between the second power supply voltage and the first ground, the control end of the second high-voltage transistor is connected to the first power supply voltage, the control end of the sixth transistor is connected to the inverted signal of the input signal, the second end of the sixth transistor is used to receive the reset pulse signal, and the seventh transistor obtains the current of the current generating circuit by mirroring; and an eighth transistor, connected between the second power supply voltage and the second signal line, the eighth transistor and the fifth transistor form a current mirror to generate the reset current signal by mirroring the current in the fifth transistor.

[0011] Optionally, the first voltage-to-current conversion circuit also includes: a first clamping diode connected between the two ends of the first transistor and a second clamping diode connected between the control end and the second end of the first high-voltage transistor; the second voltage-to-current conversion circuit also includes: a third clamping diode connected between the two ends of the fifth transistor and a fourth clamping diode connected between the control end and the second end of the second high-voltage transistor; wherein the current generating circuit includes: a third resistor and a ninth transistor connected in series between the first power supply voltage and the first ground; wherein the ninth transistor is connected to the third transistor and the seventh transistor in a current mirror manner.

[0012] Optionally, the latch malfunction protection circuit includes: a tenth transistor and an eleventh transistor connected to form a first cross-coupling structure; and a twelfth transistor and a thirteenth transistor connected to form a second cross-coupling structure, the tenth transistor and the twelfth transistor are connected in series between the second power supply voltage and the second ground of the second voltage domain, the eleventh transistor and the thirteenth transistor are connected in series between the second power supply voltage and the second ground, the control ends of the eleventh transistor and the thirteenth transistor are connected to the first node between the tenth transistor and the twelfth transistor, and the control ends of the tenth transistor and the twelfth transistor are connected to the second node between the eleventh transistor and the thirteenth transistor, wherein the first node is also used to be connected to the first signal line and the set end of the latch circuit, and the second node is also used to be connected to the second signal line and the reset end of the latch circuit.

[0013] Optionally, the latch malfunction protection circuit also includes: a fourth resistor connected between the first node and the second ground; a fifth resistor connected between the second power supply voltage and the second node, wherein the fourth resistor and the fifth resistor are used to provide an initial state for the latch circuit; a fourteenth transistor connected between the second node and the second ground, the control end of the fourteenth transistor is used to receive the in-phase signal of the output signal; and a fifteenth transistor connected between the first node and the second ground, the control end of the fifteenth transistor is used to receive the inverted signal of the output signal, wherein the fourteenth transistor and the fifteenth transistor are used to provide a positive feedback loop in the circuit according to the state of the output signal, so as to quickly pull down one of the set end and the reset end of the latch circuit when the common-mode noise occurs.

[0014] Optionally, the pulse generating circuit includes: a first pulse generating module for generating the set pulse signal according to the first edge of the input signal, and a second pulse generating module for generating the reset pulse signal according to the first edge of the inverted signal of the input signal, wherein the first pulse generating module and the second pulse generating module both include: a sixteenth transistor, a sixth resistor and a seventeenth transistor connected in series between the first power supply voltage of the first voltage domain and the first ground, the control terminals of the sixteenth transistor and the seventeenth transistor being connected to each other and used to receive the input signal or the inverted signal of the input signal, and the sixteenth transistor and the seventeenth transistor having opposite conduction types; a capacitor connected between a third node between the sixteenth transistor and the sixth resistor and the first ground; a NAND gate, whose first input terminal is used to receive the input signal or the inverted signal of the input signal, and whose second input terminal is connected to the third node; a first inverter, whose input terminal is connected to the output terminal of the NAND gate; a seventh resistor and an eighteenth transistor connected between the output terminal of the set / reset pulse signal and the first ground, and the control terminal of the eighteenth transistor is connected to the output terminal of the first inverter.

[0015] According to another aspect of the present invention, a driving circuit is provided for driving a high-side switching element and a low-side switching element in a half-bridge circuit, comprising: the above-mentioned level shifting circuit, wherein the level shifting circuit is used to convert a high-side control input signal in a first voltage domain into an output signal in a second voltage domain; a high-side driver, used to obtain a high-side driving signal according to the output signal of the level shifting circuit to control the on and off of the high-side switching element; and a low-side driver, used to obtain a low-side driving signal according to the low-side control input signal to control the on and off of the low-side switching element.

[0016] According to another aspect of the present invention, a half-bridge circuit is provided, comprising: an output circuit, comprising a high-side switching element and a low-side switching element connected in series, an input voltage supplying power to a load via the high-side switching element; and a driving circuit for driving the high-side switching element and the low-side switching element, comprising: the above-mentioned level shifting circuit, the level shifting circuit being used to convert a high-side control input signal in a first voltage domain into an output signal in a second voltage domain; a high-side driver, being used to obtain a high-side driving signal according to the output signal of the level shifting circuit to control the conduction and cutoff of the high-side switching element; and a low-side driver, being used to obtain a low-side driving signal according to the low-side control input signal to control the conduction and cutoff of the low-side switching element.

[0017] In summary, the embodiment of the present invention achieves strong common-mode noise resistance and high-speed signal transmission capabilities by adjusting the structure of the traditional level shift circuit. It uses a latch malfunction protection circuit to monitor whether the current change on the first signal line and the second signal line is generated according to the input signal. If the current change is generated according to the input signal, the latch malfunction protection circuit transmits the change on the first signal line and the second signal line to the latch circuit; if the current change is not generated according to the input signal, the latch malfunction protection circuit pulls up both the set terminal and the reset terminal of the latch circuit to prevent the state of the latch circuit from changing. Therefore, the level shift circuit of the embodiment of the present invention can suppress noise and interference in the circuit when common-mode noise occurs, avoid false triggering of the latch circuit, improve the circuit's resistance to noise, and thus improve the performance and reliability of the circuit. In addition, the level shift circuit of the embodiment of the present invention does not require a dedicated RC filter circuit to be set in the circuit, which is conducive to reducing the circuit area and reducing the circuit cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] FIG1 shows a schematic circuit diagram of a half-bridge circuit using a conventional level shift circuit.

[0020] FIG2 shows a schematic structural block diagram of a level shift circuit according to an embodiment of the present invention.

[0021] FIG3 shows a schematic circuit diagram of a level shift circuit according to an embodiment of the present invention.

[0022] FIG4 shows a schematic circuit diagram of a first pulse generating module of a level shift circuit according to an embodiment of the present invention.

[0023] FIG5 shows a schematic circuit diagram of a second pulse generating module of a level shift circuit according to an embodiment of the present invention.

[0024] FIG6 is a schematic circuit diagram of a latch malfunction protection circuit of a level shift circuit according to an embodiment of the present invention.

[0025] FIG7 shows a schematic circuit diagram of a half-bridge circuit using a level shift circuit according to an embodiment of the present invention.

[0026] 8A and 8B are schematic waveform diagrams respectively showing transmission delay of the level shift circuit according to an embodiment of the present invention.

[0027] 9A and 9B are schematic waveform diagrams showing the resistance of the level shift circuit to dv / dt noise according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0029] It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or subcircuit connected electrically or electromagnetically. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two elements.

[0030] 1 is a schematic circuit diagram of a half-bridge circuit using a conventional level shift circuit. As shown in FIG1 , the half-bridge circuit 100 includes an output circuit 110 , a high-side driving circuit 120 , and a low-side driving circuit 130 .

[0031] Output circuit 110 is composed of a high-side switching element XD1 and a low-side switching element XD2 connected in series. Input voltage VIN supplies power to load 101 via high-side switching element XD1. Load 101 receives voltage (power) from the half-bridge circuit. Load 101 is connected between a connection point HS (the potential of connection point HS is also referred to as connection point HS) between high-side switching element XD1 and low-side switching element XD2 and ground potential.

[0032] The high-side switch XD1 and the low-side switch XD2 complement each other in their on / off states, with one switching on when the other is off. To prevent circuit damage caused by a through-circuit between the high-side switch XD1 and the low-side switch XD2, a dead time is implemented to ensure that one switch is off for a period of time before the other switches on. When the low-side switch XD2 is on, the potential at the connection point HS is at ground potential. When the high-side switch XD1 is on, the potential at the connection point HS is at the input voltage VIN.

[0033] The high-side driver circuit 120 is connected to the gate terminal of the high-side switching element XD1. It consists of a level shift circuit, a high-side driver 123, a diode D0, and a capacitor C1. The level shift circuit, which includes the portion of the high-side driver circuit 120 excluding the high-side driver 123 and capacitor C1, comprises a shaping circuit 121, a latch circuit 122, a first voltage-to-current conversion circuit 124, and a second voltage-to-current conversion circuit 125.

[0034] The first voltage-current conversion circuit 124 is composed of a resistor R1 and a level-shift transistor HN1 connected in series, and outputs a level-shifted output signal Setdrn to the shaping circuit 121 via a first connection point Vx. The second voltage-current conversion circuit 125 is composed of a resistor R2 and a level-shift transistor HN2 connected in series, and outputs a level-shifted output signal Resdrn to the shaping circuit 121 via a second connection point Vy. The level-shift transistors HN1 and HN2 can be N-channel semiconductor switching elements.

[0035] A Set signal, serving as an input signal to the level shift circuit of the high-side driver circuit 120, is input to the gate of the level shift transistor HN1. A Reset signal, serving as an input signal to the level shift circuit of the high-side driver circuit 120, is input to the gate of the level shift transistor HN2. The Set signal instructs the start of the on-period (end of the off-period) of the high-side switch element XD1, while the Reset signal instructs the start of the off-period (end of the on-period) of the high-side switch element XD1.

[0036] The shaping circuit 121 is configured to input the level-shifted signals Setdrn and Resdrn, and output the two signals to both ends of the latch circuit 122 after shaping and filtering.

[0037] The latch circuit 122 receives an input of a signal from the shaping circuit 121 , and stores and outputs a value that is set or reset when the input is at a low level (L) or a high level (H).

[0038] The high-side driver 123 is connected to the high-side switch element XD1 and the latch circuit 122 , and outputs a signal HO according to an output of the latch circuit 122 , thereby controlling on and off of the high-side switch element XD1 .

[0039] Furthermore, the high-potential-side power supply terminals of the latch circuit 122 and the high-side driver 123 are connected to the floating power supply terminal HB of the high-side circuit, the anode of the diode D0 is connected to the power supply voltage VDD, and the cathode of the diode D0 is connected to the floating power supply terminal HB of the high-side circuit of the high-side driver circuit 120. The low-potential-side power supply terminals of the latch circuit 122 and the high-side driver 123 are connected to the connection point HS of the switching elements XD1 and XD2.

[0040] One end of each of the first voltage-current conversion circuit 124 and the second voltage-current conversion circuit 125 is connected to the floating power supply terminal HB of the high-side circuit of the high-side driving circuit 120 , and the other end thereof is connected to the common ground potential (VSS).

[0041] The level shift circuit further includes diodes D1 and D2. The anode of diode D1 is connected to the first connection point Vx, and the cathode of diode D1 is connected to the floating power supply terminal HB of the high-side circuit. The anode of diode D2 is connected to the second connection point Vy, and the cathode of diode D2 is connected to the floating power supply terminal HB of the high-side circuit.

[0042] The low-side driver circuit 130 includes a low-side driver 131 that controls the on / off state of the low-side switching element XD2. Its high-side power supply terminal is connected to the power supply voltage VDD, and its low-side power supply terminal is connected to the common ground potential (VSS). Low-side driver 131 receives a signal S that indicates whether to turn the low-side switching element XD2 on or off. It uses a cascaded inverter structure to amplify the current in each inverter stage to drive the gate of the low-side switching element XD2. Consequently, the low-side driver circuit 130 turns on the low-side switching element XD2 when the signal S input to the low-side driver 131 is high (H), and turns off the low-side switching element XD2 when the signal S is low (L).

[0043] When the input signal IN is at a low level (L), the low-side switch element XD2 is driven to turn on, the high-side switch element XD1 is turned off, and the connection point HS is pulled down to the common ground potential VSS. The low-voltage domain power supply voltage VDD charges the bootstrap capacitor C1 through the boost diode D0 and the low-side switch element XD2, and the voltage across capacitor C1 is close to the power supply voltage VDD. When the input signal IN changes from a low level to a high level, the input signal IN is converted into a set pulse signal Set by the logic circuit in the low-voltage domain. The set pulse signal Set is input to the input of the high-voltage level shift circuit to control the on and off of the level shift transistor HN1. When the input signal IN is at a high level, the set pulse signal Set is high, transistor HN1 is turned on, and transistor HN2 is turned off. The second connection point Vy is equal to the voltage HB of the high-voltage domain. The current when transistor HN1 is turned on generates a voltage drop Vdrop = HB-Idsat*R1 on resistor R1. This voltage drop is referenced to the floating voltage source HB. The voltage Vx of the first connection point After the voltage of HB-Vdrop falls into the floating voltage domain of the high side, it is recognized by the subsequent logic circuit. After being shaped by the shaping circuit 121, it is output to the two ends of the latch circuit 122. The latch circuit 122 outputs a high-level signal HO to control the high-side switch element XD1 to turn on. The high-side switch element XD1 generates a large current to charge the parasitic capacitance of the connection point HS, causing the connection point HS to quickly rise to the input voltage VIN. Because the voltage across the capacitor cannot change suddenly, the bootstrap capacitor C1 raises the voltage of the floating power supply terminal HB of the high-side circuit to VIN+VDD. At this time, the circuits on the high potential side are all powered by the bootstrap capacitor C1.

[0044] In conventional level-shift circuits, the switching action of a half-bridge circuit causes the connection point HS, which serves as the reference potential for the high-side circuit, to rapidly fluctuate from a low potential to a high potential or vice versa. This causes a phenomenon known as dV / dt noise (common-mode noise), in which the voltage within part (or all) of the high-side circuit fluctuates relative to the common ground potential (VSS). In high-voltage level-shift circuits, level shifting is implemented using high-voltage-resistant LDMOS devices, which have large drain-substrate parasitic capacitances, such as the parasitic capacitance Cpar1 of transistor HN1 and the parasitic capacitance Cpar2 of transistor HN2 in Figure 1. When common-mode noise dV / dt occurs, the large common-mode noise dV / dt generates a displacement current through the parasitic capacitances Cpar1 and Cpar2 of transistors HN1 and HN2. This current can cause a voltage drop across the series resistors R1 and R2, resulting in false trigger signals at the connection points Vx and Vy. When the common-mode noise dV / dt is large, it can easily pass through the shaping filter circuit and reach the latch circuit, causing the latch circuit to enter an uncertain operating state. This can lead to false triggering of subsequent latch circuits and produce erroneous outputs. This is the problem of insufficient common-mode transient noise immunity (CMTI) in traditional level shift circuits.

[0045] It can be seen from this that in traditional level shift circuits, the presence of dV / dt noise seriously threatens the reliability of high-voltage level shift circuits. False triggering can generally cause power transistors to shoot through, which may even burn out the device.

[0046] The present invention will be further described below with reference to the accompanying drawings and examples.

[0047] Figure 2 shows a schematic block diagram of a level shift circuit according to an embodiment of the present invention. As shown in Figure 2, the level shift circuit 200 of this embodiment is used to convert an input signal IN in a low-voltage domain into an output signal OUT in a high-voltage domain. The circuit includes a pulse generation circuit 210, a first voltage-to-current conversion circuit 220 (a first voltage-to-current conversion circuit, a second voltage-to-current conversion circuit), a second voltage-to-current conversion circuit 230, a latch malfunction protection circuit 240, a latch circuit 250, a shaping output circuit 260, a current generation circuit 270, and an inverter 280.

[0048] The pulse generating circuit 210 operates in a low voltage domain and is used to convert a low voltage input signal IN into a low voltage narrow pulse operating signal. For example, the pulse generating circuit 210 is used to receive the input signal IN and generate a pulse signal at each edge of the input signal IN or each time the input signal IN changes from one logic level to another. For example, the pulse generating circuit 210 can generate a set pulse signal Set in response to the input signal IN changing from a logic state of "0" to a logic state of "1", and generate a reset pulse signal Reset in response to the input signal IN changing from a logic state of "1" to a logic state of "0".

[0049] The first voltage-current conversion circuit 220 and the second voltage-current conversion circuit 230 are used to convert the low-voltage input signal IN into a current signal in the high-voltage domain and transmit it to the next-level circuit. Among them, the current generating circuit 270 is used to generate a current representing the initial state of the level shift circuit 200. The first voltage-current conversion circuit 220 and the second voltage-current conversion circuit 230 are respectively turned on at the rising edge and falling edge of the input signal IN, and when turned on, they convert the received input signal IN and the inverted signal INB of the input signal IN into corresponding current signals. For example, the first voltage-current conversion circuit 220 is controlled by the set pulse signal Set to turn on or off, and when turned on, it converts the input signal IN into a set current signal I_set. The second voltage-current conversion circuit 230 is controlled by the reset pulse signal Reset to turn on or off, and when turned on, it converts the inverted signal INB of the input signal obtained by the inverter 280 into a reset current signal I_res.

[0050] The latch malfunction protection circuit 240 is connected to the first voltage-current conversion circuit 220 and the second voltage-current conversion circuit 230 via a first signal line 201 and a second signal line 202, respectively. The circuit receives a set current signal I_set from the first voltage-current conversion circuit 220 via the first signal line 201 and a reset current signal I_res from the second voltage-current conversion circuit 230 via the second signal line 202. The latch malfunction protection circuit 240 is configured to convert the set current signal I_set and the reset current signal I_res into corresponding set drive signals Setdrn and reset drive signals Resdrn to set and reset the latch circuit 250.

[0051] The latch circuit 250 includes a set terminal for receiving the set drive signal Setdrn and a reset terminal for receiving the reset drive signal Resdrn. The latch circuit 250 is configured to output a high-voltage duty cycle signal based on the set drive signal Setdrn and the reset drive signal Resdrn. In this embodiment, the latch circuit 250 can generate corresponding logic changes based on voltage changes on the set drive signal Setdrn and the reset drive signal Resdrn. Furthermore, the latch circuit 250 of this embodiment only generates a logic change at its output terminal when the voltage at the set terminal differs from the voltage at the reset terminal. If the voltage at the set terminal and the reset terminal of the latch circuit 250 are the same (e.g., both are high), the output logic of the latch circuit 250 does not change.

[0052] In this embodiment, the latch malfunction protection circuit 240 is further configured to monitor whether current (or signal) changes on the first signal line 201 and the second signal line 202 are pulses generated in response to the input signal IN. If the latch malfunction protection circuit 240 determines that the signals on the first signal line 201 and the second signal line 202 are generated in response to the input signal IN, the latch malfunction protection circuit 240 transmits the signals to the latch circuit 250. If the latch malfunction protection circuit 240 determines that the signals on the first signal line 201 and the second signal line 202 are not generated in response to the input signal IN, the latch malfunction protection circuit 240 remains in its original state.

[0053] For example, at any given time (e.g., at the edge of the input signal IN), only one of the first voltage-to-current conversion circuit 220 and the second voltage-to-current conversion circuit 230 is enabled. That is, during normal operation, only one of the first signal line 201 and the second signal line 202 is flowing with current (or pulsed). In contrast, when common-mode noise occurs, the common-mode voltage generates current on both the first signal line 201 and the second signal line 202. Therefore, in an exemplary embodiment, the latch malfunction protection circuit 240 is configured to be high. When only one of the first signal line 201 and the second signal line 202 is flowing with current, the latch circuit 250 is generated based on the current signals on the first signal line 201 and the second signal line 202, thereby setting or resetting the latch circuit 250. Furthermore, the output logic of the latch circuit 250 can be changed in response to the set drive signal Setdrn and the reset drive signal Resdrn. When there are current signals on both the first signal line 201 and the second signal line 202, the latch malfunction protection circuit 240 sets the set drive signal Setdrn and the reset drive signal Resdrn to a high level, so the output of the latch circuit 250 remains in the previous logic state and its output does not change.

[0054] For example, when the input signal IN is at a high level, there is a current signal on the first signal line 201, and there is no current signal on the second signal line 202, the latch malfunction protection circuit 240 generates a set drive signal Setdrn at a high level based on the set current signal I_set on the first signal line 201, and the reset drive signal Resdrn is at a low level, and the output of the latch circuit 250 is a high level; and when the input signal IN is at a low level, there is no current signal on the first signal line 201, and there is a current signal on the second signal line 202, so the latch malfunction protection circuit 240 generates a set drive signal Setdrn at a low level based on the reset current signal I_res on the second signal line 202, and the reset drive signal Resdrn is at a high level, and the output of the latch circuit 250 changes to a low level. When common-mode noise occurs and current signals exist on both the first signal line 201 and the second signal line 202, the latch malfunction protection circuit 240 sets both the set drive signal Setdrn and the reset drive signal Resdrn to a high level, so the output of the latch circuit 250 remains in the previous logic state and its output does not change.

[0055] The shaped output circuit 260 is typically implemented using a digital inverter, a digital buffer, and / or a Schmitt trigger, and is used to shape and filter the high-voltage duty cycle signal output by the latch circuit 250, ultimately generating the high-voltage output signal OUT. Furthermore, the shaped output circuit 260 is also used to feed the output signal OUT back to the latch malfunction protection circuit 240, thereby forming a positive feedback loop. This prevents changes in the state of the output signal OUT when LCR resonance occurs in the high-voltage domain power supply due to common-mode noise.

[0056] FIG3 is a schematic circuit diagram of a level shift circuit according to an embodiment of the present invention. FIG4 through FIG6 are schematic circuit diagrams of a first pulse generating module, a second pulse generating module, and a latch malfunction protection circuit, respectively, within the level shift circuit according to an embodiment of the present invention. The level shift circuit according to an embodiment of the present invention will be described in detail below with reference to FIG3 through FIG6 .

[0057] In Figure 3, VCC1 represents the power supply voltage of the low-voltage domain (also called the low-side power supply voltage), VSS1 represents the ground of the low-voltage domain (also called the low-side ground), VCC2 represents the power supply voltage of the high-voltage domain (also called the high-side power supply voltage), and VSS2 represents the ground of the high-voltage domain (also called the high-side ground).

[0058] The pulse generating circuit 210 includes a first pulse generating module 211 , a second pulse generating module 212 and an inverter 213 .

[0059] The first pulse generating module 211 is used to generate a set pulse signal Set with a fixed time according to the rising edge of the input signal IN. Further, as shown in Figure 4, the first pulse generating module 211 includes a PMOS transistor MP5, NMOS transistors MN6 and MN7, a capacitor C1, resistors R4 and R5, a NAND gate 2110, and an inverter 2112. Among them, the PMOS transistor MP5, the resistor R4, and the NMOS transistor MN6 are connected in series between the low-side power supply voltage VCC1 and the low-side ground VSS1. The source of the PMOS transistor MP5 is connected to the low-side power supply voltage VCC1, the drain of the PMOS transistor MP5 is connected to the first end of the resistor R4, the second end of the resistor R4 is connected to the drain of the NMOS transistor MN6, the source of the NMOS transistor MN6 is connected to the low-side ground VSS1, and the gates of the PMOS transistor MP5 and the NMOS transistor MN6 are connected to the input signal IN. The first end of capacitor C1 is connected to the first end of resistor R4 and the drain of PMOS transistor MP5, while the second end of capacitor C1 is connected to low-side ground VSS1. One input of NAND gate 2110 is connected to input signal IN, and the other input is connected to the first end of capacitor C1. The input of inverter 2112 is connected to the output of NAND gate 2110, and the output of inverter 2112 is connected to the gate of NMOS transistor MN7. Resistor R5 and NMOS transistor MN7 are connected in series between the output of set pulse signal Set and low-side ground VSS1. The drain of NMOS transistor MN7 is connected to the end of resistor R5 farther from the output of set pulse signal Set, and the source of NMOS transistor MN7 is connected to low-side ground VSS1. When input signal IN is "0" (or a low level), PMOS transistor MP5 turns on and NMOS transistor MN6 turns off. The first end of capacitor C1 is at a high level, the output of inverter 2112 is at a low level, and NMOS transistor MN7 is turned off. When the input signal IN switches from "0" to "1" (also known as the input signal IN switches from a low level to a high level), the output of the inverter 2112 is inverted to a high level, the NMOS transistor MN7 is turned on, and at the same time the PMOS transistor MP5 is turned off, and the NMOS transistor MN6 is turned on. The capacitor C1 is discharged to the ground through the resistor R4 and the NMOS transistor MN6. When the upper terminal voltage of the capacitor C1 is lower than the flip threshold of the NAND gate 2110, the output of the inverter 2112 is flipped to a low level again, turning off the NMOS transistor MN7, so that a narrow pulse signal with a fixed time can be obtained at the output end of the set pulse signal Set.

[0060] Inverter 213 is used to generate an inverted signal INB of the input signal IN. Second pulse generation module 212 is used to generate a reset pulse signal Reset with a fixed duration based on the rising edge of inverted signal INB (corresponding to the falling edge of input signal IN). Furthermore, as shown in FIG5 , second pulse generation module 212 includes a PMOS transistor MP6, NMOS transistors MN8 and MN9, a capacitor C2, resistors R6 and R7, a NAND gate 2120, and an inverter 2121. PMOS transistor MP6, resistor R6, and NMOS transistor MN8 are connected in series between a low-side power supply voltage VCC1 and a low-side ground VSS1. The source of PMOS transistor MP6 is connected to the low-side power supply voltage VCC1, the drain of PMOS transistor MP6 is connected to the first end of resistor R6, the second end of resistor R6 is connected to the drain of NMOS transistor MN8, the source of NMOS transistor MN8 is connected to the low-side ground VSS1, and the gates of PMOS transistor MP6 and NMOS transistor MN8 are connected to the inverted input signal INB. A first end of capacitor C2 is connected to the first end of resistor R6 and the drain of PMOS transistor MP6, and a second end of capacitor C2 is connected to the low-side ground VSS1. One input of NAND gate 2120 is connected to the inverted input signal INB, and the other input is connected to the first end of capacitor C2. An input of inverter 2121 is connected to the output of NAND gate 2120, and the output of inverter 2121 is connected to the gate of NMOS transistor MN9. Resistor R7 and NMOS transistor MN9 are connected in series between the output terminal of the reset pulse signal Reset and the low-side ground VSS1. The drain of NMOS transistor MN9 is connected to the end of resistor R7 farther from the output terminal of the reset pulse signal Reset, and the source of NMOS transistor MN9 is connected to the low-side ground VSS1. When the inverted input signal INB is "0" (or a low level), PMOS transistor MP6 is turned on and NMOS transistor MN8 is turned off. The first terminal of capacitor C2 is at a high level, the output of inverter 2121 is at a low level, and NMOS transistor MN9 is turned off. When the inverted signal INB of the input signal switches from "0" to "1" (which can also be called the inverted signal INB of the input signal switches from a low level to a high level), the output of the inverter 2121 is inverted to a high level, the NMOS transistor MN9 is turned on, and at the same time the PMOS transistor MP6 is turned off, and the NMOS transistor MN8 is turned on. The capacitor C2 is discharged to ground through the resistor R6 and the NMOS transistor MN8. When the upper end voltage of the capacitor C2 is lower than the flip threshold of the NAND gate 2120, the output of the inverter 2121 is flipped to a low level again, turning off the NMOS transistor MN9. Finally, a narrow pulse signal with a fixed duration can be obtained at the output end of the reset pulse signal Reset.

[0061] Continuing with FIG3 , current generating circuit 270 includes a resistor R3 and an NMOS transistor MN5 connected in series between a low-side power supply voltage VCC1 and a low-side ground VSS1. A first end of resistor R3 is connected to the low-side power supply voltage VCC1, a second end of resistor R3 is connected to the drain and gate of NMOS transistor MN5, and a source of NMOS transistor MN5 is connected to the low-side ground VSS1. The current generated in resistor R3 by the low-side power supply voltage VCC1 is provided to the first voltage-to-current conversion circuit 220 and the second voltage-to-current conversion circuit 230 via the NMOS transistor MN5 in a current mirroring manner.

[0062] The first voltage-to-current conversion circuit 220 includes PMOS transistors MP1 and MP2 , a resistor R1 , a high-voltage NMOS transistor HN1 , NMOS transistors MN1 and MN3 , and diodes D1 and D3 . Among them, the PMOS transistor MP1, the resistor R1, the high-voltage NMOS transistor HN1, the NMOS transistor MN1, and the NMOS transistor MN3 are connected in series between the high-side power supply voltage VCC2 and the low-side ground VSS1. The source of the PMOS transistor MP1 is connected to the high-side power supply voltage VCC2. The gate and drain of the PMOS transistor MP1 are short-circuited together and connected to the first end of the resistor R1. The second end of the resistor R1 is connected to the drain of the high-voltage NMOS transistor HN1. The gate of the high-voltage NMOS transistor HN1 is connected to the low-side power supply voltage VCC1. The source of the high-voltage NMOS transistor HN1 is connected to the drain of the NMOS transistor MN1. The gate of the NMOS transistor MN1 is connected to the input signal IN. The source of the NMOS transistor MN1 is connected to the drain of the NMOS transistor MN3 and the set pulse signal Set. The gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN5 in the current generating circuit 270. The source of the NMOS transistor MN3 is connected to the low-side ground VSS1. The NMOS transistors MN3 and MN5 form a current mirror to obtain the current generated by the current generating circuit 270 through mirroring. Furthermore, the source of the PMOS transistor MP2 is connected to the high-side power supply voltage VCC2, the gate of the PMOS transistor MP2 is connected to the gate and drain of the PMOS transistor MP1, and the drain of the PMOS transistor MP2 is used to provide the set current signal I_set. The cathode of the diode D1 is connected to the source of the PMOS transistor MP1, and the anode of the diode D1 is connected to the drain of the PMOS transistor MP1. The cathode of the diode D3 is connected to the gate of the high-voltage NMOS transistor HN1, and the anode of the diode D3 is connected to the source of the high-voltage NMOS transistor HN1.

[0063] In this embodiment, diode D1 clamps the gate-source voltage VGS of PMOS transistor MP1. Diode D3 clamps the drain voltage of NMOS transistor MN1 to VCC1 + 0.7V when NMOS transistor MN1 is off, protecting NMOS transistor MN1 and high-voltage NMOS transistor HN1 from damage. High-voltage NMOS transistor HN1 is responsible for absorbing most of the high-voltage drop in first voltage-to-current conversion circuit 220 during normal operation, protecting the low-voltage transistors in first voltage-to-current conversion circuit 220. Resistor R1 limits the current in the branch circuit when first voltage-to-current conversion circuit 220 is on. When the input signal IN changes from logic state "0" to "1" (or the input signal IN changes from low level to high level), the NMOS transistor MN7 in the first pulse generating module 211 is turned on, generating a valid set pulse signal Set. The pulse signal Set pulls down the source of the NMOS transistor MN1 so that the NMOS transistor MN1 is turned on for a fixed time, which is determined by the set pulse signal Set. Then, a current is generated in the first voltage-current conversion circuit 220, flowing from the high-side power supply voltage VCC2 through the PMOS transistor MP1, the resistor R1, the high-voltage NMOS transistor HN1, the NMOS transistor MN1, the resistor R5 and the NMOS transistor MN7 to the low-side ground VSS1, and then the current in the PMOS transistor MP1 is mirrored through the PMOS transistor MP2, thereby generating the set current signal I_set and flowing into the latch malfunction protection circuit 240 through the first signal line 201.

[0064] The second voltage-to-current conversion circuit 230 includes PMOS transistors MP3 and MP4 , a resistor R2 , a high-voltage NMOS transistor HN2 , NMOS transistors MN2 and MN4 , and diodes D2 and D4 . Among them, the PMOS transistor MP4, the resistor R2, the high-voltage NMOS transistor HN2, the NMOS transistor MN2, and the NMOS transistor MN4 are connected in series between the high-side power supply voltage VCC2 and the low-side ground VSS1. The source of the PMOS transistor MP4 is connected to the high-side power supply voltage VCC2. The gate and drain of the PMOS transistor MP4 are short-circuited together and connected to the first end of the resistor R2. The second end of the resistor R2 is connected to the drain of the high-voltage NMOS transistor HN2. The gate of the high-voltage NMOS transistor HN2 is connected to the low-side power supply voltage VCC1. The source of the high-voltage NMOS transistor HN2 is connected to the drain of the NMOS transistor MN2. The gate of the NMOS transistor MN2 is connected to the inverted signal INB of the input signal. The source of the NMOS transistor MN2 is connected to the drain of the NMOS transistor MN4 and the reset pulse signal Reset. The gate of the NMOS transistor MN4 is connected to the gate of the NMOS transistor MN5 in the current generating circuit 270. The source of the NMOS transistor MN4 is connected to the low-side ground VSS1. The NMOS transistors MN4 and MN5 form a current mirror to obtain the current generated by the current generating circuit 270 through mirroring. Furthermore, the source of the PMOS transistor MP3 is connected to the high-side power supply voltage VCC2, the gate of the PMOS transistor MP3 is connected to the gate and drain of the PMOS transistor MP4, and the drain of the PMOS transistor MP3 is used to provide the reset current signal I_res. The cathode of the diode D2 is connected to the source of the PMOS transistor MP4, and the anode of the diode D2 is connected to the drain of the PMOS transistor MP4. The cathode of the diode D4 is connected to the gate of the high-voltage NMOS transistor HN2, and the anode of the diode D4 is connected to the source of the high-voltage NMOS transistor HN2.

[0065] Similarly, diode D2 clamps the gate-source voltage VGS of PMOS transistor MP4. When NMOS transistor MN2 is turned off, diode D4 clamps the drain voltage of NMOS transistor MN2 to VCC1 + 0.7V, protecting NMOS transistor MN2 and high-voltage NMOS transistor HN2 from damage. High-voltage NMOS transistor HN2 absorbs most of the high-voltage drop in first voltage-to-current conversion circuit 220 during normal operation, protecting the low-voltage transistors in first voltage-to-current conversion circuit 220. Resistor R2 limits the current in the branch when second voltage-to-current conversion circuit 230 is turned on. When the input signal IN changes from a logic state of "1" to a logic state of "0" (or the input signal IN changes from a high level to a low level), the inverted signal INB of the input signal changes from a logic state of "0" to a logic state of "1" (or the inverted signal INB of the input signal changes from a low level to a high level), and the NMOS transistor MN9 in the second pulse generating module 212 is turned on, generating a valid reset pulse signal Reset. The pulse signal Reset pulls down the source of the NMOS transistor MN2 so that the NMOS transistor MN2 is turned on for a fixed time determined by the reset pulse signal Reset. Subsequently, a current is generated in the second voltage-to-current conversion circuit 230, flowing from the high-side power supply voltage VCC2 through the PMOS transistor MP4, the resistor R2, the high-voltage NMOS transistor HN2, the NMOS transistor MN2, the resistor R7, and the NMOS transistor MN9 to the low-side ground VSS1. The current is then mirrored by the PMOS transistor MP3 in the PMOS transistor MP4, thereby generating the reset current signal I_res, which flows through the second signal line 202 into the latch malfunction protection circuit 240.

[0066] As previously described, the latch malfunction protection circuit 240 converts the set current signal I_set and the reset current signal I_res into a set drive signal Setdrn and a reset drive signal Resdrn based on current changes on the first signal line 201 and the second signal line 202. In an exemplary embodiment, the latch circuit 250 is implemented, for example, by an RS flip-flop, wherein the set terminal S is used to receive the set drive signal Setdrn, and the reset terminal R is used to receive the reset drive signal Resdrn. The latch circuit 250 generates a corresponding logic output at the output terminal Q based on voltage changes at the set terminal S and the reset terminal R.

[0067] The shaped output circuit 260 comprises four cascaded inverters 261-264. The input of the first inverter 261 is connected to the output Q of the latch circuit 250, and the output of the last inverter 263 is used to output the high-voltage output signal OUT. Furthermore, the outputs of inverters 262 and 263 are connected to the latch malfunction protection circuit 240, providing the latch malfunction protection circuit 240 with the in-phase signal OU1 and the inverted signal OUT2 of the output signal OUT, thereby forming a positive feedback loop within the circuit.

[0068] 6 , the latch malfunction protection circuit 240 of this embodiment includes resistors R8 and R9, PMOS transistors MP7 and MP8 forming a first cross-coupling structure, and NMOS transistors MN10 and MN11 forming a second cross-coupling structure. The PMOS transistors MP7 and MN10 are disposed between a high-side power supply voltage VCC2 and a high-side ground VSS2, while the PMOS transistors MP8 and MN11 are disposed between the high-side power supply voltage VCC2 and the high-side ground VSS2. The sources of the PMOS transistors MP7 and MP8 are connected to the high-side power supply voltage VCC2, the drains of the PMOS transistors MP7 and MP8 are connected to the drains of the NMOS transistors MN10 and MN11, respectively, and the sources of the NMOS transistors MN10 and MN11 are connected to the high-side ground VSS2. In this embodiment, the PMOS transistors MP7 and MP8 and the NMOS transistors MN10 and MN11 are coupled in a bistable configuration, wherein the gate of the PMOS transistor MP7 or MP8 is connected to the drain of the PMOS transistor MP8 or MP7 at a node 204 or 203, respectively, and the gate of the NMOS transistor MN10 or MN11 is connected to the drain of the NMOS transistor MN11 or MN10 at a node 204 or 203, respectively. Furthermore, the nodes 203 and 204 are also the nodes at which the first signal line 201 and the second signal line 202 are connected to the latch malfunction protection circuit 240, and the nodes at which the set terminal S and the reset terminal R of the latch circuit 250 are connected.

[0069] Resistor R8 is provided between node 203 and the high-side ground VSS2, and resistor R9 is provided between the high-side power supply voltage VCC2 and node 204. Resistors R8 and R9 are used to provide an initial state for latch circuit 250. When no current flows into latch malfunction protection circuit 240, resistor R8 pulls node 203 (also known as the set terminal S of latch circuit 250) low, and resistor R9 pulls node 204 (also known as the reset terminal R of latch circuit 250) high, causing latch circuit 250 to output a logic-low high-voltage duty cycle signal at output terminal Q.

[0070] Furthermore, latch malfunction protection circuit 240 further includes NMOS transistors MN12 and MN13. NMOS transistor MN12 is disposed between node 204 and high-side ground VSS2, while NMOS transistor MN13 is disposed between node 203 and high-side ground VSS2. The gates of NMOS transistors MN12 and MN13 receive the in-phase signal OUT1 and the inverted signal OUT2 of the output signal OUT, respectively, and provide positive feedback to the circuit during operation.

[0071] The operating principle of the level shift circuit according to an embodiment of the present invention will be described below with reference to Figures 3 and 6. As previously described, when there are no current pulses in the first voltage-to-current conversion circuit 220 and the second voltage-to-current conversion circuit 230, resistors R8 and R9 in the latch malfunction protection circuit 240 provide an initial state for the latch circuit 250, pulling the set terminal S of the latch circuit 250 low and the reset terminal R high, causing the latch circuit 250 to output a low-level logic signal. When the input signal IN is in the logic state "1", a current pulse is generated in the first signal line 201. At this time, the current in the PMOS transistor MP7 is greater than the saturation current of the NMOS transistors MN10 and MN13, and the initial state of the latch circuit is broken. At this time, the NMOS transistor MN11 and the PMOS transistor MP7 operate in the deep linear region, and the NMOS transistor MN10 and the PMOS transistor MP8 operate in the turn-off region. At this time, the set drive signal Setdrn pulls up the set terminal S of the latch circuit 250, and the reset drive signal Resdrn pulls down the reset terminal R of the latch circuit 250. The output terminal Q of the latch circuit 250 outputs a high-level signal. After passing through the shaping output circuit 260, the output signal OUT is high. When the input signal IN is in the logic state "0", a current pulse is generated in the second signal line 202. At this time, the current in the PMOS transistor MP8 is greater than the saturation current of the NMOS transistors MN11 and MN12. At this time, the NMOS transistor MN10 and the PMOS transistor MP8 operate in the deep linear region, and the NMOS transistor MN11 and the PMOS transistor MP7 operate in the shutdown region. At this time, the reset drive signal Resdrn pulls the reset terminal R of the latch circuit 250 high, and the set drive signal Setdrn pulls the set terminal S of the latch circuit 250 low. The output terminal Q of the latch circuit 250 outputs a low-level signal. After passing through the shaping output circuit 260, the output signal OUT is obtained as a low-level signal.

[0072] FIG7 shows a schematic circuit diagram of a half-bridge circuit employing a level shifting circuit according to an embodiment of the present invention. In this embodiment, half-bridge circuit 300 may be part of or correspond to a switching power converter. As shown in FIG7 , half-bridge circuit 300 includes an output circuit 310 and a drive circuit 320.

[0073] Output circuit 310 is composed of a high-side switching element XD1 and a low-side switching element XD2 connected in series. Input voltage VIN supplies power to load 101 via high-side switching element XD1. Load 101 receives voltage (power) from the half-bridge circuit. Load 101 is connected between a connection point HS (the potential of connection point HS is also referred to as connection point HS) between high-side switching element XD1 and low-side switching element XD2 and ground potential.

[0074] The high-side switch XD1 and the low-side switch XD2 complement each other in their on / off states, with one switching on when the other is off. To prevent circuit damage caused by a through-circuit between the high-side switch XD1 and the low-side switch XD2, a dead time is implemented to ensure that one switch is off for a period of time before the other switches on. When the low-side switch XD2 is on, the potential at the connection point HS is at ground potential. When the high-side switch XD1 is on, the potential at the connection point HS is at the input voltage VIN.

[0075] The driver circuit 320 includes a high-side driver circuit consisting of a level shifter circuit 321, a high-side driver 322, a diode D0, and a bootstrap capacitor Cbst. Furthermore, the driver circuit 320 includes an externally supplied power supply terminal VDD, a low-side power supply terminal VCC1, a high-side power supply terminal VCC2, a low-side ground terminal VSS1, a control input terminal HSIN for the high-side driver circuit, a control input terminal LSIN for the low-side driver circuit, a floating power supply terminal HB for the high-side circuit, a floating ground terminal HS for the high-side circuit, a driver output terminal HO for the high-side circuit, and a driver output terminal LO for the low-side circuit.

[0076] The level shift circuit 321 can be implemented using the level shift circuit 200 in the above-described embodiment. A first power supply terminal of the level shift circuit 321 is connected to the low-side power supply terminal VCC1, a second power supply terminal of the level shift circuit 321 is connected to the high-side power supply terminal VCC2, a first ground terminal of the level shift circuit 321 is connected to the low-side ground terminal, and a second ground terminal of the level shift circuit 321 is connected to the floating ground HS of the high-side circuit. The input of the level shift circuit 321 is connected to the control input terminal HSIN, and a high-voltage output signal is generated based on the low-voltage signal at the control input terminal HSIN. The input of the high-side driver 322 is connected to the output of the level shift circuit 321, and an output signal HO is generated based on the output of the level shift circuit 321, thereby controlling the on / off state of the high-side switch element XD1.

[0077] The drive circuit 320 also includes a low-side driver 323 for controlling the on / off state of the low-side switch element XD2. The high-side power supply terminal of the low-side driver 323 is connected to the low-side power supply terminal VCC1, and the low-side power supply terminal is connected to the low-side ground terminal VSS1. The low-side driver 323 is configured to amplify a signal LSIN indicating whether the low-side switch element XD2 should be turned on or off, and output the signal to the gate of the low-side switch element XD2, thereby controlling the on / off state of the low-side switch element XD2.

[0078] In this embodiment, the half-bridge driver circuit 320 has a power supply VDD on the low-voltage side to power the circuit. This power supply VDD provides a stable floating power supply HB to the high-voltage side via diode D0 and bootstrap capacitor Cbst. The principle is as follows: when the high-side switch XD1 is off, the high-side floating ground HS is at ground level, and the power supply VDD charges the bootstrap capacitor Cbst, with HB = VDD. When the high-side switch XD1 is on, the high-side floating ground HS is raised to the input voltage VIN, with the high-side floating power supply HB = VDD + VIN. The voltage difference between the high-side floating power supply HB and the power supply VDD is absorbed by diode D0. The floating high-voltage power rail is used to power certain circuits within the half-bridge driver circuit 320. HS serves as the high-voltage floating ground, and HB serves as the high-voltage floating power supply.

[0079] The following describes the common-mode noise protection principle of the level shift circuit according to an embodiment of the present invention in conjunction with Figures 3 to 7. When the signal at the control input terminal HSIN (i.e., the aforementioned input signal IN) is high, the level shift circuit 321 outputs a high-level signal, driving the high-side switch element XD1 to conduct. At the moment the high-side switch element XD1 is turned on, the noise of the high-voltage floating ground HS is coupled to the high-side power supply terminal VCC2 through the bootstrap capacitor Cbst. The voltage on the high-side power supply terminal VCC2 is respectively applied to the parasitics of the high-voltage NMOS transistors HN1 and HN2 through the PMOS transistor MP1 and the resistor R1, and the PMOS transistor MP4 and the resistor R2. The capacitors Cpar1 and Cpar2 are charged, and then a current pulse is generated simultaneously on the first signal line 201 and the second signal line 202. The current pulse is much larger than the saturation current of the NMOS transistors MN10 and MN11 in the latch malfunction protection circuit 240, so that the PMOS transistors MP7 and MP8 are turned off, so that the set terminal S and the reset terminal R of the latch circuit 250 are both high level, so that the output of the latch circuit 250 does not change, thereby suppressing the change of the output of the level shift circuit and avoiding the misoperation of the circuit.

[0080] In addition, since the high-side power supply terminal VCC2 is in an LCR resonance state at the moment when the high-side switch element XD1 is turned on, when the high-side power supply terminal VCC2 resonates upward to the highest point and then begins to resonate downward, at this time, the capacitors Cpar1 and Cpar2 discharge through the parasitic capacitance of the PMOS transistors MP1 and MP4 and the diodes D1 and D2, so that the PMOS transistors MP1, MP2, MP7, MP8, MP3 and MP4 are all in the off state, and the latch malfunction protection circuit 240 cannot work normally. At this time, the NMOS transistors MN12 and MN13 start to play a role. When the voltage When the output of the level shift circuit 321 is at a high level, the NMOS transistor MN12 is turned on and the NMOS transistor MN13 is turned off. The NMOS transistor MN12 quickly pulls down the reset terminal R of the latch circuit 250. At this time, the output of the latch circuit 250 can still be maintained at a high level, avoiding the occurrence of false triggering of the output of the level shift circuit. At the same time, the NMOS transistor MN12 can also turn on the PMOS transistor MP7 and the NMOS transistor MN11, and turn off the PMOS transistor MP8 and the NMOS transistor MN10, so that the latch malfunction protection circuit 240 starts working again. When the output of the level shift circuit 321 is at a low level, the NMOS transistor MN13 is turned on and the NMOS transistor MN12 is turned off. The NMOS transistor MN13 quickly pulls down the set terminal S of the latch circuit 250. At this time, the output of the latch circuit 250 can still be maintained at a low level, thereby avoiding false triggering of the level shift circuit. At the same time, the NMOS transistor MN13 can also turn on the PMOS transistor MP8 and the NMOS transistor MN10, so that the latch malfunction protection circuit 240 can resume operation.

[0081] Figures 8A and 8B respectively illustrate schematic waveform diagrams of the transmission delay of a level shift circuit according to an embodiment of the present invention. Figure 8A shows the waveform of the output signal OUT of the level shift circuit according to an embodiment of the present invention when a rising edge of the input signal IN occurs, and Figure 8B shows the waveform of the output signal OUT of the level shift circuit according to an embodiment of the present invention when a falling edge of the input signal IN occurs. The abscissa represents time (ms), and the ordinate represents voltage (V). As shown in Figures 8A and 8B, the level shift circuit according to an embodiment of the present invention has a very fast transmission speed. In an exemplary embodiment, the transmission speed of the level shift circuit according to the present invention for the rising edge of the input signal IN is 2.86 ns, and the transmission speed for the falling edge of the input signal IN is 2.97 ns.

[0082] Figures 9A and 9B respectively illustrate schematic waveform diagrams of the level shifter circuit's immunity to dv / dt noise (common-mode noise) according to an embodiment of the present invention. Figures 9A and 9B test the common-mode noise immunity of the level shifter circuit according to an embodiment of the present invention. When the rising rate of the high-voltage floating ground HS is 50V / ns, the high-side output signal HO of the driver circuit employing the level shifter circuit according to an embodiment of the present invention maintains a normal output waveform.

[0083] In summary, the embodiment of the present invention achieves strong common-mode noise resistance and high-speed signal transmission capabilities by adjusting the structure of the traditional level shift circuit. It uses a latch malfunction protection circuit to monitor whether the current change on the first signal line and the second signal line is generated according to the input signal. If the current change is generated according to the input signal, the latch malfunction protection circuit transmits the change on the first signal line and the second signal line to the latch circuit; if the current change is not generated according to the input signal, the latch malfunction protection circuit pulls up both the set terminal and the reset terminal of the latch circuit to prevent the state of the latch circuit from changing. Therefore, the level shift circuit of the embodiment of the present invention can suppress noise and interference in the circuit when common-mode noise occurs, avoid false triggering of the latch circuit, improve the circuit's resistance to noise, and thus improve the performance and reliability of the circuit. In addition, the level shift circuit of the embodiment of the present invention does not require a dedicated RC filter circuit to be set in the circuit, which is conducive to reducing the circuit area and reducing the circuit cost.

[0084] Furthermore, the level shift circuit of the present invention uses narrow pulses to control the first and second voltage-to-current conversion circuits to convert low-voltage input signals into high-voltage current signals. This circuit exhibits significant drive capability and can rapidly achieve level shifting, thereby increasing the circuit's operating frequency and transmission speed. Furthermore, the narrow pulse drive method of the present invention allows the first and second voltage-to-current conversion circuits to operate for a short period of time, thereby reducing circuit power consumption.

[0085] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0086] The embodiments of the present invention are described above, but these embodiments do not describe all details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A level shift circuit, for converting an input signal in a first voltage domain into an output signal in a second voltage domain, comprising: A first voltage-to-current conversion circuit, used for receiving the input signal and generating a set current signal according to the input signal; a second voltage-to-current conversion circuit, configured to receive an inverted signal of the input signal and generate a reset current signal according to the inverted signal of the input signal; a latch malfunction protection circuit, configured to receive the set current signal through a first signal line, and receive the reset current signal through a second signal line, and generate a set drive signal and a reset drive signal in the second voltage domain according to the set current signal and the reset current signal; a latch circuit having a set end for receiving the set drive signal and a reset end for receiving the reset drive signal, wherein the latch circuit is used to output corresponding logic levels when the set drive signal and the reset drive signal have different levels; as well as a shaping output circuit, used for providing the output signal according to the output of the latch circuit, Among them, the latch malfunction protection circuit is also used to set the set drive signal and the reset drive signal to the same level when common mode noise occurs, and then quickly pull down one of the set end and the reset end of the latch circuit according to the state of the output signal, so that the output of the latch circuit remains in its original state.

2. The level shift circuit according to claim 1, further comprising: A pulse generating circuit is used to generate a set pulse signal for on / off control of the first voltage-to-current conversion circuit at a first edge of the input signal, and to generate a reset pulse signal for on / off control of the second voltage-to-current conversion circuit at a second edge of the input signal.

3. The level shift circuit according to claim 2, further comprising: a current generating circuit, used to generate a current representing an initial state of the level shifting circuit, Wherein, the first voltage-to-current conversion circuit comprises: a first transistor, a first resistor, a first high-voltage transistor, a second transistor, and a third transistor connected in series between a second power supply voltage of the second voltage domain and a first ground of the first voltage domain, wherein a control terminal of the first high-voltage transistor is connected to the first power supply voltage of the first voltage domain, a control terminal of the second transistor is connected to the input signal, a second terminal of the second transistor is used to receive the set pulse signal, and the third transistor obtains the current of the current generating circuit by mirroring; and A fourth transistor is connected between the second power supply voltage and the first signal line, and the fourth transistor and the first transistor form a current mirror to generate the set current signal by mirroring the current in the first transistor.

4. The level shift circuit according to claim 3, wherein: The second voltage-to-current conversion circuit comprises: a fifth transistor, a second resistor, a second high-voltage transistor, a sixth transistor, and a seventh transistor connected in series between the second power supply voltage and the first ground, wherein a control end of the second high-voltage transistor is connected to the first power supply voltage, a control end of the sixth transistor is connected to an inverted signal of the input signal, a second end of the sixth transistor is used to receive the reset pulse signal, and the seventh transistor obtains the current of the current generating circuit by mirroring; and An eighth transistor is connected between the second power supply voltage and the second signal line, and the eighth transistor and the fifth transistor form a current mirror to generate the reset current signal by mirroring the current in the fifth transistor.

5. The level shift circuit according to claim 4, wherein: The first voltage-to-current conversion circuit also includes: a first clamping diode connected between two ends of the first transistor and a second clamping diode connected between a control end and a second end of the first high-voltage transistor, The second voltage-to-current conversion circuit also includes: a third clamping diode connected between the two ends of the fifth transistor and a fourth clamping diode connected between the control end and the second end of the second high-voltage transistor, Wherein, the current generating circuit comprises: A third resistor and a ninth transistor are connected in series between the first power supply voltage and the first ground, wherein the ninth transistor is connected to the third transistor and the seventh transistor in a current mirror manner.

6. The level shift circuit according to claim 1, wherein: The latch malfunction protection circuit comprises: a tenth transistor and an eleventh transistor connected in a first cross-coupled configuration; and a twelfth transistor and a thirteenth transistor connected in a second cross-coupled structure, The tenth transistor and the twelfth transistor are connected in series between a second power supply voltage of the second voltage domain and a second ground, The eleventh transistor and the thirteenth transistor are connected in series between the second power supply voltage and the second ground, The control terminals of the eleventh transistor and the thirteenth transistor are connected to a first node between the tenth transistor and the twelfth transistor, The control terminals of the tenth transistor and the twelfth transistor are connected to a second node between the eleventh transistor and the thirteenth transistor, The first node is further used to connect with the first signal line and the set end of the latch circuit, and the second node is further used to connect with the second signal line and the reset end of the latch circuit.

7. The level shift circuit according to claim 6, wherein: The latch malfunction protection circuit also includes: a fourth resistor connected between the first node and the second ground; a fifth resistor connected between the second power supply voltage and the second node, wherein the fourth resistor and the fifth resistor are used to provide an initial state for the latch circuit; a fourteenth transistor connected between the second node and the second ground, wherein a control terminal of the fourteenth transistor is used to receive an in-phase signal of the output signal; and a fifteenth transistor connected between the first node and the second ground, wherein a control terminal of the fifteenth transistor is used to receive an inverted signal of the output signal, The fourteenth transistor and the fifteenth transistor are used to provide a positive feedback loop in the circuit according to the state of the output signal, so as to quickly pull down one of the set terminal and the reset terminal of the latch circuit when the common mode noise occurs.

8. The level shift circuit according to claim 2, wherein: The pulse generating circuit comprises: a first pulse generating module, configured to generate the set pulse signal according to a first edge of the input signal, and A second pulse generating module is used to generate the reset pulse signal according to the first edge of the inverted signal of the input signal, Wherein, the first pulse generating module and the second pulse generating module both include: a sixteenth transistor, a sixth resistor, and a seventeenth transistor connected in series between a first power supply voltage of the first voltage domain and a first ground, control terminals of the sixteenth transistor and the seventeenth transistor being connected to each other and used to receive the input signal or an inverted signal of the input signal, and the sixteenth transistor and the seventeenth transistor having opposite conduction types; a capacitor connected between a third node between the sixteenth transistor and the sixth resistor and the first ground; A NAND gate, wherein a first input terminal thereof is used to receive the input signal or an inverted signal of the input signal, and a second input terminal thereof is connected to the third node; A first inverter, whose input terminal is connected to the output terminal of the NAND gate; A seventh resistor and an eighteenth transistor are connected between the output end of the set / reset pulse signal and the first ground, and a control end of the eighteenth transistor is connected to the output end of the first inverter.

9. A driving circuit for driving a high-side switching element and a low-side switching element in a half-bridge circuit, comprising: The level shift circuit according to any one of claims 1 to 8, wherein the level shift circuit is used to convert a high-side control input signal in a first voltage domain into an output signal in a second voltage domain; A high-side driver, used to obtain a high-side driving signal according to the output signal of the level shift circuit to control the on and off of the high-side switch element; as well as The low-side driver is used to obtain a low-side driving signal according to a low-side control input signal to control the on and off of the low-side switch element.

10. A half-bridge circuit, comprising: an output circuit including a high-side switching element and a low-side switching element connected in series, wherein an input voltage supplies power to a load via the high-side switching element; as well as A driving circuit for driving the high-side switching element and the low-side switching element, comprising: The level shift circuit according to any one of claims 1 to 8, wherein the level shift circuit is used to convert a high-side control input signal in a first voltage domain into an output signal in a second voltage domain; A high-side driver, used to obtain a high-side driving signal according to the output signal of the level shift circuit to control the on and off of the high-side switch element; and The low-side driver is used to obtain a low-side driving signal according to a low-side control input signal to control the on and off of the low-side switch element.

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