Method for preparing self-aligned transistor, self-aligned transistor, device and apparatus

Abstract

Provided in the present disclosure are a method for preparing a self-aligned transistor, a self-aligned transistor, a device and an apparatus. The method comprises: forming a hard mask and a side wall structure on a channel region of a substrate; etching the substrate on the basis of the hard mask and the side wall structure, so as to form a first semiconductor structure; removing the hard mask, and etching the first semiconductor structure and the substrate, so as to form a first active structure and a second active structure, wherein the first active structure comprises at least two fins corresponding to the side wall structure; epitaxially growing a first source structure or a first drain structure in an active region at either end of the first active structure, so as to form a first transistor, wherein the first transistor is a fin field effect transistor; and chamfering the substrate, and removing the substrate, so as to expose the second active structure; and epitaxially growing a second source structure or a second drain structure in an active region at either end of the second active structure, so as to form a second transistor, wherein the second transistor is a nanosheet field effect transistor or a planar transistor.

Description

Preparation method of self-aligned transistor, self-aligned transistor, device and equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202311226797.2 and application date September 21, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a self-aligned transistor, a self-aligned transistor, a device, and an apparatus. Background Art

[0004] As Moore's Law continues to deepen, further advancing transistor scaling is a hot topic in the industry. Stacked transistors, by integrating two or more layers of transistors vertically, further increase transistor integration density and become a key technology for further scaling integrated circuits.

[0005] In the related art, the process of preparing stacked transistors adopts a monolithic solution or a sequential solution, both of which have the following technical difficulties: (1) the thermal stability of the bottom layer device when making the upper layer device; (2) the performance of the top layer device under a low thermal budget; (3) the metal interconnection of transistors between layers.

[0006] Summary of the Invention

[0007] The present disclosure provides a method for preparing a self-aligned transistor, a self-aligned transistor, a device, and an apparatus.

[0008] The first aspect of the present disclosure provides a method for preparing a self-aligned transistor. The method includes: forming a hard mask and a sidewall structure on a channel region of a substrate, wherein the sidewall structure is located on both sides of the hard mask; etching the substrate based on the hard mask and the sidewall structure to form a first semiconductor structure; removing the hard mask and etching the first semiconductor structure to form a first active structure and a second active structure; the first active structure includes at least two fins corresponding to the sidewall structure; epitaxially growing a first source structure or a first drain structure in the active regions at both ends of the first active structure to form a first transistor, which is a fin-type field-effect transistor; flipping the substrate and removing the substrate to expose the second active structure; epitaxially growing a second source structure or a second drain structure in the active regions at both ends of the second active structure to form a second transistor, which is a nanosheet field-effect transistor or a planar transistor.

[0009] A second aspect of the present disclosure provides a self-aligned transistor. The self-aligned transistor is fabricated using the method for fabricating a self-aligned transistor as provided in the first aspect. The self-aligned transistor comprises: a first transistor, which is a fin-type field-effect transistor; and a second transistor, which is disposed opposite the first transistor and is a nanosheet field-effect transistor or a planar transistor. The first active structure of the first transistor and the second active structure of the second transistor are formed using the same spacer process.

[0010] A third aspect of the present disclosure provides a semiconductor device, comprising: the self-aligned transistor provided in the second aspect.

[0011] A fourth aspect of the present disclosure provides an electronic device, comprising: a circuit board and the semiconductor device provided by the third aspect, wherein the semiconductor device is arranged on the circuit board.

[0012] In the present disclosure, based on the hard mask and the sidewall structure, the substrate is etched to form a first semiconductor structure, the hard mask is removed, and the first semiconductor structure is etched to form a first active structure and a second active structure. Through these two etchings, a first active structure and a second active structure that are self-aligned in the vertical direction are formed, thereby realizing self-aligned stacking between transistors of different types and structures.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0015] FIG1 is a schematic diagram of a first implementation flow of a method for manufacturing a self-aligned transistor according to an embodiment of the present disclosure.

[0016] FIG2 is a schematic diagram of a first structure of a self-aligned transistor in an embodiment of the present disclosure.

[0017] 3A to 3G are schematic diagrams of a first manufacturing process of a self-aligned transistor according to an embodiment of the present disclosure.

[0018] FIG4 is a schematic diagram of a second structure of a self-aligned transistor in an embodiment of the present disclosure.

[0019] FIG5 is a schematic diagram of a third structure of a self-aligned transistor in an embodiment of the present disclosure.

[0020] FIG6 is a schematic diagram of a fourth structure of a self-aligned transistor in an embodiment of the present disclosure.

[0021] FIG. 7 is a schematic diagram of a fifth structure of a self-aligned transistor in an embodiment of the present disclosure.

[0022] 8A to 8B are schematic diagrams of a third fabrication process of a self-aligned transistor according to an embodiment of the present disclosure.

[0023] Description of reference numerals:

[0024] Self-aligned transistor 10; first transistor 11; first active structure 111; first source structure or first drain structure 112; first gate structure 113; first interlayer dielectric layer 114; first metal interconnect layer 115; first gate dielectric layer 116; dummy gate structure 117 of first transistor; second transistor 12; nanosheet 121A; bulk structure 121B; second source structure or second drain structure 122; second gate structure 123; second interlayer dielectric layer 124; second metal interconnect layer 125; second gate dielectric layer 126; dummy gate structure 127 of second transistor; insulating layer 13; carrier wafer 14; STI layer 15; insulating dielectric layer 16; spacer 17; BOX 18; bottom semiconductor material layer 21; stacked layer 22; top semiconductor material layer 23; hard mask 24; spacer structure 25; first semiconductor structure 26; columnar structure 27; first dummy gate structure 31; STI region 32; second dummy gate structure 33; gate structure 34. DETAILED DESCRIPTION

[0025] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure.

[0026] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present disclosure. The singular forms "a," "the," and "the" used in the present disclosure are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0027] At the current process node, the fin field effect transistor (FinFET) is the mainstream device, while the gate all around nanosheet field effect transistor (GAA NSFET) is considered the mainstream device for the next technology node. As Moore's Law continues to deepen, continuing to promote transistor size scaling beyond the GAA technology node is a hot topic in current industry research and development. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the key technologies for continuing the miniaturization of integrated circuit size.

[0028] In one embodiment, there are two schemes for fabricating stacked transistors. The first is a monolithic scheme, and the second is a sequential scheme.

[0029] The characteristics of the first solution include: (1) No wafer bonding technology is used, that is, N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) are made on the same substrate. This determines that the transistors on the same layer must be of the same type and structure, that is, NFET or PFET. (2) The upper and lower layer transistors must be strictly in the same plane space, and there is no alignment deviation. The advantage of this solution is that it has better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The type of transistors in each layer is fixed, making it difficult to stack transistors of different polarities or different structures. It is necessary to rely on two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, and the design flexibility is poor.

[0030] The second approach features wafer bonding and layer-by-layer processing. The thermal process during processing of the upper-layer devices may affect the lower-layer devices and interconnects, so the thermal budget of the entire processing process must be strictly controlled. However, thanks to wafer bonding, the device structure, channel crystal orientation, and even channel materials used in the upper and lower-layer transistors can be optimized accordingly to obtain better and more matched device performance. This approach currently has the following technical challenges: (1) Preparation of a high-quality upper-layer transistor active layer; (2) Thinning and defect control of the upper-layer bonded wafer; (3) Alignment errors between the upper and lower-layer transistors, which requires extremely high lithography accuracy.

[0031] The common technical difficulties faced by the above two solutions include: (1) the thermal stability of the bottom layer devices when making the upper layer devices; (2) the performance of the top layer devices under low thermal budget; and (3) the metal interconnection of transistors between layers.

[0032] In order to solve the above technical problems, the embodiments of the present disclosure provide a method for preparing a self-aligned transistor, a self-aligned transistor, a device and an apparatus to achieve self-aligned stacking between transistors of different types and structures.

[0033] In some embodiments, the self-aligned transistor can be applied to semiconductor devices such as memory and processor.

[0034] FIG1 is a schematic diagram of a first implementation flow of a method for manufacturing a self-aligned transistor according to an embodiment of the present disclosure. Referring to FIG1 , the method for manufacturing the self-aligned transistor may include steps S101 to S106 .

[0035] Step S101: forming a hard mask and a sidewall structure on a channel region of a substrate, wherein the sidewall structure is located on both sides of the hard mask.

[0036] In some embodiments, a substrate is provided, and a hard mask and a spacer structure are prepared on the substrate according to a standard process, wherein the spacer structure is located on a side of the hard mask.

[0037] In some embodiments, the hard mask does not completely cover the upper surface of the substrate, but covers a portion thereof for subsequent preparation of a first active structure in the first transistor and a second active structure in the second transistor.

[0038] In some embodiments, the self-aligned transistor provided by the embodiments of the present disclosure is a stacked transistor, which includes a first transistor and a second transistor stacked in a vertical direction. In some embodiments, the first transistor can be a FinFET, and the second transistor can be a GAA NSFET or a planar transistor. When the type of the second transistor is different, the substrate will also be set accordingly. For example, when the second transistor is a GAA NSFET, the substrate includes a three-layer structure, namely a bottom semiconductor material layer, a stacked layer and a top semiconductor material layer; in some embodiments, the stacked layer includes a first semiconductor material layer and a second semiconductor material layer deposited alternately in sequence; the first semiconductor material layer is used as a sacrificial layer to provide support for the nanosheet structure in the GAA NSFET, and the second semiconductor material layer is used to form the nanosheet structure in the GAA NSFET; the bottom semiconductor material layer, the second semiconductor material layer and the top semiconductor material layer can be made of the same material, such as silicon (Si), and the first semiconductor material layer can be made of silicon germanium (SiGe). When the second transistor is a planar transistor, the substrate can be set to a Si substrate.

[0039] In other embodiments, based on the above-mentioned configuration of the substrate, the substrate may also be a silicon-on-insulator (SOI) substrate. When the substrate is an SOI substrate, the configuration of the substrate is the same as that in the above-mentioned embodiment.

[0040] In some embodiments, the hard mask can be made of any of the following materials: titanium nitride (TiN), silicon nitride (SiN), silicon dioxide (SiO2), titanium monoxide (TiO). Other semiconductor materials can also be used to make the hard mask, and this disclosure is not limited to this. The sidewall structure can be made of any of the following materials: Si3N4, SiO2, and other semiconductor materials can also be used to make the hard mask, and this disclosure is not limited to this.

[0041] Step S102: etching the substrate based on the hard mask and the spacer structure to form a first semiconductor structure.

[0042] In some embodiments, based on the protective effects of the hard mask and the sidewall structure, the areas of the substrate not covered by the hard mask and the sidewall structure are etched. The etching depth is set according to actual conditions and is not limited in the embodiments of the present disclosure. After etching, a convex structure (i.e., the first semiconductor structure) is formed.

[0043] Step S103: removing the hard mask, and etching the first semiconductor structure and the substrate to form a first active structure and a second active structure; the first active structure includes at least two fins (also referred to as fin-shaped structures) corresponding to the spacer structure.

[0044] In some embodiments, after removing the hard mask, a portion of the top of the first semiconductor structure is exposed, and then the exposed portion of the first semiconductor structure and the substrate located at both ends of the sidewall structure are etched simultaneously to form two fins (i.e., the first active structure) and a second active structure located below the two fins.

[0045] Step S104 : epitaxially growing a first source structure or a first drain structure in the active regions at both ends of the first active structure to form a first transistor.

[0046] In some embodiments, after forming the first active structure and the second active structure, the gate region is opened by photolithography and polysilicon (poly Si) material is deposited to form a dummy gate structure, which is then filled with shallow trench isolation (STI) material to form an STI region. The upper half of the STI region (i.e., the portion corresponding to the first semiconductor structure) is removed, and then spacers are formed on the sidewalls of the exposed dummy gate structure. The spacers are used as masks to epitaxially grow a first source structure or a first drain structure, and an interlayer dielectric is deposited around the first source structure or the first drain structure. Back-end processes such as source-drain metal contacts and back-end interconnects are completed above the first source structure or the first drain structure to form a metal interconnect layer. At this point, the first transistor is formed.

[0047] Step S105: flipping the substrate over and removing the substrate to expose the second active structure.

[0048] In some embodiments, after forming the first transistor, an insulating material (e.g., SiOx) is deposited over the back-end process layers of the first transistor to form an insulating layer. This insulating layer is then wafer-bonded to a carrier wafer, and the first transistor is then flipped over. After flipping, the substrate is placed face-up, and a portion of the substrate is removed until the second active structure is exposed.

[0049] In some embodiments, the carrier wafer can provide physical support for the flipped first transistor after flipping, effectively preventing the first transistor from being broken during the preparation of the second transistor.

[0050] Step S106: epitaxially growing a second source structure or a second drain structure in the active regions at both ends of the second active structure to form a second transistor, where the second transistor is a nanosheet field effect transistor or a planar transistor.

[0051] In some embodiments, a second source structure or a second drain structure is formed in the active regions at both ends of the second active structure using the same method as that used to form the first source structure or the first drain structure.

[0052] In some possible embodiments, after the above step S106, the method for preparing the self-aligned transistor further includes: removing the dummy gate structure to form a first groove; depositing metal at the first groove to form a first gate structure of the first transistor and a second gate structure of the second transistor, respectively.

[0053] In some embodiments, a metal material is deposited at the first groove to form a gate structure. The gate structure in the area corresponding to the second active structure is removed by etching, and the second active structure is exposed, and a second groove is formed. In some embodiments, the unetched gate structure is the first gate structure in the first transistor. An insulating material is deposited on the first gate structure to form an insulating dielectric layer, which is used to isolate the first gate structure and the second gate structure. Then, a metal material is deposited on the insulating dielectric layer, that is, at the second groove, to form the second gate structure of the second transistor. In this way, self-alignment of the first gate structure and the second gate structure in the vertical direction can be achieved.

[0054] In other embodiments, after forming the first trench, the first and second gate structures may be fabricated using the following method: A metal material is deposited in the first trench to a height consistent with the height of the fin in the first transistor, thereby forming the first gate structure in the first transistor. An insulating material is then deposited over the first gate structure to form an insulating dielectric layer. A metal material is then deposited over the insulating dielectric layer to form the second gate structure in the second transistor.

[0055] In some embodiments, the insulating dielectric layer between the first gate structure and the second gate structure may not be provided, depending on practical circumstances. Thus, the first transistor and the second transistor may be interconnected through the contact between the first gate structure and the second gate structure, without the need for extending interconnection lines.

[0056] In some embodiments, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiments of the present disclosure are not limited to this.

[0057] In some embodiments, the metal materials of the first gate structure and the second gate structure may include but are not limited to: tantalum nitride (TaN), TiN, aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0058] In some embodiments, before preparing the first gate structure and the second gate structure, the above-mentioned semiconductor preparation method also includes: depositing a first gate dielectric layer on the surface of the first active structure, the first gate dielectric layer is used to isolate the first active structure and the first gate structure of the first transistor; depositing a second gate dielectric layer on the surface of the second active structure, the second gate dielectric layer is used to isolate the nanosheet structure and the second gate structure of the second transistor.

[0059] It should be noted that the materials of the first gate dielectric layer and the second gate dielectric layer can be the same material or different materials, which is set according to actual conditions and is not limited in the embodiments of the present disclosure.

[0060] Below, taking the second transistor as a GAA NSFET as an example, the self-aligned transistor provided by the embodiment of the present disclosure is described. Figure 2 is a schematic diagram of the first structure of the self-aligned transistor in the embodiment of the present disclosure. (a) in Figure 2 is a top view of the self-aligned transistor. It should be noted that, for ease of understanding, the top view only shows the fin structure and nanosheet, gate structure, source structure and drain structure; (b) is a cross-sectional view of the self-aligned transistor along the cross-sectional direction of the fin structure and nanosheet (i.e., AA' direction); (c) is a cross-sectional view of the self-aligned transistor along the cross-sectional direction of the source structure or the drain structure (i.e., BB' direction); (d) is a cross-sectional view of the self-aligned transistor along the cross-sectional direction of the gate structure (i.e., CC' direction).

[0061] As shown in FIG2 , the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12 . The first transistor 11 is a FinFET, and the second transistor 12 is a GAA NSFET. The first transistor 11 and the second transistor 12 are designed in a back-to-back configuration. In some embodiments, the active structure in the first transistor 11 (i.e., the first active structure 111 ) is two vertically parallel fins, and the active structure in the second transistor (i.e., the second active structure 121 ) is a plurality of parallel nanosheets 121A. The first active structure 111 and the second active structure 121 are formed by the same spacer process. An STI layer 15 is provided between the first interlayer dielectric layer 114 of the first transistor 11 and the second interlayer dielectric layer 124 of the second transistor 12 to isolate the first transistor 11 from the second transistor 12. An insulating dielectric layer 16 is provided between the first gate structure 113 and the second gate structure 123 to isolate the first gate structure 113 from the second gate structure 123.

[0062] The following describes the preparation process of the self-aligned transistor shown in Figure 2 in conjunction with the above preparation method. The self-aligned transistor shown in Figure 2 can be prepared by the process shown in Figures 3A to 3G, which are schematic diagrams of the first preparation process of the self-aligned transistor in the embodiment of the present disclosure.

[0063] The first step: alternately depositing SiGe / Si stacks 22 (i.e., a stack of alternately deposited first semiconductor material layers and second semiconductor material layers; in some embodiments, the first semiconductor material layer is prepared using SiGe and the second semiconductor material layer is prepared using Si) on a Si substrate (i.e., a bottom semiconductor material layer 21), wherein the thickness of the topmost SiGe layer is greater than that of the remaining SiGe layers, and depositing a Si layer (i.e., a top semiconductor material layer 23) on the SiGe / Si stack 22. The top semiconductor material layer 23 has a large thickness and can be used to make fins in the first transistor 11 (see (a) in FIG. 3A ).

[0064] In some embodiments, the topmost SiGe layer has a thickness of approximately 10 to 20 nm, the topmost Si layer has a thickness greater than 50 nm, and the remaining SiGe and Si layers have a thickness of approximately 10 nm. In some embodiments, the topmost SiGe layer has a thickness greater than that of the remaining SiGe and Si layers to effectively prevent etching of the Si layer (i.e., the nanosheet) in the stack during etching.

[0065] Step 2: A hard mask 24 and a spacer structure 25 are formed on the upper surface of the top Si layer according to standard steps (see (b) in FIG. 3A ).

[0066] In one example, the spacer structures 25 are disposed on both sides of the hard mask 24. As shown in the AA' direction in FIG3A(b), the hard mask 24 and the spacer structures 25 only cover a portion of the upper surface of the top Si layer, thus protecting this portion.

[0067] Step 3: Under the protection of the hard mask 24 and the spacer 25, the portion of the top Si layer not covered by the hard mask 24 and the spacer 25 (i.e., the first region) is etched down to the top SiGe layer, forming a first semiconductor structure 26 (see (c) in FIG. 3A ). In some embodiments, the first semiconductor structure 26 is convex.

[0068] Step 4: Remove the hard mask 24 and retain the spacer structure 25 (see (a) in FIG. 3B ).

[0069] In one example, after the hard mask 24 is removed, a portion of the upper surface of the first semiconductor structure 26 is exposed.

[0070] Step 5: Anisotropic etching is performed to etch the area of ​​the first semiconductor structure 26 not covered by the spacer structure 25 and the SiGe / Si stack (i.e., the second region) located below and on both sides of the spacer structure 25. This step forms two fins (i.e., the first active structure 111), which correspond to the spacer structure 25 and have the same width as the spacer structure 25. At the same time, the SiGe / Si stack is etched into a columnar structure 27 to facilitate the subsequent fabrication of the nanosheet 121A in the second transistor 12 (see (b) in FIG. 3B ).

[0071] In some embodiments, through a sidewall process, the fin in the first transistor 11 and the columnar structure 27 in the second transistor 12 are etched twice on a substrate, so that the first active structure in the first transistor 11 and the second active structure in the second transistor 12 are self-aligned in the vertical direction. The self-alignment of the first active structure and the second active structure realizes self-alignment between the active area of ​​the first transistor 11 and the active area of ​​the second transistor 12.

[0072] In some embodiments, the active region refers to a region on the substrate where active devices are formed, ie, a region isolated by STI.

[0073] Step 6: Remove the sidewall structure 25 and process the fins through a fin cutting process so that the spacing between the fins meets actual requirements (see (c) in FIG. 3B ).

[0074] Step 7: The gate regions of the first transistor 11 and the second transistor 12 are opened by a photolithography process, and poly Si is deposited in the gate regions to form a first dummy gate structure 31. STI material is filled in the remaining regions except the gate regions to form STI regions 32, and the STI regions 32 are polished or chemical-mechanical planarization (CMP) treated so that when the STI regions 32 are subsequently etched, the etching depths corresponding to the STI regions 32 at different locations are the same, thereby making the exposed fins have the same height (see (a) in FIG. 3C ).

[0075] In some embodiments, the STI material may be any of the following: SiN, Si3N4, SiO2, or silicon oxycarbide (SiCO), etc. The STI material may also be other oxides, which are not limited in the embodiments of the present disclosure.

[0076] Step 8: Remove the first dummy gate structure 31 to expose the fin and columnar structure 27 not covered by the STI region 32 (see (b) in FIG. 3C ).

[0077] Step 9: selectively remove the exposed SiGe layer (ie, the layer not covered by the STI region 32 ) in the columnar structure 27 by wet etching (see (c) in FIG. 3C ).

[0078] Step 10: Poly Si is deposited again on the gate region to form a second dummy gate structure 33 (see (a) in FIG. 3D ).

[0079] In one example, compared with the first dummy gate structure 31, the second dummy gate structure 33 does not include a SiGe layer in the columnar structure 28 covered by the second dummy gate structure 33. The SiGe layer deposited between two adjacent Si layers is spaced apart.

[0080] Step 11: Etch the upper portion of the STI region 32 to expose the fin (see (b) in FIG. 3D ).

[0081] It should be noted that when etching the upper portion of the STI region 32, the fin is not completely exposed. Etching should be stopped at the bottom of the fin and cover a portion of the bottom area. The etching depth of the upper portion of the STI region 32 can be set according to actual conditions and is not limited in this embodiment of the present disclosure.

[0082] Step 12: Form a spacer 17 on the sidewall of the exposed second dummy gate structure 33, and use the spacer 17 as a mask to epitaxially grow the first source structure or the first drain structure 112 in the first transistor 11, and deposit a first interlayer dielectric on the first source structure or the first drain structure 112 and between the second dummy gate structure 33 to form a first interlayer dielectric layer 114 (see (c) in Figure 3D).

[0083] In one example, the material of the first interlayer dielectric may be SiO 2 or other semiconductor materials, which is not limited in the embodiment of the present disclosure.

[0084] Step 13: Perform back-end processing (such as source-drain metal contacts and back-end interconnection) on the first source structure or the first drain structure 112 according to standard steps to form a first metal interconnection layer 115 in the first transistor 11 (see (a) in Figure 3E).

[0085] Step 14: Deposit an insulating material over the first metal interconnect layer 115 to form an insulating layer 13. Wafer-bond the insulating layer 13 to a carrier wafer 14, and then flip the first transistor 11. After flipping, place the Si substrate face-up (see (b) in Figure 3E).

[0086] Step 15: After flipping the wafer, the Si substrate is selectively removed by a CMP process until the bottom SiGe layer in the columnar structure 27 is exposed (see (c) in FIG. 3E ).

[0087] Step 16: Selectively etch the lower half of the STI region 32 to expose the complete columnar structure 27 (see (a) in FIG. 3F ).

[0088] It should be noted that when etching the lower half of the STI region 32 , a certain thickness of the STI region 32 may be retained to form an STI layer 15 (see AA′ direction in (a) of FIG. 3F ). The STI layer 15 is used to isolate the first transistor 11 from the second transistor 12 .

[0089] Step 17: Remove the SiGe layer in the columnar structure 27 to form a plurality of nanosheets 121A spaced apart in a vertical direction. Form spacers 17 on the sidewalls of the exposed second dummy gate structure 33. Using the spacers 17 as a mask, epitaxially grow the second source structure or the second drain structure 122 in the second transistor 12. Deposit a second interlayer dielectric on the second source structure or the second drain structure 122 and between the second dummy gate structures 33 to form a second interlayer dielectric layer 124 (see FIG. 3F (b)).

[0090] Step 18: The second dummy gate structure 33 is removed by etching, and a high-k dielectric material is deposited on the surfaces of the fin and nanosheet 121A to form a first gate dielectric layer 116 and a second gate dielectric layer 126. A metal material is then deposited in the gate region to form a gate structure 34. The gate structure 34 is now disposed in the gate regions of the first transistor 11 and the second transistor 12 (see FIG3F(c)).

[0091] Step 19: Etch the upper portion of the gate structure 34 to expose the nanosheet 121A. The unetched portion of the gate structure 34 serves as the first gate structure 113 in the first transistor 11. Deposit a layer of insulating material over the first gate structure 113 to form an insulating dielectric layer 16 (see FIG. 3G (a)).

[0092] In one example, the insulating dielectric layer 16 is used to isolate the first gate structure 113 from the second gate structure 123 .

[0093] Step 20: Photolithography is performed to open a hole, and a metal material is deposited on the insulating dielectric layer 16 to form a second gate structure 123 (see (b) in FIG. 3G ).

[0094] Step 21: Form a second metal interconnection layer 125 of the second transistor 12 (refer to step 13 for the process) (refer to (c) in FIG. 3G ).

[0095] At this point, the self-aligned transistor 10 in which the first transistor 11 is a FinFET and the second transistor 12 is a GAA NSFET is completed.

[0096] In other embodiments, the insulating dielectric layer 16 between the first gate structure 113 and the second gate structure 123 may not be provided. A self-aligned transistor 10 without the insulating dielectric layer 16 is shown in FIG4 , which is a schematic diagram of a second structural embodiment of a self-aligned transistor according to the present disclosure. As shown in FIG4 , except for the lack of the insulating dielectric layer, the remaining structure of the self-aligned transistor 10 is the same as that of FIG2 . The function of the self-aligned transistor without the insulating dielectric layer is also the same as that of the self-aligned transistor shown in FIG2 .

[0097] It should be noted that the substrate used in Figures 3A and 3G is a silicon substrate. When the substrate is an SOI substrate, the substrate setting method is the same as the first preparation process of the self-aligned transistor described above. The schematic diagram of the self-aligned transistor 10 finally formed is shown in Figure 5. Figure 5 is a schematic diagram of the third structure of the self-aligned transistor in the embodiment of the present disclosure. (a) in Figure 5 is a top view of the self-aligned transistor. It should be noted that for ease of understanding, the top view only shows the fin structure and nanosheet, gate structure, source structure or drain structure; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the fin structure and nanosheet (i.e., AA' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source structure or drain structure (i.e., BB' direction); (d) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., CC' direction). As shown in FIG5 , the BOX 18 is located between the fin (ie, the first active structure 111 ) of the first transistor 11 and the nanosheet 121A of the second transistor 12 . The BOX 18 can achieve electrical isolation between the fin and the nanosheet 121A.

[0098] In some embodiments, the self-aligned transistor fabricated on the SOI substrate has better subthreshold characteristics, smaller leakage current, and no latch-up problem.

[0099] In some embodiments, the second transistor 12 can also be a planar transistor. As shown in Figure 6, Figure 6 is a schematic diagram of the fourth structure of the self-aligned transistor in the embodiment of the present disclosure. (a) in Figure 6 is a top view of the self-aligned transistor. It should be noted that, for ease of understanding, (a) in Figure 5 only shows the fin structure and the block structure, the gate structure, the source structure or the drain structure. (b) in Figure 5 is a cross-sectional view of the self-aligned transistor made along the cross-sectional direction of the fin structure and the block structure (i.e., the AA' direction); (c) in Figure 6 is a cross-sectional view of the self-aligned transistor made along the cross-sectional direction of the source structure or the drain structure (i.e., the BB' direction); (d) in Figure 6 is a cross-sectional view of the self-aligned transistor made along the cross-sectional direction of the gate structure (i.e., the CC' direction).

[0100] As shown in Figure 6, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12. The first transistor 11 is a FinFET and the second transistor 12 is a planar transistor. The first transistor 11 and the second transistor 12 adopt a "back-to-back" design. In some embodiments, the fin structure in the first transistor 11 is a plurality of vertical fins, and the fin structure in the second transistor 12 is a block structure 121B. The fin structure in the first transistor 11 and the block structure 121B in the second transistor 12 are formed by the same sidewall spacer process. An STI layer 15 is provided between the first interlayer dielectric layer 114 of the first transistor 11 and the second interlayer dielectric layer 124 of the second transistor 12 to isolate the first transistor 11 from the second transistor 12. An insulating dielectric layer 16 is provided between the first gate structure 113 and the second gate structure 123 to isolate the first gate structure 113 from the second gate structure 123.

[0101] The second manufacturing process of the self-aligned transistor shown in FIG6 will be described below in combination with the above manufacturing method.

[0102] Step 1: Provide a Si substrate.

[0103] Step 2: forming a hard mask and a sidewall structure on the upper surface of the Si substrate according to standard steps (see the second step in the first preparation process of the self-aligned transistor).

[0104] Step 3: Under the protection of the hard mask and the sidewall structure, the area of ​​the Si substrate not covered by the hard mask and the sidewall structure (i.e., the third area) is etched to form the first semiconductor structure. The etching depth can be set according to actual needs. In some embodiments, the first semiconductor structure is convex.

[0105] Step 4: Remove the hard mask and retain the sidewall structure (refer to the fourth step in the first preparation process of the self-aligned transistor).

[0106] Step 5: etching the area of ​​the first semiconductor structure not covered by the sidewall structure and the Si substrate disposed below the third area (ie, the fourth area) by anisotropic etching to form fins and a block structure.

[0107] Step 6: Remove the side wall structure and process the fins through a fin cutting process so that the spacing between the fins meets actual requirements.

[0108] Step 7: forming a first dummy gate structure and an STI region (see step 7 in the first preparation process of the self-aligned transistor).

[0109] Step 8: Remove the first dummy gate structure to expose the fin and block structure not covered by the STI region.

[0110] Step 9: Poly Si is deposited again on the gate region to form a second dummy gate structure (see step 10 in the first fabrication process of the self-aligned transistor).

[0111] Step 10: Etch the upper portion of the STI region to expose the fin (see step 11 in the first preparation process of the self-aligned transistor).

[0112] Step 11: epitaxially grow the first source structure or the first drain structure in the first transistor, and deposit a first interlayer dielectric on the first source structure or the first drain structure and between the second dummy gate structure (see step 12 in the first preparation process of the self-aligned transistor).

[0113] Step 12: forming a first metal interconnection layer in the first transistor (see step 13 in the first preparation process of the self-aligned transistor).

[0114] Step 13: Deposit an insulating material over the first metal interconnect layer to form an insulating layer. Wafer-bond the insulating layer to a carrier wafer, and then flip the first transistor. After flipping, place the Si substrate face-up (see step 14 in the first fabrication process for self-aligned transistors).

[0115] Step 14: After flipping the wafer, the Si substrate is selectively removed through the CMP process until the block structure is exposed.

[0116] Step 15: Selectively etch the lower half of the STI region to expose the complete block structure.

[0117] Step 16: Form spacers on the sidewalls of the exposed second dummy gate structure, and use the spacers as a mask to epitaxially grow a second source structure or a second drain structure in the second transistor, and deposit a second interlayer dielectric on the second source structure or the second drain structure and between the second dummy gate structures (see step 17 in the first preparation process of the self-aligned transistor).

[0118] Step 17: Remove the second dummy gate structure by etching, and deposit a high-k dielectric material on the surface of the fin and block structure to form a gate dielectric layer. Then, deposit a metal material in the gate region to form a gate structure. The gate structure is now located in the gate region of the first transistor and the second transistor.

[0119] Step 18: forming a first gate structure and an insulating dielectric layer in the first transistor 11 (see step 19 in the first preparation process of the self-aligned transistor).

[0120] Step 19: Photolithographically open a hole and deposit a metal material on the insulating dielectric layer to form a second gate structure (see step 20 in the first preparation process of the self-aligned transistor).

[0121] Step 20: Form a second metal interconnection layer of the second transistor (refer to the 21st step in the first preparation process of the self-aligned transistor).

[0122] At this point, the self-aligned transistor 10 in which the first transistor 11 is a FinFET and the second transistor 12 is a planar transistor is completed.

[0123] It should be noted that the substrate used for the self-aligned transistor in FIG6 is a silicon substrate. When the substrate is an SOI substrate, the method for setting the substrate is the same as the second preparation process of the self-aligned transistor described above. The schematic diagram of the self-aligned transistor finally formed is shown in FIG7. FIG7 is a schematic diagram of the fifth structure of the self-aligned transistor in the embodiment of the present disclosure. (a) in FIG7 is a top view of the self-aligned transistor. It should be noted that, for ease of understanding, the top view only shows the fin structure and block structure, gate structure, source structure or drain structure; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the fin structure and block structure (i.e., AA' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source structure or drain structure (i.e., BB' direction); (d) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., CC' direction). As shown in FIG7 , the BOX 18 is located between the fin of the first transistor 11 and the block structure 121B of the second transistor 12 . The BOX 18 can achieve electrical isolation between the fin and the block structure 121B.

[0124] In some embodiments, the method for manufacturing a self-aligned transistor provided by the embodiments of the present disclosure may further include a third manufacturing process. Figures 8A and 8B are schematic diagrams of the third manufacturing process of a self-aligned transistor in the embodiments of the present disclosure.

[0125] In some embodiments, the third process for preparing a self-aligned transistor can be used to prepare a self-aligned transistor in which the second transistor is a GAA NSFET, or a self-aligned transistor in which the second transistor is a planar transistor. The following description will be made using a GAA NSFET as an example.

[0126] Step 1: Prepare a Si substrate and etch the fins in the first transistor 11 (i.e., the first active structure 111) and the columnar structure 27 in the second transistor 12 on the substrate (the process can be referred to steps 1 to 6 in the first preparation process of the self-aligned transistor).

[0127] Step 2: Depositing STI material on the fins and the columnar structure 27 to form an STI region 32 (see (a) in FIG. 8A ).

[0128] In one example, the STI region 32 completely wraps around the fin and the columnar structure 27 in the AA′ direction, the BB′ direction, and the CC′ direction.

[0129] Step 3: Etch the upper half of the STI region 32 until the fin in the first transistor 11 is exposed. The gate region of the first transistor 11 is opened by a photolithography process, and poly Si is deposited in the gate region to form a dummy gate structure 117 of the first transistor. Spacers 17 are formed on the sidewalls of the dummy gate structure 117 of the first transistor, and the spacers 17 are used as a mask to epitaxially grow the first source structure or the first drain structure 112 in the first transistor 11, and a first interlayer dielectric is deposited on the first source structure or the first drain structure 112 and between the dummy gate structure 117 of the first transistor to form a first interlayer dielectric layer 114 (see (b) in Figure 8A).

[0130] It should be noted that when etching the upper portion of the STI region 32, the fin is not completely exposed. Etching should be stopped at the bottom of the fin and cover a portion of the bottom area. The etching depth of the upper portion of the STI region 32 can be set according to actual conditions and is not limited in this embodiment of the present disclosure.

[0131] Step 4: Remove the dummy gate structure 117 of the first transistor and deposit a metal material in the gate region to form a first gate structure 113. Perform back-end processing (such as source / drain metal contacts and back-end interconnects) on the first source structure or the first drain structure 112 according to standard procedures to form a first metal interconnect layer 115 in the first transistor 11 (see step 13 in the first method of fabricating a self-aligned transistor) (see (c) in FIG8A ).

[0132] Step 5: Deposit an insulating material over the first metal interconnect layer 115 to form an insulating layer 13. Wafer-bond the insulating layer 13 to a carrier wafer 14, and then flip the first transistor 11. After flipping, the Si substrate is selectively removed using a CMP process until the bottom SiGe layer of the columnar structure 27 is exposed. The lower half of the STI region 32 is selectively etched to expose the complete columnar structure 27 (see steps 14 to 16 in the first fabrication process of the self-aligned transistor for this process) (see (a) in FIG8B ).

[0133] Step 6: Remove the SiGe layer in the source and drain regions of the columnar structure 27, open the gate region of the second transistor 12 by photolithography, and deposit poly Si in the gate region of the second transistor 12 to form a dummy gate structure 127 of the second transistor. Form spacers 17 on the sidewalls of the dummy gate structure 127 of the second transistor, and use the spacers 17 as a mask to epitaxially grow the second source structure or the second drain structure 122 of the second transistor 12, and deposit a second interlayer dielectric on the second source structure or the second drain structure 122 and between the dummy gate structure 127 of the second transistor to form a second interlayer dielectric layer 124 (see (b) in FIG. 8B ).

[0134] Step 7: Remove the dummy gate structure 127 of the second transistor and deposit a metal material in the gate region of the second transistor 12 to form a second gate structure 123. A second metal interconnect layer 125 in the second transistor 12 is formed on the second source structure or the second drain structure 122 according to standard steps (see step 21 in the first fabrication process of the self-aligned transistor) (see (c) in FIG8B ).

[0135] It should be noted that in the third preparation process of the above-mentioned self-aligned transistor, no insulating material is deposited between the first gate structure 113 and the second gate structure 123 (that is, the insulating dielectric layer 16 is not formed), and the isolation between the first gate structure 113 and the second gate structure 123 is achieved through the STI layer 15.

[0136] In other embodiments, during the third fabrication process of the self-aligned transistor, the STI layer 15 may not be disposed between the first gate structure 113 and the second gate structure 123. Specifically, when etching the lower half of the STI region, the STI region is completely removed at the gate region by etching. In this manner, the first transistor 11 and the second transistor 12 can be interconnected through the contact between the first gate structure 113 and the second gate structure 123, eliminating the need for interconnection wires.

[0137] In yet other embodiments, during the third fabrication process of the self-aligned transistor, an insulating dielectric layer may be disposed between the first gate structure 113 and the second gate structure 123. This is accomplished by etching the lower half of the STI region 32 to completely remove the STI region 32. Subsequently, an insulating material is deposited above the first gate structure 113 to form an insulating dielectric layer 16. The second gate structure 123 of the second transistor 12 is then fabricated on the insulating dielectric layer 16. The insulating dielectric layer 16 serves to isolate the first gate structure 113 from the second gate structure 123.

[0138] At this point, the self-aligned transistor 10 in which the first transistor 11 is a FinFET and the second transistor 12 is a GAA NSFET is completed.

[0139] In the embodiment of the present disclosure, based on the hard mask and the sidewall structure, the substrate is etched to form a first semiconductor structure, the hard mask is removed, and the first semiconductor structure and the substrate are etched to form a first active structure and a second active structure. Through these two etchings, a first active structure and a second active structure that are self-aligned in the vertical direction are formed, thereby realizing self-aligned stacking between transistors of different types and structures.

[0140] In the embodiment of the present disclosure, the self-alignment of the first active structure and the second active structure makes the active areas of the first transistor and the second transistor consistent, while solving the problem of high defect density, and greatly simplifying the process flow of stacked transistors, improving preparation efficiency and saving costs.

[0141] The method for preparing the self-aligned transistor described in the embodiment of the present disclosure is an organic fusion of the current sequential stacking transistors and monolithic stacking transistors. The technology is mature and highly reusable, which can avoid a large amount of expensive process development to save costs and has high feasibility. At the same time, in the embodiment of the present disclosure, the flip-chip transistor adopts a self-aligned "back-to-back" active area and metal gate design, so that the front and back transistors have independent signal and power supply networks and are connected through local interconnection. Without changing the extremely miniaturized 4T track unit design, it greatly releases metal wiring resources (more than 60% increase compared to traditional solutions), and there is huge room for collaborative optimization of process design. Finally, the flip-chip transistor solution is compatible with existing mainstream device architectures and can realize front and back stacking of planar transistors, FinFETs, GAA NSFETs and even vertical transistors (VTFETs) without the need for special process development for specific device architectures, making it more flexible and highly extensible from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, strong practicality and broad prospects for expansion.

[0142] The present disclosure provides a semiconductor device including the self-aligned transistor described in the above embodiment. The definition of the self-aligned transistor can be found in the self-aligned transistors shown in FIG2 , FIG4 , FIG5 , FIG6 , and FIG7 .

[0143] The present disclosure provides an electronic device comprising: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board. The semiconductor device includes the above-described semiconductor structure. The definition of a self-aligned transistor can be found in the self-aligned transistors shown in Figures 2, 4, 5, 6, and 7.

[0144] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0145] The above description is merely an exemplary embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Images