Semiconductor integrated circuit device

Abstract

This semiconductor integrated circuit device is provided with transistors (P2, P3) for performing differential amplification. Dummy transistors (DN2, DN3) are formed at positions different from those of the transistors (P2, P3) in the depth direction and overlapping in plan view. Active regions (61, 71) of the transistors (P2, P3) are configured in line symmetry and, with the same axis of symmetry, active regions (65, 75) of the dummy transistors (DN2, DN3) are also configured in line symmetry. In the active regions (65, 75) of the dummy transistors (DN2, DN3), the source and the drain at symmetrical positions have the same electrical connection state.

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a layout structure of a semiconductor integrated circuit device.

[0002] To increase the integration density of semiconductor integrated circuit devices, there is a technology called CFET (Complementary Field Effect Transistor) in which transistors are stacked in a direction perpendicular to the substrate. In this specification, the direction perpendicular to the substrate is referred to as the depth direction. Furthermore, to increase the integration density of semiconductor integrated circuit devices, a technology has been proposed in which wiring is provided directly below the transistor and the wiring is connected to the source / drain regions of the transistor.

[0003] Patent Document 1 discloses a standard cell structure using CFET technology and wiring directly below a transistor.

[0004] US Patent Application Publication No. 2022 / 0344255

[0005] Analog circuits that handle analog signals are one of the basic circuits that make up semiconductor integrated circuits. Because the analog signals handled by analog circuits are continuously changing signals, careful attention must be paid to suppressing signal variations in their layout design. In particular, in circuits that handle differential signals such as differential amplifiers, it is necessary to suppress variations between circuits that operate differentially.

[0006] However, in Patent Document 1, a layout structure using CFETs is not considered for analog circuits.

[0007] The present disclosure provides a layout structure using CFETs for an analog circuit having transistors that perform differential amplification.

[0008] A semiconductor integrated circuit device according to a first aspect of the present disclosure includes: a first transistor of a first conductivity type, the first transistor having a first active region that constitutes a channel, a source, and a drain of the transistor; a second transistor of the first conductivity type, the second transistor being located at the same position as the first transistor in a depth direction and having a second active region that constitutes the channel, the source, and a drain of the transistor; a first dummy transistor of a second conductivity type, the second transistor being located at a different position from the first transistor in the depth direction and being arranged at a position overlapping with the first transistor in a plan view; the first dummy transistor being located at the same position as the first dummy transistor in the depth direction and being arranged at a position overlapping with the second transistor in a plan view; and a second dummy transistor of the second conductivity type having a fourth active region that constitutes the channel, source, and drain of the transistor, wherein the first transistor and the first dummy transistor have gates connected to one of the differential input terminals, and the second transistor and the second dummy transistor have gates connected to the other of the differential input terminals, the first active region and the second active region are configured to be line-symmetrical with respect to a predetermined straight line in a planar view, the third active region and the fourth active region are configured to be line-symmetrical with respect to the predetermined straight line in a planar view, and the electrical connection states of the sources and drains in the third and fourth active regions that are located symmetrically with respect to the predetermined straight line are the same.

[0009] According to this aspect, a semiconductor integrated circuit device includes first and second transistors that perform differential amplification. First and second dummy transistors are formed at positions different in the depth direction from the first and second transistors and overlapping in a plan view. The first and second active regions of the first and second transistors are configured in line symmetry with respect to a predetermined straight line in a plan view. The third and fourth active regions of the first and second dummy transistors are also configured in line symmetry with respect to the same predetermined straight line. In the third and fourth active regions, the sources and drains at symmetrical positions have the same electrical connection state. This suppresses variations in the characteristics of the first and second transistors that perform differential operation, thereby suppressing variations between differential output signals.

[0010] According to the present disclosure, a layout structure using CFETs is realized that can suppress variations in differential operation.

[0011] 3A and 3B are cross-sectional views of the layout structure shown in FIGS. 2 and 3C; a variation of the layout structure of FIG. 3; another circuit configuration example of the differential amplifier according to the second embodiment; FIG. 6A and 6B are plan views of the layout structure example of the differential amplifier shown in FIG. 6C, showing the upper structure; FIG. 6B and 6C are plan views of the layout structure example of the differential amplifier shown in FIG. 6C, showing the lower structure;

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device is assumed to include a nanosheet field effect transistor (FET). In the present disclosure, the transistor included in the semiconductor integrated circuit device is not limited to a nanosheet FET.

[0013] In this specification, "VDD" and "VSS" refer to power supply voltages or the power supply itself. "INP," "INN," "OUTP," and "OUTN" refer to signals or signal terminals. In this specification, expressions such as "same wiring width" that mean the same width or the like are considered to include the range of manufacturing variations.

[0014] First Embodiment FIG. 1 is a circuit diagram showing an example of the circuit configuration of a differential amplifier according to a first embodiment. A differential amplifier is a type of analog circuit. The differential amplifier in FIG. 1 includes P-type transistors P1, P2, and P3 and resistors R1 and R2. The transistors P2 and P3 have the same size. The resistors R1 and R2 have the same resistance value.

[0015] The transistor P1 functions as a current source. The transistor P1 is connected between the power supply VDD and the node NS, and a bias voltage PBIAS is applied to the gate of the transistor P1. The transistor P1 supplies a current to the node NS.

[0016] The sources of both transistors P2 and P3 are connected to node NS. The gate of transistor P2 is connected to the differential input terminal INP, and the drain is connected to one end of resistor R1. The gate of transistor P3 is connected to the differential input terminal INN, and the drain is connected to one end of resistor R2. The other ends of resistors R1 and R2 are connected to power supply VSS. The drain of transistor P2 is connected to differential output terminal OUTP, and the drain of transistor P3 is connected to differential output terminal OUTN.

[0017] The differential amplifier of FIG. 1 amplifies a differential input signal input to differential input terminals INP and INN with a predetermined differential gain, and outputs the amplified signal from differential output terminals OUTP and OUTN.

[0018] 2 to 4 are diagrams showing an example of a layout structure using CFETs for the differential amplifier of FIG. 1. Specifically, FIG. 2 is a plan view of the upper portion including the upper-layer transistor formed on the side farther from the substrate, FIG. 3 is a plan view of the lower portion including the lower-layer transistor formed on the side closer to the substrate, and FIG. 4 is a cross-sectional view taken along line X1-X1' in FIGS. 2 and 3. In this example layout structure, a P-type nanosheet FET is formed on the upper portion, and an N-type nanosheet FET is formed on the lower portion. Transistors P1, P2, and P3 in the circuit diagram of FIG. 1 are formed on the upper portion. Dummy transistors DN1, DN2, and DN3, not shown in the circuit diagram of FIG. 1, are formed on the lower portion.

[0019] In the following description, in plan views such as Figure 2, the horizontal direction of the drawing is the X direction, the vertical direction of the drawing is the Y direction, and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0020] The transistor P1 is formed in the center of the upper part of the drawing in Fig. 2. In Fig. 2, the transistor P1 is composed of two transistors connected in parallel.

[0021] Wirings 11 and 12 extending in the X direction are formed on the M0 layer. The M0 layer is a wiring layer on the upper surface side of the semiconductor chip. The wiring 11 is a power supply wiring and supplies VDD. The wiring 12 supplies a bias voltage PBIAS.

[0022] An active region 21 that constitutes the channel, source, and drain of a P-type nanosheet FET that becomes transistor P1 is formed below power supply wiring 11. The active region 21 includes nanosheets 22a and 22b that become the channel of the P-type nanosheet FET. Portions 23a and 23b of the active region 21 that become the source of the P-type nanosheet FET are connected to the power supply wiring 11 via local wiring and vias.

[0023] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0024] The gate wirings 31a and 31b extend in the Y direction and also extend in the Z direction from top to bottom. The gate wirings 31a and 31b surround the outer peripheries of the nanosheets 22a and 22b in the Y and Z directions, respectively, via gate insulating films (not shown). The gate wirings 31a and 31b serve as gates for the P-type nanosheet FETs. The gate wirings 31a and 31b are connected to the wiring 12 of the M0 layer via vias.

[0025] The local wiring 41 extending in the Y direction is connected to the portion 24 that becomes the drain of the P-type nanosheet FET in the active region 21. The local wiring 41 is connected to a wiring 51 formed in the M1 layer through a via, an M0 wiring, and another via. The M1 layer is a wiring layer above the M0 layer. The wiring 51 is a wiring corresponding to the node NS, and extends in the Y direction to the region where the transistors P2 and P3 are formed on the lower side of the drawing.

[0026] Transistors P2 and P3 are formed at the bottom of the drawing in Fig. 2. In Fig. 2, transistors P2 and P3 are each composed of three transistors connected in parallel. Transistors P2 and P3 are arranged on the left and right of wiring 51 in the drawing. The planar layout of transistors P2 and P3 is arranged symmetrically with respect to a line Y1-Y1' extending in the Y direction. M1 wiring 51 is arranged on the center line Y1-Y1' of the line symmetry.

[0027] In the M0 layer, a wiring 13 is formed extending in the X direction from transistor P2 to transistor P3. The M0 wiring 13 is connected to an M1 wiring 51 through a via. Also, in the M0 layer, wirings 14, 15, 16, and 17 are formed extending in the X direction. The wiring 14 corresponds to the differential input terminal INP, and the wiring 15 corresponds to the differential input terminal INN. The wiring 16 is connected to a resistor R1 (not shown), and the wiring 17 is connected to a resistor R2 (not shown).

[0028] Below the M0 wiring 13, an active region 61 that forms the channel, source, and drain of the P-type nanosheet FET that becomes transistor P2, and an active region 71 that forms the channel, source, and drain of the P-type nanosheet FET that becomes transistor P3 are formed.

[0029] The active region 61 includes nanosheets 62a, 62b, and 62c that serve as the channel of the P-type nanosheet FET. In the active region 61, portions 63a and 63b that serve as the source of the P-type nanosheet FET are connected to the M0 wiring 13 via local wiring and vias. In addition, portions 64a and 64b that serve as the drain of the P-type nanosheet FET are connected to the M0 wiring 16 via local wiring and vias.

[0030] The gate wirings 36a, 36b, and 36c extend in the Y direction and also extend in the Z direction from top to bottom. The gate wirings 36a, 36b, and 36c surround the outer peripheries of the nanosheets 62a, 62b, and 62c in the Y and Z directions, respectively, via gate insulating films (not shown). The gate wirings 36a, 36b, and 36c serve as the gates of transistor P2. The gate wirings 36a, 36b, and 36c are connected to the wiring 14 of the M0 layer through vias.

[0031] The active region 71 includes nanosheets 72a, 72b, and 72c that serve as the channel of the P-type nanosheet FET. In the active region 71, portions 73a and 73b that serve as the source of the P-type nanosheet FET are connected to the M0 wiring 13 via local wiring and vias. In addition, portions 74a and 74b that serve as the drain of the P-type nanosheet FET are connected to the M0 wiring 17 via local wiring and vias.

[0032] The gate wirings 37a, 37b, and 37c extend in the Y direction and also extend in the Z direction from top to bottom. The gate wirings 37a, 37b, and 37c surround the outer peripheries of the nanosheets 72a, 72b, and 72c in the Y and Z directions, respectively, via gate insulating films (not shown). The gate wirings 37a, 37b, and 37c serve as the gates of transistor P3. The gate wirings 37a, 37b, and 37c are connected to the wiring 15 of the M0 layer through vias.

[0033] 3, an active region 25 is formed at a position overlapping the active region 21 of the transistor P1 in a planar view. In addition, active regions 65 and 75 are formed at positions overlapping the active regions 61 and 71 of the transistors P2 and P3 in a planar view. The active regions 25, 65, and 75 respectively constitute the channels, sources, and drains of the N-type nanosheet FETs that become the dummy transistors DN1, DN2, and DN3.

[0034] Wirings 81 and 82 extending in the X direction are formed on the BM0 layer. The BM0 layer is a wiring layer on the back side of the semiconductor chip. The wirings 81 and 82 are power supply wirings that supply VSS.

[0035] Gate wirings 31a and 31b surround the Y-direction and Z-direction outer peripheries of the nanosheet in active region 25, respectively, via gate insulating films (not shown). Gate wirings 36a, 36b, and 36c surround the Y-direction and Z-direction outer peripheries of the nanosheet in active region 65, respectively, via gate insulating films (not shown). Gate wirings 37a, 37b, and 37c surround the Y-direction and Z-direction outer peripheries of the nanosheet in active region 75, respectively, via gate insulating films (not shown).

[0036] The portions of the active region 25 that will become the source and drain are connected through vias to a BM0 wiring 81. The portions of the active regions 65 and 75 that will become the source and drain are connected through vias to a BM0 wiring 82.

[0037] The layout structures shown in FIGS. 2 to 4 have the following features.

[0038] The layout of the transistors P2 and P3 to which the differential signal is input is configured to be line symmetrical with respect to the line Y1-Y1' as the axis of symmetry.

[0039] Specifically, each of the transistors P2 and P3 is configured by connecting three transistors in parallel. This results in the transistors P2 and P3 having the same transistor size. The gates, sources, and drains that make up the transistors P2 and P3 are arranged symmetrically. The vias connected to the gates, sources, and drains are also arranged symmetrically. The wiring (local wiring and M0 wiring) connected to the transistors and the vias between the wirings are also arranged symmetrically. Furthermore, the wiring 51 corresponding to the node NS is arranged on the line Y1-Y1', which is the axis of symmetry, and is connected to the transistors P2 and P3.

[0040] Such a symmetrical arrangement suppresses variations in the characteristics of the transistors P2 and P3, thereby suppressing variations in the differential output signals.

[0041] Furthermore, N-conductivity type dummy transistors DN2 and DN3 formed below the transistors P2 and P3 are also arranged symmetrically with respect to the line Y1-Y1' as the axis of symmetry.

[0042] Specifically, the two dummy transistors DN2 and DN3 are each composed of three transistors superimposed on the three transistors that make up transistors P2 and P3. The gates are formed integrally with the gates of the upper transistors P2 and P3, and therefore receive the same differential input signals INP and INN as the transistors P2 and P3. The sources and drains are all connected via vias to the BM0 wiring 82 that supplies VSS. The wiring and vias connected to the dummy transistors DN2 and DN3 are arranged symmetrically with respect to the line Y1-Y1'.

[0043] In this way, by configuring the lower dummy transistors DN2 and DN3, on which the transistors P2 and P3 are formed, symmetrically in terms of their circuit and layout, variations in the finished size of the upper transistors P2 and P3 are suppressed.

[0044] Furthermore, because the gates of the transistors P2 and P3 and the dummy transistors DN2 and DN3 located below them are integrally formed, not only the gates of the transistors P2 and P3 but also the gates of the dummy transistors DN2 and DN3 act as loads on the differential input signals INP and INN. However, in the above-described configuration, the circuit and layout of the dummy transistors DN2 and DN3 are also configured symmetrically, so that variations in the load on the differential input signals INP and INN can be suppressed.

[0045] As described above, this embodiment can suppress variations in the differential operation of the differential amplifier. That is, the semiconductor integrated circuit device according to this embodiment includes transistors P2 and P3 that perform differential amplification. Dummy transistors DN2 and DN3 are formed at positions different in the depth direction from the transistors P2 and P3, but overlapping in a plan view. The active regions 61 and 71 of the transistors P2 and P3 are configured line-symmetrically with respect to the line Y1-Y1' in a plan view. The active regions 65 and 75 of the dummy transistors DN2 and DN3 are also configured line-symmetrically with respect to the line Y1-Y1'. Furthermore, in the active regions 65 and 75, the sources and drains are all connected to the power supply VSS. This suppresses variations in the characteristics of the transistors P2 and P3 that perform differential operation, thereby suppressing variations between the differential output signals.

[0046] 5 is a diagram showing a layout structure according to a modified example, and is a plan view of the lower part including the lower layer transistors. The layout structure in FIG. 5 is substantially the same as that in FIG. 3. However, the active region 25 is not connected to the BM0 wiring 81, and the active regions 65 and 75 are not connected to the BM0 wiring 82. In other words, the sources / drains of the dummy transistors DN2 and DN3 are all floating.

[0047] In this modification, the lower dummy transistors DN2 and DN3, on which the upper transistors P2 and P3 are formed, are configured symmetrically in terms of circuit and layout, thereby achieving the same effects as in the above-described embodiment.

[0048] Second Embodiment Fig. 6 is a circuit diagram showing an example of the circuit configuration of a differential amplifier according to a second embodiment. The differential amplifier in Fig. 6 includes a P-conductivity type transistor P1, N-conductivity type transistors N2 and N3, and resistors R1 and R2. The transistors N2 and N3 have the same size. The resistors R1 and R2 have the same resistance value.

[0049] The differential amplifier of Fig. 6 differs from the differential amplifier of Fig. 1 in that the P-conductivity type transistors P2 and P3 that perform differential operation are replaced by N-conductivity type transistors N2 and N3. The rest of the configuration and operation are the same as those of the differential amplifier of Fig. 1, so detailed description will be omitted here.

[0050] 7 and 8 are diagrams showing an example of a layout structure using CFETs for the differential amplifier of FIG. 6, with FIG. 7 being a plan view of the upper part and FIG. 8 being a plan view of the lower part. In this layout structure example, a P-type nanosheet FET is formed in the upper part, and an N-type nanosheet FET is formed in the lower part. Note that the cross-sectional structure can be easily inferred from the description of the first embodiment, so it is not shown here.

[0051] In the circuit diagram of Fig. 6, transistor P1 is formed in the upper portion. Transistors N2 and N3 in the circuit diagram of Fig. 6 are formed in the lower portion. Furthermore, in the lower portion, a dummy transistor DN1 (not shown in the circuit diagram of Fig. 6) is formed at a location overlapping with transistor P1 in a plan view. Furthermore, in the upper portion, dummy transistors DP2 and DP3 (not shown in the circuit diagram of Fig. 6) are formed at a location overlapping with transistors N2 and N3 in a plan view.

[0052] Transistor P1 is formed in the upper center of the drawing in Fig. 7. Also, in Fig. 8, an N-type nanosheet FET that serves as dummy transistor DN1 is formed at a position overlapping transistor P1. The configurations of this transistor P1 and dummy transistor DN1 are the same as those shown in Figs. 2 and 3, and therefore description thereof will be omitted here. M1 wiring 52 corresponding to node NS is connected to M0 wiring 111 extending in the X direction via a via.

[0053] 7, a wiring 113 extending in the X direction is formed in the M0 layer. The wiring 113 is a power supply wiring that supplies VDD. Also, wirings 114, 115, 116, and 117 extending in the X direction are formed in the M0 layer. The wiring 114 corresponds to the differential input terminal INP, and the wiring 115 corresponds to the differential input terminal INN. The wiring 116 is connected to a resistor R1 (not shown), and the wiring 117 is connected to a resistor R2 (not shown).

[0054] Transistors N2 and N3 are formed at the bottom of the drawing in Fig. 8. In Fig. 8, transistors N2 and N3 are each composed of three transistors connected in parallel. The planar layout of transistors N2 and N3 is configured to be line-symmetrical with respect to a line Y1-Y1' extending in the Y direction.

[0055] An active region 121 is formed which constitutes the channel, source, and drain of an N-type nanosheet FET that will become transistor N2. Also, an active region 131 is formed which constitutes the channel, source, and drain of an N-type nanosheet FET that will become transistor N3.

[0056] The active region 121 includes nanosheets 122a, 122b, and 122c that serve as channels of the N-type nanosheet FET. In the active region 121, portions 123a and 123b that serve as sources of the N-type nanosheet FET are connected to the M0 wiring 111 via local wiring and vias. In addition, portions 124a and 124b that serve as drains of the N-type nanosheet FET are connected to the M0 wiring 116 via local wiring and vias.

[0057] The gate wirings 136a, 136b, and 136c extend in the Y direction and also extend in the Z direction from top to bottom. The gate wirings 136a, 136b, and 136c surround the outer peripheries of the nanosheets 122a, 122b, and 122c in the Y and Z directions, respectively, via gate insulating films (not shown). The gate wirings 136a, 136b, and 136c serve as the gates of transistor N2. The gate wirings 136a, 136b, and 136c are connected to the wiring 114 of the M0 layer through vias.

[0058] The active region 131 includes nanosheets 132a, 132b, and 132c that serve as channels of the N-type nanosheet FET. In the active region 131, portions 133a and 133b that serve as sources of the N-type nanosheet FET are connected to the M0 wiring 111 via local wiring and vias. In addition, portions 134a and 134b that serve as drains of the N-type nanosheet FET are connected to the M0 wiring 117 via local wiring and vias.

[0059] The gate wirings 137a, 137b, and 137c extend in the Y direction and also extend in the Z direction from top to bottom. The gate wirings 137a, 137b, and 137c surround the outer peripheries of the nanosheets 132a, 132b, and 132c in the Y and Z directions, respectively, via gate insulating films (not shown). The gate wirings 137a, 137b, and 137c serve as the gates of transistor N3. The gate wirings 137a, 137b, and 137c are connected to the wiring 115 of the M0 layer through vias.

[0060] 7, active regions 125 and 135 are formed at positions overlapping the active regions 121 and 131 of the transistors N2 and N3 in a plan view. The active regions 125 and 135 form the channels, sources, and drains of the P-type nanosheet FETs that become the dummy transistors DP2 and DP3.

[0061] The portions of the active regions 125 and 135 that will become the source and drain are connected to the M0 wiring 113 through local wiring and vias.

[0062] The layout structures shown in Figures 7 and 8 have the same features as those of the first embodiment. That is, the layout of transistors N2 and N3, to which differential signals are input, is configured to be line-symmetrical with respect to line Y1-Y1' as the axis of symmetry. Specifically, each of transistors N2 and N3 is configured by connecting three transistors in parallel. This results in transistors N2 and N3 having the same transistor size. Furthermore, the gates / sources / drains that constitute the transistors N2 and N3 are arranged symmetrically. The wiring and vias connected to the transistors are also arranged symmetrically.

[0063] Such a symmetrical arrangement suppresses variations in the characteristics of the transistors N2 and N3, thereby suppressing variations in the differential output signals.

[0064] Furthermore, the P-conductivity type dummy transistors DP2 and DP3 formed above the transistors N2 and N3 are also arranged symmetrically with respect to the line Y1-Y1'.

[0065] Specifically, the two dummy transistors DP2 and DP3 are each composed of three transistors superimposed on the three transistors that make up transistors N2 and N3. Their gates are formed integrally with the gates of the lower transistors N2 and N3, and therefore receive the same differential input signals INP and INN as transistors N2 and N3. Their sources and drains are all connected via vias to the M0 wiring 113 that supplies VDD. The wiring and vias connected to dummy transistors DP2 and DP3 are arranged symmetrically with respect to line Y1-Y1'.

[0066] In this way, by configuring the upper dummy transistors DP2 and DP3 with the transistors N2 and N3 formed below them symmetrically in terms of their circuit and layout, variations in the finished size of the transistors, including the lower transistors N2 and N3, are suppressed.

[0067] Furthermore, because the gates of transistors N2 and N3 and the dummy transistors DP2 and DP3 above them are integrally formed, not only the gates of transistors N2 and N3 but also the gates of dummy transistors DP2 and DP3 act as loads on the differential input signals INP and INN. However, in the above-described configuration, the circuit and layout of dummy transistors DP2 and DP3 are also configured symmetrically, so that variations in the load on the differential input signals INP and INN can be suppressed.

[0068] As described above, this embodiment can suppress variations in the differential operation of the differential amplifier. That is, the semiconductor integrated circuit device according to this embodiment includes transistors N2 and N3 that perform differential amplification. Dummy transistors DP2 and DP3 are formed at positions different in the depth direction from transistors N2 and N3 and overlapping in a plan view. The active regions 121 and 131 of transistors N2 and N3 are configured line-symmetrically with respect to line Y1-Y1' in a plan view. The active regions 125 and 135 of dummy transistors DP2 and DP3 are also configured line-symmetrically with respect to line Y1-Y1'. Furthermore, in the active regions 125 and 135, the sources and drains are all connected to the power supply VDD. This suppresses variations in the characteristics of transistors N2 and N3 that perform differential operation, thereby suppressing variations between differential output signals.

[0069] As in the modified example of the first embodiment, the active regions 125, 135 constituting the dummy transistors DP2, DP3 may be configured not to be connected to the M0 wiring 113. In other words, the sources / drains of the dummy transistors DP2, DP3 may all be in a floating state.

[0070] (Other Embodiments) (Part 1) In each of the above-described embodiments, a P-type nanosheet FET is formed on the upper part and an N-type nanosheet FET is formed on the lower part. However, the conductivity types may be reversed, and an N-type nanosheet FET may be formed on the upper part and a P-type nanosheet FET may be formed on the lower part.

[0071] (2) In the above-described embodiment, the sources and drains of the dummy transistors that overlap the differentially operating transistors in plan view are all connected to the power supply, or are all floating. However, this is not limiting. For example, the sources and drains of the dummy transistors may all be connected to a predetermined node other than the power supply.

[0072] Furthermore, it is not necessary for all of the sources and drains of the dummy transistors to have the same electrical connection state. That is, in the present disclosure, it is sufficient that the electrical connection state of the sources and drains at line-symmetric positions of the dummy transistors that overlap with the differentially operating transistors in a plan view is the same. Here, the electrical connection state may be any of the following: connected to a power supply, floating, or connected to a specified node other than the power supply.

[0073] (3) In the above-described embodiment, the differentially operating transistors are configured with three transistors connected in parallel, but this is not limiting. That is, the differentially operating transistors may be configured with fewer than three transistors or more than three transistors.

[0074] In the above-described embodiment, the transistors constituting the differentially operating transistors are arranged side by side in the X direction, but this is not limiting. For example, they may be arranged side by side in the Y direction, or they may be arranged in an array in both the X and Y directions.

[0075] (No. 4) In the above-described embodiment, the layout structure has been described using the differential amplifier shown in Figures 1 and 6 as an example, but the circuit configuration to which the present disclosure can be applied is not limited to this. In other words, if the circuit includes transistors that perform differential operation, such as a differential amplifier with a configuration different from those shown in Figures 1 and 6, the same effect can be obtained by applying the layout structure described above to the transistors that perform differential operation.

[0076] (No. 5) In the above-described embodiment, the active regions, wiring, and vias of the differentially operating transistors and the dummy transistors that overlap them in plan view all have a layout structure that is line-symmetric. However, as long as the active regions are line-symmetric, the effects described in the embodiment can be obtained even if the wiring and vias are not line-symmetric. Furthermore, if the local wiring connected to the active regions is line-symmetric, even greater effects can be obtained. Alternatively, if the transistor gates are line-symmetric, even greater effects can be obtained. Furthermore, if the wiring and vias connected to the transistors are line-symmetric, variations in differential operation can be more effectively suppressed.

[0077] In the above-described embodiment, the nanosheet is illustrated as three sheet structures stacked on top of each other in a planar view, and the cross-sectional shape of the sheet structure is rectangular, but the number of sheet structures and cross-sectional shape of the nanosheet are not limited to this.

[0078] In addition, in the above-described embodiments, the transistor is a nanosheet FET, but this is not limiting. For example, a finFET or other types of transistors may be used.

[0079] The present disclosure can suppress variations in differential operation, and is therefore useful for improving the performance of semiconductor integrated circuit devices, for example.

[0080] 61, 71: Active area 65, 75: Active area 121, 131: Active area 125, 135: Active area N2, N3: Transistor P2, P3: Transistor DN2, DN3: Dummy transistor DP2, DP3: Dummy transistor INP, INN: Differential input terminal

Claims

1. A semiconductor device comprising: a first transistor of a first conductivity type having a first active region constituting a channel, a source, and a drain of the transistor; a second transistor of the first conductivity type, located at the same position as the first transistor in the depth direction and having a second active region constituting the channel, a source, and a drain of the transistor; a first dummy transistor of a second conductivity type, located at a different position from the first transistor in the depth direction and arranged to overlap with the first transistor in a planar view, and having a third active region constituting the channel, a source, and a drain of the transistor; and a second dummy transistor of the second conductivity type, located at the same position as the first dummy transistor in the depth direction and arranged to overlap with the second transistor in a planar view, and having a fourth active region constituting the channel, a source, and a drain of the transistor; one of the differential input terminals is connected to the gates of the first transistor and the first dummy transistor, and the other of the differential input terminals is connected to the gates of the second transistor and the second dummy transistor; the first active region and the second active region are configured to be linearly symmetrical with respect to a predetermined straight line as an axis in a planar view, A semiconductor integrated circuit device, wherein the third active region and the fourth active region are configured to be linearly symmetrical with respect to the specified straight line in a planar view, and the electrical connection states of sources and drains located symmetrically with respect to the specified straight line in the third and fourth active regions are identical.

2. A semiconductor integrated circuit device according to claim 1, wherein the electrical connection state is either connected to a power supply, in a floating state, or connected to a specified node other than the power supply.

3. A semiconductor integrated circuit device according to claim 1, wherein the local wiring connected to the first active region and the local wiring connected to the second active region are configured in a line symmetrical manner with respect to the specified straight line in a planar view, and the local wiring connected to the third active region and the local wiring connected to the fourth active region are configured in a line symmetrical manner with respect to the specified straight line in a planar view.

4. A semiconductor integrated circuit device according to claim 1, wherein the gate of the first transistor and the gate of the second transistor are configured to be line-symmetrical with respect to the specified straight line in a plan view, and the gate of the first dummy transistor and the gate of the second dummy transistor are configured to be line-symmetrical with respect to the specified straight line in a plan view.

Images