Signal transmission apparatus, electronic device provided with signal transmission apparatus, and vehicle provided with electronic device

Abstract

A signal transmission apparatus 200X comprises: a transmission circuit 410x that outputs a first internal signal S1 and a second internal signal S2 according to an input signal IN; a reception circuit 420x; a first drive circuit 501; and a second drive circuit 502. The transmission circuit 410x drives at least one of the first internal signal S1 and the second internal signal S2 at a specific cycle different from the cycle of the input signal IN according to an external signal ASC. The reception circuit 420x, upon detecting that the cycle of at least one of the first internal signal S1 and the second internal signal S2 is the specific cycle, disables the first drive circuit 501, and enables the second drive circuit 502.

Description

Signal transmission device, electronic device equipped with signal transmission device, and vehicle equipped with electronic device

[0001] The invention disclosed in this specification relates to a signal transmission device, an electronic device including the signal transmission device, and a vehicle including the electronic device.

[0002] 2. Description of the Related Art Signal transmission devices that transmit pulse signals while insulating input and output have been used in a variety of applications (such as power supply devices or motor drive devices).

[0003] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] International Publication No. 2022 / 196092

[0005] [Summary] The signal transmission device disclosed in Patent Document 1 leaves room for further consideration regarding the ability to arbitrarily change the drive speed of the switch element.

[0006] The signal transmission device disclosed in this specification includes a transmitter circuit, a receiver circuit, an isolation circuit, a first drive circuit, and a second drive circuit. The transmitter circuit is configured to output a first internal signal and a second internal signal that are pulse-driven in response to an input signal. The receiver circuit is configured to output a drive signal in response to the first internal signal and the second internal signal. The isolation circuit is configured to transmit the first internal signal and the second internal signal while isolating the transmitter circuit from the receiver circuit. The first drive circuit is configured to drive a switch element in response to the drive signal. The second drive circuit is configured to drive the switch element at a slower speed than the first drive circuit. The transmitter circuit drives at least one of the first internal signal and the second internal signal at a specific cycle different from the cycle of the input signal in response to an external signal different from the input signal. The receiver circuit detects that the cycle of at least one of the first internal signal and the second internal signal is the specific cycle, and disables the first drive circuit and enables the second drive circuit.

[0007] The electronic device disclosed in this specification includes a plurality of switch elements, each of which is a power transistor, and a plurality of gate driver ICs that drive the gates of the plurality of switch elements, at least one of which is the signal transmission device having the above-described configuration.

[0008] The vehicle disclosed in this specification is equipped with the electronic device having the above-described configuration.

[0009] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. FIG. 2 is a diagram showing the basic structure of a transformer chip. FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil is formed in the semiconductor device of FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is a diagram showing an enlarged view (separation structure) of region XIII shown in FIG. 7. FIG. 9 is a diagram schematically showing an example layout of a transformer chip. FIG. 10 is a diagram showing the basic configuration of an electronic device equipped with a signal transmission device of a comparative example. FIG. 11 is a block diagram showing the configuration of a signal transmission device according to a first embodiment of the present disclosure. FIG. 12 is a block diagram showing the internal configuration of a soft turn-off signal detection circuit according to the first embodiment. FIG. 13 is a timing chart showing the states of each signal when the signal transmission device according to the first embodiment switches from a normal state to a soft turn-off execution state. FIG. 14 is a block diagram showing the internal configuration of a soft turn-off signal detection circuit. Fig. 15 is a block diagram showing the configuration of a signal transmission device according to a second embodiment of the present disclosure. Fig. 16 is a block diagram showing the configuration of a soft turn-off signal detection circuit according to a second embodiment of the present disclosure. Fig. 17 is a timing chart showing the states of each signal when the signal transmission device according to the second embodiment performs a soft turn-off of a switch element. Fig. 18 is a block diagram showing an implementation example of the signal transmission device according to the present disclosure. Fig. 19 is a timing chart showing the INH signal, INL signal, GH signal, GL signal, and current values ​​when extracting charge from a smoothing capacitor. Fig. 20 is a timing chart showing the soft turn-off input signal, INH signal, and gate signal in a modified example of the signal transmission device according to the present disclosure.

[0010] [Detailed Description] <Signal Transmission Device (Basic Configuration)> Figure 1 shows the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0011] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (for example, a maximum of 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0012] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. In other words, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signal S11 or S21 in response to the logic level of the input pulse signal IN.

[0013] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0014] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0015] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V relative to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0016] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0017] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0018] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0019] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0020] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0021] More specifically, the transformer 231 outputs a received pulse signal S12 from the secondary coil 231s in response to a transmitted pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a received pulse signal S22 from the secondary coil 232s in response to a transmitted pulse signal S21 input to the primary coil 232p.

[0022] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0023] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, separate from the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0024] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby making it possible to reduce manufacturing costs.

[0025] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or xEVs such as FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0026] <Transformer Chip (Basic Structure)> Next, the basic structure of the transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0027] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0028] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21, surrounding the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23, surrounding the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0029] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via the conductive wiring Y21 and the via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via the conductive wiring Y22 and the via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via the conductive wiring Y23 and the via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0030] The secondary coil 231s is laid in a spiral shape starting from a first end connected to the external terminal T24, surrounding the periphery of the external terminal T24 in a counterclockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape starting from a first end connected to the external terminal T26, surrounding the periphery of the external terminal T26 in a clockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0031] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0032] <Transformer Chip (Two-Channel Type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0033] 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0034] The wide bandgap semiconductor is a semiconductor with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0035] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0036] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0037] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0038] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0039] The insulating sidewalls 53A to 53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form ground surfaces that are flush with the chip sidewalls 44A to 44D.

[0040] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and multiple (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, approximately 2 μm).

[0041] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0042] The second insulating layer 59 is formed on the first insulating layer 58. The second insulating layer 59 contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0043] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0044] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inward of the insulating layer 51 and spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0045] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the description of the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0046] 5 to 7 , the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0047] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0048] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0049] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0050] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0051] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0052] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0053] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0054] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0055] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0056] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0057] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0058] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0059] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0060] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0061] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0062] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0063] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0064] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0065] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0066] The multiple high potential terminals 12 are each formed in a region close to the corresponding transformer 21A to 21D in a plan view. The closeness of the high potential terminal 12 to the transformer 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0067] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0068] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0069] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0070] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0071] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0072] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of the first low potential wirings 31, a plurality of the second low potential wirings 32, a plurality of the first high potential wirings 33, and a plurality of the second high potential wirings 34 are formed.

[0073] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0074] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0075] The plurality of first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. The plurality of first low-potential wirings 31 have the same structure. In the following, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low-potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the description of the structure of the other first low-potential wirings 31, and will be omitted.

[0076] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0077] The through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0079] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0080] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0081] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0082] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0083] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0084] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0085] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0086] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the lead-out wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the lead-out wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the lead-out wiring 73, respectively.

[0087] 6 and 7 , the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23). The plurality of first high-potential wirings 33 each have a similar structure. The following description will be given taking the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0088] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0089] The high-potential connecting wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wiring 81 is formed spaced apart from the low-potential connecting wiring 72 in a plan view and does not face the low-potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wiring 72 and the high-potential connecting wiring 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0090] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the plurality of pad plug electrodes 82 has a planar area that is smaller than the planar area of ​​the high potential connecting wiring 81 in a plan view.

[0091] 7, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2<D1). The distance D1 preferably exceeds the total thickness DT of the multiple interlayer insulating layers 57 (DT<D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of the distance D1 and the distance D2 are arbitrary and are adjusted appropriately depending on the dielectric strength voltage to be achieved.

[0092] 6 and 7, semiconductor device 5 includes dummy patterns 85 embedded in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view.

[0093] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density per unit area equal to that of the high-potential coil 23. Having the line density of the dummy pattern 85 equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0094] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0095] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0096] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0097] The dummy patterns 85 include floating dummy patterns formed in an electrically floating state within the insulating layer 51 so as to be positioned around the transformers 21A to 21D.

[0098] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0099] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0100] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0101] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0102] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0103] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0104] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0105] 5 to 7 , the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0106] The device region 62 is a region that includes the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0107] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0108] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 that surrounds the device region 62 in plan view.

[0109] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0110] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, within the insulating layer 51, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating principal surface 52. Within the insulating layer 51, the seal conductor 61 may face a part of the second functional device 60 in a direction parallel to the insulating principal surface 52.

[0111] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (a plurality in this embodiment) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0112] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0113] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end-shaped form. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) form.

[0114] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0115] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined by the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0116] 7 and 8 , the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0117] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0118] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0119] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0120] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0121] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0122] 7 , the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0123] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. Increasing the total thickness of the inorganic insulating layer 140 can increase the dielectric strength voltage on the high-potential coil 23.

[0124] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable that the first inorganic insulating layer 141 be thicker than the second inorganic insulating layer 142.

[0125] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0126] The inorganic insulating layer 140 covers the entire seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the high potential terminal 12.

[0127] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0128] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Furthermore, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0129] The organic insulating layer 145 includes a first portion 146 covering the low-potential side region and a second portion 147 covering the high-potential side region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in a region outside the seal conductor 61. The first portion 146 may have an overlapping portion that rises onto the periphery (overlapping portion) of the low-potential pad opening 143.

[0130] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0131] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0132] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may also be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0133] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0134] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0135] In the above embodiment, the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0136] In the above-described embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes a plurality of transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0137] 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0138] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s forming a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s forming a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0139] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0140] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0141] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0142] Pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0143] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are drawn out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0144] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0145] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break has occurred in each coil, but also to appropriately reject defective products in which an abnormal resistance value has occurred in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0146] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0147] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0148] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0149] 9, the first transformer 301 to the fourth transformer 304 are arranged in a coupled arrangement according to the respective signal transmission directions. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary chip to the secondary chip, are formed into a first pair by a first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary chip to the primary chip, are formed into a second pair by a second guard ring 306.

[0150] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0151] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0152] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0153] 9, it is desirable that the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are wound so as to form a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. By using such a configuration, the area where the primary coil and the secondary coil overlap each other becomes larger, which makes it possible to improve the transmission efficiency of the transformer.

[0154] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0155] <Considerations on the Soft Turn-Off Function of the Signal Transmission Device> The signal transmission device 200 described above has a soft turn-off function that softly turns off the switch element provided in the secondary circuit system 200s. Soft turn-off is a turn-off operation in which the gate voltage falling slew rate is lower than that during normal turn-off, and the transition time from the ON state to the OFF state is relatively long. This switch control allows charge to be extracted from the gate of the switch element more slowly during protection operation than during normal turn-off. This, for example, can prevent momentary interruptions in the motor current during protection operation, thereby suppressing surges caused by back electromotive force in the motor coil. The configuration related to the soft turn-off function will be described in detail below, taking the electronic device 400 equipped with the signal transmission device 200 described above as an example.

[0156] <Regarding the signal transmission device 200Y as a comparative example> First, the signal transmission device 200Y will be described as a comparative example to the signal transmission device 200X of the present disclosure. Next, problems with the comparative example will be described, followed by a description of the signal transmission device 200X of the present disclosure. Note that both the signal transmission devices 200X and 200Y correspond to the signal transmission device 200 described above.

[0157] 10 is a diagram showing the basic configuration of an electronic device 400 equipped with a signal transmission device 200Y of the comparative example. The electronic device 400 of this configuration example is a type of motor drive device that converts DC power supplied from an in-vehicle battery (not shown) into AC power to drive a motor M (see FIG. 18 described later).

[0158] The electronic device 400 includes a signal transmission device 200Y, an ECU (electronic control unit) 2, and a plurality of discrete components (a switch element SW, diodes D1 and D2, and resistors R1 to R3).

[0159] The signal transmission device 200Y is a semiconductor integrated circuit device configured to transmit a gate drive signal from a primary circuit system (VCC1-GND1) to a secondary circuit system (VCC2-GND2) while isolating the primary circuit system from the secondary circuit system.

[0160] The signal transmission device 200Y has multiple external terminals (in this figure, a VCC1 terminal, an IN terminal (input terminal), a VCC2 terminal, an OUT terminal (first output terminal), and a PROOUT terminal (second output terminal)) as means for establishing electrical connection with the outside of the device.

[0161] The VCC1 terminal is a power supply terminal for the primary circuit system. The primary circuit system receives power from a voltage source E1 via the VCC1 terminal. The VCC2 terminal is a power supply terminal for the secondary circuit system. The secondary circuit system receives power from a voltage source E2 via the VCC2 terminal.

[0162] The IN terminal is a control input terminal. The IN terminal receives an input signal IN from the ECU 2. The ECU 2 is a means for comprehensively controlling the motor drive device and the vehicle in which the motor drive device is installed. The ECU 2 drives the input signal IN by switching between a high level (based on VCC1) and a low level (based on GND1).

[0163] The OUT terminal is an output terminal that outputs a drive signal Ga (first output signal) for driving the switch element SW. The OUT terminal is connected to the gate terminal of the switch element SW via resistors R1 and R2 and diodes D1 and D2.

[0164] The PROOUT terminal is an output terminal that outputs a control signal (a drive signal Gb, described later) for softly turning off the switch element SW. The PROOUT terminal is connected to the gate terminal of the switch element SW via a resistor R3. The resistance value of the resistor R3 is greater than the resistance values ​​of the resistors R1 and R2.

[0165] The OUT terminal outputs a drive signal Ga at a high level (based on VCC2) or a low level (based on GND2). The PROOUT terminal outputs a drive signal Gb that transitions relatively gradually from high to low. When the drive signal Ga is output, the drive signal Gb is not output (a state in which the output circuit 501 described later is enabled and the soft turn-off circuit 502 described later is disabled). Conversely, when the drive signal Gb is output, the drive signal Ga is not output (a state in which the output circuit 501 is disabled and the soft turn-off circuit 502 is enabled). Details of the internal configuration and operation of the signal transmission device 200Y related to the drive signals Ga and Gb will be described later.

[0166] The switch element SW is preferably a power semiconductor element capable of operating at high frequencies, such as an IGBT, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a SiC-MOSFET (Silicon Carbide-Metal Oxide Semiconductor FET), a SiC-SIT (SiC-Static Induction Transistor), or a GaN-MOSFET (Gallium Nitride-MOSFET). As shown in FIG. 10 , the electronic device 400 uses an IGBT as the switch element SW.

[0167] The gate signal Vge input to the gate terminal of the switch element SW changes in response to the drive signals Ga and Gb. That is, the signal transmission device 200Y controls the drive of the switch element SW using the drive signals Ga and Gb.

[0168] Specifically, when the gate signal Vge is at a high level (exceeding the threshold voltage of the switch element SW), the switch element SW turns on. When the gate signal Vge is at a low level (not exceeding the threshold voltage of the switch element SW), the switch element SW turns off. When the gate signal Vge transitions relatively slowly from a high level to a low level, the switch element SW turns off relatively slowly (so-called soft turn-off). Details of the soft turn-off will be described later.

[0169] The collector of the switch element SW is connected to a node n1, and the emitter of the switch element SW is connected to a node n2. Specific examples of the nodes n1 and n2 will be described later.

[0170] <Internal Configuration of Signal Transmission Device 200Y> Next, the internal configuration of the signal transmission device 200Y will be described in detail. The signal transmission device 200Y is configured by sealing a first semiconductor chip 410y, a second semiconductor chip 420y, and a third semiconductor chip 430 in a single package.

[0171] The first semiconductor chip 410y corresponds to the aforementioned primary circuit system 200p. The first semiconductor chip 410y is a controller chip on which a controller having the function of generating each signal is integrated. The first semiconductor chip 410y is driven by receiving a power supply voltage VCC1 from a voltage source E1. The first semiconductor chip 410y generates a first internal signal S1 and a second internal signal S2 based on an input signal IN.

[0172] The second semiconductor chip 420y corresponds to the aforementioned secondary circuit system 200s. The second semiconductor chip 420y is a driver chip on which a driver for controlling the drive of the switch element SW is integrated. The second semiconductor chip 420y is driven by receiving a power supply voltage VCC2 from a voltage source E2. The second semiconductor chip 420y receives a first internal signal S1 and a second internal signal S2 from the first semiconductor chip 410y via the third semiconductor chip 430. The second semiconductor chip 420y generates a drive signal Ga based on the first internal signal S1 and the second internal signal S2. The second semiconductor chip 420y also generates a drive signal Gb.

[0173] The third semiconductor chip 430 is a transformer chip on which multiple transformers (a first transformer 431 and a second transformer 432, which will be described later) are integrated. The third semiconductor chip 430 transmits the first internal signal S1 and the second internal signal S2 while providing DC insulation between the first semiconductor chip 410y and the second semiconductor chip 420y.

[0174] The first semiconductor chip 410y includes a logic circuit 415y, a first transmission circuit 411, and a second transmission circuit 412.

[0175] The logic circuit 415y receives an input signal IN input from the ECU 2, generates a first internal signal S1 and a second internal signal S2, and inputs them to the first transmission circuit 411 and the second transmission circuit 412, respectively.

[0176] The first transmission circuit 411 transmits the first internal signal S1 input from the logic circuit 415 y to the first reception circuit 421 via the first transformer 431 .

[0177] The second transmission circuit 412 transmits the second internal signal S2 input from the logic circuit 415y to the second reception circuit 422 via the second transformer 432.

[0178] The second semiconductor chip 420y has a first receiving circuit 421, a second receiving circuit 422, a logic circuit 425, a driver circuit 426y, an output circuit 501 (first drive circuit), and a soft turn-off circuit 502 (second drive circuit).

[0179] The first receiving circuit 421 receives the first internal signal S1 from the first transmitting circuit 411 via the first transformer 431 and inputs the signal S1 to the logic circuit 425 .

[0180] The second receiving circuit 422 receives the second internal signal S2 from the second transmitting circuit 412 via the second transformer 432 and inputs the signal S2 to the logic circuit 425 .

[0181] The logic circuit 425 generates a driver control signal S4 based on the input first internal signal S1 and second internal signal S2, and inputs the signal to the driver circuit 426y.

[0182] The driver circuit 426y generates drive signals Gc, Gd, and Ge based on the input driver control signal S4. The driver circuit 426y controls the output circuit 501 using the drive signals Gc and Gd. The driver circuit 426y also controls the soft turn-off circuit 502 using the drive signal Ge.

[0183] The output circuit 501 includes a transistor P1 and a transistor N1. The transistor P1 is a P-channel MOSFET. The transistor N1 is an N-channel MOSFET.

[0184] The source of the transistor P1 is connected to the VCC2 terminal. The drains of the transistors P1 and N1 are both connected to the OUT terminal. The source of the transistor N1 is connected to the GND2 terminal. The gates of the transistors P1 and N1 are connected to the driver circuit 426y.

[0185] The driving signal Gc is input to the gate terminal of the transistor P1, which is controlled to be turned on and off by the driving signal Gc.

[0186] The driving signal Gd is input to the gate terminal of the transistor N1, and the transistor N1 is controlled to be turned on and off by the driving signal Gd.

[0187] The soft turn-off circuit 502 includes a transistor N2, which is an N-channel MOSFET.

[0188] The drain of the transistor N2 is connected to the PROOUT terminal, the source of the transistor N2 is connected to the GND2 terminal, and the gate of the transistor N2 is connected to the driver circuit 426y.

[0189] The drive signal Ge is input to the gate terminal of the transistor N2, which is controlled to be turned on and off by the drive signal Ge.

[0190] Next, the operation of the signal transmission device 200Y will be described. Here, normal on / off control of the switch element SW (control when the switch element SW is not softly turned off) will be described.

[0191] Assume that a high-level input signal IN is input to the IN terminal from the ECU 2. Then, the logic circuit 415y generates a pulse in the first internal signal S1. Specifically, the logic circuit 415y detects a positive edge (a rising edge from low level to high level) of the input signal IN and generates a pulse in the first internal signal S1.

[0192] Conversely, suppose that a low-level input signal IN is input to the IN terminal from the ECU 2. In response, the logic circuit 415y generates a pulse in the second internal signal S2. Specifically, the logic circuit 415y detects a negative edge (a falling edge from high level to low level) of the input signal IN and generates a pulse in the second internal signal S2.

[0193] When the logic circuit 425 receives a pulse of the first internal signal S1, it raises the driver control signal S4 to a high level. Conversely, when the logic circuit 425 receives a pulse of the second internal signal S2, it lowers the driver control signal S4 to a low level.

[0194] When the driver circuit 426y receives a high-level driver control signal S4, it causes the drive signal Gc to fall to a low level and the drive signal Gd to fall to a low level, turning on the transistor P1 and turning off the transistor N1. As a result, a high-level (VCC2 reference) drive signal Ga is output from the OUT terminal.

[0195] Conversely, when the driver circuit 426y receives a low-level driver control signal S4, it raises the drive signal Gc to a high level and also raises the drive signal Gd to a high level, turning off the transistor P1 and turning on the transistor N1. As a result, a low-level (GND reference) drive signal Ga is output from the OUT terminal.

[0196] Unless a soft turn-off execution instruction is input as an abnormality protection function (e.g., an overcurrent protection function, described later), the driver circuit 426y maintains the drive signal Ge at a low level. Therefore, the transistor N2 remains in an off state (the soft turn-off circuit 502 is disabled). That is, no current flows from the gate terminal of the switch element SW to GND2 via the resistor R3, the PROOUT terminal, and the transistor N2. Hereinafter, the state in which the driver circuit 426y enables the output circuit 501 and disables the soft turn-off circuit 502 will be referred to simply as the "normal state."

[0197] <Considerations Regarding Soft Turn-Off> As described above, the signal transmission device 200Y has a function of softly turning off the switch element SW. For example, the signal transmission device 200Y is configured to be able to perform soft turn-off as an overcurrent protection function when it detects that an overcurrent is flowing between the collector and emitter of the switch element SW. Note that an overcurrent detection circuit (not shown) that detects the above-mentioned overcurrent may be provided either inside or outside the signal transmission device 200Y.

[0198] When the overcurrent detection circuit detects an overcurrent, the driver circuit 426y disables the output circuit 501 and enables the soft turn-off circuit 502. That is, the driver circuit 426y raises the drive signal Gc to a high level, lowers the drive signal Gd to a low level, and raises the drive signal Ge to a high level. This turns off the transistors P1 and N1 and turns on the transistor N2. Then, a low-level (GND reference) drive signal Gb is output from the PROOUT terminal.

[0199] At this time, charge is extracted from the gate terminal of the switch element SW to GND2 via resistor R3, the PROOUT terminal, and transistor N2. This causes the switch element SW to be soft turned off. Note that the state in which the driver circuit 426y disables the output circuit 501 and enables the soft turn-off circuit 502 is also referred to simply as the "soft turn-off execution state" below.

[0200] Specifically, this is as follows. As described above, the resistor R3 has a larger resistance value than the resistors R1 and R2. Therefore, the time it takes for the gate signal Vge to transition from high to low in the soft turn-off execution state is longer than the time it takes for the gate signal Vge to transition from high to low in the normal state. In other words, the slew rate of the gate signal Vge in the soft turn-off execution state is lower than the slew rate when the gate signal Vge transitions from high to low in the normal state. Therefore, the switch element SW in the soft turn-off execution state is driven at a slower speed than in the normal state, and is turned off relatively gradually (softly turned off).

[0201] The overcurrent detection circuit described above transmits the detection result directly to the second semiconductor chip 420y (more specifically, the driver circuit 426y) without going through the first semiconductor chip 410y (not shown).

[0202] However, there is a demand for soft-turning off the switch element SW at will for a purpose other than the above-mentioned purpose (= overcurrent protection). In such a case, it is necessary to transmit a signal for soft-turning off the switch element SW from the ECU 2 side (= first semiconductor chip 410y side) to the second semiconductor chip 420y.

[0203] However, as described above, the instruction to execute a soft turn-off due to the overcurrent protection function is input directly to the second semiconductor chip 420y (not shown) without passing through the first semiconductor chip 410y. Therefore, with a configuration such as the signal transmission device 200Y described above, a control signal for executing a soft turn-off cannot be transmitted from the primary circuit system side (the first semiconductor chip 410y side in FIG. 10, more specifically, the ECU 2 side) to the secondary circuit system side (the second semiconductor chip 420y side in FIG. 10). In other words, a soft turn-off cannot be arbitrarily executed by a central control means such as the ECU 2.

[0204] To address this problem, the signal transmission device 200X of the present disclosure is capable of arbitrarily executing a soft turn-off by an overall control means such as the ECU 2. The signal transmission device 200X according to each embodiment of the present disclosure will be described in detail below. The signal transmission device 200X according to each embodiment of the present disclosure includes components common to the signal transmission device 200Y described above. Therefore, the common components are denoted by the same reference numerals and will not be described again.

[0205] <Regarding the signal transmission device 200X according to the first embodiment of the present disclosure> Fig. 11 is a block diagram showing the configuration of the signal transmission device 200X according to the first embodiment of the present disclosure. As shown in Fig. 11, the signal transmission device 200X according to the embodiment of the present disclosure is used in an electronic device 400. The signal transmission device 200X is formed by sealing a first semiconductor chip 410x (transmitting circuit), a second semiconductor chip 420x (receiving circuit), and a third semiconductor chip 430 (isolation circuit) in a single package.

[0206] The signal transmission device 200X has a plurality of external terminals (in this figure, a VCC1 terminal, an IN terminal, an ASC terminal, a VCC2 terminal, an OUT terminal, and a PROOUT terminal) as means for establishing electrical connection with the outside of the device.

[0207] The ECU 2 inputs a soft turn-off input signal ASC, which can be switched between a high level (based on VCC1) and a low level (based on GND1), to the ASC terminal. For example, when soft turn-off of the switch element SW is to be executed, the ECU 2 sets the soft turn-off input signal ASC to a high level. Conversely, when soft turn-off of the switch element SW is not to be executed, the ECU 2 sets the soft turn input signal ASC to a low level.

[0208] The first semiconductor chip 410x corresponds to the primary circuit system 200p mentioned above. The first semiconductor chip 410x is a controller chip on which a controller having a function of generating each signal is integrated. The first semiconductor chip 410x is driven by receiving a power supply voltage VCC1 from a voltage source E1. The first semiconductor chip 410x generates a first internal signal S1 and a second internal signal S2 based on an input signal IN and a soft turn-off input signal ASC.

[0209] The second semiconductor chip 420x corresponds to the aforementioned secondary circuit system 200s. The second semiconductor chip 420x is a driver chip on which a driver for controlling the drive of the switch element SW is integrated. The second semiconductor chip 420x is driven by receiving a power supply voltage VCC2 from a voltage source E2. The second semiconductor chip 420x receives the first internal signal S1 and the second internal signal S2 from the first semiconductor chip 410x via the third semiconductor chip 430. The second semiconductor chip 420x generates drive signals Ga and Gb based on the first internal signal S1 and the second internal signal S2.

[0210] The first semiconductor chip 410 x includes a logic circuit 415 x , a first transmission circuit 411 , and a second transmission circuit 412 .

[0211] The logic circuit 415x receives the input signal IN and the soft turn-off input signal ASC input from the ECU 2, and generates a first internal signal S1 and a second internal signal S2.

[0212] The second semiconductor chip 420x has a first receiving circuit 421, a soft turn-off signal detection circuit 427 (detection signal generation circuit), a second receiving circuit 422, a logic circuit 425, a driver circuit 426x (drive switching circuit), an output circuit 501, and a soft turn-off circuit 502.

[0213] The soft turn-off signal detection circuit 427 generates a soft turn-off control signal S5 (detection signal) in response to the output V1 of the first receiving circuit 421. The voltage value of the output V1 corresponds to the signal level of the first internal signal S1. The generation of the soft turn-off control signal S5 will be described in detail later.

[0214] The driver circuit 426x generates the drive signals Gc, Gd, and Ge based on the driver control signal S4 and the soft turn-off control signal S5. The driver circuit 426x is basically the same as the driver circuit 426y described above, and only the differences will be described below.

[0215] Next, the operation of the signal transmission device 200X will be described. First, normal on / off control of the switch element SW (control when the switch element SW is not softly turned off) will be described.

[0216] In this case, the ECU 2 sets the soft turn-off input signal ASC to a low level. When a low-level soft turn-off input signal ASC is input to the ASC terminal, the logic circuit 415x generates periodic pulses in the first internal signal S1 and the second internal signal S2 in accordance with the input signal IN, similar to the logic circuit 415y described above. The pulse period of the first internal signal S1 and the second internal signal S2 at this time (when the soft turn-off input signal ASC is at a low level, i.e., when soft turn-off is not being executed) is set as the reference period.

[0217] The soft turn-off signal detection circuit 427 monitors the output V1 to detect the pulse period of the first internal signal S1. When the first internal signal S1 is pulse-driven at the reference period, the soft turn-off signal detection circuit 427 sets the soft turn-off control signal S5 to a low level (third logic level).

[0218] When the soft turn-off control signal S5 is at a low level, the driver circuit 426x enables the output circuit 501 and disables the soft turn-off circuit 502. More specifically, at this time, the driver circuit 426x generates drive signals Gc and Gd based on the driver control signal S4 to control the on / off of transistors P1 and N1. At the same time, the driver circuit 426x generates drive signal Ge to control transistor N2 to turn it off. This causes the switch element SW to be on / off controlled in accordance with the IN signal.

[0219] Next, the operation of the signal transmission device 200X when performing a soft turn-off will be described. In this case, the ECU 2 sets the soft turn-off input signal ASC to a high level. When the high-level soft turn-off input signal ASC is input to the ASC terminal, the logic circuit 415x pulses the first internal signal S1 at a specific period different from the reference period. More specifically, the logic circuit 415x detects a rising edge of the soft turn-off input signal ASC and begins pulsing the first internal signal S1 at the specific period.

[0220] For example, if the reference period is set to 100 ns, the specific period will be a period different from 100 ns. In this example, the specific period is set to 50 ns.

[0221] When the soft turn-off signal detection circuit 427 detects that the first internal signal S1 is pulse-driven at a specific period, it raises the soft turn-off control signal S5 to a high level (fourth logic level).

[0222] When the soft turn-off control signal S5 is at a high level, the driver circuit 426x enters a soft turn-off execution state. That is, at this time, the driver circuit 426x generates drive signals Gc to Ge so that the transistors P1 and N1 are turned off and the transistor N2 is turned on. In this state, the switch element SW is soft turned off as described above.

[0223] <Soft Turn-Off Signal Detection Circuit> Next, a detailed configuration of the soft turn-off signal detection circuit 427 will be described. Fig. 12 is a block diagram showing the internal configuration of the soft turn-off signal detection circuit 427 according to the first embodiment. As shown in Fig. 12, the soft turn-off signal detection circuit 427 includes a timer circuit 503, an AND gate 504, a UVLO circuit 505, a counter circuit 506, and an oscillator OSC.

[0224] The timer circuit 503 generates a timer drive signal S6 that corresponds to the pulse period of the first internal signal S1. More specifically, the timer circuit 503 monitors the output V1 to detect a pulse of the first internal signal S1. When the timer circuit 503 detects a pulse of the first internal signal S1, it raises the timer drive signal S6 to a high level (first logic level). The timing at which this timer drive signal S6 rises to a high level (= the timing at which the pulse of the first internal signal S1 is detected) is referred to here as the pulse detection timing (first timing).

[0225] When a first set time T1 has elapsed between the detection of one pulse and the detection of the next pulse, the timer circuit 503 causes the timer drive signal S6 to fall to a low level (second logic level). The first set time T1 is set to a time shorter than the reference period.

[0226] That is, when the first internal signal S1 is pulse-driven at the reference period, the timer drive signal S6 falls to a low level when the first set time T1 has elapsed since the pulse detection timing. Conversely, when the first internal signal S1 is pulse-driven at a period (i.e., a specific period) longer than the reference period, the next pulse detection timing arrives before the first set time T1 has elapsed since the first timing. Therefore, in this case, the timer drive signal S6 does not fall to a low level but remains at a high level.

[0227] The UVLO circuit 505 and the AND gate 504 constitute an under-voltage lockout function. That is, the UVLO circuit 505 basically inputs a high-level control signal to the AND gate 504. When the power supply voltage drops below a predetermined UVLO detection voltage (not shown) during operation of the electronic device 400, the UVLO circuit 505 inputs a low-level control signal to the AND gate 504. For ease of explanation, the UVLO circuit 505 is depicted in this figure as a component of the soft turn-off signal detection circuit 427. However, the UVLO circuit 505 can also be understood as one of the protection circuits for the second semiconductor chip 420x.

[0228] When the UVLO circuit 505 outputs a high-level control signal (when the power supply voltage exceeds the UVLO detection voltage while the electronic device 400 is operating), the AND gate 504 inputs an output signal S7 corresponding to the logic level of the timer drive signal S6 to the counter circuit 506. When the UVLO circuit 505 outputs a low-level control signal (when the power supply voltage falls below the UVLO detection voltage while the electronic device 400 is operating), the AND gate 504 outputs a low-level output signal S7 regardless of the timer drive signal S6. Therefore, even if the first internal signal S1 is pulse-driven at a specific period, soft turn-off is not executed.

[0229] The counter circuit 506 generates the soft turn-off control signal S5 according to the timer drive signal S6. Specifically, the counter circuit 506 detects the time during which the logic level of the timer drive signal S6 is maintained from the timing at which the logic level of the timer drive signal S6 switches. More specifically, the counter circuit 506 detects the time during which the high level is maintained from the rising edge of the timer drive signal S6.

[0230] In other words, the counter circuit 506 detects whether the timer drive signal S6 has switched to a low level within the second set time T2 from the timing (second timing) at which the timer drive signal S6 has switched to a high level, where the second set time T2 can be set to, for example, 160 ns.

[0231] Assume that the timer drive signal S6 remains at a high level until the second set time T2 has elapsed since the timer drive signal S6 switched to a high level. In this case, the counter circuit 506 sets the soft turn-off control signal S5 to a high level when the second set time T2 has elapsed. Assume that the timer drive signal S6 switches back to a low level before the second set time T2 has elapsed since the timer drive signal S6 switched to a high level. At this time, the counter circuit 506 sets the soft turn-off control signal S5 to a low level.

[0232] 13 is a timing chart showing the states of each signal when the signal transmission device 200X according to the first embodiment switches from a normal state to a soft turn-off execution state. From top to bottom, FIG. 13 shows the soft turn-off input signal ASC, the first internal signal S1, the timer drive signal S6, the soft turn-off control signal S5, and the gate signal Vge. The soft turn-off control of the switch element SW will be described in more detail with reference to FIG. 13.

[0233] While the soft turn-off input signal ASC is at a low level (from time t11 to time t14 in FIG. 13), the logic circuit 415x pulses the first internal signal S1 at the reference period.

[0234] First, at time t11, when a pulse occurs in the first internal signal S1, the timer drive signal S6 rises to a high level. At time t12, when the first set time T1 has elapsed since time t11, the timer drive signal S6 falls to a low level. The interval from time t11 to time t12 is shorter than the second set time T2. Therefore, the soft turn-off control signal S5 remains at a low level.

[0235] When time t13 arrives and a pulse rises again in the first internal signal S1, the timer drive signal S6 also rises to a high level again.

[0236] After that, at time t14, the soft turn-off input signal ASC rises to a high level. Then, the logic circuit 415x starts driving the first internal signal S1 in pulses at a specific cycle, starting from the previous detection timing (time t13). At time t15, the next pulse of the first internal signal S1 rises. The interval between time t13 and time t15 is one cycle of the specific cycle.

[0237] As described above, the specific period is shorter than the first set time T1. Therefore, the next detection timing (= t15) arrives before the first set time T1 has elapsed from time t13. Then, the timer drive signal S6 remains at a high level without falling to a low level.

[0238] After time t15, the soft turn-off input signal ASC remains high, and the first internal signal S1 continues to pulse at a specific cycle. Then, at time t16, which is the second set time T2 after time t15, the soft turn-off control signal S5 rises to high. This causes the driver circuit 426x to turn off transistors P1 and N1 and turn on transistor N2 (not shown). As described above, when transistor N2 turns on, charge is extracted from the gate terminal of the switch element SW, causing the switch element SW to softly turn off. Therefore, from time t16 to time t17, the gate signal Vge decreases relatively slowly at a predetermined slew rate.

[0239] <Configuration of Counter Circuit 506> Next, the configuration of the counter circuit 506 will be described. Fig. 14 is a block diagram showing the internal configuration of the counter circuit 506. As shown in Fig. 14, the counter circuit 506 includes D flip-flops DFF1 to DFF4 and an inverter INV1. The counter circuit 506 counts the number of pulses of the clock signal CLKH generated by the oscillator OSC, and generates a set signal (soft turn-off control signal S5).

[0240] The clock terminals of the D flip-flops DFF1 to DFF4 are connected to the terminal to which the clock signal CLKH is applied. The data terminal (D) of the D flip-flop DFF1 is connected to the terminal to which a high-level signal is applied (= VCC2 terminal). The output terminal (Q) of the D flip-flop DFF1 is connected to the data terminal (D) of the D flip-flop DFF2. The output terminal (Q) of the D flip-flop DFF2 is connected to the data terminal (D) of the D flip-flop DFF3. The output terminal (Q) of the D flip-flop DFF3 is connected to the data terminal (D) of the D flip-flop DFF4. The output terminal (Q) of the D flip-flop DFF4 is connected to the input terminal of the driver circuit 426x as the output terminal for the set signal S.

[0241] The reset terminal (R) of each of the D flip-flops DFF1 to DFF4 is connected to a terminal to which a reset signal RSTH is applied. The reset signal RSTH is a logically inverted signal of the output signal S7, and is generated by an inverter INV1. The inverter INV1 receives the output signal S7 of the AND gate 504 and generates the reset signal RSTH.

[0242] Counter circuit 506 having the above configuration is configured to count the number of pulses of clock signal CLKH. When the count reaches a predetermined value (4 in this figure), it raises soft turn-off control signal S5 to high level. Note that this predetermined value can be set arbitrarily by changing the number of stages of D flip-flops.

[0243] In addition, the counter circuit 506 is reset when the reset signal RSTH falls to a low level (i.e., when the output signal S7 rises to a high level, in other words, when the timer drive signal S6 rises to a high level), and the count value is returned to the initial value (=0).

[0244] The second set time T2 can be defined based on the predetermined value (the number of D flip-flop stages) and the frequency of the clock signal CLKH. Here, the predetermined value is set to 4, and the frequency of the clock signal CLKH is set to 25.6 MHz. As a result, the time it takes for the count value to reach the predetermined value is 156 ns.

[0245] <Regarding the signal transmission device 200X according to the second embodiment> Next, a second embodiment of the signal transmission device 200X will be described. Note that, hereinafter, differences from the first embodiment will be described, and configurations similar to those in the first embodiment will be denoted by the same reference numerals and will not be described again.

[0246] Fig. 15 is a block diagram showing the configuration of a signal transmission device 200X according to a second embodiment of the present disclosure. Fig. 16 is a block diagram showing the configuration of a soft turn-off signal detection circuit 427 according to the second embodiment of the present disclosure. As shown in Figs. 15 and 16, the soft turn-off signal detection circuit 427 according to this embodiment generates a soft turn-off control signal S5 in response to the output V1 of the first receiving circuit 421 and the output V2 of the second receiving circuit 422. The voltage value of the output V2 corresponds to the signal level of the second internal signal S2.

[0247] The timer circuit 503 according to this embodiment generates a timer drive signal S6 according to the pulse period of the first internal signal S1 and the pulse period of the second internal signal S2. More specifically, this is as follows.

[0248] The timer circuit 503 monitors the output V1 to detect a pulse of the first internal signal S1. The timer circuit 503 also monitors the output V2 to detect a pulse of the second internal signal S2. When the timer circuit 503 detects a pulse of the first internal signal S1 and a pulse of the second internal signal S2, it raises the timer drive signal S6 to a high level.

[0249] When the first internal signal S1 and the second internal signal S2 are pulse-driven at the reference period, the timer drive signal S6 falls to a low level when the first set time T1 has elapsed since the first timing. Conversely, when the first internal signal S1 and the second internal signal S2 are pulse-driven at a period (specific period) longer than the reference period, the next pulse detection timing arrives before the first set time T1 has elapsed since the pulse detection timing. In other words, when the first internal signal S1 and the second internal signal S2 are pulse-driven at the specific period, the timer drive signal S6 does not fall to a low level but remains at a high level.

[0250] 17 is a timing chart showing the states of each signal when the signal transmission device 200X according to the second embodiment performs a soft turn-off of the switch element SW. From top to bottom, the timing chart shows the soft turn-off input signal ASC, the input signal IN, the first internal signal S1, the second internal signal S2, the timer drive signal S6, the soft turn-off control signal S5, and the gate signal Vge. The soft turn-off control of the switch element SW will be described with reference to FIG. 17.

[0251] While the soft turn-off input signal ASC is at a low level (until time t24 in FIG. 17 ), the logic circuit 415x pulses either the first internal signal S1 or the second internal signal S2 at the reference period. Specifically, when the input signal IN is at a high level (from time t21 to t25), the logic circuit 415x pulses the first internal signal S1 at the reference period and does not drive the second internal signal S2. When the input signal IN is at a low level (from time t25 to t27), the logic circuit 415x pulses the second internal signal S2 at the reference period and does not drive the first internal signal S1.

[0252] Between times t21 and t25, the soft turn-off input signal ASC, input signal IN, first internal signal S1, timer drive signal S6, soft turn-off control signal S5, and gate signal Vge operate in the same manner as in the first embodiment described above (see times t11 to t14 in FIG. 13). Between times t21 and t25, the second internal signal S2 remains at a low level.

[0253] At time t25, the input signal IN falls to a low level. Then, at time t26, which is one reference period after time t23, the second internal signal S2 pulses. At this time, the timer circuit 503 receives the pulse of the second internal signal S2 and raises the timer drive signal S6 to a high level.

[0254] The second internal signal S2 pulses at the reference period until time t27 when the input signal IN rises to high level again. From time t26 to time t27, the timer drive signal S6 receives the pulse of the second internal signal S2 and rises to high level, and then falls to low level after the first set time T1 has elapsed. This operation is repeated.

[0255] When time t27 arrives, the soft turn-off input signal ASC rises to a high level. Then, the first internal signal S1 starts pulsing at a specific cycle, starting from time t27', which is the detection timing immediately before time t27. Then, a pulse of the first internal signal S1 rises before the first set time T1 has elapsed from time t27. As a result, the timer drive signal S6 remains at a high level between times t27 and t28 without falling to a low level.

[0256] At time t28, which is the second set time T2 after time t27', the soft turn-off control signal S5 rises to a high level. The input signal IN remains high until time t29. Therefore, the driver circuit 426x generates drive signals Gc to Ge (not shown) to maintain a normal state (a state in which the output circuit 501 is enabled and the soft turn-off circuit 502 is disabled) until time t29. That is, from time t27 to time t29, transistor P1 is on and transistors N1 and N2 are off. Therefore, the gate signal Vge is maintained at a high level from time t27 to time t29.

[0257] When time t29 arrives and input signal IN falls to a low level, internal signal S2 continues to pulse at a specific frequency until input signal IN rises to a high level (not shown). Then, driver circuit 426x raises drive signal Ga to a high level, lowers drive signal Gb to a low level, and raises drive signal Gc to a high level, turning off transistors P1 and N1 and turning on transistor N2 (not shown). This causes charge to be drawn from the gate terminal of switch element SW to GND2 via the PROOUT terminal, softly turning off switch element SW. Therefore, from time t29 to time t30, gate signal Vge gradually decreases at a predetermined slew rate.

[0258] As described above, the signal transmission device 200X according to each of the above embodiments can execute the soft turn-off operation of the switch element SW from the first semiconductor chip 410x side (=ECU 2 side). That is, it is possible to execute the soft turn-off of the switch element to be driven (the switch element SW in each of the above embodiments) arbitrarily by an overall control means such as the ECU 2.

[0259] As described above, the signal transmission device 200X according to each of the above embodiments pulses the first internal signal S1 at a specific period and performs a soft turn-off by detecting that the pulse period of the first internal signal S1 is the specific period. That is, there is no need to provide a separate signal transmission path for transmitting a control signal for performing a soft turn-off other than the transmission path of the first internal signal S1 (the path consisting of the first transmission circuit 411, the first transformer 431, and the first reception circuit 421) and the transmission path of the second internal signal S2 (the second transmission circuit 412, the second transformer 431, and the second reception circuit 422). Therefore, the signal transmission device 200X according to each of the above embodiments can suppress an increase in the circuit area of ​​each of the primary circuit system, the secondary circuit system, and the isolation circuit. Furthermore, a signal transmission device configured by encapsulating the first semiconductor chip 410x, the second semiconductor chip 420x, and the third semiconductor chip 430 in a single chip, such as the signal transmission device 200X, can suppress an increase in the chip size.

[0260] 18 is a block diagram showing an implementation example of the signal transmission device 200X of the present disclosure. An electronic device 400 equipped with the signal transmission device 200X of the present disclosure can be suitably used in an engine vehicle or an electric vehicle 450. The electronic device 400 can be suitably used as a motor drive device that controls the drive of a motor M mounted on the vehicle 450.

[0261] The motor M is a three-phase motor that is rotated and driven in response to three-phase drive voltages U / V / W input from three-phase (U-phase / V-phase / W-phase) half-bridge output stages.

[0262] The electronic device 400 includes three insulated gate drivers 1H (u / v / w), three insulated gate drivers 1L (u / v / w), three high-side switch elements SWH (u / v / w), three low-side switch elements SWL (u / v / w), an ECU 2, and a smoothing capacitor 600.

[0263] The insulated gate drivers 1H(u / v / w) drive the high-side switch elements SWH(u / v / w) by generating upper gate drive signals (corresponding to the aforementioned output signals OUT) in response to upper gate control signals (corresponding to the aforementioned input signals IN) input from the ECU 2 while insulating the ECU 2 from the high-side switch elements SWH(u / v / w).

[0264] The insulated gate drivers 1L (u / v / w) drive the low-side switch elements SWL (u / v / w) by generating a low-side gate drive signal in response to a low-side gate control signal input from the ECU 2 while insulating the ECU 2 from the low-side switch elements SWL (u / v / w).

[0265] The high-side switch elements SWH(u / v / w) are gate-driven by respective insulated gate drivers 1H(u / v / w), and are connected between a power system power supply terminal (= an application terminal of the first motor drive voltage VD1) and each phase input terminal of the motor M.

[0266] The low-side switch elements SWL(u / v / w) are gate-driven by respective insulated gate drivers 1L(u / v / w), and are connected between the input terminals of each phase of the motor M and the power system ground terminal (= the terminal to which the second motor drive voltage VD2 is applied).

[0267] In this figure, IGBTs are used as the high-side switch element SWH (u / v / w) and the low-side switch element SWL (u / v / w), but as mentioned above, SiC-MOSFETs or Si-MOSFETs can also be used instead of IGBTs.

[0268] The ECU 2 controls the rotational driving of the motor M by driving the high-side switch element SWH(u / v / w) and the low-side switch element SWL(u / v / w) via the insulated gate drivers 1H(u / v / w) and 1L(u / v / w), respectively. The ECU 2 also has a function of monitoring the FLT1 terminal and the FLT2 terminal of each of the insulated gate drivers 1H(u / v / w) and 1L(u / v / w) to perform various safety controls.

[0269] A smoothing capacitor 600 is provided to smooth the voltage between the application terminals of the first motor drive voltage VD1 and the second motor drive voltage VD2. The smoothing capacitor 600 stabilizes the DC voltage (= the voltage between the application terminals of the first motor drive voltage VD1 and the second motor drive voltage VD2) that fluctuates in accordance with fluctuations in the power consumption of the motor M.

[0270] Here, the aforementioned signal transmission device 200X can be suitably used as the insulated gate drivers 1H (u / v / w) and 1L (u / v / w), respectively. For example, the insulated gate driver 1H and the insulated gate driver 1L of one of the three phases (for example, the U phase in accordance with this figure) can be the aforementioned signal transmission device 200X.

[0271] In this case, a state in which the high-side switch element SWHu is turned on and the low-side switch element SWLu is soft-turned off (first state) and a state in which the high-side switch element SWHu is soft-turned off and the low-side switch element SWLu is turned on (second state) are alternately repeated. This makes it possible to extract the charge from the smoothing capacitor 600. More specifically, this is as follows.

[0272] 19 is a timing chart showing the INH signal (a control signal input from the ECU 2 to the insulated gate driver 1Hu), the INL signal (a control signal input to the insulated gate driver 1Lu), the GH signal (= the gate voltage of the high-side switch element SWHu), the GL signal (= the gate voltage of the low-side switch element SWLu), and the current value CI (= the discharge current flowing through the high-side switch element SWHu and the low-side switch element SWLu) when the charge of the smoothing capacitor 600 is extracted. Although not shown in FIG. 19, the soft turn-off input signal ASC described above is in a high-level state throughout the entire region of FIG. 19 (from t31 to t41).

[0273] 19, the high-side switch element SWHu is turned on when the INH signal is at a high level and soft-turned off when the INH signal is at a low level, while the low-side switch element SWLu is turned off when the INL signal is at a high level and turned on when the INL signal is at a low level.

[0274] First, at time t31, the INH signal rises to a high level. This causes the GH signal to exceed the threshold voltage (the dashed-dotted line in FIG. 19) and rise to a high level. This turns on the high-side switch element SWHu. At this time, the INL signal is at a high level. Therefore, the low-side switch element SWLu is off.

[0275] At time t32, the INH signal falls to a low level. Then, the gate signal GH falls gently. From time t32 to time t33, the gate signal GH falls gently at a predetermined slew rate. This causes the high-side switch element SWHu to be softly turned off. At time t33, the INL signal falls to a low level. Then, the gate signal GL exceeds the threshold voltage (the two-dot chain line in FIG. 19 ) and rises to a high level. This turns on the low-side switch element SWLu. Then, a discharge current flows from the smoothing capacitor 600 via the high-side switch element SWHu and the low-side switch element SWLu.

[0276] At time t35, the INL signal rises to high level, causing the low-side switch element SWLu to be soft-turned off. At time t35, the gate voltage GH falls below the threshold voltage and turns off. This prevents the discharge current from flowing from the smoothing capacitor 600 through the high-side switch element SWHu and the low-side switch element SWLu.

[0277] The current value CI of the discharge current changes depending on the on / off states of the high-side switch element SWHu and the low-side switch element SWLu. As described above, the high-side switch element SWHu is soft-turned off between times t33 and t35. Therefore, the current value CI also gradually decreases at a predetermined slew rate between times t33 and t35. Then, at time t35 when the high-side switch element SWHu turns off, the current value CI becomes zero.

[0278] At time t36, the INH signal rises to high level again, and the gate voltage GH rises to high level. This turns on the high-side switch element SWHu again. At this time, the low-side switch element SWLu is soft turned off. At time t37, the INH signal falls to low level, and the gate signal GH gradually decreases. This causes the high-side switch element SWHu to be soft turned off. At time t38, the GL signal falls below the threshold voltage, and the low-side switch element SWLu turns off. Therefore, from time t36 to t38, as in the case of times t33 to t35, a discharge current flows from the smoothing capacitor 600 via the high-side switch element SWHu and the low-side switch element SWLu.

[0279] At time t39, the INL signal falls to low level again. From time t39 to t40, the operation is the same as from time t34 to time t36.

[0280] At time t41, the GL signal falls below the threshold voltage, turning off the low-side switching element SWLu. Between time t37 and time t41, the INH signal remains at a low level, turning off the high-side switching element SWHu.

[0281] At time t42, when the INH signal rises to a high level, the gate signal GH exceeds the threshold voltage, turning on the high-side switch element SWHu. However, the low-side switch element SWLu remains off. Therefore, no discharge current flows from the smoothing capacitor 600 through the high-side switch element SWHu and the low-side switch element SWLu.

[0282] When the aforementioned signal transmission device 200X is used as the insulated gate driver 1H(u / v / w), the switch SW in Fig. 11 becomes the high-side switch SWH(u / v / w) in Fig. 18. In this case, the node n1 shown in Fig. 11 can be considered to be the application terminal of the first motor drive voltage VD1 in Fig. 18. Furthermore, the node n2 shown in Fig. 11 can be considered to be the connection terminal with the motor M in Fig. 18.

[0283] Furthermore, when the aforementioned signal transmission device 200X is used as the insulated gate driver 1L (u / v / w), the switch SW in Fig. 11 becomes the low-side switch SWL (u / v / w) in Fig. 18. In this case, the node n1 shown in Fig. 10 can be considered to be the connection end with the motor M in Fig. 18. Furthermore, the node n2 shown in Fig. 11 can be considered to be the application end of the second motor drive voltage VD2 in Fig. 18.

[0284] <Modifications> The present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention.

[0285] In the above implementation example of the present disclosure, the U-phase isolated gate driver 1H and isolated gate driver 1L are assumed to be the aforementioned signal transmission device 200X. Alternatively, only the isolated gate driver 1H can be the aforementioned signal transmission device 200X. In this case, the signal transmission device 200X is configured to perform soft turn-off when the INH signal is at high level and a rising edge to high level of the soft turn-off input signal ASC is detected. Figure 20 is a timing chart showing the soft turn-off input signal ASC, the INH signal, and the gate signal GH in this case. This modification will be described using Figure 20.

[0286] In this case, the signal transmission device 200X is in the soft turn-off execution state and soft-turns off the high-side switch element SWHu only when the INH signal is at a high level. Furthermore, when the soft turn-off input signal ASC is input, the signal transmission device 200X fixes (latches) the soft turn-off state until the next timing for switching the logic level of the INH signal arrives (in other words, until the falling edge of the INH signal is detected).

[0287] This will be explained in order using Figure 20. First, at time t51, the soft turn-off input signal ASC rises to a high level. Then, at time t52, the soft turn-off execution state described above is entered. As a result, the gate signal GH gradually decreases at a predetermined slew rate.

[0288] At time t53, the soft turn-off input signal ASC falls to low level. As described above, since the soft turn-off execution state is fixed, the GH signal continues to fall. That is, the high-side switch element SWHu continues to be soft turned off. At time t54, the INH signal falls to low level. This releases the fixation of the soft turn-off state. As a result, the gate signal falls to low level in response to the INH signal. This turns off the high-side switch element SWHu.

[0289] At time t55, the INH signal rises to high level again. This causes the GH signal to rise to high level again, turning on the high-side switch element SWHu. After that, at time t56, the soft turn-off input signal ASC rises to high level. This fixes the soft turn-off execution state again. Therefore, from time t57 onwards, the GH signal gradually falls, causing the high-side switch element SWHu to softly turn off.

[0290] In this implementation example, insulated gate bipolar transistors (IGBTs) are used as the switch element SW, the high-side switch element SWH(u / v / w)u, and the low-side switch element SWL(u / v / w), but the configuration of the half-bridge output stage is not limited to this, and MOS field-effect transistors using SiC semiconductors or MOS field-effect transistors using Si semiconductors may also be used.

[0291] <Additional Notes> The signal transmission device (200X) disclosed in the specification includes a transmission circuit (410x) configured to output a first internal signal (S1) and a second internal signal (S2) that are pulse-driven in response to an input signal (IN), a reception circuit (420x) configured to output drive signals (Ga, Gb) in response to the first internal signal (S1) and the second internal signal (S2), an isolation circuit (430) configured to transmit the first internal signal (S1) and the second internal signal (S2) while insulating between the transmission circuit (410x) and the reception circuit (420x), and a first drive circuit configured to drive a switch element (SW) in response to the drive signal (Ga). The transmission circuit (410x) drives at least one of a first internal signal (S1) and a second internal signal (S2) at a specific period different from the period of the input signal (IN) in response to an external signal (ASC) different from the input signal (IN), and the reception circuit (420x) detects that the period of at least one of the first internal signal (S1) and the second internal signal (S2) is the specific period, and disables the first drive circuit (501) and enables the second drive circuit (502) (first configuration).

[0292] In addition, the signal transmission device (200X) according to the first configuration may be configured such that the transmitting circuit (410x) drives the first internal signal (S1) at a specific period in response to the external signal (ASC), and the receiving circuit (420x) detects that the frequency of the first internal signal (S1) is at a specific period and enables the second driving circuit (502) (second configuration).

[0293] Furthermore, in the signal transmission device (200X) according to the first or second configuration, the receiving circuit (420x) includes a timer circuit (503) configured to generate a timer drive signal (S6) so as to switch between a first logic level and a second logic level in response to a first internal signal (S1), set the timer drive signal (S6) to the first logic level at a first timing of at least one of the rising and falling edges of the first internal signal (S1), and switch the timer drive signal (S6) to the second logic level when a first set time (T1) has elapsed from the first timing before the arrival of the next first timing, and a detection signal (S5) so as to switch between a third logic level and a fourth logic level in response to the timer drive signal (S6), a detection signal generating circuit (427) configured to set the detection signal (S5) to a third logic level when the duration of the first logic level of the input signal (S6) is less than a second set time (T2) and to set the detection signal (S5) to a fourth logic level when the duration is equal to or greater than the second set time (T2); and a drive switching circuit (426x) configured to enable the first drive circuit (501) and disable the second drive circuit (502) when the detection signal (S5) is at the third logic level and to disable the first drive circuit (501) and enable the second drive circuit (502) when the detection signal (S5) is at the fourth logic level, and the first set time (T1) may be configured to be shorter than the period of the input signal (IN) and longer than the specific period (third configuration).

[0294] Furthermore, in the signal transmission device (200X) according to the third configuration, the detection signal generating circuit (427) may be configured to include a reset circuit configured to output a reset signal (RSTH) when the timer drive signal (S6) is at the second logic level, an oscillator circuit (OSC) configured to output a clock signal (CLKH), and a counter circuit (506) configured to count the number of clocks of the clock signal (CLKH) to obtain a count value, and to reset the count value to 0 upon receiving the reset signal (RSTH), thereby measuring the duration based on the count value (fourth configuration).

[0295] The signal transmission device (200X) of any of the first to fourth configurations may be configured so that a first chip (410x) integrating circuit elements of the transmitting circuit (410x), a second chip (420x) integrating circuit elements of the receiving circuit (420x), the first driving circuit (501), and the second driving circuit (502), and a third chip (430x) integrating circuit elements of the isolation circuit (430) are sealed in a single package (fifth configuration).

[0296] In the signal transmission device (200X) of the fifth configuration, the first chip (410x) may be configured to have a first input terminal that receives an input signal (IN) as an external input, and a second input terminal that receives an external signal (ASC) as an external input (sixth configuration).

[0297] In the signal transmission device (200X) according to the fifth or sixth configuration, the first drive circuit (501) may generate a first output signal (Ga) that drives the switch element (SW), and the second chip (420x) may be configured to have a first output terminal that outputs the first output signal (Ga) to the outside (seventh configuration).

[0298] In a signal transmission device (200X) of any of the fifth to seventh configurations, the second drive circuit (502) may be configured to generate a second output signal (Gb) that drives the switch element (SW), and the second chip (420x) may be configured to have a second output terminal (PROOUT) that outputs the second output signal (Gb) to the outside (eighth configuration).

[0299] The electronic device (400) disclosed in the specification includes a plurality of switch elements (SW), each of which is a power transistor, and a plurality of gate driver ICs that drive the gates of the plurality of switch elements (SW), and at least one of the plurality of gate driver ICs is configured to be a signal transmission device (200X) of any of the first to eighth configurations (ninth configuration).

[0300] The vehicle (450) disclosed in the specification is configured to include the electronic device (400) according to the ninth configuration (tenth configuration).

[0301] The signal transmission device (200X) according to the first configuration makes it possible to perform a soft turn-off of the switch element (SW) to be driven as desired, and also makes it possible to suppress an increase in the circuit area of ​​each of the receiving circuit (420x), the transmitting circuit (410x), and the isolation circuit (430).

[0302] According to the signal transmission device (200X) of the second configuration, the drive speed of the switch element (SW) can be switched more suitably.

[0303] According to the signal transmission device (200X) of the third configuration, the specific period can be suitably detected.

[0304] According to the signal transmission device (200X) of the fourth configuration, the specific period can be detected more suitably.

[0305] According to the signal transmission device (200X) of the fifth configuration, it is possible to prevent the chip constituting the signal transmission device (200X) from becoming larger.

[0306] According to the signal transmission device (200X) of the sixth configuration, the first drive circuit (501) and the second drive circuit (502) can be driven by a signal received as an external input from the first chip (410x).

[0307] According to the signal transmission device (200X) of the seventh configuration, the drive control of the switch element (SW) becomes possible by the first output signal (Ga) output from the second chip (420x).

[0308] According to the signal transmission device (200X) of the eighth configuration, the drive control of the switch element (SW) becomes possible by the second output signal (Gb) output from the second chip (420x).

[0309] According to the electronic device (400) of the ninth configuration, it is possible to provide an electronic device (400) that can switch the drive speed of the switch element (SW) while suppressing an increase in the circuit area.

[0310] According to the vehicle (450) of the tenth configuration, it is possible to provide a vehicle (450) that can switch the drive speed of the switch element (SW) while suppressing an increase in the circuit area.

[0311] 5 Semiconductor device 11, 11A to 11F Low potential terminal 12, 12A to 12F High potential terminal 21, 21A to 21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 First inner end 25 First outer end 26 First spiral portion 27 Second inner end 28 Second outer end 29 Second spiral portion 31 First low potential wiring 32 Second low potential wiring 33 First high potential wiring 34 Second high potential wiring 41 Semiconductor chip 42 First main surface 43 Second main surface 44A to 44D Chip side wall 45 First functional device 51 Insulating layer 52 Insulating main surface 53A to 53D Insulating side wall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second functional device 61 Seal conductor 62 Device region 63 Outer region 64 Seal plug conductor 65 Seal via conductor 66 First inner region 67 Second inner region 71 Through wiring 72 Low-potential connection wiring 73 Lead-out wiring 74 First connection plug electrode 75 Second connection plug electrode 76 Pad plug electrode 77 Substrate plug electrode 78 First electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy pattern 86 High-potential dummy pattern 87 First high-potential dummy pattern 88 Second high-potential dummy pattern 89 First region 90 Second region 91 Third region 92 First connection portion 93 First pattern 94 Second pattern 95 Third pattern 96 First periphery line 97 Second periphery line 98 First intermediate line 99 First connection line 100 Slit 130 Separation structure 140 Inorganic insulating layer141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 First portion 147 Second portion 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p Primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 Buffer 220 Driver chip (second chip) 221, 222 Buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer chip (third chip) 230a First wiring layer (lower layer) 230b Second wiring layer (upper layer) 231, 232 Transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Transformer tip 301 First transformer 302 Second transformer 303 Third transformer 304 Fourth transformer 305 First guard ring 306 Second guard ring a1 to a8 Pads (corresponding to first current supply pads) b1 to b8 Pads (corresponding to first voltage measurement pads) c1 to c4 Pads (corresponding to second current supply pads) d1 to d4 Pads (corresponding to second voltage measurement pads) e1, e2 Pads L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil T21, T22, T23, T24, T25, T26 External terminal X First direction X21, X22, X23 Internal terminal Y Second direction Y21, Y22, Y23 Wiring Z: normal direction Z21, Z22, Z23: via 200X: signal transmission device 200Y: signal transmission device 400: electronic device 410x: first semiconductor chip (transmission circuit) 410y: first semiconductor chip 411: first transmission circuit 412: second transmission circuit415x Logic circuit 415y Logic circuit 420x Second semiconductor chip (receiving circuit) 420y Second semiconductor chip 421 First receiving circuit 422 Second receiving circuit 425 Logic circuit 426x Driver circuit (426x) 426y Driver circuit 427 Soft turn-off signal detection circuit (detection signal generation circuit) 430 Third semiconductor chip 431 First transformer 431 Second transformer 432 Second transformer 450 Vehicle 501 Output circuit 502 Soft turn-off circuit 503 Timer circuit 504 AND gate 505 UVLO circuit 506 Counter circuit 600 Smoothing capacitor D1, D2 Diodes DFF1 to DFF4 D flip-flop INV1 Inverter M Motor OSC Oscillator E1 Voltage source E2 Voltage source P1, N1, N2 Transistors R1 to R3 Resistors SW Switch element SWH (u / v / w) High-side switch SWL (u / v / w) Low-side switch ASC Soft turn-off input signal CI Current value CLKH Clock signal GH Gate signal GL Gate signal Ga to Ge Drive signal IN Input signal OUT Output signal RSTH Reset signal S Set signal S1 First internal signal S2 Second internal signal S4 Driver control signal S5 Soft turn-off control signal (detection signal) S6 Timer drive signal S7 Output signal T1 First set time T2 Second set time V1 Output V2 Output VCC1 Power supply voltage VCC2 Power supply voltage VD1 First motor drive voltageVD2 Second motor drive voltage Vge Gate signal

Claims

1. A signal transmission device comprising: a transmitting circuit configured to output a first internal signal and a second internal signal that are pulse-driven in response to an input signal; a receiving circuit configured to output a drive signal in response to the first internal signal and the second internal signal; an isolation circuit configured to transmit the first internal signal and the second internal signal while providing insulation between the transmitting circuit and the receiving circuit; a first drive circuit configured to drive a switch element in response to the drive signal; and a second drive circuit configured to drive the switch element at a slower speed than the first drive circuit, wherein the transmitting circuit drives at least one of the first internal signal and the second internal signal at a specific period different from the period of the input signal in response to an external signal different from the input signal, and the receiving circuit detects that the period of at least one of the first internal signal and the second internal signal is the specific period, and disables the first drive circuit and enables the second drive circuit.

2. A signal transmission device as described in claim 1, wherein the transmitting circuit drives the first internal signal at the specific period in response to the external signal, and the receiving circuit detects that the frequency of the first internal signal is at the specific period and enables the second driving circuit.

3. The receiving circuit comprises: a timer circuit configured to generate a timer drive signal to switch between a first logic level and a second logic level in response to the first internal signal, set the timer drive signal to the first logic level at a first timing of at least one of a rising edge and a falling edge of the first internal signal, and switch the timer drive signal to the second logic level when a first set time has elapsed from the first timing before the arrival of the next first timing; a detection signal generating circuit configured to generate a detection signal to switch between a third logic level and a fourth logic level in response to the timer drive signal, set the detection signal to the third logic level when the duration of the first logic level of the timer drive signal is less than a second set time, and set the detection signal to the fourth logic level when the duration is equal to or longer than the second set time; and a drive switching circuit configured to enable the first drive circuit and disable the second drive circuit when the detection signal is at the third logic level, and to disable the first drive circuit and enable the second drive circuit when the detection signal is at the fourth logic level, 3. The signal transmission device according to claim 1, wherein the first set time is shorter than a period of the input signal and longer than the specific period.

4. The signal transmission device according to claim 3, wherein the detection signal generating circuit comprises: a reset circuit configured to output a reset signal when the timer drive signal is at the second logic level; an oscillator circuit configured to output a clock signal; and a counter circuit configured to count the number of clocks of the clock signal to obtain a count value, and to reset the count value to 0 upon receiving the reset signal, thereby measuring the duration based on the count value.

5. A signal transmission device as claimed in any one of claims 1 to 4, in which a first chip on which circuit elements of the transmission circuit are integrated, a second chip on which circuit elements of the reception circuit, the first drive circuit and the second drive circuit are integrated, and a third chip on which circuit elements of the isolation circuit are integrated are sealed in a single package.

6. A signal transmission device as claimed in claim 5, wherein the first chip comprises: a first input terminal for receiving the input signal as an external input; and a second input terminal for receiving the external signal as an external input.

7. A signal transmission device as described in claim 5 or 6, wherein the first drive circuit generates a first output signal that drives the switch element, and the second chip has a first output terminal that outputs the first output signal to the outside.

8. A signal transmission device as described in any one of claims 5 to 7, wherein the second drive circuit generates a second output signal that drives the switch element, and the second chip has a second output terminal that outputs the second output signal to the outside.

9. An electronic device comprising: a plurality of switch elements, each of which is a power transistor; and a plurality of gate driver ICs that drive the gates of the respective switch elements, wherein at least one of the plurality of gate driver ICs is a signal transmission device according to any one of claims 1 to 8.

10. A vehicle equipped with the electronic device according to claim 9.

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