Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises a display area (100). The display area (100) comprises a plurality of circuit units (Q). Each circuit unit (Q) comprises a pixel driving circuit and at least one signal line for transmitting a constant voltage signal. The pixel driving circuit comprises at least one pixel transistor. In a direction perpendicular to the display substrate, the display substrate at least comprises a first semiconductor layer arranged on a substrate and a second semiconductor layer arranged on the side of the first semiconductor layer away from the substrate. In at least one circuit unit, one of the first semiconductor layer and second semiconductor layer comprises at least one semiconductor line, and the other one of the first semiconductor layer and second semiconductor layer comprises an active layer of the pixel transistor, the semiconductor line being connected to the signal line.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including a display area, the display area including a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit and at least one signal line transmitting a constant voltage signal, the pixel driving circuit including at least one pixel transistor; in a direction perpendicular to the display substrate, the display substrate includes at least a first semiconductor layer arranged on a base and a second semiconductor layer arranged on a side of the first semiconductor layer away from the base; in at least one circuit unit, one of the first semiconductor layer and the second semiconductor layer includes at least one semiconductor line, the other semiconductor layer includes an active layer of the pixel transistor, and the semiconductor line is connected to the signal line.

[0006] In an exemplary embodiment, in at least one circuit unit, the at least one semiconductor line includes a first semiconductor line and a second semiconductor line extending along the pixel row direction, and a third semiconductor line extending along the pixel column direction, and the first semiconductor line and the second semiconductor line are respectively connected to the third semiconductor line to form a network connection structure.

[0007] In an exemplary embodiment, in at least one circuit unit, the at least one signal line includes a first power connection line extending along the pixel row direction and a first power line extending along the pixel column direction, the first power connection line is connected to the first power line to form a mesh connection structure, and the first power connection line is connected to the first semiconductor line.

[0008] In an exemplary embodiment, an orthographic projection of the first power connection line on the substrate at least partially overlaps with an orthographic projection of the first semiconductor line on the substrate.

[0009] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate further includes a plurality of conductive layers, the first power connection line and the first power line are arranged in different conductive layers, the first power line is connected to the first power connection line through a via, and the first power connection line is connected to the first semiconductor line through a via.

[0010] In an exemplary embodiment, in at least one circuit unit, the at least one signal line includes a second power connection line extending along the pixel row direction and a second power line extending along the pixel column direction, the second power connection line and the second power line are connected to form a mesh connection structure; the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the third semiconductor line on the substrate.

[0011] In an exemplary embodiment, in at least one circuit unit, the at least one signal line includes a first initial signal line extending along the pixel row direction and a first initial connection line extending along the pixel column direction, the first initial connection line being connected to the first initial signal line to form a mesh connection structure; the orthographic projection of the first initial connection line on the substrate at least partially overlaps with the orthographic projection of the third semiconductor line on the substrate.

[0012] In an exemplary embodiment, an orthographic projection of the first initial signal line on the substrate at least partially overlaps with an orthographic projection of the second semiconductor line on the substrate.

[0013] In an exemplary embodiment, in at least one circuit unit, the at least one signal line includes a second initial signal line extending along the pixel row direction and a second initial connecting line extending along the pixel column direction, the second initial connecting line being connected to the second initial signal line to form a mesh connection structure; the orthographic projection of the second initial connecting line on the substrate at least partially overlaps with the orthographic projection of the third semiconductor line on the substrate.

[0014] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, the storage capacitor including a first plate and a second plate, the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the second plate on the substrate, the orthographic projection of the first plate on the substrate does not overlap with the orthographic projection of the semiconductor line on the substrate, and the orthographic projection of the second plate on the substrate does not overlap with the orthographic projection of the semiconductor line on the substrate.

[0015] In an exemplary embodiment, a material of the first semiconductor layer includes polysilicon, a material of the second semiconductor layer includes oxide, the first semiconductor layer includes the semiconductor line, and the second semiconductor layer includes an active layer of the pixel transistor.

[0016] In an exemplary embodiment, the display substrate further includes a frame area arranged on at least one side of the display area, the frame area includes a plurality of gate units, at least one gate unit includes a gate driving circuit, the gate driving circuit includes a plurality of gate transistors, and the active layer of the gate transistor is arranged in the same layer as the semiconductor line and is made of the same material.

[0017] In an exemplary embodiment, in a direction parallel to the display substrate, the circuit unit has a first unit area, and in at least one circuit unit, the orthographic projection of the semiconductor line on the substrate has a first area, and the ratio of the first area to the first unit area has a first ratio, and the first ratio is 0.1 to 0.2.

[0018] In an exemplary embodiment, in a direction parallel to the display substrate, the gate unit has a second unit area, and in at least one gate unit, an orthographic projection of an active layer of a plurality of gate transistors on the substrate has a second area, a ratio of the second area to the second unit area has a second ratio, and a ratio of the first ratio to the second ratio is 0.9 to 1.1.

[0019] In an exemplary embodiment, the frame area further includes a semiconductor lead extending in a direction along an edge of a display area, the semiconductor lead being connected to the semiconductor wires in a plurality of unit rows, and the display area edge being an edge of the display area close to the frame area.

[0020] In an exemplary embodiment, the semiconductor leads and the semiconductor wires are provided in the same layer and are connected to each other as an integral structure.

[0021] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0022] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a display area, the display area comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and at least one signal line transmitting a constant voltage signal, the pixel driving circuit comprising at least one pixel transistor; the manufacturing method comprising:

[0023] A first semiconductor layer and a second semiconductor layer are formed on a substrate and are arranged on a side of the first semiconductor layer away from the substrate; in at least one circuit unit, one of the first semiconductor layer and the second semiconductor layer includes at least one semiconductor line, and the other semiconductor layer includes an active layer of the pixel transistor, and the semiconductor line is connected to the signal line.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0026] FIG1 is a schematic structural diagram of a display device;

[0027] FIG2 is a schematic structural diagram of a display substrate;

[0028] FIG3 is a schematic diagram of a planar structure of a display area in a display substrate;

[0029] FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate;

[0030] FIG5 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0031] FIG6 is a schematic diagram of a planar structure of a display area in a display substrate according to an exemplary embodiment of the present disclosure;

[0032] FIG7 is a schematic structural diagram of a signal line of a network connectivity structure according to an exemplary embodiment of the present disclosure;

[0033] FIG8 is a schematic diagram showing a substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0034] 9A and 9B are schematic diagrams showing a substrate after forming a first conductive layer pattern according to the present disclosure;

[0035] 10A and 10B are schematic diagrams showing a substrate after forming a second conductive layer pattern according to the present disclosure;

[0036] 11A and 11B are schematic diagrams showing a substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0037] 12A and 12B are schematic diagrams showing a substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0038] FIG13 is a schematic diagram showing a substrate after a sixth insulating layer pattern is formed in the present disclosure;

[0039] 14A and 14B are schematic diagrams showing a substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0040] FIG15 is a schematic diagram showing a substrate after forming a first planar layer pattern according to the present disclosure;

[0041] 16A and 16B are schematic diagrams showing a substrate after a fifth conductive layer pattern is formed thereon according to the present disclosure;

[0042] FIG. 17 is a schematic diagram of a semiconductor trace in a border region according to an exemplary embodiment of the present disclosure.

[0043] Description of the accompanying drawings:

[0044] 11—first semiconductor line; 12—second semiconductor line; 13—third semiconductor line;

[0045] 21—first bottom gate electrode; 22—second bottom gate electrode; 24—fourth bottom gate electrode;

[0046] 25—fifth bottom gate electrode; 31—first active layer; 32—second active layer;

[0047] 33—third active layer; 34—fourth active layer; 35—fifth active layer;

[0048] 41—first top gate electrode; 42—second top gate electrode; 43—third gate electrode;

[0049] 44—fourth top gate electrode; 45—fifth top gate electrode; 51—first connecting electrode;

[0050] 52—second connection electrode; 53—third connection electrode; 61—first power connection line;

[0051] 62—Second power connection line; 63—First initial signal line; 64—Second initial signal line;

[0052] 71—first scanning signal line; 72—second scanning signal line; 73—third scanning signal line;

[0053] 74—light signal line; 81—first power line; 82—second power line;

[0054] 83—first initial connection line; 84—second initial connection line; 85—data signal line;

[0055] 86—anode connecting electrode; 91—first electrode plate; 92—second electrode plate;

[0056] 100—display area; 101—substrate; 102—driving circuit layer;

[0057] 103—light-emitting structure layer; 104—encapsulation structure layer; 200—binding area;

[0058] 300—border area; 301—gate active layer; 310—semiconductor wiring. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0060] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0061] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0062] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0063] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0064] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0065] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0066] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0067] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0068] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0069] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have some minor deformations due to tolerances, such as chamfers, rounded edges, and deformation. The term "approximately" in this disclosure does not strictly define the boundaries, but allows for values ​​within the range of process and measurement errors.

[0070] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0071] Figure 2 is a schematic diagram of the structure of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij forming a pixel array. The plurality of sub-pixels Pxij are configured to display dynamic or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be deformable, such as being curled, bent, folded, or rolled.

[0072] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area, which are sequentially arranged in a direction away from the display area 100. The fan-out area is connected to the display area 100 and may include at least a plurality of data fan-out lines, which are configured to connect the data signal lines of the display area in a fan-out routing manner. The bending area is arranged on a side of the fan-out area away from the display area, and may include a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area is arranged on a side of the bending area away from the display area, and may include at least an integrated circuit (IC), which is configured to be connected to a plurality of data fan-out lines. The binding pin area is arranged on a side of the driver chip area away from the display area, and may include at least a plurality of binding pins (Bonding Pad), which are configured to be bound and connected to an external flexible printed circuit (FPC).

[0073] In an exemplary embodiment, the frame area 300 may include at least a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area may include a plurality of gate units, and the gate units may include a gate drive circuit, which is connected to the scanning signal lines and the light-emitting signal lines in the display area 100. The power line area is arranged on a side of the circuit area away from the display area, and may include at least a frame power line, which may be connected to the cathode of the light-emitting device in the display area 100. The crack dam area is arranged on a side of the power line area away from the display area, and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is arranged on a side of the crack dam area away from the display area, and may include at least a cutting groove provided on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment performs cutting along the cutting grooves respectively.

[0074] In an exemplary embodiment, the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with at least one isolation dam, which may extend in a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100 .

[0075] FIG3 is a schematic diagram of a planar structure of a display area in a display substrate. As shown in FIG3 , the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0076] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a green subpixel (G) that emits green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0077] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0078] Figure 4 is a schematic cross-sectional view of the display region of a display substrate, illustrating the structure of three sub-pixels in the display region. As shown in Figure 4, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0079] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0080] Exemplary embodiments of the present disclosure provide a display substrate, which may include a display area and a border area located on at least one side of the display area. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a base and a light-emitting structure layer disposed on a side of the driving structure layer away from the base. In a plane parallel to the display substrate, the driving structure layer in the display area may include multiple circuit units constituting multiple unit rows and multiple unit columns, at least one of which may include a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The driving structure layer in the border area may include multiple gate units extending in a direction parallel to an edge of the display area, at least one of which may include a gate driving circuit configured to provide a scan signal to a scan signal line in the display area. The display area edge is the edge of the display area adjacent to the border area. The light-emitting structure layer may be disposed in the display area and include multiple light-emitting units, at least one of which may include a light-emitting device, connected to a pixel driving circuit of a corresponding circuit unit, and configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0081] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0082] An exemplary embodiment of the present disclosure provides a display substrate, comprising a display area, the display area including a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit and at least one signal line transmitting a constant voltage signal, the pixel driving circuit including at least one pixel transistor; in a direction perpendicular to the display substrate, the display substrate includes at least a first semiconductor layer disposed on a base and a second semiconductor layer disposed on a side of the first semiconductor layer away from the base; in at least one circuit unit, one of the first semiconductor layer and the second semiconductor layer includes at least one semiconductor line, the other semiconductor layer includes an active layer of the pixel transistor, and the semiconductor line is connected to the signal line.

[0083] In an exemplary embodiment, in at least one circuit unit, the at least one semiconductor line includes a first semiconductor line and a second semiconductor line extending along the pixel row direction, and a third semiconductor line extending along the pixel column direction, and the first semiconductor line and the second semiconductor line are respectively connected to the third semiconductor line to form a network connection structure.

[0084] In an exemplary embodiment, in at least one circuit unit, the at least one signal line includes a first power connection line extending along the pixel row direction and a first power line extending along the pixel column direction, the first power connection line is connected to the first power line to form a mesh connection structure, the first power connection line is connected to the first semiconductor line, and the orthographic projection of the first power connection line on the substrate at least partially overlaps with the orthographic projection of the first semiconductor line on the substrate.

[0085] In an exemplary embodiment, in at least one circuit unit, the at least one signal line includes a second power connection line extending along the pixel row direction and a second power line extending along the pixel column direction, the second power connection line and the second power line are connected to form a mesh connection structure; the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the third semiconductor line on the substrate.

[0086] In an exemplary embodiment, in at least one circuit unit, the at least one signal line includes a first initial signal line extending along the pixel row direction and a first initial connecting line extending along the pixel column direction, the first initial connecting line is connected to the first initial signal line to form a mesh connection structure; the orthographic projection of the first initial connecting line on the substrate at least partially overlaps with the orthographic projection of the third semiconductor line on the substrate, and the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor line on the substrate.

[0087] In an exemplary embodiment, in at least one circuit unit, the at least one signal line includes a second initial signal line extending along the pixel row direction and a second initial connecting line extending along the pixel column direction, the second initial connecting line being connected to the second initial signal line to form a mesh connection structure; the orthographic projection of the second initial connecting line on the substrate at least partially overlaps with the orthographic projection of the third semiconductor line on the substrate.

[0088] In an exemplary embodiment, the display substrate further includes a border area arranged on at least one side of the display area, the border area includes a plurality of gate units, at least one gate unit includes a gate driving circuit, the gate driving circuit includes a plurality of gate transistors, and the active layers of the plurality of gate transistors are arranged in the same layer as the semiconductor line, and are made of the same material, and are formed synchronously through the same patterning process.

[0089] In an exemplary embodiment, the frame area further includes a semiconductor lead extending in a direction along an edge of a display area, the semiconductor lead being connected to the semiconductor wires in a plurality of unit rows, and the display area edge being an edge of the display area close to the frame area.

[0090] In an exemplary embodiment, the semiconductor leads and the semiconductor wires are provided in the same layer and made of the same material, and are connected to each other as an integral structure.

[0091] The display substrate of this embodiment is described below with some examples.

[0092] Figure 5 is an equivalent circuit diagram of a pixel driving circuit of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit of the exemplary embodiment of the present disclosure may include 5 transistors (first transistor T1 to fifth transistor T5) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 8 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power line VDD).

[0093] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the second electrode of the second transistor T2, the gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first end of the storage capacitor C. The second node N2 is respectively connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The third node N3 is respectively connected to the second electrode of the first transistor T1, the second electrode of the third transistor T3, and the second end of the storage capacitor C. The third node N3 is also connected to the first electrode of the light emitting device EL.

[0094] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the third node N3 .

[0095] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor T1 is connected to the third node N3. When a turn-on signal is applied to the third scan signal line S3, the first transistor T1 is turned on and transmits the first initialization signal to the second terminal of the storage capacitor C and the first electrode of the light-emitting device EL, respectively, to initialize the storage capacitor C and the light-emitting device EL.

[0096] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the second initial signal line INIT2, and a second electrode of the second transistor T2 is connected to the first node N1. When a turn-on signal is applied to the second scan signal line S2, the second transistor T2 is turned on and transmits the second initial signal to the first node N1.

[0097] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor. The third transistor T3 determines the magnitude of a driving current flowing between the first power line VDD and the light emitting device EL based on a potential difference between its gate electrode and the first electrode.

[0098] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the first node N1. When a turn-on signal is applied to the first scan signal line S1, the fourth transistor T4 is turned on and transmits the data voltage to the first node N1.

[0099] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. When a turn-on signal is applied to the light emitting signal line EM, the fifth transistor T5 is turned on, forming a drive current path between the first power line VDD and the light emitting device EL, causing the light emitting device EL to emit light.

[0100] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the third node N3, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0101] In an exemplary embodiment, the first power line VDD is configured to continuously provide a constant first power signal to the pixel driving circuit, and the second power line VSS is configured to continuously provide a constant second power signal to the light-emitting device EL, wherein the voltage of the first power signal is greater than the voltage of the second power signal. The first initial signal line INIT1 and the second initial signal line INIT2 are configured to respectively provide a first initial signal and a second initial signal to the pixel driving circuit. The first initial signal and the second initial signal may be constant voltage signals, and their voltages may be between the voltage of the first power signal provided by the first power line VDD and the voltage of the second power signal provided by the second power line VSS, but this is not limited herein.

[0102] In an exemplary embodiment, the first to fifth transistors T1 to T5 in the pixel driving circuit may be P-type transistors or N-type transistors. In some possible exemplary embodiments, the first to fifth transistors T1 to T5 in the pixel driving circuit may include P-type transistors and N-type transistors.

[0103] In an exemplary embodiment, the first transistor T1 to the fifth transistor T5 in the pixel driving circuit may be low-temperature polysilicon transistors, or oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide transistor is made of metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0104] In the exemplary embodiments of the present disclosure, the first to fifth transistors T1 to T5 in the pixel driving circuit may be oxide thin-film transistors. Oxide thin-film transistors have advantages such as low leakage current. Using a display substrate provided with oxide thin-film transistors can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0105] FIG6 is a schematic diagram of a planar structure of a display area in a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of three circuit units (a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3) in a unit row. On a plane parallel to the display substrate, the display area may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one circuit unit may include a pixel driving circuit. As shown in FIG6 , the pixel driving circuit is respectively connected to a first initial signal line 63, a second initial signal line 64, a first scan signal line 71, a second scan signal line 72, a third scan signal line 73, a light-emitting signal line 74, a first power line 81, and a data signal line 85. The first scan signal line 71, the second scan signal line 72, and the third scan signal line 73 are configured to provide scan signals to the pixel driving circuit, respectively, the light-emitting signal line 74 is configured to provide a light-emitting control signal to the pixel driving circuit, the first initial signal line 63 and the second initial signal line 64 are configured to provide a first initial signal and a second initial signal to the pixel driving circuit, respectively, and the first power line 81 and the data signal line 85 are configured to provide a first power signal and a data signal to the pixel driving circuit, respectively.

[0106] In an exemplary embodiment, the shapes of the first initial signal line 63, the second initial signal line 64, the first scan signal line 71, the second scan signal line 72, the third scan signal line 73 and the light-emitting signal line 74 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the first power line 81 and the data signal line 85 can be straight lines or broken lines with the main parts extending along the second direction Y, and the first direction X and the second direction Y intersect.

[0107] In the present disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B." In an exemplary embodiment, the first direction X may be the direction of unit rows, and the second direction Y may be the direction of unit columns.

[0108] In an exemplary embodiment, the pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The plurality of transistors may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5, with the first transistor T1 to the fifth transistor T5 serving as pixel transistors of the present disclosure. The storage capacitor may include a first electrode plate 91 and a second electrode plate 92 stacked together, wherein the orthographic projection of the first electrode plate 91 on the display substrate plane at least partially overlaps the orthographic projection of the second electrode plate 92 on the display substrate plane.

[0109] In example embodiments, the first to fifth transistors T1 to T5 may be oxide transistors.

[0110] In the exemplary embodiment, a gate electrode of the first transistor T1 is connected to the third scan signal line 73, a first electrode of the first transistor T1 is connected to the first initial signal line 63, and a first electrode of the first transistor T1 is connected to the second electrode plate 92. A gate electrode of the second transistor T2 is connected to the second scan signal line 72, a first electrode of the second transistor T2 is connected to the second initial signal line 64, and a first electrode of the second transistor T2 is connected to the first electrode plate 91. A gate electrode of the fourth transistor T4 is connected to the first scan signal line 71, a first electrode of the fourth transistor T4 is connected to the data signal line 85, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line 74, and a first electrode of the fifth transistor T5 is connected to the first power line 81.

[0111] In an exemplary embodiment, the display substrate may include at least a first semiconductor layer disposed on a base and a second semiconductor layer disposed on a side of the first semiconductor layer away from the base, in a direction perpendicular to the display substrate. In at least one circuit unit, one of the first semiconductor layer and the second semiconductor layer may include at least one semiconductor line, and the other semiconductor layer may include an active layer of first to fifth transistors T1 to T5.

[0112] In example embodiments, a material of the first semiconductor layer may include polysilicon, a material of the second semiconductor layer may include oxide, at least one semiconductor wire may be disposed in the first semiconductor layer, and active layers of the first to fifth transistors T1 to T5 may be disposed in the second semiconductor layer.

[0113] In an exemplary embodiment, at least one semiconductor line can be connected to the first power line 81, or, at least one semiconductor line can be connected to the first initial signal line 63, or, at least one semiconductor line can be connected to the second initial signal line 64, and the first power line 81, the first initial signal line 63 and the second initial signal line 64 can serve as signal lines for transmitting constant voltage signals of the present disclosure.

[0114] Figure 7 is a schematic diagram of a signal line structure of a network connectivity structure according to an exemplary embodiment of the present disclosure. As shown in Figure 7, at least one semiconductor line in at least one circuit unit may include a first semiconductor line 11 and a second semiconductor line 12 extending along a first direction X (pixel row direction), and a third semiconductor line 13 extending along a second direction Y (pixel column direction). The first semiconductor line 11 and the second semiconductor line 12 are respectively connected to the third semiconductor line 13 to form a network connectivity structure.

[0115] In an exemplary embodiment, the first semiconductor wire 11 and the second semiconductor wire 12 can be respectively arranged on both sides of the second direction Y in the circuit unit, and the third semiconductor wire 13 can be arranged on one side of the first direction X in the circuit unit. The first semiconductor wire 11, the second semiconductor wire 12 and the third semiconductor wire 13 are an integrated structure connected to each other and are formed simultaneously through the same patterning process.

[0116] As shown in Figures 6 and 7, at least one circuit unit may further include a first power connection line 61 whose main portion extends along the first direction X, and the first power connection line 61 is connected to the first power line 81, so that the first power connection line 61 extending along the first direction X and the first power line 81 extending along the second direction Y form a network connectivity structure in the display area.

[0117] In an exemplary embodiment, an orthographic projection of the first power connection line 61 on the substrate at least partially overlaps with an orthographic projection of the first semiconductor line 11 on the substrate.

[0118] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may further include a plurality of conductive layers, the first power connection line 61 and the first power connection line 81 may be arranged in different conductive layers, the first power connection line 81 is connected to the first power connection line 61 through a via, and the first power connection line 61 is connected to the first semiconductor line 11 through a via.

[0119] As shown in Figures 6 and 7, at least one circuit unit may further include a second power connection line 62 whose main body extends along the first direction X and a second power line 82 whose main body extends along the second direction Y. The second power connection line 62 is connected to the second power line 82, so that the second power connection line 62 extending along the first direction X and the second power line 82 extending along the second direction Y form a network connection structure in the display area.

[0120] In an exemplary embodiment, an orthographic projection of the second power supply line 82 on the substrate at least partially overlaps an orthographic projection of the third semiconductor line 13 on the substrate.

[0121] In an exemplary embodiment, the second power connection line 62 and the second power connection line 82 may be disposed in different conductive layers, and the second power connection line 82 may be connected to the second power connection line 62 through a via.

[0122] As shown in Figures 6 and 7, at least one circuit unit may further include a first initial connection line 83 whose main part extends along the second direction Y, and the first initial connection line 83 is connected to the first initial signal line 63, so that the first initial signal line 63 extending along the first direction X and the first initial connection line 83 extending along the second direction Y form a network connection structure in the display area.

[0123] In an exemplary embodiment, an orthographic projection of the first preliminary connection line 83 on the substrate at least partially overlaps with an orthographic projection of the third semiconductor line 13 on the substrate.

[0124] In an exemplary embodiment, an orthographic projection of the first preliminary signal line 63 on the substrate at least partially overlaps an orthographic projection of the second semiconductor line 12 on the substrate.

[0125] In an exemplary embodiment, the first preliminary connection line 83 and the first preliminary signal line 63 may be disposed in different conductive layers, and the first preliminary connection line 83 may be connected to the first preliminary signal line 63 through a via.

[0126] As shown in Figures 6 and 7, at least one circuit unit may further include a second initial connection line 84 whose main portion extends along the second direction Y, and the second initial connection line 84 is connected to the second initial signal line 64, so that the second initial signal line 64 extending along the first direction X and the second initial connection line 84 extending along the second direction Y form a network connection structure in the display area.

[0127] In an exemplary embodiment, an orthographic projection of the second preliminary connection line 84 on the substrate at least partially overlaps with an orthographic projection of the third semiconductor line 13 on the substrate.

[0128] In an exemplary embodiment, the second preliminary connection line 84 and the second preliminary signal line 64 may be disposed in different conductive layers, and the second preliminary connection line 84 may be connected to the second preliminary signal line 64 through a via.

[0129] In an exemplary embodiment, in a direction perpendicular to the substrate, the display substrate may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate and sequentially disposed in a direction away from the substrate. The first semiconductor line 11, the second semiconductor line 12, and the third semiconductor line 13 may be disposed in the first semiconductor layer, the first plate 91 of the storage capacitor may be disposed in the first conductive layer, the second plate 92 of the storage capacitor may be disposed in the second conductive layer, the top gate electrodes of the plurality of transistors may be disposed in the third conductive layer, the first power connection line 61, the second power connection line 62, the first initial signal line 63, the second initial signal line 64, the first scan signal line 71, the second scan signal line 72, the third scan signal line 73, and the light emitting signal line 74 may be disposed in the fourth conductive layer, and the first power line 81, the second power line 82, the first initial connection line 83, the second initial connection line 84, and the data signal line 85 may be disposed in the fifth conductive layer.

[0130] The following is an exemplary description of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0131] In an exemplary embodiment, taking three circuit units (a first circuit unit Q1 , a second circuit unit Q2 , and a third circuit unit Q3 ) as an example, the preparation process of the display substrate may include the following operations.

[0132] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer disposed on the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 8 .

[0133] In example embodiments, the first semiconductor layer pattern of each circuit unit in the display area may include at least a first semiconductor wire 11 , a second semiconductor wire 12 , and a third semiconductor wire 13 .

[0134] In an exemplary embodiment, the shapes of the first semiconductor wire 11 and the second semiconductor wire 12 can be straight lines or broken lines with the main body extending along the first direction X. The first semiconductor wire 11 can be arranged on the side opposite to the second direction Y of the circuit unit, and the second semiconductor wire 12 can be arranged on the side of the second direction Y of the circuit unit.

[0135] In an exemplary embodiment, a semiconductor block 11-1 may be disposed on the first semiconductor line 11. The semiconductor block 11-1 may be block-shaped (e.g., rectangular) and may be disposed on a side of the first semiconductor line 11 away from the second semiconductor line 12. A first end of the semiconductor block 11-1 is connected to the first semiconductor line 11, and a second end of the semiconductor block 11-1 extends away from the second semiconductor line 12. The semiconductor block 11-1 is configured to be connected to a first power connection line formed later.

[0136] In an exemplary embodiment, the third semiconductor line 13 may be shaped as a straight line or a broken line with the main portion extending along the second direction Y, may be disposed on one side of the circuit unit in the opposite direction of the first direction X, and may be connected to the first semiconductor line 11 and the second semiconductor line 12 respectively.

[0137] In an exemplary embodiment, in at least one circuit unit, the first semiconductor wire 11 , the second semiconductor wire 12 , and the third semiconductor wire 13 may be an integrated structure connected to each other, forming semiconductor wires of a network-connected structure.

[0138] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si). In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation process on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0139] In an exemplary embodiment, the first semiconductor layer pattern in the frame region of the display substrate may include at least the active layers of multiple gate transistors. The first semiconductor lines 11, second semiconductor lines 12, and third semiconductor lines 13 in the display region are disposed on the same layer as the active layers of the multiple gate transistors in the frame region and are formed simultaneously through the same patterning process. In an exemplary embodiment, the multiple gate transistors in the frame region are polysilicon transistors.

[0140] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG9A and FIG9B , FIG9B being a planar schematic diagram of the first conductive layer in FIG9A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0141] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area may include at least a first plate 91 of a storage capacitor.

[0142] In an exemplary embodiment, the first electrode plate 91 may be rectangular, with chamfered corners, and may be disposed in a central region of the circuit unit in the first direction X and the second direction Y. In an exemplary embodiment, the first electrode plate 91 may serve as one electrode plate of a storage capacitor.

[0143] In an exemplary embodiment, the orthographic projection of the first electrode 91 on the substrate does not overlap with the orthographic projection of the first semiconductor layer on the substrate, that is, the first electrode 91 does not overlap with the first semiconductor line 11, the second semiconductor line 12 and the third semiconductor line 13, thereby preventing the first conductive layer and the first semiconductor layer from forming a transistor structure.

[0144] In an exemplary embodiment, a plate connection block 91-1 may be provided on the first plate 91. The plate connection block 91-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the first plate 91 away from the second semiconductor line 12. A first end of the plate connection block 91-1 is connected to the first plate 91, and a second end of the plate connection block 91-1 extends in a direction away from the second semiconductor line 12. The plate connection block 91-1 is configured to be connected to a second connection electrode formed subsequently.

[0145] In an exemplary embodiment, in at least one circuit unit, the first electrode plate 91 and the electrode plate connecting block 91 - 1 may be an integral structure connected to each other.

[0146] In an exemplary embodiment, the first conductive layer pattern in the frame region of the display substrate may include at least gate electrodes for multiple gate transistors. After forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform a conductorization process on the first semiconductor layer. The first semiconductor layer in the frame region shielded by the gate electrodes forms a channel region, while the first semiconductor layer not shielded by the gate electrodes is conductorized. Because the first semiconductor wires 11, second semiconductor wires 12, and third semiconductor wires 13 in the display region are not shielded by the first electrode plate 91, the first semiconductor wires 11, second semiconductor wires 12, and third semiconductor wires 13 in the display region are all conductorized.

[0147] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the second conductive layer in FIG10A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0148] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least: a first bottom gate electrode 21, a second bottom gate electrode 22, a fourth bottom gate electrode 24, a fifth bottom gate electrode 25 and a second plate 92 of the storage capacitor.

[0149] In an exemplary embodiment, the outline of the second electrode plate 92 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 92 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 91 on the substrate. The second electrode plate 92 can serve as another electrode plate of the storage capacitor, and the first electrode plate 91 and the second electrode plate 92 constitute the storage capacitor of the pixel driving circuit.

[0150] In an exemplary embodiment, the orthographic projection of the second electrode 92 on the substrate does not overlap with the orthographic projection of the first semiconductor layer on the substrate, that is, the second electrode 92 does not overlap with the first semiconductor line 11, the second semiconductor line 12 and the third semiconductor line 13, thereby avoiding the formation of parasitic capacitance between the second conductive layer and the first semiconductor layer.

[0151] In an exemplary embodiment, the second electrode 92 can also serve as a shielding electrode for the third transistor T3, shielding the channel region of the third transistor T3, blocking the light emitted by the light-emitting device and the light reflected by the film layer from irradiating the channel region of the third transistor T3, preventing the oxide transistor from drifting due to light, and improving the electrical performance of the oxide third transistor T3.

[0152] In an exemplary embodiment, the shape of the first bottom gate electrode 21 can be a strip extending along the first direction X, and can be located on one side of the second electrode plate 92 in the second direction Y. The first bottom gate electrode 21 can serve as the bottom gate electrode of the first transistor T1, and can also serve as a shielding electrode of the first transistor T1, shielding the channel region of the first transistor T1, blocking the light emitted by the light-emitting device and the light reflected by the film layer from irradiating the channel region of the first transistor T1, preventing the oxide transistor from drifting due to light, and improving the electrical performance of the oxide first transistor T1.

[0153] In an exemplary embodiment, the second bottom gate electrode 22 may be in the shape of a strip extending along the first direction X, and may be located on the side of the second electrode plate 92 in the opposite direction of the second direction Y. The second bottom gate electrode 22 may serve as the bottom gate electrode of the second transistor T2, and may also serve as a shielding electrode of the second transistor T2, shielding the channel region of the second transistor T2, blocking the light emitted by the light-emitting device and the light reflected by the film layer from irradiating the channel region of the second transistor T2, preventing the oxide transistor from drifting in characteristics due to light, and improving the electrical performance of the oxide second transistor T2.

[0154] In an exemplary embodiment, the shape of the fourth bottom gate electrode 24 can be a strip shape extending along the first direction X, and can be located between the first bottom gate electrode 21 and the second electrode plate 92. The fourth bottom gate electrode 24 can serve as the bottom gate electrode of the fourth transistor T4, and can also serve as a shielding electrode of the fourth transistor T4, shielding the channel region of the fourth transistor T4, blocking the light emitting device and the film layer reflected light from irradiating the channel region of the fourth transistor T4, preventing the oxide transistor from drifting due to light, and improving the electrical performance of the oxide fourth transistor T4.

[0155] In an exemplary embodiment, the shape of the fifth bottom gate electrode 25 can be a strip shape extending along the first direction X, and can be located on the side of the second bottom gate electrode 22 away from the second electrode plate 92. The fifth bottom gate electrode 25 can serve as the bottom gate electrode of the fifth transistor T5, and can also serve as a shielding electrode of the fifth transistor T5, shielding the channel region of the fifth transistor T5, blocking the light emission of the light-emitting device and the reflected light of the film layer from irradiating the channel region of the fifth transistor T5, preventing the oxide transistor from drifting due to light, and improving the electrical performance of the oxide fifth transistor T5.

[0156] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the second conductive layer, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the second semiconductor layer in FIG11A .

[0157] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit in the display area may include at least the first active layer 31 of the first transistor T1 to the fifth active layer 35 of the fifth transistor T5, and the first active layer 31, the third active layer 33 and the fifth active layer 35 are an integrated structure connected to each other, and the second active layer 32 and the fourth active layer 34 are an integrated structure connected to each other.

[0158] In an exemplary embodiment, in the first direction X, the second active layer 32 and the fourth active layer 34 of the integrated structure may be located on a side of the third active layer 33 in the opposite direction of the first direction X. In the second direction Y, the second active layer 32 and the fifth active layer 35 may be located on a side of the third active layer 33 in the opposite direction of the second direction Y, and the first active layer 31 and the fourth active layer 34 may be located on a side of the third active layer 33 in the second direction Y.

[0159] In exemplary embodiments, the first active layer 31 , the second active layer 32 , the fourth active layer 34 , and the fifth active layer 35 may have stripe shapes extending along the second direction Y, and the third active layer 33 may have a rectangular shape.

[0160] In an exemplary embodiment, the orthographic projection of the first active layer 31 on the substrate at least partially overlaps with the orthographic projection of the first bottom gate electrode 21 on the substrate, the orthographic projection of the second active layer 32 on the substrate at least partially overlaps with the orthographic projection of the second bottom gate electrode 22 on the substrate, the orthographic projection of the third active layer 33 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 92 on the substrate, the orthographic projection of the fourth active layer 34 on the substrate at least partially overlaps with the orthographic projection of the fourth bottom gate electrode 24 on the substrate, and the orthographic projection of the fifth active layer 35 on the substrate at least partially overlaps with the orthographic projection of the fifth bottom gate electrode 25 on the substrate.

[0161] In an exemplary embodiment, the orthographic projections of the second active layer 32 and the fourth active layer 34 of the integrated structure on the substrate at least partially overlap with the orthographic projection of the third semiconductor wire 13 on the substrate. The third semiconductor wire 13 can play a shielding role, blocking light from reaching the second transistor T2 and the fourth transistor T4, preventing the characteristics of the oxide transistors from drifting due to light, and improving the electrical performance of the oxide transistors.

[0162] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 31-2 of the first active layer may serve as the second region 33-2 of the third active layer, meaning that the second region 31-2 of the first active layer and the second region 33-2 of the third active layer may be connected to each other. The first region 33-1 of the third active layer may serve as the first region 35-1 of the fifth active layer, meaning that the first region 33-1 of the third active layer and the first region 35-1 of the fifth active layer may be connected to each other. The second region 32-2 of the second active layer may serve as the second region 34-2 of the fourth active layer, meaning that the second region 32-2 of the second active layer and the second region 34-2 of the fourth active layer may be connected to each other. The first region 31-1 of the first active layer, the first region 32-1 of the second active layer, the first region 34-1 of the fourth active layer, and the first region 35-1 of the fifth active layer may be provided separately.

[0163] In an exemplary embodiment, the orthographic projection of the first region 31-1 of the first active layer on the substrate at least partially overlaps with the orthographic projection of the second semiconductor wire 12 on the substrate, and the orthographic projection of the first region 35-1 of the fifth active layer on the substrate at least partially overlaps with the orthographic projection of the first semiconductor wire 11 on the substrate. The first semiconductor wire 11 and the second semiconductor wire 12 can play a shielding role to prevent the characteristics of the oxide transistor from drifting due to light, thereby improving the electrical performance of the oxide transistor.

[0164] In an exemplary embodiment, the second semiconductor layer may be made of oxide, and the first to fifth transistors T1 to T5 are all oxide transistors. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0165] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a plan view schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0166] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display area includes at least a first top gate electrode 41 , a second top gate electrode 42 , a third gate electrode 43 , a fourth top gate electrode 44 and a fifth top gate electrode 45 .

[0167] In an exemplary embodiment, the first top-gate electrode 41 may be in the shape of a strip extending along the first direction X and may be located on one side of the second electrode plate 92 in the second direction Y. The orthographic projection of the first top-gate electrode 41 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. The first top-gate electrode 41 may serve as the top gate electrode of the first transistor T1. In an exemplary embodiment, the orthographic projection of the first top-gate electrode 41 on the substrate at least partially overlaps with the orthographic projection of the first bottom-gate electrode 21 on the substrate. The first bottom-gate electrode 21 and the first top-gate electrode 41 form the first transistor T1 with a bottom-gate-top-gate structure.

[0168] In an exemplary embodiment, the second top-gate electrode 42 may be in the shape of a strip extending along the first direction X and may be located on a side of the second electrode plate 92 opposite to the second direction Y. The orthographic projection of the second top-gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second top-gate electrode 42 may serve as the top gate electrode of the second transistor T2. In an exemplary embodiment, the orthographic projection of the second top-gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second bottom-gate electrode 22 on the substrate. The second bottom-gate electrode 22 and the second top-gate electrode 42 form the second transistor T2 with a bottom-gate-top-gate structure.

[0169] In an exemplary embodiment, the third gate electrode 43 may be in the shape of a strip extending along the first direction X, may be located in the region where the second electrode 92 is located, and the orthographic projection of the third gate electrode 43 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate, and the third gate electrode 43 may serve as the gate electrode of the third transistor T3.

[0170] In an exemplary embodiment, the fourth top-gate electrode 44 may be in the shape of a strip extending along the first direction X and may be located between the first top-gate electrode 41 and the second electrode plate 92. The orthographic projection of the fourth top-gate electrode 44 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The fourth top-gate electrode 44 may serve as the top-gate electrode of the fourth transistor T4. In an exemplary embodiment, the orthographic projection of the fourth top-gate electrode 44 on the substrate at least partially overlaps with the orthographic projection of the fourth bottom-gate electrode 24 on the substrate. The fourth bottom-gate electrode 24 and the fourth top-gate electrode 44 form the fourth transistor T4 having a bottom-gate-top-gate structure.

[0171] In an exemplary embodiment, the fifth top-gate electrode 45 may be in the shape of a strip extending along the first direction X and may be located on a side of the second top-gate electrode 42 away from the second electrode plate 92. The orthographic projection of the fifth top-gate electrode 45 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer on the substrate. The fifth top-gate electrode 45 may serve as the top gate electrode of the fifth transistor T5. In an exemplary embodiment, the orthographic projection of the fifth top-gate electrode 45 on the substrate at least partially overlaps with the orthographic projection of the fifth bottom-gate electrode 25 on the substrate. The fifth bottom-gate electrode 25 and the fifth top-gate electrode 45 form the fifth transistor T5 with a bottom-gate-top-gate structure.

[0172] (6) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 13 .

[0173] In an exemplary embodiment, the multiple vias of each circuit unit in the display area include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17 and an eighteenth via V18.

[0174] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first initial signal line to the first region of the first active layer through the via hole.

[0175] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the second area of ​​the third active layer) on the substrate, the sixth insulating layer and the fifth insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the second area of ​​the third active layer), and the second via hole V2 is configured to connect the subsequently formed first connecting electrode to the second area of ​​the first active layer (also the second area of ​​the third active layer) through the via hole.

[0176] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed second initial signal line to the first region of the second active layer through the via hole.

[0177] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the second active layer (also the second region of the fourth active layer) on the substrate, the sixth insulating layer and the fifth insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the second active layer (also the second region of the fourth active layer), and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer (also the second region of the fourth active layer) through the via hole.

[0178] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the fifth via hole V5 are etched away to expose the surface of the first region of the fourth active layer, and the fifth via hole V5 is configured to connect a subsequently formed third connecting electrode to the first region of the fourth active layer through the via hole.

[0179] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the sixth via V6 are etched away to expose the surface of the first region of the fifth active layer, and the sixth via V6 is configured to connect a subsequently formed first power connection line to the first region of the fifth active layer through the via.

[0180] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first bottom gate electrode 21 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the seventh via hole V7 are etched away to expose the surface of the first bottom gate electrode 21, and the seventh via hole V7 is configured to connect the subsequently formed third scanning signal line to the first bottom gate electrode 21 through the via hole.

[0181] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first top gate electrode 41 on the substrate, the sixth insulating layer in the eighth via hole V8 is etched away to expose the surface of the first top gate electrode 41, and the eighth via hole V8 is configured to connect the subsequently formed third scan signal line to the first top gate electrode 41 through the via hole.

[0182] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second bottom gate electrode 22 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the ninth via hole V9 are etched away to expose the surface of the second bottom gate electrode 22, and the ninth via hole V9 is configured to connect the subsequently formed second scanning signal line to the second bottom gate electrode 22 through the via hole.

[0183] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second top gate electrode 42 on the substrate, the sixth insulating layer in the tenth via hole V10 is etched away to expose the surface of the second top gate electrode 42, and the tenth via hole V10 is configured to connect a subsequently formed second scan signal line to the second top gate electrode 42 through the via hole.

[0184] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the third gate electrode 43 on the substrate, the sixth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the third gate electrode 43, and the eleventh via hole V11 is configured to connect a subsequently formed second connecting electrode to the third gate electrode 43 through the via hole.

[0185] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the fourth bottom gate electrode 24 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the twelfth via hole V12 are etched away to expose the surface of the fourth bottom gate electrode 24, and the twelfth via hole V12 is configured to connect a subsequently formed first scanning signal line to the fourth bottom gate electrode 24 through the via hole.

[0186] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the fourth top gate electrode 44 on the substrate, the sixth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the fourth top gate electrode 44, and the thirteenth via hole V13 is configured to connect the subsequently formed first scan signal line to the fourth top gate electrode 44 through the via hole.

[0187] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the fifth bottom gate electrode 25 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the fifth bottom gate electrode 25, and the fourteenth via hole V14 is configured to connect a subsequently formed light-emitting signal line to the fifth bottom gate electrode 25 through the via hole.

[0188] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the fifth top gate electrode 45 on the substrate, the sixth insulating layer in the fifteenth via hole V15 is etched away to expose the surface of the fifth top gate electrode 45, and the fifteenth via hole V15 is configured to connect a subsequently formed light-emitting signal line to the fifth top gate electrode 45 through the via hole.

[0189] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the plate connecting block 91-1 on the first plate 91 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the plate connecting block 91-1, and the sixteenth via hole V16 is configured to connect the subsequently formed second connecting electrode to the plate connecting block 91-1 through the via hole.

[0190] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the semiconductor block 11-1 on the first semiconductor line 11 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the semiconductor block 11-1. The seventeenth via V17 is configured to connect the subsequently formed first power connection line to the semiconductor block 11-1 through the via.

[0191] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second electrode plate 92 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the second electrode plate 92, and the eighteenth via hole V18 is configured to connect the subsequently formed first connecting electrode to the second electrode plate 92 through the via hole.

[0192] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 14A and FIG. 14B , where FIG. 14B is a plan view schematic diagram of the fourth conductive layer in FIG. 14A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0193] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display area includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a first power connection line 61, a second power connection line 62, a first initial signal line 63, a second initial signal line 64, a first scanning signal line 71, a second scanning signal line 72, a third scanning signal line 73 and a light-emitting signal line 74.

[0194] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip extending along the first direction X. The first connection electrode 51 is connected to the second region of the first active layer (also the second region of the third active layer) via a second via V2, and is connected to the second electrode plate 92 via an eighteenth via V18. In an exemplary embodiment, the first connection electrode 51 enables the second electrode of the first transistor T1, the second electrode of the third transistor T3, and the second electrode plate 92 of the storage capacitor to have the same potential. The first connection electrode 51 may serve as a third node N3 of the pixel driving circuit. The first connection electrode 51 is configured to be connected to a subsequently formed anode connection electrode.

[0195] In an exemplary embodiment, the second connection electrode 52 may be in an "L" shape. A first end of the second connection electrode 52 is connected to the second region of the second active layer (also the second region of the fourth active layer) via a fourth via V4. A second end of the second connection electrode 52 is connected to the third gate electrode 43 via an eleventh via V11. The portion between the first and second ends of the second connection electrode 52 is connected to the plate connection block 91-1 via a sixteenth via V16. Since the plate connection block 91-1 is connected to the first plate 91 and the third gate electrode 43 serves as the gate electrode of the third transistor T3, the second connection electrode 52 connects the second electrode of the second transistor T2, the second electrode of the fourth transistor T4, the gate electrode of the third transistor T3, and the first plate 91 of the storage capacitor. The second connection electrode 52 may serve as the first node N1 of the pixel driving circuit.

[0196] In an exemplary embodiment, the third connection electrode 53 may be block-shaped (eg, rectangular), connected to the first region of the fourth active layer through the fifth via hole V5, and configured to be connected to a subsequently formed data signal line.

[0197] In an exemplary embodiment, the first power connection line 61 can be shaped as a straight line or a zigzag line, with its main portion extending along the first direction X. It can be disposed on the side of the circuit unit opposite the second direction Y. The first power connection line 61 is connected to the first region of the fifth active layer via the sixth via V6 and to the semiconductor block 11-1 via the seventeenth via V17. Because the first power connection line 61 is configured to connect to a subsequently formed first power line, it can write the first power signal to the first electrode of the fifth transistor T5. Since the semiconductor block 11-1 is connected to the first semiconductor line 11, and the first, second, and third semiconductor lines 11, 12, and 13 are interconnected, a network structure for transmitting the first power signal is formed within the first semiconductor layer of the display area. This improves panel uniformity, prevents display defects on the display substrate, and ensures the display quality of the display substrate.

[0198] In an exemplary embodiment, an orthographic projection of the first power connection line 61 on the substrate at least partially overlaps an orthographic projection of the first semiconductor line 11 in the first semiconductor layer on the substrate.

[0199] In an exemplary embodiment, a first power connection block 61-1 may be provided on the first power connection line 61. The first power connection block 61-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the first power connection line 61 away from the second electrode plate 92. A first end of the first power connection block 61-1 is connected to the first power connection line 61, and a second end of the first power connection block 61-1 extends in a direction away from the second electrode plate 92. The first power connection block 61-1 is configured to be connected to a first power line formed subsequently.

[0200] In an exemplary embodiment, the second power connection line 62 may be in a straight line or a broken line shape with a main portion extending along the first direction X, and may be disposed on one side of the circuit unit in the second direction Y.

[0201] In an exemplary embodiment, a second power connection block 62-1 may be provided on the second power connection line 62. The second power connection line 62 may be block-shaped (e.g., rectangular) and may be provided at least on one side of the second power connection line 62 away from the second electrode plate 92. The first end of the second power connection block 62-1 is connected to the second power connection line 62, and the second end of the second power connection block 62-1 extends in a direction away from the second electrode plate 92. The second power connection block 62-1 is configured to connect to a subsequently formed second power line. In an exemplary embodiment, only one second power connection block 62-1 may be provided for every three circuit units in a unit column. For example, the second power connection block 62-1 may be provided on a side of the first circuit unit Q1 in the opposite direction of the first direction X.

[0202] In an exemplary embodiment, the shape of the first initial signal line 63 can be a straight line or a broken line with the main portion extending along the first direction X, and can be arranged between the second power connection line 62 and the second electrode plate 92. The first initial signal line 63 is connected to the first area of ​​the first active layer through the first via V1, so that the first initial signal line 63 can write the first initial signal into the first electrode of the first transistor T1.

[0203] In an exemplary embodiment, an orthographic projection of the first preliminary signal line 63 on the substrate at least partially overlaps with an orthographic projection of the second semiconductor line 12 in the first semiconductor layer on the substrate.

[0204] In an exemplary embodiment, a first initial connection block 63-1 may be provided on the first initial signal line 63. The first initial connection block 63-1 may be block-shaped (e.g., rectangular) and may be provided at least on one side of the first initial signal line 63 near the second electrode plate 92. The first end of the first initial connection block 63-1 is connected to the first initial signal line 63, and the second end of the first initial connection block 63-1 extends toward the second electrode plate 92. The first initial connection block 63-1 is configured to connect to a subsequently formed first initial connection line. In an exemplary embodiment, in a cell column, only one first initial connection block 63-1 may be provided for every three circuit cells. For example, the first initial connection block 63-1 may be provided on one side of the first circuit cell Q1 in the first direction X.

[0205] In an exemplary embodiment, the shape of the second initial signal line 64 can be a straight line or a broken line with the main portion extending along the first direction X, and can be arranged between the first power connection line 61 and the second electrode plate 92. The second initial signal line 64 is connected to the first area of ​​the second active layer through the third via V3, so that the second initial signal line 64 can write the second initial signal into the first electrode of the second transistor T2.

[0206] In an exemplary embodiment, a second initial connection block 64-1 may be provided on the second initial signal line 64. The second initial connection block 64-1 may be block-shaped (e.g., rectangular) and may be provided at least on one side of the second initial signal line 64 away from the second electrode plate 92. The first end of the second initial connection block 64-1 is connected to the second initial signal line 64, and the second end of the second initial connection block 64-1 extends in a direction away from the second electrode plate 92. The second initial connection block 64-1 is configured to connect to a subsequently formed second initial connection line. In an exemplary embodiment, only one second initial connection block 64-1 may be provided for every three circuit cells in a cell column. For example, the first initial connection block 63-1 may be provided on one side of the second circuit cell Q2 in the first direction X.

[0207] In an exemplary embodiment, the first scan signal line 71 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The first scan signal line 71 may be disposed between the first initial signal line 63 and the second electrode plate 92. The first scan signal line 71 is connected to the fourth bottom gate electrode 24 via a twelfth via hole V12, and to the fourth top gate electrode 44 via a thirteenth via hole V13. Because the fourth bottom gate electrode 24 and the fourth top gate electrode 44 serve as the bottom gate electrode and the top gate electrode of the fourth transistor T4, respectively, the first scan signal line 71 is simultaneously connected to the fourth bottom gate electrode 24 and the fourth top gate electrode 44, thereby enabling the first scan signal line 71 to control the conduction and disconnection of the fourth transistor T4.

[0208] In an exemplary embodiment, the second scan signal line 72 may be in the shape of a straight line or a zigzag line, with its main portion extending along the first direction X. It may be disposed between the second initial signal line 64 and the second electrode plate 92. The second scan signal line 72 is connected to the second bottom gate electrode 22 via a ninth via hole V9 and to the second top gate electrode 42 via a tenth via hole V10. Because the second bottom gate electrode 22 and the second top gate electrode 42 serve as the bottom gate electrode and the second top gate electrode 42, respectively, of the second transistor T2, the second scan signal line 72 is simultaneously connected to the second bottom gate electrode 22 and the second top gate electrode 42, thereby enabling the second scan signal line 72 to control the conduction and disconnection of the second transistor T2.

[0209] In an exemplary embodiment, the third scan signal line 73 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The third scan signal line 73 may be disposed between the first initial signal line 63 and the first scan signal line 71. The third scan signal line 73 is connected to the first bottom gate electrode 21 via the seventh via V7 and to the first top gate electrode 41 via the eighth via V8. Because the first bottom gate electrode 21 and the first top gate electrode 41 serve as the bottom gate electrode and the top gate electrode of the first transistor T1, respectively, the third scan signal line 73 is simultaneously connected to the first bottom gate electrode 21 and the first top gate electrode 41. This allows the third scan signal line 73 to control the on / off state of the first transistor T1.

[0210] In an exemplary embodiment, the light-emitting signal line 74 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The light-emitting signal line 74 may be disposed between the first power connection line 61 and the second initial signal line 64. The light-emitting signal line 74 is connected to the fifth bottom gate electrode 25 via a fourteenth via hole V14 and to the fifth top gate electrode 45 via a fifteenth via hole V15. Because the fifth bottom gate electrode 25 and the fifth top gate electrode 45 serve as the bottom gate electrode and the top gate electrode of the fifth transistor T5, respectively, the light-emitting signal line 74 is simultaneously connected to the fifth bottom gate electrode 25 and the fifth top gate electrode 45. This allows the light-emitting signal line 74 to control the conduction and disconnection of the fifth transistor T5.

[0211] (8) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 15 .

[0212] In an exemplary embodiment, the plurality of via holes in each circuit unit in the display area includes at least a twenty-first via hole V21 , a twenty-second via hole V22 , and a twenty-third via hole V23 .

[0213] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first power connection block 61-1 on the first power connection line 61 on the substrate, the first flat layer within the twenty-first via V21 is etched away to expose the surface of the first power connection block 61-1, and the twenty-first via V21 is configured to connect the subsequently formed first power line to the first power connection block 61-1 through the via.

[0214] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-second via hole V22 is etched away to expose the surface of the third connecting electrode 53, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the third connecting electrode 53 through the via hole.

[0215] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the first connecting electrode 51 on the substrate, the first flat layer within the twenty-third via hole V23 is etched away to expose the surface of the first connecting electrode 51, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the first connecting electrode 51 through the via hole.

[0216] In an exemplary embodiment, the plurality of via holes in the display area may further include a thirty-first via hole V31 , a thirty-second via hole V32 , and a thirty-third via hole V33 .

[0217] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the second power connection block 62-1 on the second power connection line 62 on the substrate. The first flat layer within the thirty-first via V31 is etched away, exposing the surface of the second power connection block 62-1. The thirty-first via V31 is configured to connect a subsequently formed second power line to the second power connection block 62-1 through the via. In an exemplary embodiment, in a cell column, only one thirty-first via V31 may be provided for every three circuit cells.

[0218] In an exemplary embodiment, the orthographic projection of the 32nd via V32 on the substrate is located within the range of the orthographic projection of the first initial connection block 63-1 on the first initial signal line 63 on the substrate. The first flat layer within the 32nd via V32 is etched away, exposing the surface of the first initial connection block 63-1. The 32nd via V32 is configured to connect a subsequently formed first initial connection line to the first initial connection block 63-1 through the via. In an exemplary embodiment, in a cell column, only one 32nd via V32 may be provided for every three circuit cells.

[0219] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the orthographic projection of the second initial connection block 64-1 on the second initial signal line 64. The first flat layer within the thirty-third via V33 is etched away, exposing the surface of the second initial connection block 64-1. The thirty-third via V33 is configured to connect a subsequently formed second initial connection line to the second initial connection block 64-1 through the via. In an exemplary embodiment, only one thirty-third via V33 may be provided for every three circuit cells in a cell column.

[0220] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG16A and FIG16B , where FIG16B is a planar schematic diagram of the fifth conductive layer in FIG16A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0221] In an exemplary embodiment, the fifth conductive layer of each circuit unit in the display area includes at least a first power supply line 81 , a data signal line 85 , and an anode connection electrode 86 .

[0222] In an exemplary embodiment, the first power line 81 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first power line 81 is connected to the first power connection block 61-1 via the twenty-first via hole V21. Since the first power connection block 61-1 is connected to the first power connection line 61, a connection is established between the first power line 81 and the first power connection line 61. The first power connection line 61, whose main portion extends along the first direction X, and the first power line 81, whose main portion extends along the second direction Y, form a network of first power lines in the display area. This minimizes the resistance of the first power line and reduces the voltage drop of the first power signal, effectively improving the uniformity of the first power signal in the display substrate, effectively improving display uniformity, and enhancing display quality.

[0223] In an exemplary embodiment, a first shielding block 81-1 is connected to the first power line 81. The orthographic projection of the first shielding block 81-1 on the substrate at least partially overlaps with the orthographic projections of the fifth bottom-gate electrode 25 and the fifth top-gate electrode 45 on the substrate. The first shielding block 81-1 can shield the fifth transistor T5, reduce the influence of other signals in the pixel driving circuit on the fifth transistor T5, and improve the operating stability of the fifth transistor T5.

[0224] In an exemplary embodiment, the orthographic projection of the first power line 81 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. The first power line 81 can shield the first transistor T1, reduce the impact of light on the electrical characteristics of the first transistor T1, and improve the operating stability of the first transistor T1.

[0225] In an exemplary embodiment, the orthographic projection of the first power line 81 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The first power line 81 can shield the third transistor T3, reduce the impact of light on the electrical characteristics of the third transistor T3, and improve the operating stability of the third transistor T3.

[0226] In an exemplary embodiment, the orthographic projection of the first power line 81 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer on the substrate. The first power line 81 can shield the fifth transistor T5, reduce the impact of light on the electrical characteristics of the fifth transistor T5, and improve the operating stability of the fifth transistor T5.

[0227] In an exemplary embodiment, the data signal line 85 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The data signal line 85 is connected to the third connection electrode 53 through the twenty-second via hole V22. Since the third connection electrode 53 is connected to the first region of the fourth active layer, the data signal line 85 is connected to the first electrode of the fourth transistor T4. The data signal line 85 can write a data signal to the first electrode of the fourth transistor T4.

[0228] In an exemplary embodiment, the anode connection electrode 86 may be in the shape of a strip extending along the second direction Y. The anode connection electrode 86 is connected to the first connection electrode 51 through the twenty-third via hole V23. The anode connection electrode 86 is configured to be connected to a subsequently formed anode. Since the first connection electrode 51 is connected to the second region of the first active layer (which is also the second region of the third active layer), the subsequently formed anode is connected to the second electrode of the first transistor T1 and the second electrode of the third transistor T3, and the pixel driving circuit can drive the light-emitting device to emit light.

[0229] In an exemplary embodiment, the fifth conductive layer of the display area may further include a second power supply line 82 , a first preliminary connection line 83 , and a second preliminary connection line 84 .

[0230] In an exemplary embodiment, the second power line 82 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The second power line 82 is connected to the second power connection block 62-1 via the thirty-first via hole V31. Since the second power connection block 62-1 is connected to the second power connection line 62, a connection is established between the second power line 82 and the second power connection line 62. The second power connection line 62, whose main portion extends along the first direction X, and the second power line 82, whose main portion extends along the second direction Y, form a network of second power lines in the display area. This minimizes the resistance of the second power line and reduces the voltage drop of the second power signal, effectively improving the uniformity of the second power signal in the display substrate, effectively improving display uniformity, and enhancing display quality.

[0231] In an exemplary embodiment, in at least one cell column, a second shielding block 82-1 is connected to the second power line 82. The orthographic projection of the second shielding block 82-1 on the substrate at least partially overlaps with the orthographic projections of the second bottom-gate electrode 22 and the second top-gate electrode 42 on the substrate. The second shielding block 82-1 can shield the second transistor T2, thereby reducing the influence of other signals in the pixel driving circuit on the second transistor T2 and improving the operating stability of the second transistor T2.

[0232] In an exemplary embodiment, only one second power line 82 may be provided for every three circuit cells in a cell row. For example, the second power line 82 may be provided in the first circuit cell Q1.

[0233] In an exemplary embodiment, in at least one unit column, the orthographic projection of the second power line 82 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second power line 82 can shield the second transistor T2, reduce the impact of light on the electrical characteristics of the second transistor T2, and improve the operating stability of the second transistor T2.

[0234] In an exemplary embodiment, in at least one unit column, the orthographic projection of the second power line 82 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The second power line 82 can shield the fourth transistor T4, reduce the impact of light on the electrical characteristics of the fourth transistor T4, and improve the operating stability of the fourth transistor T4.

[0235] In an exemplary embodiment, in at least one cell column, an orthographic projection of the second power line 82 on the substrate at least partially overlaps an orthographic projection of the third semiconductor line 13 in the first semiconductor layer on the substrate.

[0236] In an exemplary embodiment, the first initial connection line 83 may be in the shape of a straight line or a broken line extending along the second direction Y. The first initial connection line 83 is connected to the first initial connection block 63-1 via the thirty-second via hole V32. Since the first initial connection block 63-1 is connected to the first initial signal line 63, a connection is established between the first initial signal line 63 and the first initial connection line 83. The first initial signal line 63, whose main portion extends along the first direction X, and the first initial connection line 83, whose main portion extends along the second direction Y, form a network of first initial signal lines in the display area. This minimizes the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, effectively improving the uniformity of the first initial signal across the display substrate, effectively improving display uniformity, and enhancing both display quality and display quality.

[0237] In an exemplary embodiment, in at least one cell column, a third shielding block 83-1 is connected to the first initial connection line 83. The orthographic projection of the third shielding block 83-1 on the substrate at least partially overlaps with the orthographic projections of the second bottom-gate electrode 22 and the second top-gate electrode 42 on the substrate. The third shielding block 83-1 can shield the second transistor T2, thereby reducing the influence of other signals in the pixel driving circuit on the second transistor T2 and improving the operating stability of the second transistor T2.

[0238] In an exemplary embodiment, only one first preliminary connection line 83 may be provided for every three circuit cells in one cell row. For example, the first preliminary connection line 83 may be provided in the second circuit cell Q2.

[0239] In an exemplary embodiment, in at least one unit column, the orthographic projection of the first initial connection line 83 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The first initial connection line 83 can shield the second transistor T2, reduce the impact of light on the electrical characteristics of the second transistor T2, and improve the operating stability of the second transistor T2.

[0240] In an exemplary embodiment, in at least one unit column, the orthographic projection of the first initial connection line 83 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The first initial connection line 83 can shield the fourth transistor T4, reduce the impact of light on the electrical characteristics of the fourth transistor T4, and improve the operating stability of the fourth transistor T4.

[0241] In an exemplary embodiment, in at least one cell column, an orthographic projection of the first preliminary connection line 83 on the substrate at least partially overlaps with an orthographic projection of the third semiconductor line 13 in the first semiconductor layer on the substrate.

[0242] In an exemplary embodiment, the second initial connection line 84 may be in the form of a straight line or a zigzag line extending along the second direction Y. The second initial connection line 84 is connected to the second initial connection block 64-1 via the thirty-third via hole V33. Since the second initial connection block 64-1 is connected to the second initial signal line 64, a connection is established between the second initial signal line 64 and the second initial connection line 84. The second initial signal line 64, whose main portion extends along the first direction X, and the second initial connection line 84, whose main portion extends along the second direction Y, form a network of second initial signal lines in the display area. This minimizes the resistance of the second initial signal line and reduces the voltage drop of the second initial signal, effectively improving the uniformity of the first initial signal across the display substrate, effectively improving display uniformity, and enhancing both display quality and display quality.

[0243] In an exemplary embodiment, in at least one cell column, a fourth shielding block 84 - 1 is connected to the second initial connection line 84 , and an orthographic projection of the fourth shielding block 84 - 1 on the substrate at least partially overlaps with an orthographic projection of the second bottom-gate electrode 22 and the second top-gate electrode 42 on the substrate. The fourth shielding block 84 - 1 can shield the second transistor T2, thereby reducing the influence of other signals in the pixel driving circuit on the second transistor T2 and improving the operating stability of the second transistor T2.

[0244] In an exemplary embodiment, only one second preliminary connection line 84 may be provided for every three circuit cells in one cell row. For example, the second preliminary connection line 84 may be provided in the third circuit cell Q2.

[0245] In an exemplary embodiment, in at least one unit column, the orthographic projection of the second initial connection line 84 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second initial connection line 84 can shield the second transistor T2, reduce the impact of light on the electrical characteristics of the second transistor T2, and improve the operating stability of the second transistor T2.

[0246] In an exemplary embodiment, in at least one unit column, the orthographic projection of the second initial connection line 84 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The second initial connection line 84 can shield the fourth transistor T4, reduce the impact of light on the electrical characteristics of the fourth transistor T4, and improve the operating stability of the fourth transistor T4.

[0247] In an exemplary embodiment, in at least one cell column, an orthographic projection of the second initial connection line 84 on the substrate at least partially overlaps an orthographic projection of the third semiconductor line 13 in the first semiconductor layer on the substrate.

[0248] In an exemplary embodiment, the first power line 81, the second power line 82, the first initial connection line 83, the second initial connection line 84 and the data signal line 85 can be folded lines of unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0249] (10) Forming a second flat layer pattern. In an exemplary embodiment, forming the second flat layer pattern may include: coating a second flat film on the substrate on which the aforementioned pattern is formed, patterning the second flat film using a patterning process to form a second flat layer covering the fifth conductive layer pattern, wherein at least an anode via is provided on the second flat layer, wherein the orthographic projection of the anode via on the substrate is located within the range of the orthographic projection of the anode connection electrode 86 on the substrate, the second flat layer in the anode via is etched away to expose the surface of the anode connection electrode 86, and the anode via is configured to connect a subsequently formed anode to the anode connection electrode 86 through the via.

[0250] At this point, the driving structure layer is prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, and a second flat layer arranged in sequence on the substrate. The first semiconductor layer may include at least a semiconductor line of a network connection structure, the first conductive layer may include at least a first electrode plate of a storage capacitor, the second conductive layer may include at least a second electrode plate of a storage capacitor and bottom gate electrodes of multiple transistors, the second semiconductor layer may include at least an active layer of multiple transistors, the third conductive layer may include at least top gate electrodes of multiple transistors, the fourth conductive layer may include at least a first power connection line, a second power connection line, a first initial signal line, a second initial signal line, a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line and multiple connection electrodes, and the fifth conductive layer may include at least a first power line, a second power line, a data signal line, a first initial connection line, a second initial connection line and an anode connection electrode.

[0251] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0252] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first planarizing layer and the second planarizing layer can be made of an organic material, such as a resin.

[0253] In an exemplary embodiment, after the driving structure layer is prepared, the light emitting structure layer may be prepared on the driving structure layer first, and then the encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.

[0254] Figure 17 is a schematic diagram of a semiconductor trace in a border region according to an exemplary embodiment of the present disclosure, illustrating the structure of the first semiconductor layer in region A of Figure 2. As shown in Figure 17, in a direction parallel to the display substrate, the display substrate may include a display region 100 and a border region 300 located on at least one side of the display region 100. The display region 100 may include at least a plurality of circuit cells Q constituting a plurality of cell rows and a plurality of cell columns. The border region 300 may include at least a plurality of gate cells G extending along a direction parallel to the edge of the display region, where the edge of the display region is the edge of the display region adjacent to the border region. In a direction perpendicular to the display substrate, the display substrate may include at least a first semiconductor layer. The first semiconductor layer of the display region 100 may include at least semiconductor lines disposed in the circuit cells Q. The first semiconductor layer of the border region 300 may include at least a plurality of gate active layers disposed in the gate cells G, and at least one semiconductor trace disposed between the circuit cells Q and the gate cells G. The semiconductor lines in the display region 100, the plurality of gate active layers in the border region 300, and the at least one semiconductor trace in the border region 300 are disposed on the same layer, made of the same material, and formed simultaneously through the same patterning process.

[0255] In an exemplary embodiment, the semiconductor wires arranged in the circuit unit Q may include at least a first semiconductor wire 11, a second semiconductor wire 12, and a third semiconductor wire 13 constituting a network connectivity structure. In a unit row, the first semiconductor wires 11 of multiple circuit units are an integrated structure connected in sequence, the second semiconductor wires 12 of multiple circuit units are an integrated structure connected in sequence, and in a unit column, the third semiconductor wires 13 of multiple circuit units are an integrated structure connected in sequence.

[0256] In an exemplary embodiment, the plurality of gate active layers 301 disposed in the gate unit G may serve as active layers of a plurality of gate transistors, and the plurality of gate transistors and capacitors constitute a gate driving circuit.

[0257] In an exemplary embodiment, the shape of the semiconductor wiring 310 arranged between the circuit unit Q and the gate unit G can be a straight line or a broken line extending in a direction parallel to the edge of the display area, and the semiconductor wiring 310 is respectively connected to the first semiconductor line 11 and the second semiconductor line 12 of multiple unit rows in the display area 100.

[0258] In an exemplary embodiment, the number of semiconductor traces 310 in the border region 300 may be one or multiple, and the multiple semiconductor traces 310 may be connected to each other.

[0259] In an exemplary embodiment, the first semiconductor wires 11 and the second semiconductor wires 12 of the plurality of cell rows in the display region 100 and the semiconductor traces 310 in the frame region 300 may be an integrated structure connected to each other.

[0260] In an exemplary embodiment, in a direction parallel to the display substrate, the circuit unit Q has a first unit area, and the gate unit G has a second unit area. In at least one circuit unit Q, the orthographic projections of the first semiconductor wire 11, the second semiconductor wire 12, and the third semiconductor wire 13 on the substrate have a first area, and in at least one gate unit G, the orthographic projections of the plurality of gate active layers 301 on the substrate have a second area. The ratio of the first area to the first unit area has a first ratio, and the ratio of the second area to the second unit area has a second ratio. The ratio of the first ratio to the second ratio can be approximately 0.9 to 1.1. For example, the ratio of the first ratio to the second ratio can be approximately 1.0.

[0261] In an exemplary embodiment, the first ratio may be approximately 0.1 to 0.2. For example, the first ratio may be approximately 0.15, that is, the proportion of the polysilicon layer in the display area is approximately 0.15.

[0262] In an exemplary embodiment, the second ratio may be approximately 0.1 to 0.2. For example, the second ratio may be approximately 0.15, that is, the proportion of the polysilicon layer in the border region is approximately 0.15.

[0263] From the structure and preparation process of the display substrate described above, it can be seen that the display substrate provided by the exemplary embodiment of the present disclosure, by setting semiconductor wires in the first semiconductor layer of the display area, the semiconductor wires are connected to the first power lines, and a mesh connection structure for transmitting the first power signal is formed in the first semiconductor layer. This can effectively reduce the resistance of the first power line, reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0264] In a display substrate, the pixel driving circuit in the display area uses oxide transistors, and the gate driving circuit in the frame area uses polysilicon transistors. Therefore, a polysilicon layer is provided in the frame area, but not in the display area, resulting in defects such as uneven etching of the polysilicon layer. The present disclosure can effectively avoid defects such as uneven etching of the polysilicon layer existing in existing display substrates by providing semiconductor lines in the polysilicon layer in the display area, thereby improving the yield of the display substrate. The present disclosure can further improve the etching uniformity of the polysilicon layer by setting the proportion of the polysilicon layer in the display area to be similar to that of the polysilicon layer in the frame area, thereby maximizing the yield of the display substrate.

[0265] The present disclosure sets semiconductor leads in the polysilicon layer in the frame area, connects the semiconductor leads to the semiconductor lines in the display area, and connects multiple semiconductor lines in the display area outside the display area, which can effectively eliminate static electricity in the display area and improve process quality and product yield.

[0266] The present disclosure forms another mesh connection structure for transmitting the first power signal in the display area by providing a first power connection line extending along a first direction X and a first power line extending along a second direction Y in the display area. That is, the display area of ​​the present disclosure is provided with two network connection structures for transmitting the first power signal, and the two network connection structures are interconnected, which can further reduce the resistance of the first power line, further reduce the voltage drop of the first power signal, further improve the uniformity of the first power signal in the display substrate, further improve the display uniformity, and maximize the display quality.

[0267] The present disclosure provides first initial signal lines extending along a first direction X and first initial connection lines extending along a second direction Y within a display area, thereby forming first initial signal lines of a network connection structure within the display area. This effectively reduces the resistance of the first initial signal lines, reduces the voltage drop of the first initial signal, effectively improves the uniformity of the first initial signal in the display substrate, effectively improves display uniformity, and improves display quality.

[0268] The present disclosure provides a second initial signal line extending along a first direction X and a second initial connection line extending along a second direction Y within the display area, thereby forming a second initial signal line with a network connection structure in the display area. This can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0269] By disposing a second power connection line extending along a first direction X and a second power line extending along a second direction Y within the display area, the present disclosure not only implements a VSS-in-pixel structure but also effectively reduces the resistance of the second power line, reduces the voltage drop of the second power signal, and effectively improves the uniformity of the second power signal within the display substrate, effectively improving display uniformity, and enhancing display quality. Furthermore, the VSS-in-pixel structure can significantly reduce the width of the frame power lead in the border area, facilitating the realization of a narrow border.

[0270] The present disclosure can effectively improve the stability of the signal voltage in each signal line and improve the operating performance of the pixel driving circuit by arranging the first power connection line to at least partially overlap with the first semiconductor line, the first initial signal line to at least partially overlap with the second semiconductor line, and the second power line, the first initial connection line, and the second initial connection line to at least partially overlap with the third semiconductor line.

[0271] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0272] The structure and preparation process shown in the above disclosure are merely exemplary. In the exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, if the pixel driving circuit uses polysilicon transistors and the gate driving circuit uses oxide transistors, the semiconductor line can be provided in the oxide layer. For another example, the semiconductor line can be connected to the first initial signal line, the second initial signal line, or the second power line, which is not limited in this disclosure.

[0273] In an exemplary embodiment, the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.

[0274] The present disclosure also provides a method for manufacturing a display substrate, for producing the display substrate provided in the above-mentioned embodiment. In an exemplary embodiment, the display substrate includes a display area, the display area including a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit and at least one signal line transmitting a constant voltage signal, the pixel driving circuit including at least one pixel transistor; the manufacturing method may include:

[0275] A first semiconductor layer and a second semiconductor layer are formed on a substrate and are arranged on a side of the first semiconductor layer away from the substrate; in at least one circuit unit, one of the first semiconductor layer and the second semiconductor layer includes at least one semiconductor line, and the other semiconductor layer includes an active layer of the pixel transistor, and the semiconductor line is connected to the signal line.

[0276] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0277] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate includes a display area, the display area includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit and at least one signal line for transmitting a constant voltage signal, and the pixel driving circuit includes at least one pixel transistor. ； In a direction perpendicular to the display substrate, the display substrate at least includes a first semiconductor layer disposed on a substrate and a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate. In at least one circuit unit, one of the first semiconductor layer and the second semiconductor layer includes at least one semiconductor line, and the other semiconductor layer includes an active layer of the pixel transistor, and the semiconductor line is connected to the signal line.

2. The display substrate according to claim 1, wherein, in at least one circuit unit, the at least one semiconductor line includes a first semiconductor line and a second semiconductor line extending along the pixel row direction, and a third semiconductor line extending along the pixel column direction, and the first semiconductor line and the second semiconductor line are respectively connected to the third semiconductor line to form a network communication structure.

3. The display substrate according to claim 2, wherein, in at least one circuit unit, the at least one signal line includes a first power connection line extending along the pixel row direction and a first power line extending along the pixel column direction, the first power connection line and the first power line are connected to form a network communication structure, and the first power connection line is connected to the first semiconductor line.

4. The display substrate according to claim 3, wherein, a positive projection of the first power connection line on the substrate at least partially overlaps a positive projection of the first semiconductor line on the substrate.

5. The display substrate according to claim 3, wherein, in a direction perpendicular to the display substrate, the display substrate further includes a plurality of conductive layers, the first power connection line and the first power line are disposed in different conductive layers, the first power line is connected to the first power connection line through a via, and the first power connection line is connected to the first semiconductor line through a via.

6. The display substrate according to claim 2, wherein, in at least one circuit unit, the at least one signal line includes a second power connection line extending along the pixel row direction and a second power line extending along the pixel column direction, the second power connection line and the second power line are connected to form a network communication structure; a positive projection of the second power line on the substrate at least partially overlaps a positive projection of the third semiconductor line on the substrate.

7. The display substrate according to claim 2, wherein, in at least one circuit unit, the at least one signal line includes a first initial signal line extending along the pixel row direction and a first initial connection line extending along the pixel column direction, the first initial connection line and the first initial signal line are connected to form a network communication structure; a positive projection of the first initial connection line on the substrate at least partially overlaps a positive projection of the third semiconductor line on the substrate.

8. The display substrate according to claim 7, wherein, the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor line on the substrate.

9. The display substrate according to claim 2, wherein, in at least one circuit unit, the at least one signal line includes a second initial signal line extending along the pixel row direction and a second initial connection line extending along the pixel column direction, and the second initial connection line is connected to the second initial signal line to form a mesh communication structure; the orthographic projection of the second initial connection line on the substrate at least partially overlaps with the orthographic projection of the third semiconductor line on the substrate.

10. The display substrate according to claim 1, wherein, the pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate, the orthographic projection of the first electrode plate on the substrate does not overlap with the orthographic projection of the semiconductor line on the substrate, and the orthographic projection of the second electrode plate on the substrate does not overlap with the orthographic projection of the semiconductor line on the substrate.

11. The display substrate according to claim 1, wherein, the material of the first semiconductor layer includes polysilicon, the material of the second semiconductor layer includes an oxide, the first semiconductor layer includes the semiconductor line, and the second semiconductor layer includes the active layer of the pixel transistor.

12. The display substrate according to any one of claims 1 to 11, wherein, the display substrate further includes a border area provided on at least one side of the display area, the border area includes a plurality of gate units, at least one gate unit includes a gate driving circuit, the gate driving circuit includes a plurality of gate transistors, and the active layers of the gate transistors are provided on the same layer as the semiconductor line and have the same material.

13. The display substrate according to claim 12, wherein, in a direction parallel to the display substrate, the circuit unit has a first unit area, in at least one circuit unit, the orthographic projection of the semiconductor line on the substrate has a first area, and the ratio of the first area to the first unit area has a first ratio, and the first ratio is from 0.1 to 0.

2.

14. The display substrate according to claim 13, wherein, in a direction parallel to the display substrate, the gate unit has a second unit area, in at least one gate unit, the orthographic projection of the active layers of the plurality of gate transistors on the substrate has a second area, and the ratio of the second area to the second unit area has a second ratio, and the ratio of the first ratio to the second ratio is from 0.9 to 1.

1.

15. The display substrate according to claim 12, wherein, the border area further includes semiconductor leads, the semiconductor leads extend along the edge direction of the display area, and the semiconductor leads are connected to the semiconductor lines in a plurality of unit rows, and the edge of the display area is the edge of the display area close to the border area.

16. The display substrate according to claim 15, wherein, the semiconductor lead and the semiconductor wire are disposed in the same layer and are an integrally connected structure.

17. A display device, comprising the display substrate according to any one of claims 1 to 16.

18. A method for manufacturing a display substrate, the display substrate including a display area, the display area including a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit and at least one signal wire for transmitting a constant voltage signal, the pixel driving circuit including at least one pixel transistor; the manufacturing method comprises: forming a first semiconductor layer on a substrate and a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate; in at least one circuit unit, one of the first semiconductor layer and the second semiconductor layer includes at least one semiconductor wire, and the other semiconductor layer includes an active layer of the pixel transistor, and the semiconductor wire is connected to the signal wire.

Images