Display panel and display device

Abstract

A display panel, comprising: a base (10), a plurality of sub-pixels (PX) and a plurality of data lines (DL) which are located in a display area (AA), and a plurality of multiplexing circuits (40), a plurality of multiplexing data lines (61) and a plurality of multiplexing control lines (51, 52, 53, 54, 55, 56, 57, 58, 59) which are located in a first frame area (B1), wherein the orthographic projections of the plurality of multiplexing data lines (61) and the plurality of multiplexing control lines (51, 52, 53, 54, 55, 56, 57, 58, 59) on the base (10) do not overlap; and the plurality of multiplexing data lines (61) comprise a first group of multiplexing data lines (61a) and a second group of multiplexing data lines (61b), a portion of at least one of the multiplexing control lines (51, 52, 53, 54, 55, 56, 57, 58, 59) being located between the first group of multiplexing data lines (61a) and the second group of multiplexing data lines (61b).

Description

Display panel and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, display devices using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display panel and a display device.

[0006] On the one hand, this embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels and a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, and a plurality of multiplexing control lines. The substrate includes a display area and a first frame area located on at least one side of the display area. A plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. A plurality of multiplexing circuits, a plurality of multiplexing data lines, and a plurality of multiplexing control lines are located in the first frame area. The multiplexing circuit is connected to at least two multiplexing control lines among the plurality of multiplexing control lines, a multiplexing data line, and at least two data lines among the plurality of data lines, and is configured to provide the data signal transmitted by the one reset data line to the at least two data lines under the control of the at least two multiplexing control lines. The plurality of multiplexing data lines and the plurality of multiplexing control lines do not overlap in their orthographic projections onto the substrate. The plurality of multiplexed data lines are divided into a first group of multiplexed data lines and a second group of multiplexed data lines, and a portion of at least one multiplexed control line is located between the first group of multiplexed data lines and the second group of multiplexed data lines.

[0007] In some exemplary embodiments, the first border area includes at least a first signal access area and a second signal access area, the second signal access area being located on a side of the first signal access area away from the display area; and a plurality of multiplexing control contact pads being provided in the second signal access area. The multiplexing control line includes a first sub-line, a second sub-line, and a third sub-line, the third sub-line being connected between the first sub-line and the second sub-line. The third sub-line is located in the first signal access area. The second sub-line is located on a side of the first signal access area closer to the display area and between the first group of multiplexing data lines and the second group of multiplexing data lines. The first sub-line is connected to the multiplexing control contact pad of the second signal access area.

[0008] In some exemplary embodiments, the first signal access area is provided with a plurality of first multiplexing transfer pads and a plurality of second multiplexing transfer pads. The first sub-line of the multiplexing control line is connected to the third sub-line via the first multiplexing transfer pad, and the second sub-line of the multiplexing control line is connected to the third sub-line via the second multiplexing transfer pad.

[0009] In some exemplary embodiments, the first signal access area has a plurality of sides, and the plurality of first multiplexing transfer pads and the plurality of second multiplexing transfer pads are arranged along the same side.

[0010] In some exemplary embodiments, the first signal access area is further provided with a first group of data contact pads and a second group of data contact pads; the first group of data contact pads is connected to the first group of multiplexed data lines, and the second group of data contact pads is connected to the second group of multiplexed data lines. The plurality of first multiplexed transfer pads are divided into a first group of first multiplexed transfer pads and a second group of first multiplexed transfer pads. The plurality of second multiplexed transfer pads are located between the first group of data contact pads and the second group of data contact pads. The first group of first multiplexed transfer pads is located on a side of the first group of data contact pads away from the plurality of second multiplexed transfer pads, and the second group of first multiplexed transfer pads is located on a side of the second group of data contact pads away from the plurality of second multiplexed transfer pads.

[0011] In some exemplary embodiments, the first signal access area has at least a first side and a second side extending in the same direction, and the second side is located on the side of the first side away from the display area; the multiple first multiplexing transfer pads are arranged along the second side, and the multiple second multiplexing transfer pads are arranged along the first side.

[0012] In some exemplary embodiments, in an extension direction of the second sub-line, the plurality of first multiplexing transfer pads and the plurality of second multiplexing transfer pads are at least partially aligned.

[0013] In some exemplary embodiments, a plurality of DC signal transmission lines are provided in the first border region; and the first sub-line of the multiplexing control line and at least one DC signal transmission line overlap in orthographic projection on the substrate.

[0014] In some exemplary embodiments, the second signal access area is further provided with a plurality of DC signal contact pads arranged along a first direction; the plurality of DC signal contact pads are configured to connect to the plurality of DC signal transmission lines; and the plurality of multiplexing control contact pads are located on a side of the plurality of DC signal contact pads that is close to an edge of the display panel.

[0015] In some exemplary embodiments, a plurality of square wave signal transmission lines are further provided in the first frame area, and the first sub-line of the multiplexing control line overlaps with an orthographic projection of at least one square wave signal transmission line on the substrate.

[0016] In some exemplary embodiments, the second signal access region is further provided with a plurality of square wave signal contact pads arranged along the first direction; the plurality of square wave signal contact pads are configured to connect to the plurality of square wave signal transmission lines. At least one square wave signal contact pad is provided between the plurality of multiplexing control contact pads and the plurality of DC signal contact pads.

[0017] In some exemplary embodiments, a plurality of DC signal transmission lines are provided in the first border region; and the first sub-line of the multiplexing control line and the plurality of DC signal transmission lines have no overlap in their orthographic projections on the substrate.

[0018] In some exemplary embodiments, the second signal access region is further provided with a plurality of DC signal contact pads arranged along a first direction; the plurality of DC signal contact pads are configured to connect to the plurality of DC signal transmission lines; and the plurality of multiplexing control contact pads are located on a side of the plurality of DC signal contact pads away from an edge of the display panel.

[0019] In some exemplary embodiments, the first border region is provided with a first power lead and a first shielding electrode, the first shielding electrode being connected to the first power lead; the first shielding electrode is located on a side of the first signal access region that is close to the display area. The second sub-lines of the plurality of multiplexed control lines are divided into a first group of second sub-lines and a second group of second sub-lines. The first shielding electrode is located between the first group of second sub-lines and the second group of second sub-lines.

[0020] In some exemplary embodiments, an orthographic projection of the first shielding electrode on the substrate does not overlap with an orthographic projection of the second sub-lines of the plurality of multiplexing control lines on the substrate.

[0021] In some exemplary embodiments, a second shielding electrode is further provided in the first border area. The second shielding electrode is located on a side of the first shielding electrode away from the substrate, and the second shielding electrode is electrically connected to the first shielding electrode. The orthographic projection of the second shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first shielding electrode on the substrate.

[0022] In some exemplary embodiments, the second shielding electrode is located on a side of the second sub-line of the plurality of multiplexing control lines away from the substrate, and an orthographic projection of the second shielding electrode on the substrate overlaps with an orthographic projection of the second sub-line of at least one multiplexing control line on the substrate.

[0023] On the other hand, this embodiment provides a display device including the display panel as described above.

[0024] In some exemplary embodiments, the display device further includes a driver chip connected to the display panel and a flexible printed circuit board. The first border region of the display panel includes at least a first signal access area and a second signal access area, with the second signal access area located on a side of the first signal access area away from the display area. The driver chip's orthographic projection on the display panel is located in the first signal access area, and at least some of the pins of the flexible printed circuit board are located in the second signal access area.

[0025] On the other hand, this embodiment provides a display panel comprising: a substrate, a plurality of sub-pixels and a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, and a plurality of multiplexing control lines. The substrate comprises a display area and a first frame area located on at least one side of the display area. The first frame area comprises at least a first signal access area, wherein the first signal access area is provided with a plurality of data contact pads. A plurality of sub-pixels and a plurality of data lines are located in the display area. The plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. A plurality of multiplexing circuits, a plurality of multiplexing data lines, and a plurality of multiplexing control lines are located in the first frame area. The multiplexing circuit is connected to at least two of the plurality of multiplexing control lines, a multiplexing data line, and at least two of the plurality of data lines, and is configured to provide the data signal transmitted by the one reset data line to the at least two data lines under the control of the at least two multiplexing control lines. The plurality of multiplexing data lines are connected to the plurality of data contact pads in the first signal access area. The orthographic projections of the multiplexed data lines and the multiplexed control lines on the substrate do not overlap; a portion of at least one multiplexed control line is located in the first signal access area.

[0026] In some exemplary embodiments, the first border area further includes a second signal access area, located on a side of the first signal access area away from the display area, and provided with a plurality of multiplexing control contact pads. The multiplexing control line includes a first sub-line, a second sub-line, and a third sub-line, the third sub-line being connected between the first sub-line and the second sub-line. The third sub-line is located in the first signal access area. The second sub-line is located on a side of the first signal access area closer to the display area. The first sub-line is connected to the multiplexing control contact pads of the second signal access area.

[0027] In some exemplary embodiments, the third sub-lines of the multiple multiplexing control lines are divided into a first group of third sub-lines and a second group of third sub-lines, and the first group of third sub-lines and the second group of third sub-lines are arranged along a first direction; the extension direction of the third sub-lines of the multiple multiplexing control lines crosses the extension direction of the second sub-lines.

[0028] In some example embodiments, an extending direction of the third sub-line of the plurality of multiplexing control lines is the same as an extending direction of the second sub-line.

[0029] In some exemplary embodiments, the plurality of multiplexed data lines are divided into a first group of multiplexed data lines and a second group of multiplexed data lines. The second sub-lines of the plurality of multiplexed control lines are divided into a first group of second sub-lines and a second group of second sub-lines; the first group of second sub-lines and the second group of second sub-lines are located between the first group of multiplexed data lines and the second group of multiplexed data lines. The first border area is provided with a first power lead and a first shielding electrode, the first shielding electrode being connected to the first power lead; the first shielding electrode is located on a side of the first signal access area close to the display area; and the first shielding electrode is located between the first group of second sub-lines and the second group of second sub-lines.

[0030] In some exemplary embodiments, a second shielding electrode is further provided in the first border area. The second shielding electrode is located on a side of the first shielding electrode away from the substrate, and the second shielding electrode is electrically connected to the first shielding electrode. The orthographic projection of the second shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first shielding electrode on the substrate.

[0031] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0032] Summary of the Figures

[0033] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0034] FIG1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0035] FIG2 is a partial cross-sectional schematic diagram of a display area of ​​a display panel according to at least one embodiment of the present disclosure;

[0036] FIG3 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0037] FIG4 is a diagram illustrating an arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure;

[0038] FIG5A is a partial plan view of a first frame region according to at least one embodiment of the present disclosure;

[0039] FIG5B is a partial plan view of a first border region according to at least one embodiment of the present disclosure;

[0040] FIG6A is a schematic top view of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0041] FIG6B is a schematic diagram of the multiplexing circuit after the first source / drain metal layer is formed in FIG6A ;

[0042] FIG6C is a schematic diagram of the multiplexing circuit after forming the second gate metal layer in FIG6A ;

[0043] FIG7 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure;

[0044] FIG8 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure;

[0045] FIG9 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure;

[0046] FIG10 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure;

[0047] FIG11 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure;

[0048] FIG12 is a partial schematic diagram of a second fan-out area according to at least one embodiment of the present disclosure;

[0049] FIG13 is another partial schematic diagram of the second fan-out area according to at least one embodiment of the present disclosure;

[0050] FIG14 is another partial schematic diagram of the second fan-out area according to at least one embodiment of the present disclosure;

[0051] FIG15 is a schematic partial cross-sectional view along the QQ' direction in FIG14;

[0052] FIG. 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0053] Details

[0054] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0055] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0056] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0057] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0058] In this specification, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "coupled" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meanings of these terms in this disclosure based on the specific circumstances.

[0059] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0060] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0061] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. The functions of "source electrode" and "drain electrode" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0062] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0063] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0064] In this disclosure, "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "same" includes both completely identical and substantially the same, and "substantially the same" means that the difference in value is within 10%.

[0065] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0066] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0067] With the advancement of display technology, increasing the screen-to-body ratio and reducing bezel size are key areas for improvement. Current display panels often incorporate multiplexing circuits (MUX) to reduce the number of data lines, thereby minimizing bezel size. For example, in wearable devices such as watches, the multiplexing circuit is crucial to the display quality. Especially in low grayscale displays, differences in signal load across the multiplexing circuit can lead to display artifacts such as light and dark stripes or a split screen. For example, when the multiplexing circuit adopts a 1:N (N is an odd number, such as N=9) design (i.e., the multiplexing circuit provides the data signal of a multiplexed data line to at least N data lines under the control of N multiplexing control lines), the N multiplexing control lines cannot be evenly divided into two groups for wiring, and there must be a difference in the signal load of the multiplexing control lines; when the multiplexing circuit adopts a 1:M (M is an even number, such as M=6) design (i.e., the multiplexing circuit provides the data signal of a multiplexed data line to at least M data lines under the control of M multiplexing control lines), although the M multiplexing control lines can be evenly divided into two groups for wiring, and the uniform wiring on the left and right is conducive to improving the low grayscale image quality, in the case of extremely low grayscale, the display panel will still have a split screen phenomenon, which cannot meet the user's further improved image quality requirements. Moreover, the signal load of the multiplexing control line of the multiplexing circuit is easily affected by other signals (e.g., data signals). Since the data signal is a high-frequency signal, the crosstalk between the multiplexing control signal and the data signal will affect the writing of the data signal, thereby affecting the display quality and causing poor display of the display panel.

[0068] This embodiment provides a display panel and a display device, which can reduce the influence of other signals (such as data signals) on the multiplexing control signal transmitted by the multiplexing control line, and is conducive to improving the image quality uniformity of the display panel.

[0069] This embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels and a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, and a plurality of multiplexing control lines. The substrate includes a display area and a first frame area located on at least one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. The plurality of multiplexing circuits, the plurality of multiplexing data lines, and the plurality of multiplexing control lines are located in the first frame area. The multiplexing circuit is connected to at least two of the plurality of multiplexing control lines, a multiplexing data line, and at least two of the plurality of data lines, and is configured to provide the data signal transmitted by the one reset data line to the at least two data lines under the control of the at least two multiplexing control lines. The orthographic projections of the plurality of multiplexing data lines and the plurality of multiplexing control lines on the substrate do not overlap. The plurality of multiplexed data lines are divided into a first group of multiplexed data lines and a second group of multiplexed data lines, and a portion of at least one multiplexed control line is located between the first group of multiplexed data lines and the second group of multiplexed data lines. In some examples, a portion of each of the plurality of multiplexed control lines may be located between the first group of multiplexed data lines and the second group of multiplexed data lines. Alternatively, a portion of several of the plurality of multiplexed control lines may be located between the first group of multiplexed data lines and the second group of multiplexed data lines, and the remaining multiplexed control lines may bypass the first group of multiplexed data lines and the second group of multiplexed data lines.

[0070] In some examples, the multiplexing circuit may adopt a 1:n design, that is, the multiplexing circuit may provide a data signal of one multiplexed data line to at least n data lines under the control of n multiplexing control lines. Here, n may be an integer greater than 1, for example, n may be 2, 3, 6, or 9. This embodiment is not limited to this.

[0071] The wiring method of the multiplexed control lines of the display panel of this embodiment can avoid overlapping with multiple multiplexed data lines, reduce the impact of the multiplexed data lines on the multiplexed control signals transmitted by the multiplexed control lines, and help improve the display quality of the display panel.

[0072] In some exemplary embodiments, the first border area may include at least: a first signal access area and a second signal access area, and the second signal access area may be located on a side of the first signal access area away from the display area. The second signal access area is provided with a plurality of multiplexing control contact pads. The multiplexing control line may include: a first sub-line, a second sub-line and a third sub-line, and the third sub-line is connected between the first sub-line and the second sub-line. The third sub-line may be located in the first signal access area. The second sub-line may be located on a side of the first signal access area close to the display area, and between the first group of multiplexing data lines and the second group of multiplexing data lines. The first sub-line is connected to the multiplexing control contact pad of the second signal access area. In this example, the third sub-line of at least one multiplexed control line is arranged in the first signal access area, which can avoid overlapping with multiple multiplexed data lines and eliminate the coupling capacitance generated by the overlap of the multiplexed data lines and the multiplexed control lines; moreover, the second sub-line of at least one multiplexed control line can be located between the first group of multiplexed data lines and the second group of multiplexed data lines, without overlapping with the multiplexed data lines, and maintaining a certain spacing distance between the multiplexed data lines, which can reduce the coupling capacitance between the multiplexed control line and the multiplexed data line in the three-dimensional space, thereby ensuring the display quality at extremely low grayscale.

[0073] In some exemplary embodiments, the first signal access area may be provided with multiple first multiplexing transfer pads and multiple second multiplexing transfer pads. The first sub-line of the multiplexing control line is connected to the third sub-line via the first multiplexing transfer pad, and the second sub-line of the multiplexing control line is connected to the third sub-line via the second multiplexing transfer pad. In this example, by providing the first multiplexing transfer pad and the second multiplexing transfer pad in the first signal access area, the connection between the first sub-line and the third sub-line, and the second sub-line and the third sub-line is achieved. This not only ensures the effectiveness of the connection, but also helps to ensure the uniformity of the film layer pattern in the first signal access area.

[0074] In some exemplary embodiments, the first signal access area may have multiple sides, and multiple first multiplexing transfer pads and multiple second multiplexing transfer pads may be arranged along the same side. In some examples, the first signal access area may also be provided with a first group of data contact pads and a second group of data contact pads; the first group of data contact pads is connected to the first group of multiplexed data lines, and the second group of data contact pads is connected to the second group of multiplexed data lines. The multiple first multiplexing transfer pads may be divided into a first group of first multiplexing transfer pads and a second group of first multiplexing transfer pads. The multiple second multiplexing transfer pads are located between the first group of data contact pads and the second group of data contact pads. The first group of first multiplexing transfer pads may be located on a side of the first group of data contact pads away from the multiple second multiplexing transfer pads, and the second group of first multiplexing transfer pads may be located on a side of the second group of data contact pads away from the multiple second multiplexing transfer pads. The arrangement of the first multiplexing transfer pads and the second multiplexing transfer pads in this example may be beneficial to wiring within the first signal access area.

[0075] In some exemplary embodiments, the first signal access area may have at least a first side and a second side extending in the same direction, the second side being located on a side of the first side away from the display area. A plurality of first multiplexing transfer pads may be arranged along the second side, and a plurality of second multiplexing transfer pads may be arranged along the first side. In some examples, in the extension direction of the second sub-line, the plurality of first multiplexing transfer pads and the plurality of second multiplexing transfer pads are at least partially aligned. The arrangement of the first multiplexing transfer pads and the second multiplexing transfer pads in this example can help reduce the overlap of the first sub-line of the multiplexing control line with the remaining signal lines.

[0076] In some exemplary embodiments, a plurality of DC signal transmission lines may be provided in the first border area; the first sub-line of the multiplexing control line and at least one DC signal transmission line may overlap in their orthographic projections on the substrate. In some examples, the second signal access area may also be provided with a plurality of DC signal contact pads arranged along the first direction; the plurality of DC signal contact pads are configured to be connected to the plurality of DC signal transmission lines. The plurality of multiplexing control contact pads are located on a side of the plurality of DC signal contact pads close to the edge of the display panel. In some examples, the DC signal transmission line may include: a first power lead and a second power lead, the first power lead may be configured to transmit a high potential signal, and the second power lead may be configured to transmit a low potential signal. This example performs wiring by arranging the multiplexing control line to overlap with the DC signal transmission line, which helps to reduce the overlap of the multiplexing control line with the remaining signal lines and reduce the crosstalk of the multiplexing control signal.

[0077] In some exemplary embodiments, the first border area may also be provided with a plurality of square wave signal transmission lines, and the first sub-line of the multiplexing control line may also overlap with the orthographic projection of at least one square wave signal transmission line on the substrate. In some examples, the second signal access area is further provided with a plurality of square wave signal contact pads arranged along the first direction; the plurality of square wave signal contact pads are configured to be connected to the plurality of square wave signal transmission lines. At least one square wave signal contact pad may be provided between the plurality of multiplexing control contact pads and the plurality of DC signal contact pads. In some examples, the square wave signal transmission line may include: a control signal line that provides a control signal to the gate drive circuit. The setting method of this example can facilitate the wiring of the multiplexing control line.

[0078] In some exemplary embodiments, a plurality of DC signal transmission lines are provided in the first border area; the first sub-line of the multiplexing control line and the plurality of DC signal transmission lines may not overlap in their orthographic projections on the substrate. In some examples, the second signal access area is further provided with a plurality of DC signal contact pads arranged along the first direction; the plurality of DC signal contact pads are configured to be connected to the plurality of DC signal transmission lines. The plurality of multiplexing control contact pads may be located on a side of the plurality of DC signal contact pads away from the edge of the display panel. This example can reduce the overlap of the multiplexing control line with the remaining signal lines except the multiplexing data line, thereby avoiding crosstalk between the multiplexing control signal and the remaining signals.

[0079] In some exemplary embodiments, a first power lead and a first shielding electrode are provided in the first border area, and the first shielding electrode is connected to the first power lead. The first shielding electrode is located on a side of the first signal access area close to the display area. The second sub-lines of the multiplexed control lines can be divided into a first group of second sub-lines and a second group of second sub-lines. The first shielding electrode can be located between the first group of second sub-lines and the second group of second sub-lines. By providing the first shielding electrode in this example, crosstalk to the multiplexed control signal can be reduced.

[0080] In some exemplary embodiments, the first border region may further be provided with a second shielding electrode, the second shielding electrode being located on a side of the first shielding electrode away from the substrate. The second shielding electrode is electrically connected to the first shielding electrode. The orthographic projection of the second shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first shielding electrode on the substrate. In some examples, the second shielding electrode is located on a side of the second sub-line of the plurality of multiplexing control lines away from the substrate, and the orthographic projection of the second shielding electrode on the substrate may overlap with the orthographic projection of the second sub-line of at least one multiplexing control line on the substrate. By providing the second shielding electrode in this example, the influence of data signals, other external signals, or electric fields on the multiplexing control signals can be shielded.

[0081] The solution of this embodiment is illustrated below through multiple examples.

[0082] Figure 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the display panel may include: a display area AA, a first border area B1 located on one side of the display area AA, and a second border area B2 located on the remaining sides of the display area AA. The first border area B1 may be connected to the second border area B2. For example, the first border area B1 may be the bottom border of the display panel, and the second border area B2 may include the remaining border area of ​​the display panel excluding the bottom border.

[0083] In some examples, as shown in FIG1 , the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX may be configured to display a dynamic image or a still image. The display area AA may be referred to as an active area. In some examples, the display area AA may be circular or elliptical. However, this embodiment is not limited thereto. For example, the display area may be other shapes such as a rectangle. In some examples, the display panel may be a flexible panel, and thus the display panel may be deformable, such as being curled, bent, folded, or rolled up.

[0084] In some examples, as shown in FIG1 , the display area AA may include: a display structure layer provided on a substrate, or may include a display structure layer and a touch structure layer provided in sequence on a substrate. For example, the display panel may integrate a touch structure to form a touch structure on a thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE) structure. The Touch on TFE structure mainly includes a flexible multi-layer covering surface type (FMLOC, Flexible Multi-Layer On Cell) structure and a flexible single-layer covering surface type (FSLOC, Flexible Single-Layer On Cell) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The driving chip (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0085] In some examples, the display structure layer may include multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may be arranged along the second direction Y, and each gate line GL may extend along the first direction X; the multiple data lines DL may be arranged along the first direction X, and each data line DL may extend along the second direction Y. The orthographic projections of the multiple gate lines GL and the multiple data lines DL on the substrate may intersect to form multiple sub-pixel regions. One sub-pixel PX may be arranged in one sub-pixel region. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide gate drive signals to the multiple sub-pixels PX. For example, the gate drive signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0086] In some examples, as shown in FIG1 , the first direction X may be an extending direction (e.g., a row direction) of the gate lines GL in the display area AA, and the second direction Y may be an extending direction (e.g., a column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0087] In some examples, a pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0088] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0089] In some examples, the multiple transistors in the pixel circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the difficulty of display panel manufacturing, and improve product yield. In other examples, the multiple transistors in the pixel circuit can include P-type transistors and N-type transistors.

[0090] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel, that is, an LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0091] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0092] In some examples, the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0093] FIG2 is a partial cross-sectional schematic diagram of the display area of ​​a display panel according to at least one embodiment of the present disclosure. FIG2 illustrates the structure of a sub-pixel in the display area as an example. In this example, the multiple transistors in the pixel circuit are of the same type. For example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors or oxide thin-film transistors.

[0094] In some examples, as shown in FIG2 , in a direction perpendicular to the display panel, the display area of ​​the display panel may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the substrate 10. The display structure layer may include at least: a circuit structure layer 12 and a light-emitting structure layer 13. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.

[0095] In some examples, FIG2 illustrates a thin film transistor 21 and a capacitor 22 included in a sub-pixel as an example. In some examples, the circuit structure layer 12 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 10. A first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source-drain metal layer, a passivation layer 104 and a first planarizing layer 105 may be disposed between the first source-drain metal layer and the second source-drain metal layer, and a second planarizing layer 106 may be disposed on the side of the second source-drain metal layer away from the substrate 10. The first gate insulating layer 101, the second gate insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 may be inorganic insulating layers, and the first planarizing layer 105 and the second planarizing layer 106 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer may be provided on the side of the semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel and can also improve the adhesion of the film layer in the display panel to the substrate. In other examples, the passivation layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the first planarization layer can be provided. In other examples, the second source and drain metal layer and the second planarization layer can be omitted.

[0096] In some examples, as shown in FIG2 , the semiconductor layer in the display area may include at least an active layer 210 of a thin film transistor 21. The active layer 210 of the thin film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a gate electrode 213 of the thin film transistor 21 and a first electrode 221 of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin film transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 10. The second gate metal layer may include at least a second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, they may coincide. The first source / drain metal layer may include at least a first electrode 211 and a second electrode 212 of the thin film transistor 21. The interlayer insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The first electrode 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the second electrode 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least an anode connection electrode 23. The anode connection electrode 23 can be connected to the second electrode 212 of the thin-film transistor 21 through a via formed in the passivation layer 104 and the first planarization layer 105. In some examples, the gate lines of the display area may be located in the first gate metal layer, and the data lines and high-potential power lines of the display area may be located in the second source-drain metal layer. However, this embodiment is not limited to this. In other examples, the second source-drain metal layer may be omitted, and the data lines and high-potential power lines of the display area may be located in the first source-drain metal layer.

[0097] In some examples, as shown in FIG2 , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the second planar layer 106 and electrically connected to the anode connection electrode 23 through a pixel via provided in the second planar layer 106. The pixel definition layer 134 is disposed on the first electrode 131 and the second planar layer 106. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0098] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light according to the required grayscale.

[0099] In some examples, the light-emitting layers of light-emitting elements emitting light of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0100] In some examples, as shown in FIG2 , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of an inorganic material, and the second encapsulation layer 142 may be made of an organic material. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0101] In some examples, the touch structure layer 15 may include multiple touch units. At least one touch unit may include at least one touch electrode. The orthographic projection of at least one touch electrode on the substrate may include the orthographic projections of multiple sub-pixels on the substrate. When the touch unit includes multiple touch electrodes, the multiple touch electrodes may be arranged at intervals, and adjacent touch electrodes may be connected to each other through connecting portions. The touch electrodes and the connecting portions may be in the same layer structure. In some examples, the touch electrode may have a rhombus shape, for example, a regular rhombus, a horizontally long rhombus, or a vertically long rhombus. However, this embodiment is not limited to this. In some examples, the touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons.

[0102] In some examples, as shown in FIG1 , the first bezel area B1 may include: a first fan-out area B11, a bending area B12, a second fan-out area B13, a first signal access area B14, and a second signal access area B15, which are sequentially arranged in a direction away from the display area AA. The first fan-out area B11 may be connected to the second bezel area B2 and located on one side of the display area AA. The first fan-out area B11 may be provided with a plurality of multiplexing circuits. The bending area B12 may be connected to the first fan-out area B11 and the second fan-out area B13 and located on a side of the first fan-out area B11 away from the display area AA. The second fan-out area B13 may be located on a side of the bending area B12 away from the display area AA. The first signal access area B14 may be located on a side of the second fan-out area B13 away from the display area AA. The second signal access area B15 may be located on a side of the first signal access area B14 away from the display area AA.

[0103] FIG3 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. FIG3 illustrates a multiplexing circuit 40 using a 1:9 design as an example. In some examples, as shown in FIG3 , a multiplexing circuit 40 can be electrically connected to nine multiplexing control lines (e.g., including first to ninth multiplexing control lines 51 to 59), a multiplexing data line 61, and multiple data lines (e.g., including first to ninth data lines DL1 to DL9). The multiplexing circuit 40 can include nine multiplexing transistors (i.e., first to ninth multiplexing transistors M1 to M9). The gates of the nine multiplexing transistors can be connected to different multiplexing control lines respectively, that is, the gate of the first multiplexing transistor M1 is connected to the first multiplexing control line 51, the gate of the second multiplexing transistor M2 is connected to the second multiplexing control line 52, the gate of the third multiplexing transistor M3 is connected to the third multiplexing control line 53, the gate of the fourth multiplexing transistor M4 is connected to the fourth multiplexing control line 54, the gate of the fifth multiplexing transistor M5 is connected to the fifth multiplexing control line 55, the gate of the sixth multiplexing transistor M6 is connected to the sixth multiplexing control line 56, the gate of the seventh multiplexing transistor M7 is connected to the seventh multiplexing control line 57, the gate of the eighth multiplexing transistor M8 is connected to the eighth multiplexing control line 58, and the gate of the ninth multiplexing transistor M9 is connected to the ninth multiplexing control line 59.

[0104] In some examples, the first electrodes of the nine multiplexing transistors can all be connected to the same multiplexing data line 61. The second electrodes of the nine multiplexing transistors are respectively connected to different data lines of the display area. For example, the second electrode of the first multiplexing transistor M1 is connected to the first data line DL1, the second electrode of the second multiplexing transistor M2 is connected to the second data line DL2, the second electrode of the third multiplexing transistor M3 is connected to the third data line DL3, the second electrode of the fourth multiplexing transistor M4 is connected to the fourth data line DL4, the second electrode of the fifth multiplexing transistor M5 is connected to the fifth data line DL5, the second electrode of the sixth multiplexing transistor M6 is connected to the sixth data line DL6, the second electrode of the seventh multiplexing transistor M7 is connected to the seventh data line DL7, the second electrode of the eighth multiplexing transistor M8 is connected to the eighth data line DL8, and the second electrode of the ninth multiplexing transistor M9 is connected to the ninth data line DL9.

[0105] In some examples, a first data line DL1 may be connected to a first group of sub-pixels P1 and configured to provide data signals to the first group of sub-pixels P1. A second data line DL2 may be connected to a second group of sub-pixels P2 and configured to provide data signals to the second group of sub-pixels P2. A third data line DL3 may be connected to a third group of sub-pixels P3 and configured to provide data signals to the third group of sub-pixels P3. A fourth data line DL4 may be connected to a fourth group of sub-pixels P4 and configured to provide data signals to the fourth group of sub-pixels P4. A fifth data line DL5 may be connected to a fifth group of sub-pixels P5 and configured to provide data signals to the fifth group of sub-pixels P5. A sixth data line DL6 may be connected to a sixth group of sub-pixels P6 and configured to provide data signals to the sixth group of sub-pixels P6. A seventh data line DL17 may be connected to a seventh group of sub-pixels P7 and configured to provide data signals to the seventh group of sub-pixels P7. An eighth data line DL8 may be connected to an eighth group of sub-pixels P18 and configured to provide data signals to the eighth group of sub-pixels P8. The ninth data line DL9 may be connected to the ninth group of sub-pixels P9 and configured to provide a data signal to the ninth group of sub-pixels P9.

[0106] In some examples, a group of sub-pixels may include at least one column of sub-pixels in the display area. A column of sub-pixels may, for example, include a plurality of sub-pixels arranged along the second direction Y. For example, the first group of sub-pixels P1, the fourth group of sub-pixels P4, and the seventh group of sub-pixels P7 may be configured to emit a first color light, the second group of sub-pixels P2, the fifth group of sub-pixels P5, and the eighth group of sub-pixels P8 may be configured to emit a second color light, and the third group of sub-pixels P3, the sixth group of sub-pixels P6, and the ninth group of sub-pixels P9 may be configured to emit a third color light. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. This embodiment is not limited to this.

[0107] In some examples, nine multiplexing control lines can control multiple multiplexing circuits 40 to provide data signals to the sub-pixels of the display area. As shown in Figure 3, the first multiplexing control line 51 can be configured to provide a first multiplexing control signal to control the multiplexing circuit 40 to provide data signals to the first group of sub-pixels P1. The second multiplexing control line 52 can be configured to provide a second multiplexing control signal to control the multiplexing circuit 40 to provide data signals to the second group of sub-pixels P2. The third multiplexing control line 53 can be configured to provide a third multiplexing control signal to control the multiplexing circuit 40 to provide data signals to the third group of sub-pixels P3. The fourth multiplexing control line 54 can be configured to provide a fourth multiplexing control signal to control the multiplexing circuit 40 to provide data signals to the fourth group of sub-pixels P4. The fifth multiplexing control line 55 can be configured to provide a fifth multiplexing control signal to control the multiplexing circuit 40 to provide data signals to the fifth group of sub-pixels P5. The sixth multiplexing control line 56 can be configured to provide a sixth multiplexing control signal to control the multiplexing circuit 40 to provide data signals to the sixth group of sub-pixels P6. The seventh multiplexing control line 57 can be configured to provide a seventh multiplexing control signal to control the multiplexing circuit 40 to provide data signals to the seventh group of sub-pixels P7. The eighth multiplexing control line 58 can be configured to provide an eighth multiplexing control signal to control the multiplexing circuit 40 to provide data signals to the eighth group of sub-pixels P8. The ninth multiplexing control line 59 can be configured to provide a ninth multiplexing control signal to control the multiplexing circuit 40 to provide data signals to the ninth group of sub-pixels P9.

[0108] Figure 4 illustrates an example arrangement of multiplexed control lines and multiplexed data lines in at least one embodiment of the present disclosure. Figure 4 illustrates only a few multiplexed data lines as an example. Figure 4 schematically illustrates the general routing of multiplexed control lines and multiplexed data lines in the second fan-out region of the display panel. This embodiment does not limit the number of multiplexed data lines. This example uses the 1:9 design shown in Figure 3 as an example for multiplexing circuits.

[0109] In some examples, multiple multiplexed data lines 61 can be located on a side of the first signal access region B14 near the bend region B12. The multiple multiplexed data lines 61 can be divided into a first group of multiplexed data lines 61a and a second group of multiplexed data lines 61b. The multiple multiplexed data lines 61 can be connected to multiple data bend connection lines within the bend region B12. The multiple multiplexed data lines 61 can extend generally along the second direction Y and extend to connect to multiple data contact pads within the first signal access region B14.

[0110] In some examples, as shown in FIG4 , a plurality of contact pads arranged along the first direction X are provided in the second signal access area B15, for example, a plurality of multiplexing control contact pads 721 and a plurality of first contact pads 722. The plurality of multiplexing control contact pads 721 can be divided into a first group of multiplexing control contact pads 721a and a second group of multiplexing control contact pads 721b. The plurality of first contact pads 722 can be located between the first group of multiplexing control contact pads 721a and the second group of multiplexing control contact pads 721b in the first direction X. For example, the first group of multiplexing control contact pads 721a can be located on one side of the plurality of first contact pads 722 in the opposite direction of the first direction X, and the second group of multiplexing control contact pads 721b can be located on one side of the plurality of first contact pads 722 in the first direction X. The plurality of first contact pads 722 can be connected to the plurality of second side contact pads (the plurality of second side contact pads 714 shown in FIG5B ) in the first signal access area B14 through a plurality of first pin connection lines 731.

[0111] In some examples, as shown in FIG4 , the nine multiplexing control lines can be divided into the following two groups: a first group of multiplexing control lines (for example, including the sixth multiplexing control line to the ninth reset control line) and a second group of multiplexing control lines (for example, including the first multiplexing control line to the fifth multiplexing control line). The first group of multiplexing control lines can go from the first signal access area B14 along the side opposite to the first direction X (for example, the left side), bypass the side of the first signal access area B14, access the first signal access area B14, and then lead out from the middle position of the first signal access area B14 to the side of the bending area B12; the second group of multiplexing control lines can go from the first signal access area B14 along the side of the first direction X (for example, the right side), bypass the side of the first signal access area B14, access the first signal access area B14, and then lead out from the middle position of the first signal access area B14 to the side of the bending area B12. This example does not limit the grouping method of the nine multiplexing control lines or the number of multiplexing control lines included in each group. In other examples, the first group of multiplexing control lines may include five multiplexing control lines, and the second group of multiplexing control lines may include four multiplexing control lines; in other examples, the first group of multiplexing control lines may include the seventh to ninth multiplexing control lines and the fourth multiplexing control line, and the second group of multiplexing control lines may include the first to third multiplexing control lines, the fifth multiplexing control line, and the sixth multiplexing control line.

[0112] In some examples, as shown in FIG4 , each multiplexing control line may include a first sub-line, a second sub-line, and a third sub-line connected between the first and second sub-lines. For example, the first multiplexing control line may include a first sub-line 511, a third sub-line 513, and a second sub-line 512 connected in sequence. The second multiplexing control line may include a first sub-line 521, a third sub-line 523, and a second sub-line 522 connected in sequence. The third multiplexing control line may include a first sub-line 531, a third sub-line 533, and a second sub-line 532 connected in sequence. The fourth multiplexing control line may include a first sub-line 541, a third sub-line 543, and a second sub-line 542 connected in sequence. The fifth multiplexing control line may include a first sub-line 551, a third sub-line 553, and a second sub-line 552 connected in sequence. The sixth multiplexing control line may include a first sub-line 561, a third sub-line 563, and a second sub-line 562 connected in sequence. The seventh multiplexing control line may include a first sub-line 571, a third sub-line 573, and a second sub-line 572 connected in sequence. The eighth multiplexing control line may include: a first sub-line 581, a third sub-line 583, and a second sub-line 582 connected in sequence. The ninth multiplexing control line may include: a first sub-line 591, a third sub-line 593, and a second sub-line 592 connected in sequence.

[0113] In some examples, as shown in FIG4 , the first sub-line 561 of the sixth multiplexing control line, the first sub-line 571 of the seventh multiplexing control line, the first sub-line 581 of the eighth multiplexing control line, and the first sub-line 591 of the ninth multiplexing control line can serve as the first group of first sub-lines 501 a. The first sub-line 561 of the sixth multiplexing control line, the first sub-line 571 of the seventh multiplexing control line, the first sub-line 581 of the eighth multiplexing control line, and the first sub-line 591 of the ninth multiplexing control line within the first group of first sub-lines 501 a can be arranged sequentially in a direction away from the first signal access area B14. This embodiment does not limit the arrangement order of the multiple first sub-lines within the first group of first sub-lines. In other examples, the first sub-line 561 of the sixth multiplexing control line, the first sub-line 571 of the seventh multiplexing control line, the first sub-line 581 of the eighth multiplexing control line, and the first sub-line 591 of the ninth multiplexing control line within the first group of first sub-lines 501 a can be arranged sequentially in a direction approaching the first signal access area B14.

[0114] In some examples, the first group of first sub-lines 501a can be connected to the first group of multiplexing control contact pads 721a in the second signal access area B15. For example, each first sub-line in the first group of first sub-lines 501a can be connected to at least one multiplexing control contact pad 721 in the first group of multiplexing control contact pads 721a.

[0115] In some examples, the first sub-line 511 of the first multiplexing control line, the first sub-line 521 of the second multiplexing control line, the first sub-line 531 of the third multiplexing control line, the first sub-line 541 of the fourth multiplexing control line, and the first sub-line 551 of the fifth multiplexing control line can serve as the second group of first sub-lines 501b. The first sub-line 511 of the first multiplexing control line, the first sub-line 521 of the second multiplexing control line, the first sub-line 531 of the third multiplexing control line, the first sub-line 541 of the fourth multiplexing control line, and the first sub-line 551 of the fifth multiplexing control line within the second group of first sub-lines 501b can be arranged sequentially in a direction away from the first signal access area B14. This embodiment is not limited to this.

[0116] In some examples, the second group of first sub-lines 501b can be connected to the second group of multiplexing control contact pads 721b in the second signal access area B15. For example, each first sub-line in the second group of first sub-lines 501b can be connected to at least one multiplexing control contact pad 721 in the second group of multiplexing control contact pads 721b.

[0117] In some examples, the second sub-lines of the nine multiplexing control lines can be located between the first group of multiplexing data lines 61a and the second group of multiplexing data lines 61b. The second sub-lines of the nine multiplexing control lines can be connected to multiple multiplexing control meandering connection lines within the bending region B12. The second sub-line 562 of the sixth multiplexing control line, the second sub-line 572 of the seventh multiplexing control line, the second sub-line 582 of the eighth multiplexing control line, and the second sub-line 592 of the ninth multiplexing control line can serve as the first group of second sub-lines 502a. The second sub-line 512 of the first multiplexing control line, the second sub-line 522 of the second multiplexing control line, the second sub-line 532 of the third multiplexing control line, the second sub-line 542 of the fourth multiplexing control line, and the second sub-line 552 of the fifth multiplexing control line can serve as the second group of second sub-lines 502b. The second group of second sub-lines 502b can be located on one side of the first group of second sub-lines 502a in the first direction X.

[0118] In some examples, the second sub-line 562 of the sixth multiplexing control line, the second sub-line 572 of the seventh multiplexing control line, the second sub-line 582 of the eighth multiplexing control line, and the second sub-line 592 of the ninth multiplexing control line within the first group of second sub-lines 502 a can be sequentially arranged along a direction opposite to the first direction X, and can all extend along the second direction Y. The second sub-line 512 of the first multiplexing control line, the second sub-line 522 of the second multiplexing control line, the second sub-line 532 of the third multiplexing control line, the second sub-line 542 of the fourth multiplexing control line, and the second sub-line 552 of the fifth multiplexing control line within the second group of second sub-lines 502 b can be sequentially arranged along the first direction X, and can all extend along the second direction Y.

[0119] In some examples, the third sub-line of the nine multiplexing control lines can be located in the first signal access area B14. One end of each multiplexing control line can be connected to the first sub-line, and the other end can be connected to the second sub-line, so that the first sub-line and the second sub-line are electrically connected bypassing the multiplexing data lines 61.

[0120] In some examples, the third sub-line 563 of the sixth multiplexing control line, the third sub-line 573 of the seventh multiplexing control line, the third sub-line 583 of the eighth multiplexing control line, and the third sub-line 593 of the ninth multiplexing control line can serve as the first group of third sub-lines 503 a. The third sub-line 563 of the sixth multiplexing control line, the third sub-line 573 of the seventh multiplexing control line, the third sub-line 583 of the eighth multiplexing control line, and the third sub-line 593 of the ninth multiplexing control line within the first group of third sub-lines 503 a can be arranged sequentially along a direction opposite to the second direction Y.

[0121] In some examples, the third sub-line 513 of the first multiplexing control line, the third sub-line 523 of the second multiplexing control line, the third sub-line 533 of the third multiplexing control line, the third sub-line 543 of the fourth multiplexing control line, and the third sub-line 553 of the fifth multiplexing control line can serve as the second group of third sub-lines 503 b. The third sub-line 513 of the first multiplexing control line, the third sub-line 523 of the second multiplexing control line, the third sub-line 533 of the third multiplexing control line, the third sub-line 543 of the fourth multiplexing control line, and the third sub-line 553 of the fifth multiplexing control line within the second group of third sub-lines 503 b can be arranged sequentially along a direction opposite to the second direction Y.

[0122] In some examples, the first group of third sub-lines 503a and the second group of third sub-lines 503b can be arranged along the first direction X. The extension direction of each third sub-line can intersect the extension direction of the second sub-line. For example, the third sub-lines extend at least along the first direction X, and the second sub-lines extend at least along the second direction Y.

[0123] In some examples, the first signal access area B14 may be provided with a plurality of first multiplexing transfer pads 711a and 711b and a plurality of second multiplexing transfer pads 712a and 712b. The first signal access area B14 may have multiple sides. The plurality of first multiplexing transfer pads 711a and 711b and the plurality of second multiplexing transfer pads 712a and 712b may be arranged along the same side of the first signal access area B14, for example, along a side of the first signal access area B14 near the bending area B12. The plurality of second multiplexing transfer pads 712a and 712b may be located between the plurality of first multiplexing transfer pads 711a and the plurality of first multiplexing transfer pads 711b. Multiple first multiplexing transfer pads 711a and multiple second multiplexing transfer pads 712a can be located on both sides of the multiple data contact pads (for example, the data contact pads 713a shown in Figure 5B) connected to the first group of multiplexing data lines 61a; multiple first multiplexing transfer pads 711b and multiple second multiplexing transfer pads 712b can be located on both sides of the multiple data contact pads (for example, the data contact pads 713b shown in Figure 5B) connected to the second group of multiplexing data lines 61b.

[0124] In some examples, multiple first multiplexing transfer pads 711a can serve as a first group of first multiplexing transfer pads, which can be connected to the first group of first sub-lines 501a and the first group of third sub-lines 503a. Multiple first multiplexing transfer pads 711b can serve as a second group of first multiplexing transfer pads, which can be connected to the second group of first sub-lines 501b and the second group of third sub-lines 503b. For example, each first multiplexing transfer pad can be connected to one first sub-line and one third sub-line.

[0125] In some examples, multiple second multiplexing transfer pads 712a can serve as a first group of second multiplexing transfer pads, and the second group of second multiplexing transfer pads can be connected to the first group of third sub-lines 503a and the first group of second sub-lines 502a. Multiple second multiplexing transfer pads 712b can serve as a second group of second multiplexing transfer pads, and the second group of second multiplexing transfer pads can be connected to the second group of third sub-lines 503b and the second group of second sub-lines 502b. For example, each second multiplexing transfer pad can be connected to one second sub-line and one third sub-line.

[0126] In this example, by routing the multiple multiplexing control lines within the first signal access area, they can avoid overlapping with the multiple multiplexing data lines, eliminating the coupling capacitance generated by the overlap between the multiplexing data lines and the multiplexing control lines. Furthermore, the second sub-lines of the multiple multiplexing control lines can be located between the first group of multiplexing data lines and the second group of multiplexing data lines, avoiding overlap or proximity with the multiplexing data lines and maintaining a certain spacing distance from the multiplexing data lines. This can reduce the coupling capacitance between the multiplexing control lines and the multiplexing data lines in three dimensions, thereby ensuring display quality at very low grayscales.

[0127] The detailed structure of the first border area of ​​the display panel of this example is described below with examples.

[0128] Figure 5A is a partial plan view of the first border area of ​​at least one embodiment of the present disclosure. Figure 5A illustrates a portion of the first fan-out area B11, the bending area B12, and the second fan-out area B13 of the first border area. Figure 5A provides an overall diagram of the panel detection lines, control lead lines, multiplexed data lead lines, data bending connection lines, touch bending connection lines, detection bending connection lines, control bending connection lines, multiplexed data lines, and panel detection lead lines in the first border area. This example does not limit the number of various routing lines in the first border area.

[0129] In some examples, as shown in FIG5A , the first fan-out region B11 may be connected to the display region AA and the second bezel region. The first fan-out region B11 may be provided with a first power line 311, second power lines 321a and 321b, a plurality of display lead lines, a plurality of panel detection lines (including a first group of panel detection lines 331a and a second group of panel detection lines 331b), and a plurality of multiplexing circuits 40.

[0130] In some examples, as shown in FIG5A , the first power line 311 may have a main portion and a first extension portion (not shown) extending along the edge of the display area AA. The main portion of the first power line 311 may be approximately located at the centerline of the first fan-out area B11 in the first direction X, and the centerline of the first fan-out area B11 in the first direction X may be parallel to the second direction Y. The main portion of the first power line 311 may be approximately n-shaped and extend toward one side of the bend area B12. The first extension portion of the first power line 311 may be electrically connected to multiple high-potential power lines in the display area AA. For example, the first power line 311 may be located in the first source and drain metal layer, and the high-potential power line of the display area may be located in the second source and drain metal layer. The high-potential power line may extend to the first fan-out area B11 and connect to the first power line 311.

[0131] In some examples, as shown in Figure 5A, the second power lines 321a and 321b can be located on opposite sides of the first power line 311 in the first direction X. The second power line 321a can extend from the left side along the edge of the display panel to the second frame area, and the second power line 321b can extend from the right side along the edge of the display panel to the second frame area. The second power lines 321a and 321b can be connected in the second frame area to provide low-potential power signals to multiple sub-pixels in the display area AA. In some examples, the first power line 311 and the second power lines 321a and 321b can be a same-layer structure, for example, both can be located in the first source and drain metal layer. However, this embodiment is not limited to this. In other examples, the first power line 311 and the second power lines 321a and 321b can adopt a double-layer routing structure of the first source and drain metal layer and the second source and drain metal layer.

[0132] In some examples, as shown in FIG5A , the multiplexing circuit 40 can be configured to provide data signals to multiple data lines using a single signal source (e.g., connected to a multiplexed data line). For example, multiple data lines (e.g., nine data lines) in the display area AA can extend to the first fan-out area B11 and be connected to the same multiplexing circuit 40. A portion of the multiplexing circuit 40 can be located on the side of the main portion of the first power line 311 near the display area AA and arranged sequentially along the first direction X; another portion of the multiplexing circuit 40 can be arranged in a stepped manner along the edge of the display area AA.

[0133] In some examples, the first fan-out region B11 may further include multiple shift register units of a gate drive circuit. Each shift register unit may be connected to at least one gate line of the display area AA and configured to provide a gate drive signal to the at least one gate line of the display area AA. For example, the shift register unit may be located on a side of the multiplexing circuit away from the display area AA, or the shift register unit may be arranged with an interval between the multiplexing circuit and the multiplexing circuit. This embodiment is not limited to this.

[0134] In some examples, as shown in FIG5A , the multiple display lead lines of the first fan-out area B11 may include at least: multiple control lead lines (e.g., including a first group of control lead lines 64 a and a second group of control lead lines 64 b ), and multiple multiplexed data lead lines (e.g., including a first group of multiplexed data lead lines 62 a and a second group of multiplexed data lead lines 62 b ).

[0135] In some examples, as shown in Figure 5 A, a plurality of multiplexed data lead-out lines can be electrically connected to a plurality of multiplexing circuits 40. A multiplexed data lead-out line can be configured to transmit data signals to a multiplexing circuit 40 so that multiplexing circuit 40 provides data signals to the plurality of data lines connected thereto. A plurality of multiplexed data lead-out lines can, for example, be divided into a first group of multiplexed data lead-out lines 62a and a second group of multiplexed data lead-out lines 62b. Every group of multiplexed data lead-out lines can comprise a plurality of multiplexed data lead-out lines, and the number of two groups of multiplexed data lead-out lines can be the same or different. The first group of multiplexed data lead-out lines 62a and the second group of multiplexed data lead-out lines 62b can be located at the both sides of the main body of the first power line 311 in the first direction X. For example, the first group of multiplexed data lead lines 62a can be located on the side of the main portion of the first power line 311 opposite to the first direction X and extend to the left; the second group of multiplexed data lead lines 62b can be located on the side of the main portion of the first power line 311 in the first direction X and extend to the right. Each group of multiplexed data lead lines can be divided into two parts, one part extending from the side of the control lead line close to the display area along the edge of the display area, and the other part extending from the side of the control lead line away from the display area to the edge of the display area. Multiple multiplexed data lead lines can be located on the side of the second power lines 331a and 331b close to the substrate. Multiple multiplexed data lead lines can be co-layer structures, for example, all located in the second gate metal layer.

[0136] 5A , the orthographic projections of the plurality of control lead lines on the substrate may overlap with the orthographic projections of the main portion of the first power line 311 on the substrate. For example, the plurality of control lead lines may be located in the second gate metal layer.

[0137] In some examples, as shown in Figure 5A, a plurality of control lead wires can be divided into a first group of control lead wires 64a and a second group of control lead wires 64b. Each group of control lead wires can include a plurality of control lead wires. The number of the first group of control lead wires 64a can be greater than or equal to the number of the second group of control lead wires 64b. The first group of control lead wires 64a and the second group of control lead wires 64b can be adjacent in a first direction X, the first group of control lead wires 64a can extend to the left, and the second group of control lead wires 64b can extend to the right.

[0138] In some examples, the plurality of control leads may include: a plurality of multiplexing control leads and a plurality of drive control leads. For example, the plurality of multiplexing control leads are connected to a plurality of multiplexing circuits 40 and can be configured to provide multiplexing control signals to the plurality of multiplexing circuits 40; the plurality of drive control leads are connected to a gate drive circuit and can provide drive control signals (such as a start signal, a clock signal, a power signal, etc.) to the gate drive circuit.

[0139] In some examples, multiple panel inspection lines can be configured to perform crack detection in display area AA. The multiple panel inspection lines can be divided into a first group of panel inspection lines 331a and a second group of panel inspection lines 331b. The first group of panel inspection lines 331a can overlap with the second power supply line 321a in the orthographic projection of the substrate, and the second group of panel inspection lines 331b can overlap with the second power supply line 321b in the orthographic projection of the substrate. For example, the multiple panel inspection lines can be in the same layer structure, such as all located in the second gate metal layer.

[0140] In some examples, as shown in Figure 5A, the bending region B12 can be configured to bend the second fan-out region B13, the first signal access region B14, and the second signal access region B15 toward the back of the display area AA. The bending region B12 can be provided with multiple curved connecting lines to connect the traces transmitting the same signal within the first fan-out region B11 and the second fan-out region B13. The multiple curved connecting lines in the bending region B12 can be co-layered, for example, all located in the second source and drain metal layer or the first source and drain metal layer.

[0141] In some examples, as shown in Figure 5A, the multiple bending connection lines may include: first power bending connection lines 31a, 31b, 31c and 31d, second power bending connection lines 32a and 32b, a first group of detection bending connection lines 33a and a second group of detection bending connection lines 33b, a first group of touch bending connection lines 34a and a second group of touch bending connection lines 34b, a first group of data bending connection lines 36a and a second group of data bending connection lines 36b, and a group of control bending connection lines 35. The second power zigzag connection line 32a, the first group of detection zigzag connection lines 33a, the first group of data zigzag connection lines 36a, the first power zigzag connection line 31a, the first group of touch zigzag connection lines 34a, the first power zigzag connection line 31b, a group of control zigzag connection lines 35, the first power zigzag connection line 31c, the second group of touch zigzag connection lines 34b, the first power zigzag connection line 31d, the second group of data zigzag connection lines 36b, the second group of detection zigzag connection lines 33b, and the second power zigzag connection lines 32b may be arranged sequentially along the first direction X. The group of control zigzag connection lines 35 may include at least: a plurality of multiplexing control zigzag connection lines and a plurality of driving control zigzag connection lines. The plurality of multiplexing control zigzag connection lines may be connected to the plurality of multiplexing control lines of the second fan-out area B13.

[0142] In this example, by setting a first power bend connection line between the data bend connection line and the touch bend connection line, and setting a first power bend connection line between the control bend connection line and the touch bend connection line, it is beneficial to shield the mutual interference between the data bend connection line and the touch bend connection line, and between the control bend connection line and the touch bend connection line.

[0143] Figure 5B is a partial plan view of the first border area of ​​at least one embodiment of the present disclosure. Figure 5B illustrates a portion of the second fan-out area B13 of the first border area, and a partial structure of the first signal access area B14 and the second signal access area B15. Figure 5B takes the ninth multiplexing control line and the first multiplexing control line as examples to illustrate the wiring design of multiple multiplexing control lines. Figure 5B provides an overall schematic diagram of the multiplexing data line, the control connection line, and the second control line segment of the control signal line in the first border area. The first control line segment and the third control line segment of the control signal line are only illustrated as a few lines. This example does not limit the number of multiple lines in the first border area.

[0144] In some examples, as shown in Figures 5A and 5B, the second fan-out area B13 can be provided with at least a first power lead 312, a second power lead 322a and 322b, a plurality of panel detection lead lines (including a first group of panel detection lead lines 332a and a second group of panel detection lead lines 332b), a plurality of multiplexed data lines (including a first group of multiplexed data lines 61a and a second group of multiplexed data lines 61b), a plurality of control connection lines (including a first group of control connection lines 65a and a second group of control connection lines 65b), a plurality of control signal lines (including a first group of control signal lines 66a and a second group of control signal lines 66b), and a plurality of multiplexed control lines (for example, including a ninth multiplexed control line 59 and a first multiplexed control line 51).

[0145] In some examples, as shown in FIG5A , the first power lead 312 may include a first main portion 3121 extending along a first direction X, four first connection portions 3120 connected to the first main portion 3121, and a first extension portion 3122 and a second extension portion 3123 connected to the first main portion 3121. The four first connection portions 3120 may be connected to a side of the first main portion 3121 near the bending region B12. The four first connection portions 3120 may be generally strip-shaped and extend along the second direction Y. The four first connection portions 3120 may be connected one-to-one to the first power fold connection lines 31a, 31b, 31c, and 31d in the bending region B12. The first power lead 312 may be connected to the first power line 311 in the first fan-out region B11 via the four first power fold connection lines 31a, 31b, 31c, and 31d in the bending region B12. The first extension portion 3122 and the second extension portion 3123 can be connected to the side of the first main portion 3121 away from the bending region B12. The first main portion 3121, the four first connection portions 3120, the first extension portion 3122, and the second extension portion 3123 can be an interconnected, integrated structure. For example, the first power lead 312 can be located in the first source / drain metal layer, or the first power lead 312 can be a dual-layer structure arranged in the first source / drain metal layer and the second source / drain metal layer.

[0146] In some examples, as shown in FIG5B , the first extension portion 3122 of the first power lead 312 can extend substantially along the third direction and then extend toward the second signal access area B15 along the second direction Y. The second extension portion 3123 of the first power lead 312 can extend substantially along the fourth direction and then extend toward the second signal access area B15 along the second direction Y. The third direction intersects both the first direction X and the second direction Y, the fourth direction intersects both the first direction X and the second direction Y, and the third direction intersects the fourth direction. For example, the third direction can be perpendicular to the fourth direction.

[0147] In some examples, as shown in Figures 5A and 5B, the second power lead 322a can be located on one side of the first power lead 312 in the opposite direction of the first direction X, and the second power lead 322b can be located on one side of the first power lead 312 in the first direction X. The second power lead 322a can be connected to the second power line 321a via the second power connection line 32a in the bending area B12. The second power lead 322b can be connected to the second power line 321b via the second power connection line 32b in the bending area B12. For example, the second power lead 322a and the second power lead 322b can be located in the first source and drain metal layer; alternatively, the second power lead 322a and the second power lead 322b can be a double-layer routing structure arranged in the first source and drain metal layer and the second source and drain metal layer.

[0148] In some examples, as shown in Figures 5A and 5B, the second power lead 322a can extend in the second direction Y, the third direction, and the second direction Y in sequence until it reaches the second signal access area B15. The second power lead 322b can extend in the second direction Y, the fourth direction, and the second direction Y in sequence until it reaches the second signal access area B15. The second power lead 322a and 322b and the first power lead 312 can be arranged on the same layer.

[0149] In some examples, as shown in FIG5A , the plurality of panel detection lead lines in the second fan-out area B13 can be divided into a first group of panel detection lead lines 332 a and a second group of panel detection lead lines 332 b. The plurality of panel detection lead lines in the first group of panel detection lead lines 332 a can be connected to the plurality of panel detection lines in the first group of panel detection lines 331 a in the first fan-out area B11 via the plurality of detection bend connection lines in the first group of detection bend connection lines 33 a in the bending area B12. The plurality of panel detection lead lines in the second group of panel detection lead lines 332 b can be connected to the plurality of panel detection lines in the first group of panel detection lines 331 b in the first fan-out area B11 via the plurality of detection bend connection lines in the second group of detection bend connection lines 33 b in the bending area B12. The first group of panel detection lead lines 332 a can be located on one side of the second power lead line 322 a in the first direction X. The second group of panel detection lead lines 332 b can be located on the side of the second power lead line 322 b in the opposite direction of the first direction X. In some examples, the plurality of panel detection lead lines may be in a same-layer structure, for example, they may all be located in the first gate metal layer.

[0150] In some examples, as shown in FIG5A , the plurality of multiplexed data lines in the second fan-out area B13 can extend substantially along the second direction Y toward the first signal access area B14. The plurality of multiplexed data lines can be divided into a first group of multiplexed data lines 61 a and a second group of multiplexed data lines 61 b. The plurality of multiplexed data lines in the first group of multiplexed data lines 61 a can be connected to the plurality of multiplexed data lead lines of the first group of multiplexed data lead lines 62 a in the first fan-out area B11 via the plurality of data bend connection lines of the first group of data bend connection lines 36 a in the bend area B12. The plurality of multiplexed data lines in the second group of multiplexed data lines 61 b ​​can be connected to the plurality of multiplexed data lead lines of the second group of multiplexed data lead lines 62 b in the first fan-out area B11 via the plurality of data bend connection lines of the second group of data bend connection lines 36 b in the bend area B12. For example, the first group of multiplexed data lines 61a can be configured to provide data signals to sub-pixels in the left half of the display area AA, and the second group of multiplexed data lines 61b can be configured to provide data signals to sub-pixels in the right half of the display area AA.

[0151] In some examples, as shown in Figures 5A and 5B, the multiple control connection lines in the second fan-out area B13 can extend along the second direction Y toward the side of the first signal access area B14. The multiple control connection lines may include a first group of control connection lines 65a and a second group of control connection lines 65b. The multiple control connection lines of the first group of control connection lines 65a and the second group of control connection lines 65b can be connected to the multiple control lead lines of the first group of control lead lines 64a and the second group of control lead lines 64b in the first fan-out area B11 through the multiple control bend connection lines within a group of control bend connection lines 35 in the bend area B12. The multiple control connection lines in this example may include: multiple drive control connection lines and multiple multiplexing control connection lines. The multiplexing control connection lines can be located in the middle of the multiple drive control connection lines.

[0152] In some examples, as shown in FIG5B , the plurality of control signal lines in the second fan-out area B13 may include a first group of control signal lines 66 a and a second group of control signal lines 66 b. The first group of control signal lines 66 a may be connected to a plurality of drive control connection lines within the first group of control connection lines 65 a, and the second group of control signal lines 66 b may be connected to a plurality of drive control connection lines within the second group of control connection lines 65 b. The first group of control signal lines 66 a may bypass the first signal access area B14 from one side (e.g., the left side) along the first direction X and extend toward the second signal access area B15. The second group of control signal lines 66 b may bypass the first signal access area B14 from the other side (e.g., the right side) along the first direction X and extend toward the second signal access area B15.

[0153] In some examples, the plurality of control signal lines in the second fan-out region B13 may include a plurality of drive control lines. The plurality of drive control lines may be connected to the plurality of drive control lead lines in the first fan-out region B11 and configured to provide drive control signals (e.g., including a start signal, a clock signal, a voltage signal, etc.) to the gate drive circuit.

[0154] In some examples, as shown in FIG5B , at least one control signal line in the first group of control signal lines 66a may include a first control line segment 661a, a second control line segment 662a, and a third control line segment 663a, which are connected in sequence. One end of the first control line segment 661a may be connected to a drive control connection line in the first group of control connection lines 65a, and the other end may be connected to one end of the second control line segment 662a. The other end of the second control line segment 662a may be connected to one end of the third control line segment 663a, and the other end of the third control line segment 663a may be connected to the second signal access area B15. At least one control signal line in the second group of control signal lines 66b may include a first control line segment 661b, a second control line segment 662b, and a third control line segment 663b, which are connected in sequence. One end of the first control line segment 661b can be connected to a drive control line within the second group of control lines 65b, and the other end can be connected to one end of the second control line segment 662b. The other end of the second control line segment 662b can be connected to one end of the third control line segment 663b, and the other end of the third control line segment 663b can be connected to the second signal access area B15. In some examples, the third control line segments 663a and 663b and the first control line segments 661a and 661b can be co-layered, for example, located in the first source and drain metal layer, and the second control line segments 662a and 662b can be located in the second gate metal layer.

[0155] In some examples, the orthographic projection of the first control line segment 661a on the substrate may partially overlap with the orthographic projection of the first group of multiplexed data lines 61a on the substrate, and the orthographic projection of the first control line segment 661b on the substrate may partially overlap with the orthographic projection of the second group of multiplexed data lines 61b on the substrate. The first control line segments 661a and 661b of the control signal lines transmitting the same signal may be electrically connected via a connecting line extending along the first direction X. The connecting line may be located in the first source / drain metal layer and may overlap with the orthographic projections of the first group of multiplexed data lines 61a and the second group of multiplexed data lines 61b on the substrate.

[0156] In some examples, the routing of multiple multiplexed control lines can be different from the routing of multiple control signal lines to avoid overlapping of multiplexed control lines and multiplexed data lines and affecting the display effect. The routing of multiplexed control lines is described below using the ninth multiplexed control line 59 and the first multiplexed control line 51 as examples.

[0157] In some examples, as shown in FIG5B , the second sub-line 592 of the ninth multiplexing control line 59 can be located on a side of the first control line segment 661a of the first group of control signal lines 66a away from the first group of multiplexing data lines 61a. The second sub-line 592 can be connected to the multiplexing control connection lines within the first group of control connection lines 65a. The second sub-line 592 can extend along the second direction Y to the first signal access area B14 and connect to the second multiplexing transfer pad 712a within the first signal access area B14. The second multiplexing transfer pad 712a is connected to one end of the third sub-line 593 within the first signal access area B14. The third sub-line 593 can extend at least along the first direction X. The other end of the third sub-line 593 can be connected to one end of the first sub-line 591 via the first multiplexing transfer pad 711a. The first sub-line 591 can cross the first control line segment 661a of some of the control signal lines in the first group of control signal lines 66a and extend to the second signal access area B15. The orthographic projection of the first sub-line 591 on the substrate may overlap with the orthographic projections of the first extension portion 3122 of the first power lead-out line 312 and the second power lead-out line 322 a on the substrate.

[0158] In some examples, as shown in FIG5B , the second sub-line 512 of the first multiplexing control line 51 can be located on a side of the first control line segment 661b of the second group of control signal lines 66b away from the second group of multiplexing data lines 61b. The second sub-line 512 can be connected to a multiplexing control connection line within the second group of control connection lines 65b. The second sub-line 512 can extend along the second direction Y to the first signal access area B14 and connect to the second multiplexing transfer pad 712b within the first signal access area B14. The second multiplexing transfer pad 712b is connected to one end of the third sub-line 513 within the first signal access area B14. The third sub-line 513 can extend at least along the first direction X. The other end of the third sub-line 513 can be connected to one end of the first sub-line 511 via the first multiplexing transfer pad 711b. The third sub-line 513 can be located on one side of the third sub-line 593 in the first direction X within the first signal access area B14. The first sub-line 511 can cross the first control line segment 661b of some of the control signal lines in the second group of control signal lines 66b and extend toward the second signal access area B15. The orthographic projection of the first sub-line 511 on the substrate can overlap with the orthographic projections of the second extension portion 3123 of the first power lead 312 and the second power lead 322b on the substrate.

[0159] In some examples, the third sub-line 593 is, for example, located in the first gate metal layer. The first sub-line 591 may include a first line segment, a second line segment, a third line segment, and a fourth line segment connected in sequence; the first line segment may be connected to the multiplexing control contact pad 721 within the second signal access area B15, and the fourth line segment may be connected to the first multiplexing transfer pad 711a within the first signal access area B14. The second line segment may overlap with the orthographic projection of the first power lead 312 and the second power lead 322a on the substrate, and the fourth line segment may overlap with the orthographic projection of the first control line segment 661a of some control signal lines of the first group of control signal lines 66a on the substrate. The first line segment and the third line segment may, for example, be located in the first source and drain metal layer, the second line segment may, for example, be located in the second gate metal layer, and the fourth line segment may, for example, be located in the first gate metal layer. The first multiplexing transfer pad 711a may, for example, be a double-layer pin structure disposed in the first gate metal layer and the first source and drain metal layer. The second sub-line 592 may include a fifth segment and a sixth segment connected in sequence. The fifth segment may be connected to the second multiplexing adapter pad 712a within the first signal access area B14, and the sixth segment may be connected to the multiplexing control connection line within the first group of control connection lines 65a. The fifth segment may, for example, be located in the first gate metal layer, and the sixth segment may, for example, be located in the first source / drain metal layer. The second multiplexing adapter pad 712a may, for example, be a double-layer pin structure disposed in the first gate metal layer and the first source / drain metal layer.

[0160] In some examples, the fourth line segment of the first sub-line 591 of the ninth multiplexing control line, the portion of the first multiplexing transfer pad 711a located in the first gate metal layer, the third sub-line 593, the portion of the second multiplexing transfer pad 712a located in the first gate metal layer, and the fifth line segment of the second sub-line 592 can be an integrated structure connected to each other, for example, located in the first gate metal layer. The multiplexing control connection line connected to the sixth line segment of the second sub-line 592 of the ninth multiplexing control line can be located in the second gate metal layer. This embodiment is not limited to this. In other examples, the sixth line segment of the second sub-line 592 of the ninth multiplexing control line and the multiplexing control connection line to which it is connected can be an integrated structure connected to each other, for example, located in the second gate metal layer.

[0161] Regarding the wiring methods and film layer settings of the remaining multiplexing control lines, reference can be made to the description of the ninth multiplexing control line, so they will not be repeated here.

[0162] In some examples, as shown in FIG5B , the first signal access area B14 can be configured to house a driver chip (IC). For example, the driver chip housed in the first signal access area B14 can be a display driver chip or a touch and display driver integrated circuit (TDDI). The first signal access area B14 can also be referred to as a driver chip placement area. The driver chip can be configured to generate data signals required to drive the sub-pixels.

[0163] In some examples, as shown in FIG5B , the first signal access area B14 can be substantially rectangular. The first signal access area B14 can have a first side proximal to the bending area B12, a second side distal to the bending area B12, and a third side and a fourth side connected between the first and second sides. The fourth side can be located on one side of the third side in the first direction X. The first and second sides can, for example, extend along the first direction X, and the third and fourth sides can, for example, extend along the second direction Y.

[0164] In some examples, the first signal access area B14 may be provided with a plurality of first side contact pads, a plurality of second side contact pads 714, a plurality of third side contact pads 715, and a plurality of fourth side contact pads 716. The plurality of first side contact pads may be arranged in sequence along the extension direction of the first side (e.g., the first direction X), and may include at least: a first group of multiplexing transfer pads (including a plurality of first multiplexing transfer pads 711a), a second group of multiplexing transfer pads (including a plurality of first multiplexing transfer pads 711b), a plurality of second multiplexing transfer pads 712a and 712b, a first group of data contact pads (including a plurality of data contact pads 713a), and a second group of data contact pads (including a plurality of data contact pads 713b). The plurality of data contact pads 713a and 713b may be configured to receive data signals from the driver chip. Multiple data contact pads 713a can be located between the multiple first multiplexing transfer pads 711a and the multiple second multiplexing transfer pads 712a and connected to the first group of multiplexing data lines 61a; multiple data contact pads 713b can be located between the multiple second multiplexing transfer pads 712b and the multiple first multiplexing transfer pads 711b and connected to the second group of multiplexing data lines 61b. The multiple second multiplexing transfer pads 712a and 712b can be located between the multiple data contact pads 713a and 713b. Contact pads connected to the multiple touch transfer lines 74 can be provided between the multiple second multiplexing transfer pads 712a and the multiple second multiplexing transfer pads 712b. The multiple touch transfer lines 74 can be configured to connect to the touch leads of the touch structure layer to transmit touch signals.

[0165] In some examples, the plurality of second side contact pads 714 can be sequentially arranged along the extension direction of the second side (e.g., the first direction X). The plurality of third side contact pads 715 can be sequentially arranged along the extension direction of the third side (e.g., the second direction Y), for example, in a staggered arrangement. The plurality of fourth side contact pads 716 can be sequentially arranged along the extension direction of the fourth side (e.g., the second direction Y), for example, in a staggered arrangement.

[0166] In some examples, as shown in FIG5B , the second signal access area B15 may be provided with multiple contact pads, which may be configured to bind a flexible printed circuit (FPC) so that multiple signal lines (e.g., control signal lines, power lines, etc.) are connected to an external control device through the multiple contact pads. The second signal access area B15 may also be referred to as a circuit binding area.

[0167] In some examples, the multiple contact pads of the second signal access area B15 may include: multiple first contact pads 722, multiple second contact pads (including a first group of second contact pads 723a and a second group of second contact pads 723b), multiple DC signal contact pads (including a first group of DC signal contact pads 724a and a second group of DC signal contact pads 724b), multiple square wave signal contact pads 725, and multiplexing control contact pads 721.

[0168] In some examples, the plurality of contact pads of the second signal access area B15 can be arranged along the first direction X. The plurality of first contact pads 722 can be located between the first group of second contact pads 723a and the second group of second contact pads 723b. The plurality of first contact pads 722 can be connected to the plurality of second side contact pads 714 in the first signal access area B14 via a plurality of first pin connection lines 731. The first group of second contact pads 723a can be connected to the plurality of third side contact pads 715 in the first signal access area B14 via a plurality of second pin connection lines 732. The second group of second contact pads 723b can be connected to the plurality of fourth side contact pads 716 in the first signal access area B14 via a plurality of third pin connection lines 733.

[0169] In some examples, the first group of DC signal contact pads 724a can be located on a side of the first group of second contact pads 723a away from the plurality of first contact pads 722, and the second group of DC signal contact pads 724a can be located on a side of the second group of second contact pads 723b away from the plurality of first contact pads 722. Each group of DC signal contact pads can include: at least one first voltage contact pad 7241 and at least one second voltage contact pad 7242. Within each group of DC signal contact pads, the first voltage contact pad 7241 can be located on a side of the second voltage contact pad 7242 that is closer to the first signal access area B14. The first voltage contact pad 7241 can be configured to connect to the first power lead 312, and the second voltage contact pad 7241 can be configured to connect to the second power lead 322a or 322b.

[0170] In some examples, the multiple square wave signal contact pads 725 can be located on a side of the multiple DC signal contact pads away from the first signal access area B14, for example, on a side of the multiple DC signal contact pads close to an edge of the display panel in the first direction X. The multiplexing control contact pads 721 can be located between the multiple square wave signal contact pads 725 and adjacent to the square wave signal contact pads 725. For example, the multiplexing control contact pads 721 can be disposed between the multiplexing control contact pads 721 and the DC signal contact pads, and the multiple square wave signal contact pads 725 can be disposed on a side of the multiplexing control contact pad 721 away from the DC signal contact pads.

[0171] In some examples, the first and second control signal lines 66a and 66b can be connected to the plurality of square wave signal contact pads 725 in the second signal access region B15. The first sub-lines of the plurality of multiplexing control lines can be connected to the plurality of multiplexing control contact pads 721 in the second signal access region B15.

[0172] In this example, because the multiplexing control contact pad 721 of the second signal access area B15 is located outside the DC signal contact pad, and multiple square wave signal contact pads 725 are provided between the DC signal contact pad and the multiplexing control contact pad, the first sub-line of the multiplexing control line is connected to the multiplexing control contact pad, then crosses over the multiple control signal lines connected to the square wave signal contact pad 725, and then enters the first signal access area B14 and connects to the third sub-line, thereby bypassing the multiplexing data line. This example can eliminate the poor display effect caused by the overlap of multiple multiplexing data lines and multiple multiplexing control lines, thereby improving the display effect.

[0173] The signal transmission wiring in the first border area of ​​this example can be as shown in Table 1. Among them, the data signal can be provided by the data contact pad in the first signal access area B14, and the drive control signal, the first power signal, the second power signal, and the multiplexing control signal (for example, including the first multiplexing control signal to the ninth multiplexing control signal) can be provided by the contact pad in the second signal access area B15.

[0174] Table 1

[0175] The wiring method of the multiplexed control line in this example can avoid overlapping with multiple multiplexed data lines and eliminate the coupling capacitance generated by the overlap of the multiplexed data lines and the multiplexed control lines; moreover, the second sub-line of the multiplexed control line is located between the first group of multiplexed data lines and the second group of multiplexed data lines, and maintains a certain distance from the multiplexed data lines (part of the second sub-line is not adjacent to the multiplexed data lines), thereby reducing the coupling capacitance between the multiplexed data lines and the multiplexed control lines in three-dimensional space, thereby improving the display effect and ensuring display quality at extremely low grayscales.

[0176] Figure 6A is a schematic top view of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 6B is a schematic diagram of the multiplexing circuit after forming the first source and drain metal layer in Figure 6A. Figure 6C is a schematic diagram of the multiplexing circuit after forming the second gate metal layer in Figure 6A. Figure 6A shows a schematic top view of a multiplexing circuit using a 1:9 design.

[0177] In some examples, as shown in Figures 6A to 6C, the active layers of the nine multiplexing transistors of the multiplexing circuit can be located in the semiconductor layer. The active layer of each multiplexing transistor can include: a first region, a second region, and a channel region located between the first region and the second region. The first active layer M10 of the first multiplexing transistor M1, the second active layer M20 of the second multiplexing transistor M2, the third active layer M30 of the third multiplexing transistor M3, the fourth active layer M40 of the fourth multiplexing transistor M4, the fifth active layer M50 of the fifth multiplexing transistor M5, the sixth active layer M60 of the sixth multiplexing transistor M6, the seventh active layer M70 of the seventh multiplexing transistor M7, the eighth active layer M80 of the eighth multiplexing transistor M8, and the ninth active layer M90 of the ninth multiplexing transistor M9 can be arranged in sequence along the first direction X. The orthographic projection of the active layers of the nine multiplexing transistors on the substrate can be approximately rectangular.

[0178] In some examples, the gates of the nine multiplexing transistors of the multiplexing circuit can be located in the first gate metal layer. The orthographic projection of the gate of each multiplexing transistor on the substrate can cover the orthographic projection of the channel region of the corresponding active layer on the substrate. The gate M13 of the first multiplexing transistor M1, the gate M23 of the second multiplexing transistor M2, the gate M33 of the third multiplexing transistor M3, the gate M43 of the fourth multiplexing transistor M4, the gate M53 of the fifth multiplexing transistor M5, the gate M63 of the sixth multiplexing transistor M6, the gate M73 of the seventh multiplexing transistor M7, the gate M83 of the eighth multiplexing transistor M8, and the gate M93 of the ninth multiplexing transistor M9 can all extend along the second direction Y and be arranged in sequence along the first direction X. The lengths of the gate M13 of the first multiplexing transistor M1, the gate M23 of the second multiplexing transistor M2, the gate M33 of the third multiplexing transistor M3, the gate M43 of the fourth multiplexing transistor M4, the gate M53 of the fifth multiplexing transistor M5, the gate M63 of the sixth multiplexing transistor M6, the gate M73 of the seventh multiplexing transistor M7, the gate M83 of the eighth multiplexing transistor M8 and the gate M93 of the ninth multiplexing transistor M9 along the second direction Y can increase sequentially.

[0179] In some examples, the first electrodes and the second electrodes of the nine multiplexing transistors of the multiplexing circuit may be located in the first source-drain metal layer. The first electrode M11 of the first multiplexing transistor M1 can be connected to the first area of ​​the first active layer M10 of the first multiplexing transistor M1 through a plurality of (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; the first electrode M21 of the second multiplexing transistor M2 can be connected to the first area of ​​the second active layer M20 of the second multiplexing transistor M2 through a plurality of (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; the first electrode M31 of the third multiplexing transistor M3 can be connected to the first area of ​​the third active layer M30 of the third multiplexing transistor M3 through a plurality of (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; the first electrode M41 of the fourth multiplexing transistor M4 can be connected to the first area of ​​the fourth active layer M40 of the fourth multiplexing transistor M4 through a plurality of (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; the first electrode M51 of the fifth multiplexing transistor M5 can be connected to the first area of ​​the fourth active layer M40 of the fourth multiplexing transistor M4 through a plurality of (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer The first electrode M91 of the ninth multiplexing transistor M9 can be connected to the first area of ​​the ninth active layer M90 of the ninth multiplexing transistor M9 through the multiple (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer.

[0180] In some examples, the first electrode M11 of the first multiplexing transistor M1, the first electrode M21 of the second multiplexing transistor M2, the first electrode M31 of the third multiplexing transistor M3, the first electrode M41 of the fourth multiplexing transistor M4, the first electrode M51 of the fifth multiplexing transistor M5, the first electrode M61 of the sixth multiplexing transistor M6, the first electrode M71 of the seventh multiplexing transistor M7, the first electrode M81 of the eighth multiplexing transistor M8, and the first electrode M91 of the ninth multiplexing transistor M9 are connected to the first auxiliary line 402. The first electrodes of the nine multiplexing transistors and the first auxiliary line 402 can be interconnected as an integral structure. The first auxiliary line 402 is linear and extends along the first direction X. The first auxiliary line 402 can be connected to the multiplexing data lead line 62 located in the first gate metal layer through a via defined in the interlayer insulating layer and the second gate insulating layer. The multiplexing data lead lines connected to adjacent multiplexing circuits can be located in different conductive layers. For example, multiple multiplexing data lead lines can be arranged alternately in the first gate metal layer and the second gate metal layer.

[0181] In some examples, the second electrode M12 of the first multiplexing transistor M1 can be connected to the second region of the first active layer M10 of the first multiplexing transistor M1 through multiple (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; the second electrode M22 of the second multiplexing transistor M2 can be connected to the second region of the second active layer M20 of the second multiplexing transistor M2 through multiple (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; the second electrode M32 of the third multiplexing transistor M3 can be connected to the second region of the third active layer M30 of the third multiplexing transistor M3 through multiple (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; the second electrode M42 of the fourth multiplexing transistor M4 can be connected to the second region of the fourth active layer M40 of the fourth multiplexing transistor M4 through multiple (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; the second electrode M52 of the fifth multiplexing transistor M5 can be connected to the second region of the fourth active layer M40 of the fourth multiplexing transistor M4 through multiple (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer A plurality of (four) vias opened in the first gate insulating layer are connected to the second region of the fifth active layer M50 of the fifth multiplexing transistor M5; a second electrode M62 of the sixth multiplexing transistor M6 can be connected to the second region of the sixth active layer M60 of the sixth multiplexing transistor M6 through a plurality of (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; a second electrode M72 of the seventh multiplexing transistor M7 can be connected to the second region of the seventh active layer M70 of the seventh multiplexing transistor M7 through a plurality of (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; a second electrode M82 of the eighth multiplexing transistor M8 can be connected to the second region of the eighth active layer M80 of the eighth multiplexing transistor M8 through a plurality of (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; a second electrode M92 of the ninth multiplexing transistor M9 can be connected to the second region of the ninth active layer M90 of the ninth multiplexing transistor M9 through a plurality of (four) vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer.

[0182] In some examples, data lines DL1 to DL9 may be located in the second source-drain metal layer. Data line DL1 may be connected to the second electrode M12 of the first multiplexing transistor M1 through a via provided in the first planar layer and the passivation layer. Data line DL2 may be connected to the second electrode M22 of the second multiplexing transistor M2 through a via provided in the first planar layer and the passivation layer. Data line DL3 may be connected to the second electrode M32 of the third multiplexing transistor M3 through a via provided in the first planar layer and the passivation layer. Data line DL4 may be connected to the second electrode M42 of the fourth multiplexing transistor M4 through a via provided in the first planar layer and the passivation layer. Data line DL5 may be connected to the second electrode M52 of the fifth multiplexing transistor M5 through a via provided in the first planar layer and the passivation layer. Data line DL6 may be connected to the second electrode M62 of the sixth multiplexing transistor M6 through a via provided in the first planar layer and the passivation layer. Data line DL7 may be connected to the second electrode M72 of the seventh multiplexing transistor M7 through a via provided in the first planar layer and the passivation layer. The data line DL8 can be connected to the second electrode M82 of the eighth multiplexing transistor M8 through a via hole defined in the first planar layer and the passivation layer. The data line DL9 can be connected to the second electrode M92 of the ninth multiplexing transistor M9 through a via hole defined in the first planar layer and the passivation layer.

[0183] In some examples, the multiplexing control lead-out lines are directly connected to the multiplexing control lines as an example for illustration. Multiple multiplexing control lead-out lines (e.g., the first multiplexing control lead-out line 641 to the ninth multiplexing control lead-out line 649) can be located in the first source and drain metal layer. Multiple multiplexing control lead-out lines can extend at least along the first direction X and be arranged in sequence along the second direction Y. Multiple multiplexing control lines (e.g., the first multiplexing control line 51 to the ninth multiplexing control line 59) can be located at least in the second gate metal layer. Multiple multiplexing control lines can extend at least along the second direction Y and be arranged along the first direction X.

[0184] In some examples, the first multiplexing control lead 641 can be connected to the gate M13 of the first multiplexing transistor M1 and the first multiplexing control line 51, and is configured to transmit a first multiplexing control signal. The second multiplexing control lead 642 can be connected to the gate M23 of the second multiplexing transistor M2 and the second multiplexing control line 52, and is configured to transmit a second multiplexing control signal. The third multiplexing control lead 643 can be connected to the gate M33 of the third multiplexing transistor M3 and the third multiplexing control line 53, and is configured to transmit a third multiplexing control signal. The fourth multiplexing control lead 644 can be connected to the gate M43 of the fourth multiplexing transistor M4 and the fourth multiplexing control line 54, and is configured to transmit a fourth multiplexing control signal. The fifth multiplexing control lead 645 can be connected to the gate M53 of the fifth multiplexing transistor M5 and the fifth multiplexing control line 55, and is configured to transmit a fifth multiplexing control signal. The sixth multiplexing control lead-out line 646 can be connected to the gate M63 of the sixth multiplexing transistor M6 and the sixth multiplexing control line 56, and is configured to transmit the sixth multiplexing control signal. The seventh multiplexing control lead-out line 647 can be connected to the gate M73 of the seventh multiplexing transistor M7 and the seventh multiplexing control line 57, and is configured to transmit the seventh multiplexing control signal. The eighth multiplexing control lead-out line 648 can be connected to the gate M83 of the eighth multiplexing transistor M8 and the eighth multiplexing control line 58, and is configured to transmit the eighth multiplexing control signal. The ninth multiplexing control lead-out line 649 can be connected to the gate M93 of the ninth multiplexing transistor M9 and the ninth multiplexing control line 59, and is configured to transmit the ninth multiplexing control signal. The setting method of this example is conducive to the reasonable arrangement of the multiplexing circuit in the first fan-out area.

[0185] Figure 7 illustrates another exemplary arrangement of multiplexed control lines and multiplexed data lines in accordance with at least one embodiment of the present disclosure. Figure 7 illustrates only a few multiplexed data lines as an example. Figure 7 schematically illustrates the general routing of multiplexed control lines and multiplexed data lines in the second fan-out region of the display panel. This embodiment does not limit the number of multiplexed data lines. This example uses the 1:9 design of the multiplexing circuit shown in Figure 3 as an example.

[0186] In some examples, as shown in Figure 7, within the first signal access area B14, multiple first multiplexing transfer pads 711a can be arranged along the extension direction of the third side (e.g., the second direction Y), multiple first multiplexing transfer pads 711b can be arranged along the extension direction of the fourth side (e.g., the second direction Y), and multiple second multiplexing transfer pads 712a and 712b can be arranged along the extension direction of the first side (e.g., the first direction X). The arrangement direction of the multiple first multiplexing transfer pads is different from the arrangement direction of the multiple second multiplexing transfer pads. In some examples, the multiple first multiplexing transfer pads 711a can be located on the side of the third side contact pad 715 close to the first side, and the multiple first multiplexing transfer pads 711b can be located on the side of the fourth side contact pad 716 close to the first side. In some examples, within the second signal access area B14, the multiplexing control contact pad 721 can be set between the DC signal contact pad and the second contact pad to reduce the overlap of the first sub-line of the multiplexing control line and the control signal line. However, this embodiment is not limited to this.

[0187] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0188] Figure 8 illustrates another exemplary arrangement of multiplexed control lines and multiplexed data lines in accordance with at least one embodiment of the present disclosure. Figure 8 illustrates only a few multiplexed data lines as an example. Figure 8 schematically illustrates the general routing of multiplexed control lines, multiplexed data lines, and the first power supply lead in the second fan-out region of the display panel. This embodiment does not limit the number of multiplexed data lines. This example uses the 1:9 design of the multiplexing circuit shown in Figure 3 as an example.

[0189] In some examples, as shown in FIG8 , the first extension portion 3122 of the first power lead 312 in the second fan-out region can be connected to at least one first voltage contact pad 7241 within the first group of DC signal contact pads within the second signal access region B15, and the second extension portion 3123 can be connected to at least one first voltage contact pad 7241 within the second group of DC signal contact pads within the second signal access region B15. The first group of DC signal contact pads can be located inside the first group of multiplexing control contact pads 721a, and the second group of DC signal contact pads can be located inside the second group of multiplexing control contact pads 721b. For example, no square wave signal contact pads may be provided between the first group of DC signal contact pads and the first group of multiplexing control contact pads 721a, and no square wave signal contact pads may be provided between the second group of DC signal contact pads and the second group of multiplexing control contact pads 721b.

[0190] In some examples, the orthographic projection of the first sub-line of the first group of multiplexing control lines (e.g., the first sub-line 591 of the ninth multiplexing control line) on the substrate may overlap with the orthographic projection of the first extension portion 3122 of the first power lead 312 on the substrate; the orthographic projection of the first sub-line of the second group of multiplexing control lines (e.g., the first sub-line 511 of the first multiplexing control line) on the substrate may overlap with the orthographic projection of the second extension portion 3123 of the first power lead 312 on the substrate. The orthographic projections of the first sub-line of the multiplexing control lines on the substrate may not overlap with those of the square wave signal transmission lines (e.g., including multiple control signal lines).

[0191] In some examples, within the second signal access area B15, the second voltage contact pad is located on the inner side of the multiplexing control contact pad 721, then the orthographic projection of the first sub-line of the multiplexing control line on the substrate may overlap with the orthographic projection of the second power lead line on the substrate; within the second signal access area B15, the second voltage contact pad is located on the outer side of the multiplexing control contact pad 721, then the orthographic projection of the first sub-line of the multiplexing control line on the substrate may not overlap with the orthographic projection of the second power lead line on the substrate.

[0192] In the display panel of this example, after the first sub-line of the multiplexing control line is connected to the multiplexing control contact pad 721, it extends to the side close to the bending area B12. It only needs to cross the DC signal transmission line (such as the first power lead, or the first power lead and the second power lead) and then connect to the third sub-line in the first signal access area B14. The third sub-line is led out at the middle position of the first signal access area B14 and connected to the second sub-line, thereby bypassing the multiplexing data line and avoiding the overlap of the multiplexing control line and the multiplexing data line. This example reduces the overlap of the multiplexing control line and the remaining square wave signal transmission lines, which can avoid crosstalk of the multiplexing control signal, thereby avoiding poor screen splitting at low grayscale. The rest of the description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0193] Figure 9 illustrates another exemplary arrangement of multiplexed control lines and multiplexed data lines in accordance with at least one embodiment of the present disclosure. Figure 8 illustrates only a few multiplexed data lines as an example. Figure 9 schematically illustrates the general arrangement of multiplexed control lines, multiplexed data lines, and the first power supply lead in the second fan-out region of the display panel. This embodiment does not limit the number of multiplexed data lines. This example illustrates the 1:9 design of the multiplexing circuit shown in Figure 3.

[0194] In some examples, as shown in FIG9 , within the second signal access area B15 , the first voltage contact pad 7241 to which the first power lead 312 is connected may be located outside the multiplexing control contact pad 721 . A square wave signal contact pad may not be provided between the first voltage contact pad 7241 and the multiplexing control contact pad 721 . However, this embodiment is not limited to this. In other examples, at least one square wave signal contact pad may be provided between the first voltage contact pad 7241 and the multiplexing control contact pad 721 .

[0195] In the display panel of this example, after the first sub-line of the multiplexing control line is connected to the multiplexing control contact pad 721, it extends to the side close to the bending area B12, without crossing any signal, and directly accesses the first signal access area B14, and is connected to the third sub-line. The third sub-line is led out at the middle position of the first signal access area B14 and connected to the second sub-line, thereby bypassing the multiplexing data line and avoiding the overlap of the multiplexing control line and the multiplexing data line. This example reduces the overlap of the multiplexing control line with the DC signal and square wave signal transmission lines, which can avoid crosstalk of the multiplexing control signal, thereby avoiding poor screen splitting at low grayscale. The rest of the description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0196] Figure 10 is another example diagram of the arrangement of multiplexed control lines and multiplexed data lines in at least one embodiment of the present disclosure. Figure 10 illustrates several multiplexed data lines as examples. Figure 10 shows a schematic diagram of the approximate routing of multiplexed control lines and multiplexed data lines in the second fan-out region of the display panel. This embodiment does not limit the number of multiplexed data lines. This example uses the 1:9 design shown in Figure 3 as an example for multiplexing circuits. Figure 10 only labels the ninth multiplexed control line 59 and the first multiplexed control line 51 for illustration purposes.

[0197] In some examples, as shown in FIG10 , within the second signal access area B15 , the plurality of first contact pads can be divided into two groups: a first group of first contact pads 722 a and a second group of first contact pads 722 b. The plurality of multiplexing control contact pads 721 can be located between the first group of first contact pads 722 a and the second group of first contact pads 722 b. Within the first signal access area B14 , the plurality of first multiplexing transfer pads 711 can be arranged along the extension direction of the second side edge, and the plurality of second multiplexing transfer pads 712 can be arranged along the extension direction of the first side edge. The plurality of first multiplexing transfer pads 711 and the plurality of second multiplexing transfer pads 712 can be arranged at least partially aligned in the second direction Y.

[0198] 10 , the first sub-lines of the plurality of multiplexing control lines (such as the first sub-line 511 of the first multiplexing control line 51 and the ninth sub-line 591 of the ninth multiplexing control line 59) can be located in the middle of the plurality of first pin connection lines 731. The first sub-line, the second sub-line, and the third sub-line of each multiplexing control line can extend at least along the second direction Y.

[0199] In the display panel of this example, the multiplexing control contact pad can be located in the middle of the second signal access area. After the multiplexing control line is connected to the multiplexing control contact pad, it can extend directly in the direction close to the bending area B12, and after passing through the first signal access area B14, extend to between the first group of multiplexing data lines 61a and the second group of multiplexing data lines 61b. The arrangement of the multiplexing control lines in this example can bypass the multiplexing data lines to avoid overlapping between the multiplexing control lines and the multiplexing data lines. Moreover, this example can reduce the overlap of the multiplexing control lines with the remaining DC signal and square wave signal transmission lines, and can avoid crosstalk of the multiplexing control signals, thereby avoiding poor screen splitting at low grayscale. The remaining description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0200] Figure 11 illustrates another exemplary arrangement of multiplexed control lines and multiplexed data lines in accordance with at least one embodiment of the present disclosure. Figure 11 illustrates only a few multiplexed data lines as an example. Figure 11 schematically illustrates the general routing of multiplexed control lines, multiplexed data lines, and first power supply leads in the second fan-out region of the display panel. This embodiment does not limit the number of multiplexed data lines. This example uses the 1:9 design shown in Figure 3 as an example for the multiplexing circuit.

[0201] In some examples, as shown in FIG11 , the second fan-out area B is further provided with a first shielding electrode 81. The first shielding electrode 81 can be connected to the first power lead 312. For example, the first shielding electrode 81 and the first power lead 312 can be an integral structure connected to each other. The first shielding electrode 81 can be located on a side of the first signal access area B14 close to the bending area B12. The first shielding electrode 81 can be connected to a side of the first main body 3121 of the first power lead 312 away from the bending area B12. The length of the first shielding electrode 81 along the first direction X can be less than or equal to the length of the first main body 3121 of the first power lead 312 along the first direction X.

[0202] In some examples, the first power lead 312 can be a single-layer trace, for example, located in the first source-drain metal layer or the second source-drain metal layer, and the first shielding electrode 81 can be located in the same layer as the first power lead 312. In other examples, the first shielding electrode 81 and the first power lead 312 can be different-layer structures. For example, the first shielding electrode 81 can be located in the second source-drain metal layer and connected to the first power lead 312 located in the first source-drain metal layer. In other examples, the first power lead 312 can be a double-layer trace, for example, located in the first source-drain metal layer and the second source-drain metal layer, and the first shielding electrode 81 can be located in the first source-drain metal layer or the second source-drain metal layer and connected to a portion of the trace of the first power lead arranged in the same layer.

[0203] In some examples, as shown in FIG11 , the first shielding electrode 81 may be located between the first group of second sub-lines 502a and the second group of second sub-lines 502b. The orthographic projection of the first shielding electrode 81 on the substrate may not overlap with the orthographic projection of the first group of second sub-lines 502a and the second group of second sub-lines 502b on the substrate. In this example, by setting the first shielding electrode between the two groups of second sub-lines, the crosstalk to the multiplexing control signal can be reduced. However, this embodiment is not limited to this. In other examples, the first shielding electrode may be located between the second sub-lines and the multiplexing data line. For example, a first shielding electrode is set between the first group of second sub-lines and the first group of multiplexing data lines, and another first shielding electrode is set between the second group of second sub-lines and the second group of multiplexing data lines, thereby reducing the crosstalk between the data signal and the multiplexing control signal.

[0204] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0205] FIG12 is a partial schematic diagram of the second fan-out area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG12 , the first power lead 312 and the first shielding electrode 81 may both be located in the first source-drain metal layer, and the first power lead 312 and the first shielding electrode 81 may be an integral structure connected to each other. At least a portion of the second sub-line of the plurality of multiplexing control lines may be located in the first source-drain metal layer and adjacent to the first shielding electrode 81. The orthographic projection of the first shielding electrode 81 on the substrate may not overlap with the orthographic projection of the second sub-line of the plurality of multiplexing control lines on the substrate. The rest of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0206] FIG13 is another partial schematic diagram of the second fan-out region of at least one embodiment of the present disclosure. In some examples, as shown in FIG13 , the first power lead 312 and the second power lead 322a and 322b can all be double-layer routing structures disposed in the first source-drain metal layer and the second source-drain metal layer. The second fan-out region is also provided with a second shielding electrode 82 connected to the first shielding electrode. The first shielding electrode can be located in the first source-drain metal layer and can be an integral structure interconnected with the routing portion of the first power lead 312 located in the first source-drain metal layer. The second shielding electrode 82 can be located in the second source-drain metal layer and can be an integral structure interconnected with the routing portion of the first power lead 312 located in the second source-drain metal layer.

[0207] In some examples, the second shielding electrode 82 can be connected to the first shielding electrode via a groove defined in the first planar layer and the passivation layer. The orthographic projection of the second shielding electrode 82 on the substrate can include the orthographic projection of the first shielding electrode on the substrate. For example, the orthographic projection of the second shielding electrode 82 on the substrate can overlap with the orthographic projection of the first shielding electrode on the substrate; alternatively, the orthographic projection of the second shielding electrode 82 on the substrate can cover the orthographic projection of the first shielding electrode on the substrate. However, this embodiment is not limited to this. For example, the orthographic projection of the first shielding electrode on the substrate can cover the orthographic projection of the second shielding electrode on the substrate.

[0208] In some examples, the orthographic projection of the second shielding electrode 82 on the substrate may not overlap with the orthographic projection of the second sub-lines of the plurality of multiplexing control lines (such as the second sub-lines 592 and 512). For example, the second shielding electrode 82 may be located between the first group of second sub-lines and the second group of second sub-lines.

[0209] This example utilizes first and second shielding electrodes located on different film layers, each connected to a first power lead, to reduce the IR drop of the first power signal. This improves display image uniformity and further shields against signal interference. The remainder of the display panel of this example can be found in the description of the preceding embodiment and will not be further elaborated here.

[0210] Figure 14 is another partial schematic diagram of the second fan-out region of at least one embodiment of the present disclosure. Figure 15 is a partial cross-sectional schematic diagram along the QQ' direction in Figure 14.

[0211] In some examples, as shown in FIG14 , the first power lead 312 and the second power lead 322a and 322b can each be a double-layer routing structure disposed in the first source / drain metal layer and the second source / drain metal layer. The second fan-out region is further provided with a second shielding electrode 82 connected to the first shielding electrode. The first shielding electrode can be located in the first source / drain metal layer and can be interconnected with the routing portion of the first power lead 312 located in the first source / drain metal layer as an integrated structure. The second shielding electrode 82 can be located in the second source / drain metal layer and can be interconnected with the routing portion of the first power lead 312 located in the second source / drain metal layer as an integrated structure.

[0212] In some examples, as shown in Figures 14 and 15 , the second shield electrode 82 can be connected to the first shield electrode 81 via a groove defined in the first planar layer and the passivation layer. The orthographic projection of the second shield electrode 82 on the substrate can include the orthographic projection of the first shield electrode on the substrate. For example, the orthographic projection of the second shield electrode 82 on the substrate can cover the orthographic projection of the first shield electrode 81 on the substrate.

[0213] In some examples, the orthographic projection of the second shielding electrode 82 on the substrate may overlap with the orthographic projection of the second sub-lines of the multiplexed control lines (for example, including the second sub-lines 592 and 512) on the substrate. The second sub-lines of the multiplexed control lines may be in the same layer structure as the first shielding electrode 81, for example, both are located in the first source and drain metal layer. However, this embodiment is not limited to this. In other examples, the second sub-lines of the multiplexed control lines may be located in a conductive layer on the side of the first source and drain metal layer close to the substrate, for example, the first gate metal layer or the second gate metal layer.

[0214] In this example, by providing a second shielding electrode to shield the second sub-line of the multiplexing control line, the data signal and the influence of other external signals or electric fields on the multiplexing control signal can be shielded. The rest of the display panel of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0215] In other examples, the grouping manner of the multiple multiplexing control lines and the arrangement order of the multiple multiplexing control lines in each group of multiplexing control lines can be adjusted according to the situation.

[0216] In other examples, the multiplexing circuit may adopt a 1:6 design, but this embodiment is not limited to this.

[0217] This embodiment also provides a display panel, comprising: a substrate, a plurality of sub-pixels and a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, and a plurality of multiplexing control lines. The substrate includes a display area and a first frame area located on at least one side of the display area. The first frame area includes at least a first signal access area, wherein the first signal access area is provided with a plurality of data contact pads. A plurality of sub-pixels and a plurality of data lines are located in the display area. The plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. A plurality of multiplexing circuits, a plurality of multiplexing data lines, and a plurality of multiplexing control lines are located in the first frame area. The multiplexing circuit is connected to at least two of the plurality of multiplexing control lines, a multiplexing data line, and at least two of the plurality of data lines, and is configured to provide the data signal transmitted by the one reset data line to the at least two data lines under the control of the at least two multiplexing control lines. The plurality of multiplexing data lines are connected to the plurality of data contact pads in the first signal access area. The orthographic projections of the multiplexed data lines and the multiplexed control lines on the substrate do not overlap; a portion of at least one multiplexed control line is located in the first signal access area. In some examples, a portion of a multiplexed control line is located in the first signal access area, or a portion of each of the multiplexed control lines is located in the first signal access area.

[0218] This example sets a portion of at least one multiplexing control line in the first signal access area to avoid overlapping with multiple multiplexing data lines, thereby reducing the impact of the multiplexing data line on the multiplexing control signal transmitted by the multiplexing control line, which is beneficial to improving the display quality of the display panel.

[0219] In some exemplary embodiments, the first border area further includes a second signal access area, located on a side of the first signal access area away from the display area, and provided with a plurality of multiplexing control contact pads. The multiplexing control line includes a first sub-line, a second sub-line, and a third sub-line, the third sub-line being connected between the first sub-line and the second sub-line. The third sub-line is located in the first signal access area. The second sub-line is located on a side of the first signal access area closer to the display area. The first sub-line is connected to the multiplexing control contact pads of the second signal access area.

[0220] In some exemplary embodiments, the third sub-lines of the multiple multiplexing control lines are divided into a first group of third sub-lines and a second group of third sub-lines, and the first group of third sub-lines and the second group of third sub-lines are arranged along a first direction; the extension direction of the third sub-lines of the multiple multiplexing control lines crosses the extension direction of the second sub-lines.

[0221] In some example embodiments, an extending direction of the third sub-line of the plurality of multiplexing control lines is the same as an extending direction of the second sub-line.

[0222] In some exemplary embodiments, the plurality of multiplexed data lines are divided into a first group of multiplexed data lines and a second group of multiplexed data lines. The second sub-lines of the plurality of multiplexed control lines are divided into a first group of second sub-lines and a second group of second sub-lines; the first group of second sub-lines and the second group of second sub-lines are located between the first group of multiplexed data lines and the second group of multiplexed data lines. The first border area is provided with a first power lead and a first shielding electrode, the first shielding electrode being connected to the first power lead; the first shielding electrode is located on a side of the first signal access area close to the display area; and the first shielding electrode is located between the first group of second sub-lines and the second group of second sub-lines.

[0223] In some exemplary embodiments, a second shielding electrode is further provided in the first border area. The second shielding electrode is located on a side of the first shielding electrode away from the substrate, and the second shielding electrode is electrically connected to the first shielding electrode. The orthographic projection of the second shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first shielding electrode on the substrate.

[0224] The description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0225] Figure 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 16 , this embodiment provides a display device 91 comprising a display panel 910 according to the aforementioned embodiment. In some examples, display panel 910 may be an OLED display panel, such as an OLED display panel with an integrated touchscreen structure. Display device 91 may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, or may be a product or component with both touchscreen and display functions.

[0226] In some examples, the display device 91 may be a wearable display device, for example, a display device that can be worn on a human body in some manner. For example, the display device 91 may be a smart watch, a smart bracelet, etc. However, this embodiment is not limited to this.

[0227] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display panel, comprising: a substrate including a display area and a first border area located at at least one side of the display area; a plurality of sub-pixels and a plurality of data lines located in the display area, the plurality of data lines being connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; a plurality of multiplexing circuits, a plurality of multiplexed data lines, and a plurality of multiplexed control lines located in the first border area; the multiplexing circuit is connected to at least two of the plurality of multiplexed control lines, one multiplexed data line, and at least two of the plurality of data lines, and is configured to provide, under the control of the at least two multiplexed control lines, the data signals transmitted by the one reset data line to the at least two data lines; orthographic projections of the plurality of multiplexed data lines and the plurality of multiplexed control lines on the substrate do not overlap; the plurality of multiplexed data lines are divided into a first group of multiplexed data lines and a second group of multiplexed data lines, and a part of at least one of the plurality of multiplexed control lines is located between the first group of multiplexed data lines and the second group of multiplexed data lines.

2. The display panel according to claim 1, wherein, the first border area at least includes: a first signal access area and a second signal access area, the second signal access area being located on a side of the first signal access area away from the display area; a plurality of multiplexed control contact pads are provided in the second signal access area; the multiplexed control line includes: a first sub-line, a second sub-line, and a third sub-line, the third sub-line being connected between the first sub-line and the second sub-line; the third sub-line is located in the first signal access area; the second sub-line is located on a side of the first signal access area close to the display area and between the first group of multiplexed data lines and the second group of multiplexed data lines; the first sub-line is connected to the multiplexed control contact pads in the second signal access area.

3. The display panel according to claim 2, wherein, a plurality of first multiplexed transfer pads and a plurality of second multiplexed transfer pads are provided in the first signal access area; the first sub-line of the multiplexed control line is connected to the third sub-line through the first multiplexed transfer pad, and the second sub-line of the multiplexed control line is connected to the third sub-line through the second multiplexed transfer pad.

4. The display panel according to claim 3, wherein, the first signal access area has a plurality of side edges, and the plurality of first multiplexed transfer pads and the plurality of second multiplexed transfer pads are arranged along the same side edge.

5. The display panel according to claim 4, wherein, a first group of data contact pads and a second group of data contact pads are further provided in the first signal access area; the first group of data contact pads are connected to the first group of multiplexed data lines, and the second group of data contact pads are connected to the second group of multiplexed data lines; the plurality of first multiplexed transfer pads are divided into a first group of first multiplexed transfer pads and a second group of first multiplexed transfer pads; the plurality of second multiplexed transfer pads are located between the first group of data contact pads and the second group of data contact pads; The first first multiplexing transfer pad of the first group is located on a side of the first group of data contact pads away from the plurality of second multiplexing transfer pads, and the first first multiplexing transfer pad of the second group is located on a side of the second group of data contact pads away from the plurality of second multiplexing transfer pads.

6. The display panel according to claim 3, wherein, The first signal access area at least has a first side edge and a second side edge with the same extending direction, and the second side edge is located on a side of the first side edge away from the display area; the plurality of first multiplexing transfer pads are arranged along the second side edge, and the plurality of second multiplexing transfer pads are arranged along the first side edge.

7. The display panel according to claim 6, wherein, In the extending direction of the second sub-line, at least part of the plurality of first multiplexing transfer pads and the plurality of second multiplexing transfer pads are arranged in alignment.

8. The display panel according to any one of claims 2 to 5, wherein, A plurality of DC signal transmission lines are provided in the first border area; a first sub-line of the multiplexing control line and at least one DC signal transmission line overlap in the orthographic projection on the substrate.

9. The display panel according to claim 8, wherein, The second signal access area is further provided with a plurality of DC signal contact pads arranged in a first direction; the plurality of DC signal contact pads are configured to be connected to the plurality of DC signal transmission lines; the plurality of multiplexing control contact pads are located on a side of the plurality of DC signal contact pads close to the edge of the display panel.

10. The display panel according to claim 9, wherein, A plurality of square wave signal transmission lines are further provided in the first border area, and a first sub-line of the multiplexing control line also overlaps with at least one square wave signal transmission line in the orthographic projection on the substrate.

11. The display panel according to claim 10, wherein, The second signal access area is further provided with a plurality of square wave signal contact pads arranged in a first direction; the plurality of square wave signal contact pads are configured to be connected to the plurality of square wave signal transmission lines; at least one square wave signal contact pad is provided between the plurality of multiplexing control contact pads and the plurality of DC signal contact pads.

12. The display panel according to claim 2, wherein, A plurality of DC signal transmission lines are provided in the first border area; a first sub-line of the multiplexing control line and the plurality of DC signal transmission lines do not overlap in the orthographic projection on the substrate.

13. The display panel according to claim 12, wherein, The second signal access area is further provided with a plurality of DC signal contact pads arranged in a first direction; the plurality of DC signal contact pads are configured to be connected to the plurality of DC signal transmission lines; the plurality of multiplexing control contact pads are located on a side of the plurality of DC signal contact pads away from the edge of the display panel.

14. The display panel according to any one of claims 2 to 13, wherein, The first border region is provided with a first power supply lead-out line and a first shielding electrode, and the first shielding electrode is connected to the first power supply lead-out line; the first shielding electrode is located on a side of the first signal access region close to the display region; the second sub-lines of the plurality of multiplexed control lines are divided into a first group of second sub-lines and a second group of second sub-lines; the first shielding electrode is located between the first group of second sub-lines and the second group of second sub-lines.

15. The display panel according to claim 14, wherein, a positive projection of the first shielding electrode on the substrate does not overlap with a positive projection of the second sub-lines of the plurality of multiplexed control lines on the substrate.

16. The display panel according to claim 14, wherein, the first border region is further provided with a second shielding electrode, the second shielding electrode is located on a side of the first shielding electrode away from the substrate, and the second shielding electrode is electrically connected to the first shielding electrode; a positive projection of the second shielding electrode on the substrate at least partially overlaps with a positive projection of the first shielding electrode on the substrate.

17. The display panel according to claim 16, wherein, the second shielding electrode is located on a side of the second sub-lines of the plurality of multiplexed control lines away from the substrate, and a positive projection of the second shielding electrode on the substrate overlaps with a positive projection of at least one second sub-line of the plurality of multiplexed control lines on the substrate.

18. A display device, comprising the display panel according to any one of claims 1 to 17.

19. The display device according to claim 18, further comprising: a driving chip and a flexible circuit board connected to the display panel, wherein the first border region of the display panel at least includes: a first signal access region and a second signal access region, the second signal access region is located on a side of the first signal access region away from the display region; a positive projection of the driving chip on the display panel is located in the first signal access region, and at least some pins of the flexible circuit board are located in the second signal access region.

20. A display panel, comprising: a substrate, including a display region and a first border region located on at least one side of the display region, the first border region at least includes: a first signal access region, and the first signal access region is provided with a plurality of data contact pads; a plurality of sub-pixels and a plurality of data lines, located in the display region, the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels; a plurality of multiplexing circuits, a plurality of multiplexed data lines and a plurality of multiplexed control lines, located in the first border region; the multiplexing circuit is connected to at least two of the plurality of multiplexed control lines, one multiplexed data line and at least two of the plurality of data lines, and is configured to provide, under the control of the at least two multiplexed control lines, the data signal transmitted by the one reset data line to the at least two data lines; the plurality of multiplexed data lines are connected to the plurality of data contact pads in the first signal access region; The orthographic projections of the multiple multiplexed data lines and the multiple multiplexed control lines on the substrate do not overlap; a part of at least one multiplexed control line among the multiple multiplexed control lines is located in the first signal access area.

21. The display panel according to claim 20, wherein, The first border area further includes: a second signal access area, the second signal access area is located on a side of the first signal access area away from the display area, and a plurality of multiplexed control contact pads are provided in the second signal access area; The multiplexed control line includes: a first sub-line, a second sub-line, and a third sub-line, and the third sub-line is connected between the first sub-line and the second sub-line; the third sub-line is located in the first signal access area; the second sub-line is located on a side of the first signal access area close to the display area; the first sub-line is connected to the multiplexed control contact pad in the second signal access area.

22. The display panel according to claim 21, wherein, The third sub-lines of the multiple multiplexed control lines are divided into a first group of third sub-lines and a second group of third sub-lines, and the first group of third sub-lines and the second group of third sub-lines are arranged along a first direction; the extending direction of the third sub-lines of the multiple multiplexed control lines intersects with the extending direction of the second sub-lines.

23. The display panel according to claim 21, wherein, The extending direction of the third sub-lines of the multiple multiplexed control lines is the same as the extending direction of the second sub-lines.

24. The display panel according to claim 21, wherein, The multiple multiplexed data lines are divided into a first group of multiplexed data lines and a second group of multiplexed data lines; The second sub-lines of the multiple multiplexed control lines are divided into a first group of second sub-lines and a second group of second sub-lines; the first group of second sub-lines and the second group of second sub-lines are located between the first group of multiplexed data lines and the second group of multiplexed data lines; A first power supply lead-out line and a first shielding electrode are provided in the first border area, and the first shielding electrode is connected to the first power supply lead-out line; the first shielding electrode is located on a side of the first signal access area close to the display area; the first shielding electrode is located between the first group of second sub-lines and the second group of second sub-lines.

25. The display panel according to claim 24, wherein, A second shielding electrode is further provided in the first border area, the second shielding electrode is located on a side of the first shielding electrode away from the substrate, and the second shielding electrode is electrically connected to the first shielding electrode; the orthographic projection of the second shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first shielding electrode on the substrate.

Images