High-quality sic crystal, crystal bar, substrate, and semiconductor device

Abstract

The present application provides a high-quality SiC crystal, a crystal bar, a substrate, and a semiconductor device, relating to the technical field of silicon carbide wafers. The SiC crystal contains a faceted area and a non-faceted area, the faceted area is located on the outer circumferential end face of the SiC crystal, the distance between the edge of the faceted area away from the outer circumferential end face and the outer circumferential end face does not exceed 3% of the diameter of the SiC crystal, and the SiC crystal is directly grown by using a PVT method without subsequent processing. During subsequent processing of the crystal, the faceted area is removed, with a relatively low cutting loss rate, so that a whole crystal bar, as well as a wafer and a substrate processed therefrom, do not have faceted areas. The present invention ensures that a device end has higher yield, performance and reliability.

Description

High-quality SiC crystal, crystal rod, substrate and semiconductor device

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on September 28, 2023, with application number 202311265574.7 and invention name “A high-quality silicon carbide substrate and semiconductor device”, and the Chinese patent application filed with the Patent Office of China on November 3, 2023, with application number 202311464892.6 and invention name “A SiC crystal with a small face at the edge, its wafer and semiconductor device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of silicon carbide wafers, and in particular to a high-quality SiC crystal, a crystal rod, a substrate, and a semiconductor device. Background Art

[0003] Currently, silicon carbide crystals face two major challenges: 1. Quality issues, which impact the yield, performance, and reliability of silicon carbide devices; and 2. Cost issues, which hinder the application of silicon carbide in the end market. Material quality, resulting in loss of material and device yield, is the primary reason for the high cost and difficulty in application of silicon carbide crystals.

[0004] The quality problems of silicon carbide crystals fall into two categories: one is material quality and yield problems caused by defects, which are explicit quality problems; the other is material yield and device performance reliability problems caused by consistency problems.

[0005] Currently, because growth features are an inherent property of SiC crystals grown by sublimation, they are present on both SiC crystals and substrates grown by conventional physical vapor transport (PVT). These features are commonly referred to in the art as "facets," "growth facets," or "characteristic growth surfaces." In this application, these facets do not refer to growth interfaces.

[0006] Improving quality and reducing costs are the goals of the sustainable development of silicon carbide crystal materials. Especially as the silicon carbide industry rapidly enters the stage of large-scale production and application, the stability, consistency, and reliability of silicon carbide material performance will play a vital role in industrial development.

[0007] Summary of the Invention

[0008] In order to solve the above problems, the first aspect of the present application provides a SiC crystal with a small face located at the edge, wherein the SiC crystal contains a small face area and a non-small face area; the small face area is located at the outer circumferential end face of the SiC crystal, and the distance between the edge of the small face area away from the outer circumferential end face and the outer circumferential end face does not exceed 3% of the diameter of the SiC crystal, and the SiC crystal is directly grown by the PVT method without subsequent processing.

[0009] The outer circumferential end face refers to the edge position of the crystal lateral growth, or the edge position of the crystal. The edge of the facet region away from the outer circumferential end face refers to the end of the facet region close to the center of the silicon carbide crystal.

[0010] In some embodiments, the maximum cross-sectional area of ​​the faceted region accounts for less than 10% of the cross-sectional area of ​​the crystal along the diameter direction; and / or the volume of the faceted region accounts for less than 2% of the volume of the entire crystal. For example, the faceted region can be located at the edge of an upper or lower corner of the crystal.

[0011] In some embodiments, the maximum cross-sectional area of ​​the faceted region accounts for less than 5% of the cross-sectional area of ​​the crystal along the diameter direction; and / or the volume of the faceted region accounts for less than 0.6% of the volume of the entire crystal. The overall shape of the faceted region can be triangular, conical, spherical, ellipsoidal, or rhombus-shaped. However, the present application is not limited to this, and the faceted region can be of irregular shape.

[0012] In some embodiments, the in-plane resistivity difference of the facet region is more than 5 times the in-plane resistivity difference of the non-facet region; and / or the transmittance difference of the facet region is more than 5 times the transmittance difference of the non-facet region; and / or the TDV of the facet region is more than 6 times the TDV of the non-facet region.

[0013] In some embodiments, the in-plane resistivity difference of the facet region is more than 8 times the in-plane resistivity difference of the non-facet region; and / or the transmittance difference of the facet region is more than 14 times the transmittance difference of the non-facet region; and / or the TDV of the facet region is more than 10 times the TDV of the non-facet region.

[0014] In some embodiments, the cross section of the facet region along the diameter direction is elliptical, crescent-shaped, or circular. However, the present application is not limited thereto, and the cross section of the facet region along the diameter direction may be irregularly shaped.

[0015] A second aspect of the present application provides a facet-free silicon carbide crystal rod, which is obtained by removing the facet region from the SiC crystal with facets located at the edge.

[0016] A third aspect of the present application provides a SiC wafer, wherein the SiC wafer is obtained by removing the facet area from the SiC crystal with the facet located at the edge, and the facet-free silicon carbide crystal rod is obtained by cutting. The SiC wafer does not contain any one or more of facets, highly doped regions, and defect aggregation regions over the entire area.

[0017] In some embodiments, the SiC wafer has an in-plane resistivity difference of no more than 2 mΩ·cm; and / or a transmittance difference of no more than 3%; and / or a TDV of less than 200 cm -2 .

[0018] In some embodiments, the SiC wafer has an in-plane resistivity difference of no more than 1 mΩ·cm; and / or a transmittance difference of no more than 2%; and / or a TDV of less than 100 cm -2 .

[0019] In some embodiments, the SiC wafer is a silicon carbide wafer of any thickness, for example, a SiC wafer having a thickness of not less than 200 μm, or a silicon carbide wafer having a thickness of not less than 300 μm, or a silicon carbide wafer having a thickness of not less than 400 μm.

[0020] In some embodiments, the SiC wafer may be N2-doped or co-doped with any other element. Alternatively, nitrogen may be co-doped with any one or more of P, As, Ge, Sn, B, and Al, and the resulting silicon carbide wafer may be conductive.

[0021] In the present application, the silicon carbide substrate uses a SiC crystal with a small face located at the edge. The small face area is removed to obtain a facet-free silicon carbide crystal rod, which is then cut in sequence to obtain a peeling sheet. The peeling sheet is then thinned, polished, and cleaned in sequence to obtain a silicon carbide substrate sheet. The silicon carbide wafer in the present application is obtained directly by cutting.

[0022] In a fourth aspect, the present application provides a high-quality silicon carbide substrate, which is obtained by processing the SiC crystal with the above-mentioned small facet located at the edge by removing the small facet area. The silicon carbide substrate is conductive and does not contain any one or more of the growth feature surface, high doping area and defect aggregation area within its entire area; the silicon carbide substrate is prepared by the PVT method.

[0023] The growth characteristic surface is an inherent property of SiC crystals produced by the PVT method. The high-quality silicon carbide substrate in this application can change the movement trend of the growth characteristic surface during PVT growth, causing it to move toward the edge of the crystal and fix it within 5 mm from the edge of the crystal. When the crystal is actually used, the edge is cut. Therefore, after the crystal is cut, ground, polished and other processes, a silicon carbide substrate without a growth characteristic surface can be obtained.

[0024] Due to the existence of the growth feature surface in the original substrate, defects will be concentrated in this area. During the element doping process, the elements will be induced to gather and increase at the growth feature surface, thus showing uneven doping. The resistivity at the growth feature surface is also higher than that in other areas, and the overall light transmittance uniformity of the substrate is poor. The above limits the large-scale use of silicon carbide substrates.

[0025] The high-quality silicon carbide substrate in this application has no growth feature surface, and the entire substrate is uniformly distributed in both the radial and axial directions. Therefore, it can fundamentally curb the generation and aggregation of defects, avoid element aggregation during the doping process, and achieve uniform element doping, thereby improving the doping uniformity, resistivity uniformity and transmittance uniformity of the substrate. Therefore, the devices produced using this silicon carbide substrate not only have good performance themselves, but also have good consistency in mass production, which is conducive to industrial promotion and use.

[0026] In some embodiments, the silicon carbide substrate is N-type doped, and the N-type element doping concentration is greater than 1e 18 cm -3 , the properties over the entire area of ​​the silicon carbide substrate satisfy the following conditions.

[0027] a. The in-plane resistivity difference is not higher than 2.0 mΩ·cm.

[0028] b. The transmittance difference is not higher than 3%.

[0029] For example, the in-plane resistivity difference is no greater than 1.0 mΩ·cm; or the in-plane resistivity difference is no greater than 0.9 mΩ·cm; or the in-plane resistivity difference is no greater than 0.7 mΩ·cm. In-plane resistivity refers to the resistivity at any test location within the plane of the silicon carbide substrate.

[0030] In some embodiments, the doping concentration is 2e 18 ~7e 18 cm -3 , the in-plane resistivity difference is 0.62 to 0.86 mΩ·cm.

[0031] In some embodiments, the transmittance difference is no higher than 2%; or the transmittance difference is no higher than 1%; or the transmittance difference is no higher than 0.8%.

[0032] In some embodiments, the transmittance difference is 0.5% to 1.6%. Optionally, the transmittance difference is 0.5% to 1%. In some embodiments, the substrate is a silicon carbide substrate of any thickness. For example, the thickness of the silicon carbide substrate is not less than 200 μm; or the thickness of the silicon carbide substrate is not less than 300 μm; or the thickness of the silicon carbide substrate is not less than 400 μm.

[0033] For example, the N-type element is doped with N2 or co-doped with any other element, resulting in an in-plane resistivity difference of 0.62 to 0.86 mΩ·cm and a transmittance difference of 0.5% to 1.6%. Alternatively, nitrogen can be co-doped with any one or more of P, As, Ge, Sn, B, and Al, and the resulting silicon carbide substrate remains conductive.

[0034] The above N-type element doping concentration is greater than 1e18cm -3 , which belongs to medium-high nitrogen doping. For those skilled in the art, the higher the doping concentration, the more likely it is that there will be uneven doping, and therefore the difference in in-plane resistivity will be greater. In the process of controlling the movement trend of the growth feature surface, the present application fixes the growth feature surface at the edge of the crystal, thereby improving the doping uniformity during the doping process and making the light transmittance of the substrate more uniform.

[0035] The transmittance is related to the doping concentration and uniformity in the crystal. The transmittance difference of the silicon carbide substrate of the present application is no more than 3%, which can represent the uniform transmittance of the silicon carbide substrate, thereby helping to improve the quality of the downstream device-end lithography process and thus improve device performance.

[0036] In some embodiments, the silicon carbide substrate TDV is less than 200 cm -2 Optionally, the TDV of the silicon carbide substrate is less than 100 cm -2 Optionally, the silicon carbide substrate TDV is less than 10cm -2 The total density variation (TDV) is defined as the density of edge dislocations (TEDs) or screw dislocations (TSDs) within a specific grid of a substrate, such as 1mmx1mm, 2mmx2mm, 5mmx5mm, or 10mmx10mm squares. The TDV is calculated as the difference between the maximum and minimum TED / TSD densities (dmax - dmin).

[0037] Since the growth feature surface is eliminated in the silicon carbide substrate of the present application, the TED and TSD distributions can be made more uniform, so the TDV value is relatively low, indicating that the overall dislocation distribution of the substrate is relatively uniform, eliminating the problem of low overall defect density but high local density in the current substrate.

[0038] When the above substrate is used to prepare power electronic devices, due to the characteristics of low in-plane resistivity difference and low transmittance difference, it is possible to ensure that the device has excellent electrical performance and reliability during the device production process.

[0039] In some embodiments, the size of the silicon carbide wafer or silicon carbide substrate may be 4 inches, 6 inches, 8 inches, 10 inches, or 12 inches.

[0040] A fifth aspect of the present application provides a semiconductor device, which contains the above-mentioned SiC wafer or high-quality silicon carbide substrate.

[0041] In some embodiments, since facets are an inherent property of SiC crystals produced by sublimation, such facet regions exist on SiC crystals and wafers produced by conventional physical vapor transport methods. To secure the facets at the edges of the crystal and remove them during subsequent crystal processing, thereby achieving a facet-free state on the entire crystal ingot and the resulting wafers and substrates, the processing method for SiC crystals with facets located at the edges of the present application includes a crystal stabilization growth stage. The growth process conditions during the crystal stabilization growth stage include the following steps:

[0042] S1: There is a limiting edge near the crystal growth edge, the distance between the limiting edge and the crystal growth edge is not greater than 5mm, and a negative radial temperature gradient of -5°C / mm to 0.1°C / mm is set between the limiting edge and the crystal growth edge; a continuous positive temperature gradient is set from the limiting edge to the crystal center, and the continuous positive temperature gradient value is ≤3°C / cm;

[0043] S2: using a seed crystal larger than the target silicon carbide crystal to be grown for crystal growth, wherein the seed crystal diameter is at least 5 mm larger than the target crystal and the substrate diameter, and the high-quality silicon carbide substrate is obtained by processing the target crystal.

[0044] In some embodiments, the distance between the limiting edge and the crystal growth edge is no more than 3 mm.

[0045] In some embodiments, in step S1: with 5 mm from the crystal growth edge as the boundary, a negative radial temperature gradient of -5°C / mm to 0.1°C / mm is set within a range less than 5 mm from the crystal growth edge; a continuous positive temperature gradient is set within a range greater than 5 mm from the crystal growth edge, and the continuous positive temperature gradient value is ≤3°C / cm.

[0046] In some embodiments, in step S1 , a negative radial temperature gradient of -3°C / mm to -1°C / mm is set within a range less than 5 mm from the crystal growth edge.

[0047] The radial temperature gradient is calculated as the ratio of the temperature difference (T2-T1) between the temperature T1 of the point closer to the center of the wafer and the temperature T2 of the point farther from the center of the wafer, and the distance d between the two points, in the radial direction radiating outward from the center of the wafer. The positive (positive) temperature gradient ΔT = (T2-T1) / d; otherwise, it is a negative temperature gradient, ΔT = (T1-T2) / d.

[0048] The preparation method used in this application is to drive the growth feature surface to move toward the edge of the crystal and fix it within 5mm of the crystal edge under the setting of step S1 to obtain a high-quality silicon carbide substrate. However, it will be understood by those skilled in the art that the movement trend of the growth feature surface may also be controlled by other methods to obtain the silicon carbide substrate of this application. Therefore, this application only illustrates the preparation method of the high-quality silicon carbide substrate prepared this time. Other methods for controlling the trend of the growth feature surface are not within the scope of this application.

[0049] The radial temperature gradient of crystal growth in step S1 can be set by conventional technical means in the industry, such as adjusting the temperature or pressure in the growth chamber or the thickness of the insulation layer material for overall adjustment. The discontinuous temperature gradient setting can be achieved by structurally improving the crystal growth chamber and optimizing the temperature distribution of the crystal growth interface, thereby achieving controllable adjustment of the temperature gradient, such as placing a material with lower thermal conductivity than the central area at the edge of the crystal growth chamber to reduce the heat loss at the edge, thereby achieving a temperature distribution jump at the crystal growth interface; conversely, if a material with higher thermal conductivity is placed at the edge of the crystal growth or the thickness of the edge insulation layer is reduced, a reverse temperature gradient distribution can be set; in addition, different thermal field structures or new materials can be set in the growth chamber to adjust the temperature distribution, such as setting a TaC coating material with high reflectivity on the graphite ring at the edge of the crystal growth, so that the heat radiation in the growth chamber is concentrated to the edge of the crystal growth, thereby achieving a temperature gradient jump. Through the above more common technical means used in the industry, the scheme can be configured according to actual needs to achieve the purpose of adjusting the temperature gradient in the crystal growth chamber.

[0050] In some embodiments, during the stable crystal growth stage, the temperature in the growth chamber is first raised to above 2200°C at a rate of 10-50°C / min, and the pressure in the growth chamber is simultaneously reduced to 1-100 mbar, and then the crystal growth is maintained for more than 50 hours under the settings of steps S1 and S2.

[0051] In some embodiments, during the stable crystal growth stage, the temperature in the growth chamber is first increased to above 2200°C at a rate of 10-30°C / min, while the pressure is reduced to 5-50 mbar, and then the crystal growth is maintained for more than 50 hours under the settings of steps S1 and S2.

[0052] In this application, the PVT method is used to prepare silicon carbide crystals. The crystal growth uses isostatically pressed graphite as the raw material of the growth chamber (crucible), and SiC powder is used as the raw material for crystal growth. In order to ensure the excellent and stable electrical properties of silicon carbide, in some embodiments of this application, a silicon carbide synthetic powder with a certain purity is used. The total impurity content of the silicon carbide powder is not higher than 1E19cm -3In some embodiments, the total impurity content in the silicon carbide powder is not higher than 1E 17 cm -3 .

[0053] In the present application, when silicon carbide crystals grow, SiC powder is loaded into a graphite crucible chamber and a SiC seed crystal is placed on the top of the growth chamber. The crucible is then sealed and wrapped in a thermal insulation material made of graphite soft felt or hard felt. The crucible is then moved into the crystal growth equipment chamber for crystal growth.

[0054] In some embodiments, before the crystal stable growth stage, a crystal nucleation stage is further included, and the growth process conditions of the crystal nucleation stage include the following steps:

[0055] After the crystal growth chamber is sealed, the growth chamber is evacuated to 10 -3 Pa, after the vacuum stage stabilizes for a period of time, inert gas is introduced to gradually increase the pressure in the growth chamber to 100-1000mbar and then stabilize it. At the same time, nitrogen is introduced into the chamber at 1ml / min-100ml / min.

[0056] In some embodiments, during the crystal nucleation stage, while the pressure in the growth chamber is increased, the temperature in the growth chamber is gradually increased from room temperature to 1600-2100° C. and then kept constant, and the crystal stabilization growth stage is performed after maintaining the constant temperature and pressure for 5-50 hours.

[0057] In some embodiments, during the crystal nucleation stage, the temperature in the growth chamber is kept constant at 1800-2100° C., and the pressure in the growth chamber is kept constant at 300-800 mbar. After maintaining the constant temperature and pressure for 30-50 hours, the crystal stable growth stage is performed.

[0058] During the crystal nucleation stage, the silicon carbide powder sublimates to form a crystal nucleus. Subsequently, during the stable crystal growth stage, the silicon carbide powder can fully sublimate and be transferred to the seed crystal for stable growth, ultimately obtaining a silicon carbide crystal. Since the seed crystal diameter in step S2 is at least 5 mm larger than the target crystal and the substrate diameter, the prepared SiC crystal has an edge processing allowance, and high-quality silicon carbide crystals can be obtained by cutting the edges. For example, the seed crystal diameter is 160 mm and the substrate diameter is 150 mm, or the seed crystal diameter is 210 mm and the substrate diameter is 200 mm. Therefore, it is possible to ensure the smooth preparation of large-size silicon carbide substrates and improve the quality of the prepared silicon carbide substrates.

[0059] Compared with the prior art, the present invention achieves at least one of the following beneficial effects:

[0060] (1) In the present application, the facet region of the SiC crystal with the facet located at the edge is directly fixed at the edge of the crystal during the PVT growth process, and the distance between the edge of the facet region and the outer circumferential end face is no more than 3% of the diameter of the SiC crystal. The facet region is removed during the subsequent processing of the crystal, and a low cutting loss rate is achieved, so that there is no facet region on the entire crystal rod and the wafer and substrate processed therefrom.

[0061] (2) The SiC wafers of the present application have a high degree of uniformity, for example, electrical uniformity (e.g., resistivity uniformity), transmittance uniformity, and defect distribution uniformity. In addition, the SiC wafers of the present application have no visible facet regions.

[0062] (3) The silicon carbide substrate of the present application has high electrical uniformity (for example, resistivity uniformity), high transmittance uniformity and high defect distribution uniformity. When the substrate is cut for use in preparing semiconductor devices, the effective area utilization rate can be improved. Compared with other substrates of the same area, the semiconductor devices prepared therefrom not only have good performance, but also are produced in larger quantities, which can reduce the production cost of semiconductor devices.

[0063] (4) The TDV of the silicon carbide substrate of this application is less than 200cm over the entire area -2 , which eliminates the current problem of low overall defect density but high local density in the substrate, and there are almost no defects such as dislocations and stacking faults, so it is more suitable for large-scale promotion and use.

[0064] (5) The silicon carbide substrate of the present application has no visible growth feature surface, the resistivity difference over the entire area is no more than 2.0 mΩ·cm, and the transmittance difference is no more than 3%. Therefore, it means that the silicon carbide substrate has a high degree of uniformity, and the semiconductor devices prepared using the silicon carbide substrate have higher yield, performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0066] FIG1 shows an exemplary embodiment of a schematic structural diagram of a silicon carbide substrate containing facets visible to the naked eye according to the present invention;

[0067] FIG2 shows an exemplary embodiment of a schematic diagram of a facet growth process of the present application;

[0068] FIG3 shows an exemplary embodiment of a schematic diagram of a SiC crystal structure with facets located at the edge of the present application;

[0069] FIG4 shows a diagram of a light transmittance test method;

[0070] FIG5 shows a resistivity mapping diagram of a silicon carbide substrate according to Example 1 of the present application;

[0071] FIG6 shows a resistivity mapping diagram of a silicon carbide substrate according to Example 2 of the present application;

[0072] FIG7 shows a resistivity mapping diagram of a silicon carbide substrate according to Example 3 of the present application;

[0073] FIG8 shows a resistivity mapping diagram of a silicon carbide substrate according to Example 4 of the present application;

[0074] FIG9 shows a resistivity mapping diagram of a silicon carbide substrate in Comparative Example 1 of the present application;

[0075] FIG10 shows a resistivity mapping diagram of a silicon carbide substrate in Comparative Example 1 of the present application;

[0076] FIG11 shows a resistivity mapping diagram of a silicon carbide substrate in Comparative Example 1 of the present application;

[0077] FIG12 shows a resistivity mapping diagram of a silicon carbide substrate in Comparative Example 1 of the present application;

[0078] FIG13 is a comparison chart of the light transmittance of the silicon carbide substrate of Example 2 of the present application and the silicon carbide substrate of Comparative Example 1;

[0079] FIG14 shows a curve diagram showing a change in light transmittance of a silicon carbide substrate according to Example 3 of the present application;

[0080] FIG15 shows a schematic diagram of the structure of a silicon carbide substrate without growth feature surfaces according to the present application. DETAILED DESCRIPTION

[0081] In order to more clearly understand the above-mentioned objectives, features and advantages of the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features therein can be combined with each other in the absence of conflict.

[0082] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present application is not limited to the specific embodiments disclosed below.

[0083] Currently, existing silicon carbide substrates or silicon carbide wafers have growth feature surfaces, and the resistivity at the growth feature surfaces is too low, resulting in uneven resistivity distribution, uneven transmittance distribution, and uneven carrier concentration change rate across the entire area of ​​the silicon carbide substrate. This may lead to defects such as dislocations and stacking faults in this area, and may also cause problems such as stacking fault expansion during subsequent use of the device. To address the above problems, the present application provides a high-quality silicon carbide substrate with no visible growth feature surfaces across the entire area of ​​the silicon carbide substrate, and highly uniform resistivity, doping concentration, transmittance, and carrier concentration across the entire area of ​​the silicon carbide substrate.

[0084] In the process of preparing silicon carbide crystals in the following Examples 1-5, the growth feature surface can be locked at the edge of the silicon carbide crystal. As the crystal edge is processed, a silicon carbide substrate or silicon carbide wafer without a growth feature surface is obtained. Due to the disappearance of the inherent structural property of the growth feature surface, the number of defects in the silicon carbide substrate or silicon carbide wafer itself is reduced and aggregation will not occur. At the same time, the aggregation of elements in the doping process can be avoided, that is, the existence of high-doping areas is avoided, thereby improving the doping uniformity, light transmittance uniformity and resistivity uniformity of the silicon carbide substrate or silicon carbide wafer with a structure without a growth feature surface.

[0085] Example 1

[0086] This embodiment relates to a method for preparing a 6-inch high-quality silicon carbide substrate, which specifically includes the following steps:

[0087] (1) Crystal nucleation stage

[0088] The silicon carbide powder and seed crystal were placed in the crucible, and then the growth chamber was sealed and evacuated to 10 -3 After stabilizing the vacuum for a period of time, inert gas was introduced to gradually increase the pressure in the growth chamber to 100 mbar. Simultaneously, nitrogen was introduced into the chamber at a rate of 100 ml / min. During the crystal nucleation phase, while the pressure in the growth chamber increased, the furnace temperature was gradually raised from room temperature to 1600°C using the power setting and maintained for 50 hours.

[0089] (2) Stable crystal growth stage

[0090] After the crystal nucleation stage is completed, the temperature is raised to 2200°C at a rate of 20°C / min, and the pressure in the growth chamber is reduced to 50 mbar by adjusting the pressure controller and maintained for 50 hours.

[0091] S1: With 5 mm from the crystal growth edge as the boundary, a negative radial temperature gradient of -0.1 °C / mm is set within a range less than 5 mm from the crystal growth edge, and a continuous positive temperature gradient of 1 °C / cm is set within a range greater than 5 mm from the crystal growth edge;

[0092] S2: Using a seed crystal larger than the target silicon carbide crystal diameter for crystal growth, the seed crystal diameter is 5 mm larger than the target crystal diameter. The target crystal is cut, ground, polished, and processed to obtain the target silicon carbide substrate.

[0093] Example 2

[0094] This embodiment relates to a method for preparing a 6-inch high-quality silicon carbide substrate, which specifically includes the following steps:

[0095] (1) Crystal nucleation stage

[0096] The silicon carbide powder and seed crystal were placed in the crucible, and then the growth chamber was sealed and evacuated to 10 -3 After stabilizing the vacuum for a period of time, inert gas was introduced to gradually increase the pressure in the growth chamber to 300 mbar. Simultaneously, nitrogen was introduced at a rate of 40 ml / min. During the crystal nucleation phase, while the pressure in the growth chamber increased, the furnace temperature was gradually raised from room temperature to 1800°C using the power setting and maintained for 30 hours.

[0097] (2) Stable crystal growth stage

[0098] After the crystal nucleation stage, the temperature was raised to 2400°C at a rate of 30°C / min, and the pressure in the growth chamber was reduced to 10 mbar by adjusting the pressure controller and maintained for 70 hours.

[0099] S1: With 4.5 mm from the crystal growth edge as the boundary, a negative radial temperature gradient of -5 °C / mm is set within a range less than 4.5 mm from the crystal growth edge, and a continuous positive temperature gradient of 1 °C / cm is set within a range greater than 4.5 mm from the crystal growth edge;

[0100] S2: Using a seed crystal larger than the target silicon carbide crystal diameter for crystal growth, the seed crystal diameter is 6 mm larger than the target crystal diameter. The target crystal is cut, ground, polished, and processed to obtain the target silicon carbide substrate.

[0101] Example 3

[0102] This embodiment relates to a method for preparing a 6-inch high-quality silicon carbide substrate, which specifically includes the following steps:

[0103] (1) Crystal nucleation stage

[0104] The silicon carbide powder and seed crystal were placed in the crucible, and then the growth chamber was sealed and evacuated to 10 -3 After stabilizing the vacuum for a period of time, inert gas was introduced, gradually raising the pressure in the growth chamber to 500 mbar. Simultaneously, nitrogen was introduced at a rate of 40 ml / min. During the crystal nucleation phase, while the pressure in the growth chamber increased, the furnace temperature was gradually raised from room temperature to 2100°C using the power setting and maintained for 50 hours.

[0105] (2) Stable crystal growth stage

[0106] After the crystal nucleation stage, the temperature was raised to 2500°C at a rate of 10°C / min, and the pressure in the growth chamber was reduced to 20 mbar by adjusting the pressure controller and maintained for 70 hours.

[0107] S1: With 3.5 mm from the crystal growth edge as the boundary, a negative radial temperature gradient of -3 ° C / mm is set within the range less than 3.5 mm from the crystal growth edge, and a continuous positive temperature gradient of 3 ° C / cm is set within the range greater than 3.5 mm from the crystal growth edge;

[0108] S2: Using a seed crystal larger than the target silicon carbide crystal diameter for crystal growth, the seed crystal diameter is 6 mm larger than the target crystal diameter. The target crystal is cut, ground, polished, and processed to obtain the target silicon carbide substrate.

[0109] Example 4

[0110] This embodiment relates to a method for preparing a 6-inch high-quality silicon carbide substrate, which specifically includes the following steps:

[0111] (1) Crystal nucleation stage

[0112] The silicon carbide powder and seed crystal were placed in the crucible, and then the growth chamber was sealed and evacuated to 10 -3 Pa, and after a period of stabilization in the vacuum stage, inert gas was introduced to gradually increase the pressure in the growth chamber to 300 mbar. Simultaneously, nitrogen was introduced into the chamber at 30 ml / min, and phosphorus was doped. During the crystal nucleation stage, while the pressure in the growth chamber increased, the furnace temperature was gradually increased from room temperature to 2000°C using the power setting and maintained for 50 hours.

[0113] (2) Stable crystal growth stage

[0114] After the crystal nucleation stage, the temperature was raised to 2600°C at a rate of 40°C / min, while the pressure in the growth chamber was reduced to 20 mbar by adjusting the pressure controller and maintained for 80 hours.

[0115] S1: With a distance of 3 mm from the crystal growth edge as the boundary, a negative radial temperature gradient of -4°C / mm is set within a range less than 3 mm from the crystal growth edge, and a continuous positive temperature gradient of 0.5°C / cm is set within a range greater than 3 mm from the crystal growth edge;

[0116] S2: Using a seed crystal larger than the target silicon carbide crystal diameter for crystal growth, the seed crystal diameter is 8 mm larger than the target crystal diameter. The target crystal is cut, ground, polished, and processed to obtain the target silicon carbide substrate.

[0117] Example 5

[0118] The difference between this embodiment and embodiment 2 is that in step S1, a negative radial temperature gradient of -1°C / mm is set within a range less than 4.5 mm from the crystal growth edge, and an 8-inch silicon carbide substrate is prepared in this embodiment. The remaining steps are the same as in embodiment 2.

[0119] Comparative Example 1

[0120] The difference between this comparative example and Example 2 is that in step S1, a continuous positive temperature gradient is set from the center to the edge of the crystal, and the continuous positive temperature gradient is 3°C / cm. The remaining steps are the same as in Example 2.

[0121] Comparative Example 2

[0122] The difference between this comparative example and Example 2 is that in step S1, a negative radial temperature gradient of -6°C / mm is set within a range less than 4.5 mm from the crystal growth edge, and an 8-inch silicon carbide substrate is prepared in this example. The remaining steps are the same as in Example 2.

[0123] Experimental Example 1

[0124] The SiC crystal prepared by the above method has a facet located at the edge, and the position of the facet region in the crystal is tested and shown in Table 1. The volume of the facet region can be calculated by calculus or modeling.

[0125] Table 1 Position test table of small facet area in crystal

[0126] Among them, referring to Table 1, it can be seen that the distance between the small face area and the edge of the crystal in the SiC crystal of the present application is controlled within 5mm. In the PVT production process of the present application, the small face area is directly controlled to be away from the outer circumferential end face of the crystal, and the small face is driven to move to the outer area of ​​the crystal target diameter. In the subsequent crystal processing process, the small face area can be removed at a lower cutting rate, thereby obtaining a SiC crystal with fewer defects. In Comparative Examples 1 and 2, the small face area is in the middle position, within the range of the crystal target diameter, resulting in a lower yield, performance and reliability of the device end obtained by subsequent processing.

[0127] The SiC crystal with the facet located at the edge obtained in Example was processed to remove the facet area, and then directly cut to obtain a SiC wafer. The comparative example 1 was cut to form a silicon carbide wafer. The performance test of the SiC wafer is shown in Table 2.

[0128] The in-plane resistivity difference is “the maximum in-plane resistivity - the minimum in-plane resistivity”; the transmittance difference is “the maximum transmittance - the minimum transmittance”.

[0129] Table 2 SiC wafer performance test table

[0130] As shown in Table 2, it can be seen that the SiC wafer of the present application has no small facets visible to the naked eye, the resistivity within the SiC wafer surface is uniform, there is no abnormally low-resistance area, and the transmittance and TDV are highly uniform.

[0131] On the basis of Examples 1-4, the SiC crystals prepared in Examples 1-4 were directly cut to obtain SiC wafers with small faces at the edges, and the performance of the obtained silicon carbide wafers containing small faces was tested, as shown in Table 3.

[0132] Table 3 Performance test table of silicon carbide wafers with small facets

[0133] Referring to Table 3, it can be seen that the in-plane resistivity difference of the small-facet area is more than 4 times the in-plane resistivity difference of the non-small-facet area; the transmittance difference of the small-facet area is more than 5 times the transmittance difference of the non-small-facet area; and the TDV of the small-facet area is more than 6 times the TDV of the non-small-facet area.

[0134] In the present application, SiC crystals with only small faces at the edge are directly grown by the PVT method without subsequent processing. The small facet area is fixed to the outer circumferential end face of the SiC crystal, and the small facet area is removed during the subsequent processing of the crystal. With a low cutting loss rate, the entire crystal rod and the wafers and substrates processed therefrom are free of small facet areas, thereby reducing the production cost of the silicon carbide crystal and ensuring that silicon carbide wafers with few defects and high uniformity are obtained.

[0135] Experimental Example 2

[0136] The above examples and comparative examples all used the PVT crystal growth method to prepare silicon carbide crystals. The same edge cutting (removal of 5 mm), radial cutting, grinding, and polishing processes were used in both examples and comparative examples to produce silicon carbide substrates. The performance of the resulting silicon carbide substrate samples was tested, and the results are shown in Table 4. The specific testing methods are as follows:

[0137] The resistivity was measured using a Semilab WT-2000 low-resistance tester at 73 points evenly and symmetrically distributed within the silicon carbide substrate. In this application, a mapping diagram was used to characterize the resistivity distribution of the substrate.

[0138] The transmittance was measured using a haze meter CS-700 at several points along the diameter of the substrate, passing through the center and the growth feature surface area. The test method is shown in Figure 4.

[0139] Silicon carbide substrates with no growth feature surface of different sizes and doping concentrations were prepared by the above method. The performance test results of the silicon carbide substrates with no growth feature surface of Examples 6-10 and Comparative Example 2 are shown in Table 4.

[0140] The in-plane resistivity difference is “the maximum in-plane resistivity - the minimum in-plane resistivity”; the transmittance difference is “the maximum transmittance - the minimum transmittance”.

[0141] Table 4 Silicon carbide substrate performance test table

[0142] The present application sets a discontinuous temperature gradient distribution in the radial direction of the crystal growth surface to ensure that the edge of the crystal has sufficient lateral growth driving force and the edge of the crystal has the ability to continue to expand and grow. The crystals of the embodiment and the comparative example undergo the same conventional edge cutting, radial cutting, grinding, and polishing processes without changing the quality of the substrate. Therefore, according to the data in Table 1, it can be seen that the preparation method of the present application can control the movement trend of the growth feature surface and lock it at the edge of the crystal. The movement trend control refers to Figure 2; and referring to Figure 3, the growth feature surface at the edge of the crystal can be removed as the edge of the crystal is cut. Therefore, the substrates of Examples 1-5 do not have a growth feature surface, and the existing positive temperature gradient in Comparative Example 1 and the edge temperature gradient of -6°C / mm in Comparative Example 2 cannot make the growth feature surface move to the edge and be fixed at the edge.

[0143] The silicon carbide substrates of Comparative Examples 1 and 2 both contain growth feature surfaces visible to the naked eye, and their structures are shown in Figure 1. It can be seen that the silicon carbide substrates without growth feature surfaces do not contain any black spots similar to "birthmarks" over the entire area. The silicon carbide substrates prepared in Examples 1-5 do not contain growth feature surfaces visible to the naked eye, and their structures are shown in Figure 15. It can be seen from the above examples and comparative examples and Figures 1 and 15 that silicon carbide substrates without growth feature surfaces are prepared by the preparation method of the present application. Combined with the other parameters disclosed in Table 4, it can be seen that due to the absence of the growth feature surface structure, the in-plane resistivity difference of the silicon carbide substrate is no more than 2.0 mΩ·cm, the transmittance difference is no more than 3%, and the TDV is less than 200 cm -2 , indicating that the overall performance of the silicon carbide substrate has been improved. In contrast, the in-plane resistivity difference of the silicon carbide substrate containing the growth feature surface in Comparative Examples 1 and 2 is greater than 5 mΩ·cm, the transmittance difference is greater than 10%, and the TDV is greater than 400 cm -2 , which means the overall performance of the silicon carbide substrate is poor.

[0144] Figure 5 shows a resistivity mapping diagram of the silicon carbide substrate in Example 1 of the present application, Figure 6 shows a resistivity mapping diagram of the silicon carbide substrate in Example 2 of the present application, Figure 7 shows a resistivity mapping diagram of the silicon carbide substrate in Example 3 of the present application, and Figure 8 shows a resistivity mapping diagram of the silicon carbide substrate in Example 4 of the present application. Referring to Figures 5-8, the horizontal axis represents the diameter of the silicon carbide substrate, the center point of the silicon carbide substrate is the coordinate 00, the device test area in the mapping diagram is (-60mm, 60mm), the vertical axis represents the resistivity, and the color change represents the resistivity distribution. It can be seen that the resistivity distribution within the surface of the silicon carbide substrate of the present application is uniform, there is no abnormally low-resistance area, and the resistivity in-plane difference is less than 3mΩ·cm; in some embodiments, the resistivity in-plane difference is less than 1mΩ·cm.

[0145] Figures 9, 10, 11 and 12 respectively show the resistivity mapping diagrams of the silicon carbide substrate of comparative example 1 of the present application. The inventors conducted four sets of repeated experiments on comparative example 1. Referring to Figures 9, 10, 11 and 12, the center point of the silicon carbide substrate is coordinate 00, the horizontal axis represents the test silicon carbide substrate area of ​​(-60mm, 60mm), and the vertical axis represents the resistivity. It can be seen that due to the existence of the growth feature surface, there is an obvious low-resistance abnormal area in the resistivity distribution, and the resistivity in-plane difference is usually greater than 5mΩ·cm.

[0146] Figure 13 shows a comparison of the transmittance of the silicon carbide substrate of Example 2 of the present application and the silicon carbide substrate of Comparative Example 1. In Figure 13, the horizontal axis represents the number of test points and the vertical axis represents the transmittance. The circle curve is the transmittance curve of the silicon carbide substrate of Example 2, and the square curve is the transmittance curve of the silicon carbide substrate of Comparative Example 1. As can be seen from Figure 13, the visible light transmittance of Comparative Example 1 in the growth feature surface area drops sharply. This is because the doping concentration and carrier concentration in the growth feature surface area are much higher than those in other areas, resulting in the absorption of part of the visible light band. The silicon carbide substrate prepared in Example 2 of the present application eliminates the problem of excessive doping concentration and carrier concentration at the growth feature surface, and the impurity and carrier concentrations in the substrate surface are evenly distributed, and the uniformity and consistency of transmittance in the visible light surface are greatly improved.

[0147] FIG14 shows a curve diagram of light transmittance variation of the silicon carbide substrate in Example 3 of the present application. The horizontal axis represents different test coordinate points of the silicon carbide substrate, and the vertical axis represents light transmittance. It can be seen from FIG14 that the light transmittance distribution within the surface is uniform.

[0148] Since the growth feature surface is eliminated in this application, the resistivity uniformity and transmittance uniformity inside the substrate are greatly improved. There are no inclusions or accumulations of defects such as dislocations and micropipes at the growth feature surface that exist in normal substrates inside the substrate, so the substrate quality and yield are greatly improved; the performance and reliability of the substrate in subsequent device processes and use will be greatly improved.

[0149] According to the above analysis, the silicon carbide substrate prepared as shown in Examples 1-5 is processed in a way that breaks through the conventional continuous positive radial temperature distribution design. A negative radial temperature gradient is innovatively designed at the crystal growth edge to drive the growth characteristic surface to change its movement trend, thereby locking the growth characteristic surface in the crystal edge area. Combined with the seed crystal diameter being at least 5 mm larger than the target diameter, the growth characteristic surface is finally fixed within 5 mm from the crystal edge. Subsequently, after the crystal is cut, ground, polished, and other processes, a silicon carbide substrate without a growth characteristic surface can be obtained.

[0150] Since the elimination of the growth feature surface is completed during the crystal growth stage, the subsequent substrate processing technology will not affect the above-mentioned electrical properties. Therefore, this application does not impose any special restrictions on the substrate processing method, and it is a routine operation for those skilled in the art. Such a growth scheme is simple and easy to implement, and can ensure the stress and defect control under a continuous and small temperature gradient in the center area of ​​the crystal. Through the above innovation, the growth feature surface can be fixed at the edge of the crystal and removed during the subsequent crystal processing process, so that there is no growth feature surface on the entire crystal rod and the substrate processed therefrom, thereby achieving the purpose of eliminating the defect aggregation area and ensuring the device end yield and reliability.

[0151] However, the present application discloses methods for preparing silicon carbide substrates without growth feature surfaces, including but not limited to these methods. Those skilled in the art may also prepare the silicon carbide substrate using other methods capable of controlling the characteristic growth surface. Therefore, the preparation methods disclosed in this application are merely illustrative and do not constitute a limitation on the performance of the silicon carbide substrate itself. Those skilled in the art may also develop new preparation methods to obtain the silicon carbide substrate of this application through existing technical reserves and creative work. Other preparation methods are beyond the scope of this application and will not be further studied.

[0152] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A SiC crystal with a facet located at an edge, wherein: The SiC crystal contains a small face region and a non-small face region; the small face region is located at the outer circumferential end face of the SiC crystal, the distance between the edge of the small face region away from the outer circumferential end face and the outer circumferential end face does not exceed 3% of the diameter of the SiC crystal, and the SiC crystal is directly grown by the PVT method without subsequent processing.

2. The SiC crystal according to claim 1, wherein: The maximum cross-sectional area of ​​the facet region accounts for less than 10% of the cross-sectional area of ​​the crystal along the diameter direction; and / or the volume of the small face region accounts for less than 2% of the total crystal volume.

3. The SiC crystal according to claim 2, wherein: The maximum cross-sectional area of ​​the facet region accounts for less than 5% of the cross-sectional area of ​​the crystal along the diameter direction; and / or the volume of the small face region accounts for less than 0.6% of the total crystal volume.

4. The SiC crystal according to claim 1, wherein: The in-plane resistivity difference of the area containing facets is more than 5 times that of the area without facets; and / or the transmittance difference of the faceted area is more than 5 times the transmittance difference of the non-faceted area; The TDV of the and / or facet area is more than 6 times that of the non-facet area.

5. The SiC crystal according to claim 4, wherein: The in-plane resistivity difference of the area containing facets is more than 8 times that of the area without facets; and / or the transmittance difference of the faceted area is more than 14 times the transmittance difference of the non-faceted area; The TDV of the and / or facet area is more than 10 times that of the non-facet area.

6. A facetless silicon carbide ingot, wherein: The facet-free silicon carbide crystal rod is obtained by removing the facet region from the SiC crystal with the facet located at the edge as claimed in any one of claims 1 to 5.

7. A high-quality silicon carbide substrate, wherein: The high-quality silicon carbide substrate is obtained by processing a SiC crystal with a small face located at the edge according to any one of claims 1 to 5, the silicon carbide substrate is conductive, and does not contain any one or more of the growth feature surface, high doping area and defect aggregation area within its entire area; the silicon carbide substrate is prepared by the PVT method.

8. The high-quality silicon carbide substrate according to claim 7, wherein: The silicon carbide substrate is N-type doped, and the N-type element doping concentration is greater than 1e 18 cm -3 , the properties of the silicon carbide substrate over the entire area satisfy the following conditions; a. The in-plane resistivity difference is not higher than 2.0mΩ·cm; b. The transmittance difference is not higher than 3%.

9. The high-quality silicon carbide substrate according to claim 8, wherein: The in-plane resistivity difference is no higher than 1.0 mΩ·cm.

10. The high-quality silicon carbide substrate according to claim 9, wherein: The doping concentration is 2e 18 ~7e 18 cm -3 , the in-plane resistivity difference is 0.62 to 0.86 mΩ·cm.

11. The high-quality silicon carbide substrate according to claim 8, wherein: The transmittance difference is 0.5% to 1.6%.

12. The high-quality silicon carbide substrate according to claim 8, wherein: The N-type element doping is N2 doping, the in-plane resistivity difference is 0.62-0.86 mΩ·cm, and the transmittance difference is 0.5%-1.6%.

13. The high-quality silicon carbide substrate according to claim 8, wherein: The silicon carbide substrate TDV is less than 200cm -2 .

14. The high-quality silicon carbide substrate according to claim 13, wherein: The silicon carbide substrate TDV is less than 100cm -2 .

15. The high-quality silicon carbide substrate according to claim 7, wherein: The size of the silicon carbide substrate is 6 inches, 8 inches, 10 inches or 12 inches.

16. A semiconductor device, wherein: The semiconductor device comprises the high-quality silicon carbide substrate according to claim 7.

Images