Inductor and preparation method therefor

Abstract

Provided in the embodiments of the present disclosure are an inductor and a preparation method therefor. The inductor comprises a base, a first outer electrode and a second outer electrode. The base comprises a plurality of base layers which are sequentially stacked, each base layer comprising a first insulating layer, an electrode layer and a second insulating layer, wherein the electrode layer is provided on the first insulating layer, and electrode layers of the base layers are electrically connected in sequence to form an inner electrode; and the second insulating layer is provided on the first insulating layer and is located on the same surface of the first insulating layer as the electrode layer, and the second insulating layer has gaps distributed on the peripheral side of the electrode layer, the distance from the gaps to the peripheral side surface of the electrode layer being d1, and d1≥10 μm, and the gaps each being filled with a low-dielectric-constant medium. The first outer electrode and the second outer electrode are respectively provided at two ends of the base, and both the first outer electrode and the second outer electrode are electrically connected to the inner electrode.

Description

Inductor and method for manufacturing the same

[0001] Related cross-references

[0002] This disclosure claims priority to Chinese patent application number 2023112679845 filed with the Patent Office of China on September 26, 2023, with the invention name “Inductor and Method for Making the Same”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an inductor and a method for making the same. Background Art

[0004] In the related art, inductors usually have two types of structures: horizontal and vertical. Among them, the current of the inductor with a horizontal structure is larger, but the self-resonant frequency is lower, while the current of the inductor with a vertical structure is smaller, and the self-resonant frequency is higher. In order to obtain an inductor that takes into account both large current and high self-resonant frequency, the self-resonant frequency is increased by using ferrite materials with low magnetic permeability in the inductor with a horizontal structure. However, this brings about the problem of narrow impedance bandwidth and inability to take into account both low-frequency and high-frequency impedance at the same time. The inductor with a vertical structure can increase the current by increasing the number of electrode turns, but it brings about the problems of complex structure and low production yield.

[0005] That is, it is difficult for existing inductors to simultaneously take into account large current and high self-resonant frequency while avoiding the problems of narrow impedance bandwidth, complex structure, and low manufacturing yield.

[0006] Summary of the Invention

[0007] (1) Technical issues to be resolved

[0008] In the prior art, it is difficult for inductors to simultaneously handle large currents and high self-resonant frequencies while avoiding problems such as narrow impedance bandwidth, complex structure, and low manufacturing yield.

[0009] (2) Technical solution

[0010] According to various embodiments of the present disclosure, an inductor and a method for manufacturing the same are provided.

[0011] An inductor, comprising:

[0012] A substrate, the substrate comprising a plurality of sequentially stacked base layers, each of the base layers comprising a first insulating layer, an electrode layer, and a second insulating layer, the electrode layer being disposed on the first insulating layer, the electrode layers of each base layer being sequentially electrically connected to form an internal electrode, the second insulating layer being disposed on the first insulating layer and being located on the same surface of the first insulating layer as the electrode layer, the second insulating layer having a gap, the gap being distributed around the electrode layer, and the distance from the gap to the peripheral side surface of the electrode layer being d1, d1 being ≥ 10 μm, and the gap being filled with a low-dielectric-constant dielectric;

[0013] a first external electrode, the first external electrode being provided at one end of the substrate and electrically connected to the internal electrode; and

[0014] A second external electrode is provided at an end of the substrate facing away from the first external electrode, and the second external electrode is electrically connected to the internal electrode.

[0015] A method for preparing an inductor, the method comprising:

[0016] providing a plurality of first insulating layers;

[0017] An electrode layer, a second insulating layer, and a low-dielectric constant medium are formed on one side of each of the first insulating layers, wherein the low-dielectric constant medium is distributed around the electrode layer, and a distance d1 from the low-dielectric constant medium to the side surface of the electrode layer is d1, and d1 is ≥ 10 μm;

[0018] The plurality of first insulating layers formed with the electrode layer, the second insulating layer and the low dielectric constant medium are sequentially stacked to form a substrate, and the electrode layers formed on the first insulating layers are sequentially electrically connected to form an internal electrode;

[0019] A first outer electrode and a second outer electrode are provided. The first outer electrode and the second outer electrode are respectively arranged on two opposite sides of the substrate. The first outer electrode is electrically connected to the inner electrode, and the second outer electrode is electrically connected to the inner electrode.

[0020] Other features and advantages of the present disclosure will be described in the following description and, in part, will become apparent from the description or be learned through practice of the present disclosure. The objectives and other advantages of the present disclosure are realized and obtained by the structures particularly pointed out in the description, claims, and drawings. Details of one or more embodiments of the present disclosure are set forth in the following drawings and description.

[0021] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, optional embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0023] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] FIG1 is a schematic structural diagram of an inductor disclosed in one or more embodiments of the present disclosure;

[0025] FIG2 is a schematic diagram of an exploded structure of an inductor disclosed in one or more embodiments of the present disclosure;

[0026] FIG3 is a schematic structural diagram of a base layer disclosed in one or more embodiments of the present disclosure;

[0027] FIG4 is a comparison diagram of impedance spectra of comparative examples and embodiments disclosed in one or more embodiments of the present disclosure;

[0028] FIG5 is a schematic structural diagram of a substrate according to one or more embodiments of the present disclosure;

[0029] FIG6 is a schematic diagram of the AA cross-sectional structure in FIG3 ;

[0030] FIG7 is a schematic flow chart of a method for preparing an inductor according to one or more embodiments of the present disclosure;

[0031] FIG8 is a schematic structural diagram of a first insulating layer disclosed in one or more embodiments of the present disclosure;

[0032] 9 is a schematic structural diagram of a first insulating layer having an electrode layer, a second insulating layer, and a low-k dielectric according to one or more embodiments of the present disclosure;

[0033] FIG10 is a schematic structural diagram of a first insulating layer having an electrode layer and a second insulating layer formed thereon according to one or more embodiments of the present disclosure;

[0034] FIG11 is a schematic structural diagram of a first insulating layer formed with a low dielectric constant medium according to one or more embodiments of the present disclosure;

[0035] FIG12 is a schematic structural diagram of a substrate according to one or more embodiments of the present disclosure;

[0036] FIG13 is a schematic flow chart of another method for preparing an inductor disclosed in one or more embodiments of the present disclosure;

[0037] FIG14 is a schematic structural diagram of a first insulating layer having an electrode layer, a second insulating layer, and a first dielectric layer according to one or more embodiments of the present disclosure;

[0038] FIG15 is a schematic structural diagram of a substrate (part of the base layer omitted) disclosed in one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0041] The terms "first" and "second" in the specification and claims of this disclosure are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first camera" and "second camera" are used to distinguish different cameras, rather than to describe a specific order of cameras.

[0042] In the embodiments of the present disclosure, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present disclosure should not be interpreted as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner. In addition, in the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" refers to two or more.

[0043] Please refer to Figures 1 to 3, which are schematic diagrams of the structure of an inductor 100 provided in one or more embodiments of the present disclosure. The inductor 100 includes a substrate 10, a first external electrode 20, and a second external electrode 30. The substrate 10 includes a plurality of base layers 10a stacked in sequence. Each base layer 10a includes a first insulating layer 11, an electrode layer 12, and a second insulating layer 13. The electrode layer 12 is provided on the first insulating layer 11. The electrode layers 12 of each base layer 10a are electrically connected in sequence to form an internal electrode 12a. The second insulating layer 13 is provided on the first insulating layer 11 and is connected to the second insulating layer 13. The electrode layer 12 is located on the same surface of the first insulating layer 11, and the second insulating layer 13 has a gap 13a. The gap 13a is distributed on the peripheral side of the electrode layer 12, and the distance from the gap 13a to the peripheral side surface 121 of the electrode layer 12 is d1, d1 ≥ 10 μm. The gap 13a is filled with a low dielectric constant medium 14, and the first external electrode 20 is provided on one side of the substrate 10. The first external electrode 20 is electrically connected to the internal electrode 12a. The second external electrode 30 is provided on the side of the substrate 10 away from the first external electrode 20, and the second external electrode 30 is electrically connected to the internal electrode 12a.

[0044] As shown in FIG3 , in order to facilitate the distinction between the electrode layer 12 , the second insulating layer 13 and the low dielectric constant medium 14 , the low dielectric constant medium 14 is filled with cross-section lines in FIG3 . Other views are only for better illustrating the low dielectric constant medium 14 , which will not be described in detail later.

[0045] In this embodiment, electrode layers 12 and second insulating layers 13 are formed on the first insulating layer 11 of the base layer 10a. Multiple base layers 10a are stacked sequentially, so that the electrode layers 12 of each base layer 10a are electrically connected to form an inner electrode 12a. The inner electrode 12a is electrically connected to the first and second outer electrodes 20 and 30, respectively, located at opposite ends of the substrate 10, achieving electrical conductivity. In other words, the inductor 100 adopts a horizontal structure, which offers high current capacity, a relatively simple structure, and a high manufacturing yield. Furthermore, the gaps 13a in the second insulating layer 13 are filled with a low-dielectric-constant dielectric 14, reducing the parasitic capacitance between the inner electrode 12a and the first and second outer electrodes 20 and 30, thereby increasing the self-resonant frequency (SRF) and bandwidth of the inductor 100. In other words, the inductor 100 of this embodiment can simultaneously handle high current and a high SRF, while also offering a wide impedance bandwidth, a relatively simple structure, and a high manufacturing yield.

[0046] In addition, the distance d1 from the gap 13a of the second insulating layer 13 to the peripheral side surface 121 of the electrode layer 12 is ≥10μm. Part of the second insulating layer 13 can be used to separate the electrode layer 12 and the gap 13a, thereby preventing foreign matter (such as water vapor or plating solution in the preparation process) from entering the gap 13a and affecting the performance of the electrode layer 12. The reliability of the inductor 100 is relatively high.

[0047] Optionally, as shown in FIG3 , the distance d1 from the gap 13a of the second insulating layer 13 to the peripheral side surface 121 of the electrode layer 12 may be 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, etc., which is not specifically limited in this embodiment.

[0048] One of the inventive aspects of this embodiment is that the second insulating layer 13 has gaps 13a distributed around the electrode layer 12 and filled with a low-dielectric-constant dielectric 14. This is one of the differences between this embodiment and the conventional horizontal inductor 100. Using the conventional horizontal inductor 100 as a comparative example, various parameters of the inductor 100 were tested. The experimental data are shown in Table 1 and Figure 4 below (Figure 4 is a comparison of the impedance spectra of the comparative example and the embodiment, with the horizontal axis representing frequency and the vertical axis representing impedance).

[0049] Table 1 Comparison of parameters between comparative examples and examples

[0050] Table 1 and Figure 4 show that, while maintaining the same dimensions, the inductor 100 of the embodiment exhibits significantly improved self-resonant frequency and bandwidth compared to the comparative example. With the exception of a slight decrease in low-frequency impedance, all other parameters remain identical, and the high-frequency impedance is also improved. In other words, while employing a conventional horizontal structure, the inductor 100 of the embodiment maintains a high current flow, a relatively simple structure, and a high manufacturing yield. By employing a method of filling the inductor 100 with a low-k dielectric 14, the inductor 100 of the embodiment achieves a significant increase in self-resonant frequency and bandwidth without degrading other performance characteristics.

[0051] Optionally, as shown in Figures 3 and 5 , the electrode layer 12 is configured in a coiled shape extending around a straight line along the stacking direction x of the plurality of base layers 10a. The circumferential side surfaces 121 of the electrode layer 12 include opposing inner side surfaces 121a and outer side surfaces 121b, with the inner side surface 121a being disposed toward the straight line along the stacking direction x. A gap 13a is distributed along the inner circumference of the electrode layer 12, with the distance d1 from the gap 13a to the inner side surface 121a of the electrode layer 12 being provided. Alternatively, a gap 13a is distributed along the outer circumference of the electrode layer 12, with the distance d1 from the gap 13a to the outer side surface 121b of the electrode layer 12 being provided. Thus, this embodiment provides three distribution patterns for the gaps 13a: distribution along the inner circumference of the electrode layer 12, distribution along the outer circumference of the electrode layer 12, and distribution along both the inner and outer circumferences of the electrode layer 12. Depending on the distribution pattern, the self-resonant frequency and bandwidth of the inductor 100 are increased to varying degrees. This distribution pattern can be selected based on practical circumstances and is not specifically limited in this embodiment.

[0052] Exemplarily, the electrode layer 12 is configured in a coiled shape extending around a straight line in the stacking direction x of the base layer 10a. The gap 13a extends along the extension direction of the electrode layer 12, and the extension length of the gap 13a is greater than or equal to 10 percent of the extension length of the electrode layer 12. If the extension length of the gap 13a is less than 10 percent of the extension length of the electrode layer 12, the extension length of the gap 13a is smaller, the overall volume of the gap 13a is smaller, and the proportion of the gap 13a is lower. The volume of the low-permittivity dielectric 14 that can be filled by the gap 13a is smaller, and the improvement in the self-resonant frequency and bandwidth of the inductor 100 is smaller. Therefore, the extension length of the gap 13a can be greater than or equal to 10 percent of the extension length of the electrode layer 12, the overall volume of the gap 13a is larger and the proportion of the gap 13a is higher. The volume of the low-permittivity dielectric 14 that can be filled by the gap 13a is larger, and the improvement in the self-resonant frequency and bandwidth of the inductor 100 is greater. The extension length of the gap 13a can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, etc. of the extension length of the electrode layer 12, which is not specifically limited in this embodiment.

[0053] In some embodiments, the electrode layer 12 is configured in a coiled shape extending around a straight line in the stacking direction x of the base layer 10a, and the gap 13a extends from one end of the electrode layer 12 to the other end of the electrode layer 12 along the extension direction of the electrode layer 12. In this way, the extension length of the gap 13a is substantially equal to the extension length of the electrode layer 12, and the gap 13a extends continuously and uninterruptedly. While other dimensions of the gap 13a remain the same, the volume of the gap 13a can be maximized, and the volume of the low-dielectric-constant dielectric 14 that can be filled in the gap 13a is increased, further improving the self-resonant frequency and bandwidth of the inductor 100.

[0054] In other embodiments, the gaps 13a may be discontinuous and intermittent, that is, multiple gaps 13a are sequentially spaced along the extension direction of the electrode layer 12. This is not specifically limited in this embodiment. Discontinuous and intermittent gaps 13a contribute less to the overall volume of the inductor 100 than continuous and uninterrupted gaps 13a, resulting in a less effective increase in the self-resonant frequency and bandwidth of the inductor 100.

[0055] For example, as shown in FIG5 , the electrode layer 12 is configured in a coiled shape extending around a line along the stacking direction x of the base layer 10a. The circumferential side surface 121 of the electrode layer 12 includes an outer side surface 121b disposed opposite the line along the stacking direction x. The margin between the outer side surface 121b and the surface of the base 10 is L. The width of the gap 13a along the circumferential direction of the electrode layer 12 is d2, where 0.1L≤d2≤0.8L. If the width d2 of the gap 13a along the circumferential direction of the electrode layer 12 is less than 0.1L, the width d2 is small, the volume of the low-dielectric-constant dielectric 14 that can be filled in the gap 13a is small, and the improvement in the self-resonant frequency and bandwidth of the inductor 100 is small. If the width d2 of gap 13a along the circumferential direction of electrode layer 12 is greater than 0.8L, this width d2 is large, and there is a risk of cracking at gap 13a. For example, when substrate 10 is subjected to warm water isostatic pressing, the stress at gap 13a is high, and there is a risk of cracking due to expansion, resulting in a low production yield. Therefore, the width d2 of gap 13a along the circumferential direction of electrode layer 12 can be 0.1L≤d2≤0.8L. This allows gap 13a to be filled with a larger volume of low-k dielectric 14, significantly improving the self-resonant frequency and bandwidth of inductor 100, and preventing cracking at gap 13a, resulting in a higher production yield. The width d2 of gap 13a along the circumferential direction of electrode layer 12 can be 0.1L, 0.2L, 0.3L, 0.4L, 0.5L, 0.6L, 0.7L, 0.8L, etc., and this embodiment does not specifically limit this.

[0056] For example, in this embodiment, the width d2 of the gap 13 a along the circumferential direction of the electrode layer 12 is preferably 0.5L.

[0057] Optionally, as shown in FIG6 , the thickness of the electrode layer 12 along the stacking direction x of the multiple base layers 10a is t1, and the depth of the gap 13a along the stacking direction x is h, where 0.1t1≤h≤1.5t1. If the depth h of the gap 13a along the stacking direction x is less than 0.1t1, the depth h is small, the volume of the low-dielectric constant medium 14 that can be filled in the gap 13a is small, and the improvement in the self-resonant frequency and bandwidth of the inductor 100 is small. If the depth h of the gap 13a along the stacking direction x is greater than 1.5t1, the depth h is large, the thickness of the second insulating layer 13 is large, and while the overall thickness of the base layers 10a remains unchanged, the thickness of the first insulating layer 11 is small, the distance between the electrode layers 12 of two adjacent base layers 10a is small, and the insulation effect of the first insulating layer 11 is poor. Therefore, the depth h of gap 13a along the stacking direction x can be 0.1t1 ≤ h ≤ 1.5t1. This allows gap 13a to be filled with a larger volume of low-k dielectric 14, significantly improving the self-resonant frequency and bandwidth of inductor 100. Furthermore, the thickness of first insulating layer 11 is greater, and the distance between electrode layers 12 of two adjacent base layers 10a is larger, resulting in a better insulation effect of first insulating layer 11. The depth h of gap 13a along the stacking direction x can be 0.1t1, 0.3t1, 0.5t1, 0.7t1, 0.9t1, t1, 1.1t1, 1.3t1, or 1.5t1, though this embodiment does not impose any specific limitations on this.

[0058] For example, in this embodiment, the depth h of the gap 13 a along the stacking direction x is preferably t1 .

[0059] Among them, the dielectric constant of the low dielectric constant medium 14 is ε, 1≤ε≤14, which can be selected according to actual conditions. The dielectric constant ε of the low dielectric constant medium 14 can be 1, 3, 5, 7, 9, 11, 13, 14, etc., and this embodiment does not make any specific limitation on this.

[0060] In some embodiments, the material of the low dielectric constant medium 14 includes one or more of glass, ceramic, and air. This embodiment provides a variety of materials of dielectrics with different dielectric constants, which can be selected according to actual conditions and are not specifically limited in this embodiment.

[0061] Exemplarily, the material of the low dielectric constant medium 14 includes one or more of glass and ceramics. Thus, the low dielectric constant medium 14 is solid, and its shape matches the shape of the gap 13a.

[0062] When the material of the low dielectric constant medium 14 includes one or more of glass and ceramic, the dimensions of the low dielectric constant medium 14 are as follows:

[0063] Optionally, the thickness of the electrode layer 12 along the stacking direction x of the multiple base layers 10a is t1, and the thickness of the low-dielectric constant dielectric 14 along the stacking direction x is t2, where 0.1t1≤t2≤1.5t1. If the thickness t2 of the low-dielectric constant dielectric 14 along the stacking direction x is less than 0.1t1, the thickness t2 is small, the volume of the low-dielectric constant dielectric 14 is small, and the improvement in the self-resonant frequency and bandwidth of the inductor 100 is small. If the thickness t2 of the low-dielectric constant dielectric 14 along the stacking direction x is greater than 1.5t1, the thickness t2 is large, and the low-dielectric constant dielectric 14 partially protrudes outside the gap 13a. Alternatively, the thickness of the second insulating layer 13 is large. While maintaining the overall thickness of the base layer 10a unchanged, the thickness of the first insulating layer 11 is small, the distance between the electrode layers 12 of two adjacent base layers 10a is small, and the insulation effect of the first insulating layer 11 is poor. Therefore, the thickness t2 of the low-k dielectric 14 along the stacking direction x can be 0.1t1≤t2≤1.5t1. The large volume of the low-k dielectric 14 significantly improves the self-resonant frequency and bandwidth of the inductor 100. Furthermore, the thickness of the first insulating layer 11 is large, and the distance between the electrode layers 12 of two adjacent base layers 10a is large, which improves the insulation effect of the first insulating layer 11. Furthermore, the thickness t2 of the low-k dielectric 14 along the stacking direction x can be 0.1t1, 0.3t1, 0.5t1, 0.7t1, 0.9t1, 1.1t1, 1.3t1, or 1.5t1, which is not specifically limited in this embodiment.

[0064] For example, in this embodiment, the thickness t2 of the low-k dielectric 14 along the stacking direction x is preferably t1.

[0065] In some embodiments, as shown in FIG5 , the electrode layer 12 is configured in a coiled shape extending around a straight line in the stacking direction x of the base layer 10 a . The circumferential side surface 121 of the electrode layer 12 includes an outer side surface 121 b . The margin between the outer side surface 121 b and the surface of the base 10 is L. The width of the low-dielectric constant dielectric 14 along the circumferential side of the electrode layer 12 is d3, where 0.1L≤d3≤0.8L. If the width of the low-dielectric constant dielectric 14 along the circumferential side of the electrode layer 12 is d3<0.1L, the width d3 is small, the volume of the low-dielectric constant dielectric 14 is small, and the improvement in the self-resonant frequency and bandwidth of the inductor 100 is small. If the width d3 of the low-k dielectric 14 along the circumferential side of the electrode layer 12 is greater than 0.8L, this width d3 is relatively large, and there is a risk of cracking in the low-k dielectric 14. For example, when the substrate 10 is subjected to warm water isostatic pressing, the stress in the low-k dielectric 14 is relatively high, which may lead to cracking due to elongation, resulting in a low manufacturing yield. Therefore, the width d3 of the low-k dielectric 14 along the circumferential side of the electrode layer 12 can be 0.1L≤d2≤0.8L. This increases the volume of the low-k dielectric 14, significantly improving the self-resonant frequency and bandwidth of the inductor 100, and preventing cracking in the low-k dielectric 14, resulting in a higher manufacturing yield. The width d3 of the low-k dielectric 14 along the circumferential direction of the electrode layer 12 can be 0.1L, 0.2L, 0.3L, 0.4L, 0.5L, 0.6L, 0.7L, 0.8L, etc., which is not specifically limited in this embodiment.

[0066] For example, in this embodiment, the width d3 of the low-k dielectric 14 along the circumferential direction of the electrode layer 12 is preferably 0.5L.

[0067] One or more embodiments of the present disclosure provide an inductor 100. An electrode layer 12 and a second insulating layer 13 are formed by forming a first insulating layer 11 of a base layer 10a. Multiple base layers 10a are stacked sequentially, so that the electrode layers 12 of each base layer 10a are electrically connected to form an inner electrode 12a. The inner electrode 12a is electrically connected to the first and second outer electrodes 20 and 30, respectively, located at opposite ends of the base 10, thereby achieving electrical conductivity. Specifically, the inductor 100 employs a horizontal structure, resulting in high current flow, a relatively simple structure, and a high manufacturing yield. Furthermore, a low-dielectric-constant dielectric 14 is filled in the gaps 13a of the second insulating layer 13 to reduce the parasitic capacitance between the inner electrode 12a and the first and second outer electrodes 20 and 30, thereby increasing the self-resonant frequency and bandwidth of the inductor 100. In other words, the inductor 100 of this embodiment can simultaneously handle high current and a high self-resonant frequency, while also having a wide impedance bandwidth, a relatively simple structure, and a high manufacturing yield.

[0068] In addition, the distance d1 from the gap 13a of the second insulating layer 13 to the peripheral side surface 121 of the electrode layer 12 is ≥10μm. Part of the second insulating layer 13 can be used to separate the electrode layer 12 and the gap 13a, thereby preventing foreign matter (such as water vapor or plating solution in the preparation process) from entering the gap 13a and affecting the performance of the electrode layer 12. The reliability of the inductor 100 is relatively high.

[0069] Please refer to FIG7 , which is a flow chart of a method for manufacturing an inductor according to one or more embodiments of the present disclosure. The method includes:

[0070] 201. Provide multiple first insulating layers 11.

[0071] Specifically, step 101 may include forming a roll of ferrite ceramic green tape on a PET film (Polyethylene Glycol Terephthalate) by a casting method, and cutting the ferrite ceramic green tape to form a single-layer green tape of a certain size, as shown in FIG. 8 , i.e., the first insulating layer 11 .

[0072] 203. An electrode layer 12, a second insulating layer 13 and a low dielectric constant medium 14 are formed on one side of each first insulating layer 11. The low dielectric constant medium 14 is distributed around the electrode layer 12, and the distance from the low dielectric constant medium 14 to the side surface of the electrode layer 12 is d1, d1 ≥ 10 μm.

[0073] As shown in FIG. 9 , FIG. 9 shows the first insulating layer 11 having an electrode layer 12 , a second insulating layer 13 and a low-k dielectric 14 formed thereon after step 203 is implemented.

[0074] In this embodiment, the material of the low dielectric constant medium 14 in step 203 includes one or more of glass and ceramic. This embodiment provides a variety of materials of dielectrics with different dielectric constants, which can be selected according to actual conditions and are not specifically limited in this embodiment.

[0075] In this way, after the low-k dielectric 14 is formed in step 203, the tightness of the substrate 10 formed in step 205 can be maintained throughout the subsequent processing steps. Compared with the method of not forming the low-k dielectric 14 but leaving a gap (gap 13a) here, the risk of cracking of the substrate 10 can be reduced, and the production yield of the inductor is higher.

[0076] The electrode layer 12 may be formed on one side of the first insulating layer 11 by covering the first insulating layer 11 with a conductive electrode material (such as silver, copper, graphite, etc.) to form the electrode layer 12 .

[0077] Optionally, the process of covering the first insulating layer 11 with the conductive electrode material may be screen printing, vapor deposition, spin coating, or dry film pressing, etc., which is not specifically limited in this embodiment.

[0078] For example, forming the second insulating layer 13 on one side of the first insulating layer 11 may specifically include printing ferrite printing paste on a non-electrode region (ie, a region where the electrode layer 12 is not formed) on the first insulating layer 11 .

[0079] Optionally, the process of forming the low-k dielectric 14 on the first insulating layer 11 may be screen printing, vapor deposition, spin coating, dry film pressing, etc., which is not specifically limited in this embodiment.

[0080] There is no particular order in which the electrode layer 12 , the second insulating layer 13 and the low-k dielectric 14 are formed, and the order in which they are formed can be changed according to actual conditions.

[0081] As an optional embodiment, step 203 may be: as shown in Figure 10, an electrode layer 12 and a second insulating layer 13 are formed on one side of each first insulating layer 11, the second insulating layer 13 has a gap 13a, the gap 13a is distributed on the peripheral side of the electrode layer 12, and the distance from the gap 13a to the peripheral side of the electrode layer 12 is d1, d1 ≥ 10μm, as shown in Figure 9, a low dielectric constant medium 14 is filled in the gap 13a.

[0082] There is no particular order in which the electrode layer 12 and the second insulating layer 13 are formed, and the order in which they are formed can be changed according to actual conditions.

[0083] As another optional embodiment, step 203 may be: as shown in Figure 11, a low dielectric constant medium 14 is formed on one side of each first insulating layer 11, as shown in Figure 9, an electrode layer 12 and a second insulating layer 13 are formed on one side of each first insulating layer 11, the low dielectric constant medium 14 is distributed on the peripheral side of the electrode layer 12, and the distance from the low dielectric constant medium 14 to the peripheral side surface of the electrode layer 12 is d1, d1 ≥ 10μm, and the second insulating layer 13 is distributed on two opposite sides of the low dielectric constant medium 14.

[0084] There is no particular order in which the electrode layer 12 and the second insulating layer 13 are formed, and the order in which they are formed can be changed according to actual conditions.

[0085] 205. Multiple first insulating layers 11 having electrode layers 12, second insulating layers 13 and low-k dielectrics 14 are stacked in sequence to form a substrate 10, and the electrode layers 12 formed on each first insulating layer 11 are electrically connected in sequence to form internal electrodes.

[0086] As shown in FIG. 12 , FIG. 12 shows the substrate 10 formed after step 205 is implemented.

[0087] Illustratively, after step 205, the preparation method may include the following steps: warm water isostatic pressing, cutting, debinding, sintering, chamfering, etc. In this way, warm water isostatic pressing can make the substrate 10 more compact and improve the overall strength of the substrate 10. Cutting can cut the substrate 10 into multiple pieces according to a certain size. Debinding can remove organic matter (such as adhesive) present in the first insulating layer 11 and the second insulating layer 13, thereby making the substrate 10 more compact and improving the overall strength of the substrate 10. Sintering can make the substrate 10 magnetic and improve the strength of the substrate 10. Chamfering refers to forming rounded corners on the substrate 10.

[0088] 207. Provide a first external electrode and a second external electrode, and respectively arrange the first external electrode and the second external electrode on two opposite sides of the substrate 10, the first external electrode being electrically connected to the internal electrode, and the second external electrode being electrically connected to the internal electrode.

[0089] Illustratively, after step 207 , the preparation method may include the following steps: electroplating the first external electrode and the second external electrode to form solder joints on the first external electrode and the second external electrode for electrically connecting the inductor to other components.

[0090] By using the preparation method of one or more embodiments of the present invention, one or more inductors of the embodiments can be prepared, wherein the gaps of the prepared inductors are filled with a low dielectric constant medium, and the material of the low dielectric constant medium includes one or more of glass and ceramic.

[0091] Moreover, the inductor prepared using the preparation method of one or more embodiments has the beneficial effects of the inductor of one or more embodiments. For example, the preparation method of one or more embodiments can prepare an inductor having the same dimensional parameters (such as the thickness and width of the low dielectric constant medium, etc.) as one or more embodiments. That is, the structure and size of the prepared inductor can refer to one or more embodiments, and this embodiment will not be repeated.

[0092] One or more embodiments of the present disclosure provide a method for preparing an inductor. The inductor prepared by this method can simultaneously take into account large current and high self-resonant frequency, and has a wide impedance bandwidth, a simple structure, and a high preparation yield.

[0093] Please refer to FIG13 , which is a flow chart of another method for preparing an inductor according to one or more embodiments of the present disclosure. The method includes:

[0094] 301. Provide a plurality of first insulating layers 11.

[0095] Specifically, step 101 may include forming a roll of ferrite ceramic green tape on a PET film (Polyethylene Glycol Terephthalate) by a casting method, and cutting the ferrite ceramic green tape to form a single-layer green tape of a certain size, as shown in FIG. 8 , i.e., the first insulating layer 11 .

[0096] 303. An electrode layer 12, a second insulating layer 13 and a first dielectric 15 are formed on one side of each first insulating layer 11. The first dielectric 15 is distributed around the electrode layer 12, and the distance from the first dielectric 15 to the side surface of the electrode layer 12 is d1, d1 ≥ 10 μm. The first dielectric 15 includes a consumable material 15a.

[0097] As shown in FIG. 14 , FIG. 14 shows the first insulating layer 11 on which the electrode layer 12 , the second insulating layer 13 and the first dielectric 15 are formed after step 303 is implemented.

[0098] For example, consumable material 15a may include a material that evaporates at high temperatures, such as resin. In this way, during sintering in a subsequent process, consumable material 15a can be removed, leaving a gap a where consumable material 15a originally existed. This gap a is then filled with air, which has a lower dielectric constant and can increase the self-resonant frequency and bandwidth of the inductor.

[0099] In some embodiments, the first dielectric 15 further includes a low-dielectric-constant dielectric 14. Optionally, the low-dielectric-constant dielectric 14 is made of one or more of glass and ceramic. This embodiment provides a variety of dielectric materials with different dielectric constants, which can be selected based on actual conditions and are not specifically limited in this embodiment.

[0100] In this way, in the subsequent process, during sintering, the consumable material 15a can be removed while retaining the low dielectric constant medium 14. The air filled in the gap a formed at the original position of the consumable material 15a and the low dielectric constant medium 14 can jointly improve the self-resonant frequency and bandwidth of the inductor.

[0101] Furthermore, after the low-k dielectric 14 is formed in step 303, the tightness of the substrate formed in step 305 can be maintained until the subsequent sintering step. Compared with the method of not forming the low-k dielectric 14 but leaving a space (gap) here, the risk of substrate cracking can be reduced, and the preparation yield of the inductor is higher.

[0102] The electrode layer 12 may be formed on one side of the first insulating layer 11 by covering the first insulating layer 11 with a conductive electrode material (such as silver, copper, graphite, etc.) to form the electrode layer 12 .

[0103] Optionally, the process of covering the first insulating layer 11 with the conductive electrode material may be screen printing, vapor deposition, spin coating, or dry film pressing, etc., which is not specifically limited in this embodiment.

[0104] For example, forming the second insulating layer 13 on one side of the first insulating layer 11 may specifically include printing ferrite printing paste on a non-electrode region (ie, a region where the electrode layer 12 is not formed) on the first insulating layer 11 .

[0105] Optionally, the process of forming the first dielectric 15 on the first insulating layer 11 may be screen printing, vapor deposition, spin coating, dry film pressing, etc., which is not specifically limited in this embodiment.

[0106] There is no particular order in which the electrode layer 12 , the second insulating layer 13 and the first dielectric 15 are formed, and the order in which they are formed can be changed according to actual conditions.

[0107] As an optional embodiment, step 303 may be: forming an electrode layer 12 and a second insulating layer 13 on one side of each first insulating layer 11, the second insulating layer 13 having a gap, the gap being distributed on the peripheral side of the electrode layer 12, and the distance from the gap to the peripheral side surface of the electrode layer 12 is d1, d1 ≥ 10 μm, and the gap is filled with a first medium 15.

[0108] There is no particular order in which the electrode layer 12 and the second insulating layer 13 are formed, and the order in which they are formed can be changed according to actual conditions.

[0109] As another optional embodiment, step 303 may be: forming a first dielectric 15 on one side of each first insulating layer 11, forming an electrode layer 12 and a second insulating layer 13 on one side of each first insulating layer 11, the first dielectric 15 is distributed on the peripheral side of the electrode layer 12, and the distance from the first dielectric 15 to the peripheral side surface of the electrode layer 12 is d1, d1 ≥ 10 μm, and the second insulating layer 13 is distributed on two opposite sides of the first dielectric 15.

[0110] There is no particular order in which the electrode layer 12 and the second insulating layer 13 are formed, and the order in which they are formed can be changed according to actual conditions.

[0111] 305. Multiple first insulating layers 11 formed with electrode layers 12, second insulating layers 13 and first dielectrics 15 are stacked in sequence to form a substrate, and the electrode layers 12 formed on each first insulating layer 11 are electrically connected in sequence to form an internal electrode.

[0112] Illustratively, after step 305 , the preparation method may include the following steps: warm water isostatic pressing, cutting, and debinding.

[0113] 307. Sinter the substrate to remove the consumable material 15a. In this way, by sintering the substrate, the substrate is given magnetic properties and its strength is increased. At the same time, the heat of sintering can be used to volatilize the consumable material 15a, achieving the purpose of removing the consumable material 15a, killing two birds with one stone.

[0114] As shown in FIG15 , FIG15 is a substrate (part of the base layer is omitted) after step 307 is performed. Compared with FIG14 , the consumable material 15a in FIG14 is volatilized and removed during sintering, and a vacancy a is formed at the location of the consumable material 15a.

[0115] Illustratively, after step 307 , the preparation method may include chamfering.

[0116] 309. Provide a first external electrode and a second external electrode, and respectively arrange the first external electrode and the second external electrode on two opposite sides of the substrate, the first external electrode being electrically connected to the internal electrode, and the second external electrode being electrically connected to the internal electrode.

[0117] Illustratively, after step 309 , the preparation method may include the following steps: electroplating the first external electrode and the second external electrode to form solder joints on the first external electrode and the second external electrode for electrically connecting the inductor to other components.

[0118] By using the preparation method of one or more embodiments of the present invention, one or more inductors of the embodiments can be prepared, wherein the gaps of the prepared inductors are filled with a low-dielectric constant medium and air, and the material of the low-dielectric constant medium includes one or more of glass and ceramic.

[0119] Moreover, the inductor prepared using the preparation method of one or more embodiments has the beneficial effects of the inductor of one or more embodiments. For example, the preparation method of one or more embodiments can prepare an inductor having the same dimensional parameters (such as the thickness and width of the low dielectric constant medium, etc.) as one or more embodiments. That is, the structure and size of the prepared inductor can refer to one or more embodiments, and this embodiment will not be repeated.

[0120] Among them, the main difference between the inductor prepared by the preparation method of one or more embodiments and the inductor prepared by the preparation method of one or more embodiments is that the materials filled in the gaps of the inductor are different. The gaps of the inductor prepared by one or more embodiments are filled with air, while the gaps of the inductor prepared by one or more embodiments do not have air.

[0121] One or more embodiments of the present disclosure provide a method for preparing an inductor. The inductor prepared by this method can simultaneously take into account large current and high self-resonant frequency, and has a wide impedance bandwidth, a simple structure, and a high preparation yield.

[0122] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims. Industrial Applicability

[0124] The inductor and its preparation method provided by the present disclosure can simultaneously take into account large current and high self-resonant frequency, and has a wide impedance bandwidth, a simple structure, and a high preparation yield, and has strong industrial applicability.

Claims

1. An inductor, comprising: A substrate, the substrate comprising a plurality of base layers stacked in sequence, each of the base layers comprising a first insulating layer, an electrode layer and a second insulating layer, the electrode layer being arranged on the first insulating layer, the electrode layers of each of the base layers being electrically connected in sequence to form an internal electrode, the second insulating layer being arranged on the first insulating layer and being located on the same surface of the first insulating layer as the electrode layer, the second insulating layer having a gap, the gap being distributed on the peripheral side of the electrode layer, and the distance from the gap to the peripheral side surface of the electrode layer being d1, d1 ≥ 10 μm, and the gap being filled with a low dielectric constant medium; A first external electrode, the first external electrode is disposed at one end of the substrate, and the first external electrode is electrically connected to the internal electrode; as well as A second external electrode is provided at an end of the substrate away from the first external electrode, and the second external electrode is electrically connected to the internal electrode.

2. The inductor according to claim 1, wherein The electrode layer is configured in a winding shape extending around a straight line in which the stacking direction of the base layer is located, the gap extends along an extension direction of the electrode layer, and an extension length of the gap is greater than or equal to 10 percent of an extension length of the electrode layer.

3. The inductor according to claim 1, wherein: The electrode layer is configured to be in a winding shape extending around a straight line in which the stacking direction of the base layer is located, and the gap extends from one end of the electrode layer to the other end of the electrode layer along the extending direction of the electrode layer.

4. The inductor according to claim 1, wherein: The electrode layer is constructed in a winding shape extending around a straight line where the stacking direction of the base layer is located, and the circumferential side surface of the electrode layer includes an outer side surface arranged away from the straight line where the stacking direction is located, the margin amount between the outer side surface and the surface of the substrate is L, and the width of the gap along the circumferential side direction of the electrode layer is d2, 0.1L≤d2≤0.8L.

5. The inductor according to claim 1, wherein The electrode layer is constructed in a winding shape extending around a straight line in which the stacking directions of the multiple base layers are located, and the peripheral side surfaces of the electrode layer include relative inner side surfaces and outer side surfaces, and the inner side surfaces are arranged toward the straight line in which the stacking directions are located, and the gaps are distributed on the inner side surfaces of the electrode layer, and the distance from the gaps to the inner side surfaces of the electrode layer is d1, and / or the gaps are distributed on the outer side surfaces of the electrode layer, and the distance from the gaps to the outer side surfaces of the electrode layer is d1.

6. The inductor according to claim 1, wherein The thickness of the electrode layer along the stacking direction of the plurality of base layers is t1, the depth of the gap along the stacking direction is h, and 0.1t1≤h≤1.5t1.

7. The inductor according to any one of claims 1 to 6, wherein: The material of the low dielectric constant medium includes one or more of glass, ceramic, and air.

8. The inductor according to claim 7, wherein: When the material of the low dielectric constant medium includes one or more of glass and ceramic, the thickness of the electrode layer along the stacking direction of the multiple base layers is t1, and the thickness of the low dielectric constant medium along the stacking direction is t2, 0.1t1≤t2≤1.5t1.

9. The inductor according to claim 7, wherein: When the material of the low dielectric constant medium includes one or more of glass and ceramic, the peripheral side surface of the electrode layer includes an outer side surface arranged opposite to the straight line where the stacking direction is located, the margin amount between the outer side surface and the surface of the substrate is L, and the width of the low dielectric constant medium along the peripheral side direction of the electrode layer is d3, 0.1L≤d3≤0.8L.

10. A method for preparing an inductor, comprising: providing a plurality of first insulating layers; An electrode layer, a second insulating layer and a low dielectric constant medium are formed on one side of each of the first insulating layers, wherein the low dielectric constant medium is distributed around the electrode layer, and a distance from the low dielectric constant medium to the side surface of the electrode layer is d1, and d1 ≥ 10 μm; The plurality of first insulating layers formed with the electrode layer, the second insulating layer and the low dielectric constant medium are stacked in sequence to form a substrate, and the electrode layers formed on the first insulating layers are electrically connected in sequence to form an internal electrode; A first outer electrode and a second outer electrode are provided. The first outer electrode and the second outer electrode are respectively arranged on two opposite sides of the substrate. The first outer electrode is electrically connected to the inner electrode, and the second outer electrode is electrically connected to the inner electrode.

11. The preparation method according to claim 10, wherein: The electrode layer, the second insulating layer and the low dielectric constant medium are formed on one side of each of the first insulating layers, the low dielectric constant medium is distributed on the peripheral side of the electrode layer, and the distance from the low dielectric constant medium to the peripheral side of the electrode layer is d1, d1 ≥ 10 μm, including: The electrode layer and the second insulating layer are formed on one side of each of the first insulating layers, wherein the second insulating layer has a gap, the gap is distributed on the peripheral side of the electrode layer, and the distance from the gap to the peripheral side surface of the electrode layer is d1, d1 ≥ 10 μm; The low dielectric constant medium is filled in the gap.

12. The preparation method according to claim 10 or 11, wherein: The material of the low dielectric constant medium includes one or more of glass and ceramic.

13. A method for preparing an inductor, comprising: providing a plurality of first insulating layers; An electrode layer, a second insulating layer and a first medium are formed on one side of each of the first insulating layers, the first medium is distributed on the peripheral side of the electrode layer, and the distance between the first medium and the peripheral side of the electrode layer is d1, d1≥10 μm, and the first medium includes consumables; The plurality of first insulating layers formed with the electrode layer, the second insulating layer and the first medium are stacked in sequence to form a substrate, and the electrode layers formed on the first insulating layers are electrically connected in sequence to form an internal electrode; Sintering the substrate to remove the consumables; A first outer electrode and a second outer electrode are provided. The first outer electrode and the second outer electrode are respectively arranged on two opposite sides of the substrate. The first outer electrode is electrically connected to the inner electrode, and the second outer electrode is electrically connected to the inner electrode.

14. The preparation method according to claim 13, wherein: The electrode layer, the second insulating layer and the first dielectric are formed on one side of each of the first insulating layers, the first dielectric is distributed on the peripheral side of the electrode layer, and the distance from the first dielectric to the peripheral side of the electrode layer is d1, d1≥10 μm, including: The electrode layer and the second insulating layer are formed on one side of each of the first insulating layers, wherein the second insulating layer has a gap, the gap is distributed on the peripheral side of the electrode layer, and the distance from the gap to the peripheral side surface of the electrode layer is d1, d1 ≥ 10 μm; The gap is filled with the first medium.

15. The preparation method according to claim 13 or 14, wherein: The first medium also includes a low dielectric constant medium.

16. The preparation method according to claim 15, wherein: The material of the low dielectric constant medium includes one or more of glass and ceramic.

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