Silicon wafer, solar cell and module

Abstract

A silicon wafer. The concentration of antimony in the silicon wafer is 1E+12 cm-3 to 2E+16 cm-3, preferably 4E+14 cm-3 to 2E+16 cm-3, preferably 4.30E+14 cm-3 to 1.9E+16 cm-3, and further preferably 4.45E+14 cm-3 to 1.87E+16 cm-3; the rate of change of the resistivity of the silicon wafer is ≤ 0.6, optionally the rate of change of the resistivity being ≤ 0.5, and optionally the rate of change of the resistivity being ≤ 0.4. The present application also relates to a solar cell comprising the silicon wafer and a battery module. The solar cell comprises a silicon substrate, the surface of at least one side of the silicon substrate being internally provided with a doped region; the silicon substrate contains antimony; the doped region is doped with doping elements, the doping elements being selected from third main group elements or fifth main group elements; the concentration of the antimony in the silicon substrate is 1E+12 cm-3 to 2E+16 cm-3 , preferably 4E+14 cm-3 to 2E+16 cm-3, preferably 4.3E+14 cm-3 to 1.9E+16 cm-3, and further preferably 4.45E+14 cm-3 to 1.87E+16 cm-3; the rate of change of the resistivity of the silicon substrate is ≤ 0.6, optionally the rate of change of the resistivity being ≤ 0.5, and optionally the rate of change of the resistivity being ≤ 0.4.

Description

Silicon wafers, solar cells and modules Technical Field

[0001] The present application relates to the field of solar photovoltaics, and in particular to a silicon wafer, and to solar cells and battery modules. Background Art

[0002] Conventional phosphorus-doped silicon wafers, due to the phosphorus segregation coefficient of 0.35, typically have a head-to-tail resistivity ratio of 6-7 times for N-type single crystal silicon rods. This resistivity varies significantly across the depth of the wafer, and due to the instability of the growth interface during the crystal pulling process, the radial resistivity of the phosphorus-doped wafer is also uneven, negatively impacting back-end cell processing. This uneven concentration leads to non-uniform carrier distribution within the wafer, increasing carrier capture and scattering, and reducing carrier transport efficiency, which can lead to decreased cell performance and reduced photoelectric conversion efficiency.

[0003] Summary of the Invention

[0004] Currently, conventional phosphorus-doped N-type silicon wafers are primarily controlled for resistivity uniformity by adjusting crucible rotation, pulling speed, argon flow rate, furnace pressure, and other process techniques. The inventors of this application have achieved a balance between minority carrier lifetime and transmission resistance by controlling the concentration of doping elements in the silicon wafer. Combined with uniform doping with antimony, this achieves resistivity uniformity, further reduces the lateral and longitudinal transmission resistance of carriers, and improves battery efficiency, thereby completing the technical solution of this application. Specifically, this application relates to the following solutions:

[0005] 1. A silicon wafer, wherein:

[0006] The concentration of antimony in the silicon wafer is 1E+12cm -3 to 2E+16cm -3 , preferably 4E+14cm -3 to 2E+16cm -3 , preferably 4.3E+14cm -3 to 1.9E+16cm -3 ; More preferably 4.45E+14cm -3 to 1.87E+16cm -3 ;

[0007] The resistivity change rate of the silicon wafer is ≤0.8; the optional resistivity change rate is ≤0.6; the optional resistivity change rate is ≤0.5; and the optional resistivity change rate is ≤0.4.

[0008] 2. The silicon wafer according to item 1, wherein the average resistivity offset rate of the silicon wafer is ≤8%; the average resistivity offset rate is optionally ≤5%, the average resistivity offset rate is optionally ≤4.5%; the average resistivity offset rate is further optionally ≤4%; the resistivity of the silicon wafer is optionally 0.3-1000Ω·cm, optionally 0.3-100Ω·cm, optionally 0.3~10Ω·cm, optionally 0.4~8Ω·cm; optionally 0.5~6Ω·cm.

[0009] 3. The silicon wafer according to item 1 or 2, wherein the resistivity change rate of the silicon wafer is ≥0.01, and the resistivity change rate is optionally ≥0.1.

[0010] 4. The silicon wafer according to any one of items 1 to 3, wherein the average resistivity shift rate is ≥0.1%, and optionally the average resistivity shift rate is ≥1%.

[0011] 5. A solar cell comprising a silicon substrate, the silicon substrate being formed from the above-mentioned silicon wafer, the silicon substrate having a doped region on at least one surface thereof, the silicon substrate containing antimony, the doped region being doped with a doping element selected from a Group III element or a Group V element,

[0012] The antimony concentration in the silicon substrate is 1E+12cm -3 to 2E+16cm -3 , preferably 4E+14cm -3 to 2E+16cm -3 , preferably 4.3E+14cm -3 to 1.9E+16cm -3 ; More preferably 4.45E+14cm -3 to 1.87E+16cm -3 ;

[0013] The resistivity change rate of the silicon substrate is ≤0.8; the resistivity change rate can be selected to be ≤0.6; the resistivity change rate can be selected to be ≤0.5; and the resistivity change rate can be selected to be ≤0.4.

[0014] 6. The solar cell according to item 5, wherein the surface of at least one side of the silicon substrate has at least one doping layer.

[0015] 7. The solar cell according to item 6, wherein at least one passivation layer is provided between the doping layer and the doping region.

[0016] 8. In the solar cell according to item 5, the concentration of antimony in the doped region is substantially constant in the thickness direction of the silicon substrate.

[0017] 9. The solar cell according to item 5, wherein:

[0018] In the doping region, the sum of the concentration of antimony element and the concentration of doping element is less than or equal to 1E+21cm -3 .

[0019] 10. The solar cell according to item 5, wherein

[0020] When the doping element is a Group III element, the thickness of the doping region is in the range of 30 to 650 mm; or

[0021] When the doping element is a Group V element, the thickness of the doping region ranges from 100 to 200 nm.

[0022] 11. The solar cell according to item 5, wherein

[0023] The doping region includes a first doping region and a second doping region,

[0024] An interface passivation layer and a doping passivation layer are sequentially stacked on the surface of the first doped region on the side away from the silicon substrate,

[0025] doping a first doping element in the doped passivation layer,

[0026] The second doping region on the silicon substrate is further doped with a second doping element,

[0027] The first doping region and the second doping region have opposite conductivity types.

[0028] 12. The solar cell according to item 11, wherein

[0029] The first doping element is a Group V element, the second doping element is a Group III element,

[0030] In the doped passivation layer, the concentration of the first doping element at a first preset depth from the surface of the doped passivation layer on a side away from the silicon substrate is greater than the concentration of the second doping element at the same first preset depth from the surface of the second doping region. The thickness of the doped passivation layer ranges from 100 to 400 nm, and the first preset depth is less than or equal to the thickness of the doped passivation layer.

[0031] 13. The solar cell according to item 11, wherein

[0032] The first doping element is a Group V element, the second doping element is a Group III element,

[0033] An interface passivation layer and a doping passivation layer are sequentially stacked on a surface of the second doped region on a side away from the silicon substrate;

[0034] In the doped passivation layer, the concentration of the first doping element at a first preset depth from the surface of the doped passivation layer on the side away from the silicon substrate in the first doping region is greater than the concentration of the second doping element at a first preset depth from the surface of the doped passivation layer on the side away from the silicon substrate in the second doping region, the thickness of the doped passivation layer on the first doping region ranges from 100 to 400 nm, the thickness of the doped passivation layer on the second doping region ranges from 100 to 400 nm, and the first preset depth is less than or equal to the thickness of the doped passivation layer on the first doping region.

[0035] 14. The solar cell according to item 12, wherein

[0036] doping a first doping element into the interface passivation layer,

[0037] In the direction from the doped passivation layer to the interface passivation layer, in the interface passivation layer, the concentration of the first doping element at a second preset depth from the surface of the doped passivation layer away from the silicon substrate is greater than the concentration of the second doping element at a second preset depth from the surface of the second doping region, the thickness range of the interface passivation layer is 0.5 to 5 nm, and the second preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer and the interface passivation layer.

[0038] 15. The solar cell according to item 13, wherein

[0039] The interface passivation layer of the first doping region is doped with a first doping element, and the interface passivation layer of the second doping region is doped with a second doping element.

[0040] In the direction from the doped passivation layer to the interface passivation layer, in the interface passivation layer, the concentration of the first doping element at a second preset depth on the surface of the doped passivation layer away from the silicon substrate in the first doping region is greater than the concentration of the second doping element at a second preset depth on the surface of the doped passivation layer away from the silicon substrate in the second doping region, the thickness of the interface passivation layer on the first doping region ranges from 0.5 to 5 nm, the thickness of the interface passivation layer on the second doping region ranges from 0.5 to 5 nm, and the second preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer and the interface passivation layer on the first doping region.

[0041] 16. The solar cell according to item 12, wherein

[0042] In the direction from the doped passivation layer to the surface of the first doped region, in the silicon substrate, the concentration of the first doping element at a third preset depth from the surface of the doped passivation layer on the side away from the silicon base is greater than the concentration of the second doping element at a third preset depth from the surface of the second doped region, the thickness range of the first doped region is 30 to 100 nm, and the third preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer, the interface passivation layer and the first doped region.

[0043] 17. The solar cell according to item 13, wherein

[0044] In the direction from the doped passivation layer to the surface of the first doped region, in the silicon substrate, the concentration of the first doping element at a third preset depth from the surface of the doped passivation layer of the first doped region away from the silicon substrate is greater than the concentration of the second doping element at a third preset depth from the surface of the doped passivation layer of the second doped region away from the silicon substrate, the thickness range of the first doped region is 30 to 100 nm, and the third preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer, the interface passivation layer and the first doped region on the first doped region.

[0045] 18. The solar cell according to item 5, wherein

[0046] When the doping element is a Group III element, the thickness of the doping region is in the range of 80 to 180 nm;

[0047] When the doping element is a Group V element, the thickness of the doping region ranges from 30 to 100 nm.

[0048] 19. The solar cell according to item 5, wherein the surface square resistance variation rate of the silicon substrate surface is ≤0.6; the surface square resistance variation rate is optionally ≤0.4; the surface square resistance variation rate is optionally ≤0.3; the surface square resistance variation rate is optionally ≤0.2.

[0049] 20. The solar cell according to item 19, wherein the surface square resistance variation rate of the silicon substrate surface is ≥0.001; the surface square resistance variation rate is optionally ≥0.01.

[0050] 21. A solar cell according to any one of items 5 to 20, wherein the cell includes an electrode formed on a light absorber, the electrode includes a metal crystal portion in contact with the light absorber, the metal crystal portion includes an antimony element, wherein the light absorber includes a silicon substrate and a region for separating carriers generated by the silicon substrate.

[0051] 22. The battery according to item 21, wherein the metal crystal portion further comprises a doping element, and a concentration of the doping element is greater than a concentration of the antimony element.

[0052] 23. The solar cell according to any one of items 5 to 22, wherein the mechanical strength of the cell is greater than 50 MPa.

[0053] 24. A cell string comprising a plurality of solar cells according to any one of items 5 to 23 interconnected by conductive interconnectors.

[0054] 25. The cell string according to item 24, wherein the curvature of the solar cells is less than or equal to 2 mm.

[0055] 26. The cell string according to item 25, wherein the connecting wires are bonded to the solar cells by welding or conductive bonding.

[0056] 27. The battery string according to item 26, wherein the welding comprises a heating step.

[0057] 28. The battery string according to item 27, wherein the temperature range of the heating step is 100-160 degrees Celsius, and the curvature of the solar cell is less than or equal to 1.5 mm.

[0058] 29. The battery string according to item 27, wherein the temperature range of the heating step is 165-200 degrees Celsius, and the curvature of the solar cell is less than or equal to 2 mm.

[0059] 30. The cell string according to any one of items 24 to 29, wherein the conductive interconnect comprises an electrical contact portion that contacts an electrode of the solar cell, the electrical contact portion comprising antimony element.

[0060] 31. A solar cell module comprising a plurality of cells, an encapsulation layer, a cover plate and a back plate as described in any one of items 5 to 23, wherein the sealing layer seals the plurality of cells and is located between the cover plate and the back plate.

[0061] 32. The solar module of item 31, wherein the curvature of the cell is less than or equal to 1.2 mm.

[0062] 33. The solar module according to item 31, wherein the cells protrude toward the cover plate to form a curved shape.

[0063] 34. The solar module according to any one of items 31 to 33, further comprising a frame, wherein the edges of the cover plate and / or back plate are embedded in the mounting portion of the frame.

[0064] 35. The solar module according to any one of items 31 to 33, wherein the cover sheet and / or the back sheet are transparent sheets.

[0065] 36. The solar module according to any one of items 31 to 33, wherein the back sheet is a non-transparent sheet.

[0066] 37. A solar module according to any one of items 31 to 36, wherein a plurality of solar cells according to any one of items 5 to 23 are interconnected by a conductive interconnect, wherein the conductive interconnect comprises an electrical contact portion that contacts an electrode of the solar cell, and wherein the electrical contact portion comprises antimony element.

[0067] Effects of the Invention

[0068] Since the silicon wafer of the present application reasonably controls the concentration of antimony elements, a balance between minority carrier lifetime and transmission resistance is achieved, and combined with the uniform doping of antimony elements, the resistivity of the silicon wafer or bare silicon wafer itself is uniform, the resistivity change rate is small, and the average offset rate of the resistivity is small. Using such silicon wafers to prepare batteries can further reduce the lateral and longitudinal transmission resistance of carriers, thereby ultimately achieving an increase in battery efficiency. Using the silicon wafer of the present application, the minority carrier lifetime of the silicon wafer is high, the short-circuit current of the prepared battery is improved, and the battery efficiency is further improved. In the present application, since the thickness and doping uniformity of the doping region formed by direct doping in the silicon substrate part of the solar cell (the silicon substrate prepared from the raw silicon wafer) are controlled, it is beneficial to the separation of carriers, reduce carrier recombination, increase short-circuit current and open-circuit voltage, and can further reduce free carrier Auger recombination, further improving short-circuit current.

[0069] In addition, the battery of the present application can not only overcome the crystalline silicon lattice distortion caused by single element doping, which results in many defects in the heavily doped area, but also improve light absorption and increase battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] FIG1 shows a method for testing the resistivity change rate of a silicon wafer;

[0071] FIG2 shows a method for testing the surface square resistance change rate of a silicon wafer;

[0072] Figure 3 shows a typical structure of a TOPCon battery.

[0073] FIG4 shows a schematic diagram of a battery stringing process according to some embodiments.

[0074] FIG5 shows another schematic diagram of a battery stringing process according to some embodiments.

[0075] FIG6 shows a schematic diagram of a specific structure of a battery assembly according to some embodiments.

[0076] FIG7 shows another specific schematic structural diagram of a battery assembly according to some embodiments. DETAILED DESCRIPTION

[0077] The following embodiments of the present application are intended only to illustrate specific implementation methods for implementing the present application and are not to be construed as limiting the present application. Any other changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principles of the present application are deemed equivalent replacements and fall within the scope of protection of the present application.

[0078] The specific embodiments of the present application will be described in more detail below. However, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0079] It should be noted that certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different nouns to refer to the same component. This specification and claims do not use the difference in nouns as a way to distinguish components, but use the difference in the functions of the components as the criterion for distinction. As mentioned throughout the specification and claims, "including" or "comprising" is an open term, so it should be interpreted as "including but not limited to". The subsequent description of the specification is a preferred embodiment of the present application, but the description is based on the general principles of the specification and is not intended to limit the scope of the present application. The scope of protection of this application shall be as defined by the attached claims.

[0080] As used herein, "substantially free" with respect to a particular component is used herein to mean that the particular component is not purposefully formulated into the composition and / or is present only as a contaminant or in trace amounts. Thus, the total amount of the particular component resulting from any unintentional contamination of the composition is less than 0.05%, preferably less than 0.01%. Most preferred are compositions wherein the amount of the particular component is undetectable by standard analytical methods.

[0081] As used in this specification, "a" or "an" may mean one or more. As used in the claims, when used with the word "comprising", the word "a" or "an" may mean one or more than one.

[0082] The term "or" is used in the claims to mean "and / or" unless explicitly stated to refer only to alternatives or the alternatives are mutually exclusive, although this disclosure supports a definition referring only to alternatives and "and / or." As used herein, "another" can mean at least a second or more.

[0083] Those skilled in the art will understand that silicon wafers generally refer to raw material bare silicon wafers, and silicon substrates generally refer to the parts formed by silicon wafers in batteries. Light absorbers generally refer to functional bodies in batteries for absorbing photons, generating photogenerated carriers and separating photogenerated carriers, which include silicon substrates and regions for separating carriers generated by silicon substrates (such as tunneling layers and doped polycrystalline layers in TOPCON structures), wherein the silicon substrate is used to absorb light and generate photogenerated carriers. It is understandable that simple emission-reducing layers, other functional layers, and electrodes do not belong to light absorbers. Those skilled in the art will understand that light absorbers or silicon substrates can be recovered from batteries, and the silicon substrate defined in this application can be obtained by peeling off different stacked structures.

[0084] In the present application, the doped region can also be used to separate photogenerated carriers, such as the region in the TOPCon cell described below where a Group III element (such as boron) is diffused.

[0085] That is, the silicon substrate is obtained from a bare silicon wafer, and the silicon substrate includes a silicon base portion and a doped region portion, wherein the silicon base portion is a body region that is not doped during the battery process, and its performance is the same as that of the bare silicon wafer of the raw material. The doped region may be a region whose other performance and parameters are basically the same as those of the body region except for the doping element, such as a doped region formed by direct doping or internal diffusion doping inside the bare silicon wafer. The doping element may be a Group III element, such as boron, aluminum, gallium, indium, thallium, or a Group V element, such as nitrogen, phosphorus, arsenic, antimony, and bismuth. In addition, in some cases, the doped region is antimony element or doping element, such as Group III element and Group V element, specifically where B or P is concentrated. In some cases, the doped region may be basically the same as the body region, that is, it mainly includes an antimony doped region.

[0086] In a structural cell with at least part of TOPCon (e.g., TOPCon cell, local TOPCon cell, back contact hybrid cell and TBC cell), the silicon substrate generally includes a doped region formed within the surface of at least one side of the silicon substrate, and the performance of this doped region is the same as that of the raw material bare silicon wafer. The doped region may be substantially the same as the body region except for the doping element, that is, the antimony element concentration, resistivity change rate, resistivity offset rate and other properties are substantially the same. Such a doped region may be formed by directly doping the bare silicon wafer as described in detail below, or by doping the doping element into the bare silicon wafer through layers such as a doped passivation layer and an interface passivation layer. In the present application, for a structural cell with at least part of TOPCon, a doped region generally refers to a region formed by direct doping or internal doping inside the raw silicon wafer, wherein the internal doping is formed by doping polysilicon called a doping layer through a tunneling layer called a passivation layer into the interior of the bare silicon wafer.

[0087] In the case of crystalline silicon heterojunction cells (HJT / HIT) and full back electrode back contact heterojunction cells (HBC), the doped region also refers to the doped region within the internal surface of at least one side of the silicon substrate. In this case, the doped region includes antimony elements or doping elements, such as third-group elements and fifth-group elements, specifically where B or P is concentrated, or the doped region may be basically the same as the body region, that is, it mainly includes an antimony doped region. Furthermore, at least one side of the silicon substrate has a doped amorphous silicon layer as a doping layer and an intrinsic amorphous silicon layer as a passivation layer. In this case, the doping elements may or may not enter the raw silicon wafer.

[0088] In the present application, there is no further limitation on the silicon wafer itself involved in the above-mentioned present application. It can be a silicon wafer obtained after machining and slicing after the silicon rod is drawn (it can also be called a bare silicon wafer). The silicon substrate in the present application can be a part of the silicon substrate that is peeled off and recovered from the battery component, as long as it can have a certain shape and can be in the form of a sheet, that is, the size of one surface is larger than the size of the surface perpendicular to it, and it is flat or plate-shaped. There is no limitation on the size of the silicon wafer or silicon substrate of the present application. The silicon wafer or silicon substrate can be of any size, and the light absorber is recovered from the battery component and the peeled part of the silicon substrate of other layer structures is peeled off. In addition, those skilled in the art can understand that during peeling, if the doped area is partially destroyed, as long as part of the doped area still exists, it should be understood as the silicon substrate described in the present application, and the battery with such a silicon substrate also meets the definition of the present application. For example, in a specific embodiment, the length of at least one side of the silicon wafer or silicon substrate of the present application (including the silicon substrate after the recovery and peeling of other layer structures) is greater than 156 mm, for example, it can be 158±2 mm, (160±2) mm, (165±2) mm, (170±2) mm, (175±2) mm, (180±2) mm, (185±2) mm, 190±2 mm, (195±2) mm, (200±2) mm, (205±2)mm, (210±2)mm, (215±2)mm, (220±2)mm, (225±2)mm, (230±2)mm, (235±2)mm, (240±2)mm, (245±2)mm, (250±2)mm, (255±2)mm, (260±2)mm, (265±2)mm, (270±2)mm, (275±2)mm, and any ranges between these values. For example, in a specific embodiment, the thickness of the silicon wafer or silicon substrate of the present application (including the portion of the silicon substrate after recovery and stripping of other layer structures) is at least 40 to 170 μm, for example, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, or 160 μm. In a specific embodiment, the size of the portion of the silicon substrate after recovery and stripping of other layer structures can be smaller than the above size, as long as the antimony concentration and resistivity can be detected, and the resistivity change rate, resistivity average offset rate, and other limitations of the present application can be calculated.

[0089] In the present application, the concentration of antimony in a silicon wafer or silicon substrate can be detected by any method known to those skilled in the art, and those skilled in the art can select based on demand, for example, by SIMS, ICP-MS, GDMS and other methods, preferably by ICP-MS method. It will be understood by those skilled in the art that the concentration of antimony in a silicon wafer or silicon substrate can refer to the concentration of antimony at any site on the surface of the silicon wafer or silicon substrate, in the silicon wafer or silicon substrate, or can be the average value of the antimony concentration at multiple locations, or the average value of the antimony concentration on the entire silicon wafer or silicon substrate. Those skilled in the art can select any of the above-mentioned sites for detection based on actual conditions such as the detection conditions and the instruments used, or can calculate the average value of multiple sites after detecting multiple sites as the concentration of antimony. In a specific embodiment, the concentration of antimony refers to the average value detected on the thickness of the silicon wafer or silicon substrate, for example, the concentration of antimony in the silicon wafer is detected in a thickness direction using the SIMS method, and the average value in this thickness direction is obtained.

[0090] In the present application, the concentration of the doping element, the first doping element or the second doping element in the silicon substrate can be detected by any method known to those skilled in the art. Those skilled in the art can select based on demand, for example, by SIMS, ICP-MS, GDMS and other methods, preferably by ICP-MS method. Those skilled in the art will understand that the concentration of the doping element, the first doping element or the second doping element in the silicon substrate can refer to the surface of the doping region of the silicon substrate, the concentration of the doping element, the first doping element or the second doping element at any site in the doping region of the silicon substrate, of course, it can also be the average value of the concentration of the doping element, the first doping element or the second doping element at multiple locations or the average value of the concentration of the doping element, the first doping element or the second doping element within the doping region of the entire silicon substrate. Those skilled in the art can select the above-mentioned arbitrary sites for detection based on actual conditions such as the detection conditions and the instruments used, or can calculate the average value of the multiple sites after detecting multiple sites to serve as the concentration of the doping element, the first doping element or the second doping element. In a specific embodiment, the concentration of the doping element, the first doping element or the second doping element refers to the average value detected over the thickness of the doping region of the silicon substrate. For example, the concentration of the doping element, the first doping element or the second doping element in the doping region of the silicon substrate is detected in a thickness direction using the SIMS method, and the average value in this thickness direction is calculated.

[0091] In the present application, the resistivity of a silicon wafer or silicon substrate can be detected by any method known to those skilled in the art, and those skilled in the art can select based on demand, for example, by testing with a four-probe tester, or by testing with a method such as a non-contact eddy current method (for example, a terahertz offline two-dimensional imaging device (FalconWave-S) can be used for detection), or by testing with a four-probe tester. Those skilled in the art will understand that the resistivity of a silicon wafer or silicon substrate can refer to the resistivity detection data of any site on the surface of a silicon wafer or silicon substrate, or in a silicon wafer or silicon substrate, or can be the average value of the resistivity detection data of multiple locations or the average value of the resistivity on the entire silicon wafer or silicon substrate. Those skilled in the art can select the above-mentioned arbitrary sites for detection based on the actual conditions such as the detection conditions and the instruments used, or can calculate the average value of multiple sites after detecting multiple sites to serve as the resistivity of the silicon wafer or silicon substrate. In a specific embodiment, the resistivity of a silicon wafer or silicon substrate refers to the average value of the resistivity detected in the thickness direction of the silicon wafer or silicon substrate, for example, the resistivity of each site of the silicon wafer or silicon substrate is detected in a thickness direction using a four-probe tester, and the average value in this thickness direction is obtained.

[0092] In the present application, the resistivity change rate refers to the ratio of resistivity change with position. In the present application, the resistivity change rate of a silicon wafer or silicon substrate refers to the maximum value of the resistivity at any multiple sites in the silicon wafer or silicon substrate minus the minimum value and divided by the average value of the resistivity at any multiple sites in the silicon wafer or silicon substrate calculated. For example, those skilled in the art can arbitrarily select any site on the surface of a silicon wafer or silicon substrate, in a silicon wafer or silicon substrate for detection, using a non-contact eddy current method (such as a terahertz offline two-dimensional imaging device (FalconWave-S)) or by a method such as a four-probe tester to analyze the resistivity of the n sites tested, select the maximum value, minimum value and average value therein, and calculate. Those skilled in the art will fully appreciate that n only needs to be a positive integer greater than or equal to 2, but typically can be, for example, a positive integer greater than 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, or 100. Alternatively, the entire surface of the silicon wafer or silicon substrate may be scanned to obtain the average resistivity of any plurality of points on the surface of the silicon wafer or silicon substrate in a direction perpendicular to the surface of the silicon wafer or silicon substrate. Based on the scan results of the entire surface, the maximum resistivity value Rmax and the minimum resistivity value Rmin are selected, and the average resistivity value Rv is calculated using the resistivity change rate calculation formula (Rmax-Rmin) / Rv. In actual operation, the resistivity change rate of a silicon wafer or silicon substrate can be measured by the following method: a resistivity surface scan of the silicon wafer or silicon substrate is performed using a terahertz offline two-dimensional imaging device (FalconWave-S) or a four-probe tester, and a line is selected from the center point of the silicon wafer or silicon substrate to the edge of the silicon wafer or silicon substrate, as shown in FIG1 . The black line in FIG1 represents the selected line, and the average resistivity value Rv on the selected line is obtained, as well as the maximum resistivity value Rmax and the minimum resistivity value Rmin on the selected line of the silicon wafer or silicon substrate. The resistivity change rate is (Rmax-Rmin) / Rv. In addition, those skilled in the art will fully understand that the black line shown in FIG1 is merely for convenience, and any line can be drawn on the silicon wafer or silicon substrate to detect the resistivity change rate of the silicon wafer or silicon substrate.

[0093] In the present application, resistivity offset rate is the ratio of resistivity to position offset. In the present application, the resistivity offset rate of silicon wafer or silicon substrate refers to the absolute value of the difference between the mean value of the resistivity on any site in silicon wafer or silicon substrate and the resistivity of any multiple sites of silicon wafer or silicon substrate divided by the calculated value of the mean value of resistivity. For example, those skilled in the art can arbitrarily select any site in silicon wafer or silicon substrate surface, silicon wafer or silicon substrate to detect, by non-contact eddy current method (such as terahertz off-line two-dimensional imaging equipment (FalconWave-S)) or by methods such as four-probe tester, the resistivity of i sites tested is analyzed. The resistivity average offset rate of silicon wafer or silicon substrate refers to the mean value of resistivity offset rate on any i sites. Those skilled in the art will fully understand that i only needs to be a positive integer greater than or equal to 3, but can generally be, for example, a positive integer greater than 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95 or 100. In actual operation, the resistivity shift rate of the silicon wafer or silicon substrate can be calculated by the following specific method, that is, a resistivity surface scan of the silicon wafer or silicon substrate is performed by a terahertz offline two-dimensional imaging device (FalconWave-S) or a four-probe tester, and a line from the center point to the edge of the silicon wafer or silicon substrate is selected to obtain the average resistivity value Rv on the selected line and the resistivity value per 1 μm on the selected line, that is, Ri (i=1, 2, 3...), and the resistivity shift rate is The average resistivity shift rate can be obtained by averaging the values ​​of the selected i points on the selected line. Furthermore, it is fully understood by those skilled in the art that the black line shown in FIG1 is merely for convenience, and that any line can be drawn on the silicon wafer or silicon substrate to detect the resistivity change rate of the silicon wafer or silicon substrate.

[0094] In the present application, the surface square resistance change rate characterizes the ratio of the square resistance change between any positions on the surface of an object. For example, the surface square resistance change rate of a silicon substrate refers to the maximum value of the square resistance at any multiple sites on the doped surface of the silicon substrate minus the minimum value and divided by the average value of the square resistance of any multiple sites on the silicon substrate. For example, a person skilled in the art can arbitrarily select any site on the doped surface for detection, use a four-probe square resistance resistivity tester to detect, analyze the square resistance of the n sites tested, select the maximum value, minimum value and average value therefrom, and calculate. A person skilled in the art can also fully understand that n is a positive integer greater than or equal to 2, but can generally be, for example, a positive integer greater than 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95 or 100. In actual operation, the result calculated by the following method can be used as the surface square resistance change rate of the silicon substrate. First, the five points shown in Figure 2 are obtained for the doped silicon substrate, and the square resistance of the five points is detected using a four-probe square resistance resistivity tester. The average square resistance value Fv of the five points is calculated, and the maximum square resistance value Fmax and the minimum resistivity value Fmin among the five points are obtained. The square resistance change rate is (Fmax-Fmin) / Fv.

[0095] In this application, the mechanical strength test method of silicon wafers or silicon substrates is based on GB / T 6569-2006, Test Method for Bending Strength of Fine Ceramics. In the test method used, bending strength refers to the maximum stress at which a material breaks under bending load.

[0096] Those skilled in the art will fully understand that the above-mentioned inspection of silicon wafers or silicon substrates can be conducted on silicon wafers or silicon substrates of any size, on bare silicon wafers obtained by cutting after the silicon rod is drawn, or on silicon substrates after other layer structures are recovered from cells or modules. As long as the inspection results obtained after the inspection are conducted according to the method described in this application, they should be considered to be covered within the scope of the silicon wafers, solar cells, cell strings or solar modules claimed for protection in this application.

[0097] In this application, the method for detecting whether a silicon wafer or silicon substrate contains a certain element can be detected by SIMS, ICP-MS, GDMS and the like, preferably by ICP-MS to detect metal elements. In this application, solar cells are also referred to as batteries.

[0098] In a specific embodiment of the present application, antimony is doped only as a Group V doping element in a silicon wafer (e.g., a bare silicon wafer) or silicon substrate of the present application to replace phosphorus. In this case, those skilled in the art will appreciate that, depending on the source of the silicon wafer raw material, the silicon wafer or silicon substrate itself may contain other elements, such as any one, two, or three of phosphorus, gallium, and germanium, but only antimony is actively doped as a Group V doping element to replace phosphorus.

[0099] The present application provides a silicon wafer (sometimes also referred to as a bare silicon wafer in this application), wherein the concentration of antimony in the silicon wafer is 1E+12cm -3 to 2E+16cm -3 , preferably 4E+14cm -3 to 2E+16cm -3 , and the resistivity change rate of the silicon wafer is ≤0.8. For example, the concentration of antimony in the silicon wafer can be 1E+12cm -3 、1.1E+12cm -3 、1.2E+12cm -3 、1.3E+12cm -3 、1.4E+12cm -3 、1.5E+12cm -3 、1.6E+12cm -3 、1.7E+12cm -3 、1.8E+12cm -3 、1.9E+12cm -3 、2E+12cm -3 , 2.1E+12cm -3 , 2.2E+12cm -3 、2.3E+12cm -3 、2.4E+12cm -3 、2.5E+12cm -3 、2.6E+12cm -3 、2.7E+12cm -3 、2.8E+12cm -3 、2.9E+12cm -3 、3E+12cm -3 、3.1E+12cm -3 、3.2E+12cm -3 、3.3E+12cm -3 、3.4E+12cm -3 、3.5E+12cm -3 、3.6E+12cm -3 、3.7E+12cm -3 、3.8E+12cm-3 、3.9E+12cm -3 、4E+12cm -3 、4.1E+12cm -3 、4.2E+12cm -3 、4.3E+12cm -3 、4.4E+12cm -3 、4.5E+12cm -3 、4.6E+12cm -3 、4.7E+12cm -3 、4.8E+12cm -3 、4.9E+12cm -3 、5E+12cm -3 、5.1E+12cm -3 、5.2E+12cm -3 、5.3E+12cm -3 、5.4E+12cm -3 、5.5E+12cm -3 、5.6E+12cm -3 、5.7E+12cm -3 、5.8E+12cm -3 、5.9E+12cm -3 、6E+12cm -3 、6.1E+12cm -3 、6.2E+12cm -3 、6.3E+12cm -3 、6.4E+12cm -3 、6.5E+12cm -3 、6.6E+12cm -3 、6.7E+12cm -3 、6.8E+12cm -3 、6.9E+12cm -3 、7E+12cm -3 、7.1E+12cm -3 、7.2E+12cm -3 、7.3E+12cm -3 、7.4E+12cm -3 、7.5E+12cm -3 、7.6E+12cm -3 、7.7E+12cm -3 、7.8E+12cm -3 、7.9E+12cm -3 、8E+12cm -3 、8.1E+12cm -3 、8.2E+12cm-3 、8.3E+12cm -3 、8.4E+12cm -3 、8.5E+12cm -3 、8.6E+12cm -3 、8.7E+12cm -3 、8.8E+12cm -3 、8.9E+12cm -3 、9E+12cm -3 、9.1E+12cm -3 、9.2E+12cm -3 、9.3E+12cm -3 、9.4E+12cm -3 、9.5E+12cm -3 、9.6E+12cm -3 、9.7E+12cm -3 、9.8E+12cm -3 、9.9E+12cm -3 、1E+13cm -3 、1.1E+13cm -3 、1.2E+13cm -3 、1.3E+13cm -3 、1.4E+13cm -3 、1.5E+13cm -3 、1.6E+13cm -3 、1.7E+13cm -3 、1.8E+13cm -3 、1.9E+13cm -3 、2E+13cm -3 、2.1E+13cm -3 、2.2E+13cm -3 、2.3E+13cm -3 、2.4E+13cm -3 、2.5E+13cm -3 、2.6E+13cm -3 、2.7E+13cm -3 、2.8E+13cm -3 、2.9E+13cm -3 、3E+13cm -3 、3.1E+13cm -3 、3.2E+13cm -3 、3.3E+13cm -3 、3.4E+13cm -3 、3.5E+13cm -3、3.6E+13cm -3 、3.7E+13cm -3 、3.8E+13cm -3 、3.9E+13cm -3 、4E+13cm -3 、4.1E+13cm -3 、4.2E+13cm -3 、4.3E+13cm -3 、4.4E+13cm -3 、4.5E+13cm -3 、4.6E+13cm -3 、4.7E+13cm -3 、4.8E+13cm -3 、4.9E+13cm -3 、5E+13cm -3 、5.1E+13cm -3 、5.2E+13cm -3 、5.3E+13cm -3 、5.4E+13cm -3 、5.5E+13 cm -3 、5.6E+13cm -3 、5.7E+13cm -3 、5.8E+13cm -3 、5.9E+13cm -3 、6E+13cm -3 、6.1E+13cm -3 、6.2E+13cm -3 、6.3E+13cm -3 、6.4E+13cm -3 、6.5E+13cm -3 、6.6E+13cm -3 、6.7E+13cm -3 、6.8E+13cm -3 、6.9E+13cm -3 、7E+13cm -3 、7.1E+13cm -3 、7.2E+13cm -3 、7.3E+13cm -3 、7.4E+13cm -3 、7.5E+13cm -3 、7.6E+13cm -3 、7.7E+13cm -3 、7.8E+13cm -3 、7.9E+13cm-3 、8E+13cm -3 、8.1E+13cm -3 、8.2E+13cm -3 、8.3E+13cm -3 、8.4E+13cm -3 、8.5E+13cm -3 、8.6E+13cm -3 、8.7E+13cm -3 、8.8E+13cm -3 、8.9E+13cm -3 、9E+13cm -3 、9.1E+13cm -3 、9.2E+13cm -3 、9.3E+13cm -3 、9.4E+13cm -3 、9.5E+13cm -3 、9.6E+13cm -3 、9.7E+13cm -3 、9.8E+13cm -3 、9.9E+13cm -3 、1E+14cm -3 、1.1E+14cm -3 、1.2E+14cm -3 、1.3E+14cm -3 、1.4E+14cm -3 、1.5E+14cm -3 、1.6E+14cm -3 、1.7E+14cm -3 、1.8E+14cm -3 、1.9E+14cm -3 、2E+14cm -3 、2.1E+14cm -3 、2.2E+14cm -3 、2.3E+14cm -3 、2.4E+14cm -3 、2.5E+14cm -3 、2.6E+14cm -3 、2.7E+14cm -3 、2.8E+14cm -3 、2.9E+14cm -3 、3E+14cm -3 、3.1E+14cm -3 、3.2E+14cm -3 、3.3E+14cm-3 、3.4E+14cm -3 、3.5E+14cm -3 、3.6E+14cm -3 、3.7E+14cm -3 、3.8E+14cm -3 、3.9E+14cm -3 、4E+14cm -3 、4.1E+14cm -3 、4.2E+14cm -3 、4.3E+14cm -3 、4.4E+14cm -3 、4.5E+14cm -3 、4.6E+14cm -3 、4.7E+14cm -3 、4.8E+14cm -3 、4.9E+14cm -3 、5E+14cm -3 、5.1E+14cm -3 、5.2E+14cm -3 、5.3E+14cm -3 、5.4E+14cm -3 、5.5E+14cm -3 、5.6E+14cm -3 、5.7E+14cm -3 、5.8E+14cm -3 、5.9E+14cm -3 、6E+14cm -3 、6.1E+14cm -3 、6.2E+14cm -3 、6.3E+14cm -3 、6.4E+14cm -3 、6.5E+14cm -3 、6.6E+14cm -3 、6.7E+14cm -3 、6.8E+14cm -3 、6.9E+14cm -3 、7E+14cm -3 、7.1E+14cm -3 、7.2E+14cm -3 、7.3E+14cm -3 、7.4E+14cm -3 、7.5E+14cm -3 、7.6E+14cm -3、7.7E+14cm -3 、7.8E+14cm -3 、7.9E+14cm -3 、8E+14cm -3 、8.1E+14cm -3 、8.2E+14cm -3 、8.3E+14cm -3 、8.4E+14cm -3 、8.5E+14cm -3 、8.6E+14cm -3 、8.7E+14cm -3 、8.8E+14cm -3 、8.9E+14cm -3 、9E+14cm -3 、9.1E+14cm -3 、9.2E+14cm -3 、9.3E+14cm -3 、9.4E+14cm -3 、9.5E+14cm -3 、9.6E+14cm -3 、9.7E+14cm -3 、9.8E+14cm -3 、9.9E+14cm -3 、1E+15cm -3 、1.1E+15cm -3 、1.2E+15cm -3 、1.3E+15cm -3 、1.4E+15cm -3 、1.5E+15cm -3 、1.6E+15cm -3 、1.7E+15cm -3 、1.8E+15cm -3 、1.9E+15cm -3 、2E+15cm -3 、2.1E+15cm -3 、2.2E+15cm -3 、2.3E+15cm -3 、2.4E+15cm -3 、2.5E+15cm -3 、2.6E+15cm -3 、2.7E+15cm -3 、2.8E+15cm -3 、2.9E+15cm -3 、3E+15cm -3、3.1E+15cm -3 、3.2E+15cm -3 、3.3E+15cm -3 、3.4E+15cm -3 、3.5E+15cm -3 、3.6E+15cm -3 、3.7E+15cm -3 、3.8E+15cm -3 、3.9E+15cm -3 、4E+15cm -3 、4.1E+15cm -3 、4.2E+15cm -3 、4.3E+15cm -3 、4.4E+15 cm -3 、4.5E+15cm -3 、4.6E+15cm -3 、4.7E+15cm -3 、4.8E+15cm -3 、4.9E+15cm -3 、5E+15cm -3 、5.1E+15cm -3 、5.2E+15cm -3 、5.3E+15cm -3 、5.4E+15cm -3 、5.5E+15cm -3 、5.6E+15cm -3 、5.7E+15cm -3 、5.8E+15cm -3 、5.9E+15cm -3 、6E+15cm -3 、6.1E+15cm -3 、6.2E+15cm -3 、6.3E+15cm -3 、6.4E+15cm -3 、6.5E+15cm -3 、6.6E+15cm -3 、6.7E+15cm -3 、6.8E+15cm -3 、6.9E+15cm -3 、7E+15cm -3 、7.1E+15cm -3 、7.2E+15cm -3 、7.3E+15cm -3 、7.4E+15cm-3 、7.5E+15cm -3 、7.6E+15cm -3 、7.7E+15cm -3 、7.8E+15cm -3 、7.9E+15cm -3 、8E+15cm -3 、8.1E+15cm -3 、8.2E+15cm -3 、8.3E+15cm -3 、8.4E+15cm -3 、8.5E+15cm -3 、8.6E+15cm -3 、8.7E+15cm -3 、8.8E+15cm -3 、8.9E+15cm -3 、9E+15cm -3 、9.1E+15cm -3 、9.2E+15cm -3 、9.3E+15cm -3 、9.4E+15cm -3 、9.5E+15cm -3 、9.6E+15cm -3 、9.7E+15cm -3 、9.8E+15cm -3 、9.9E+15cm -3 、1E+16cm -3 、1.1E+16cm -3 、1.2E+16cm -3 、1.3E+16cm -3 、1.4E+16cm -3 、1.5E+16cm -3 、1.6E+16cm -3 、1.7E+16cm -3 、1.8E+16cm -3 、1.9E+16cm -3 、2E+16cm -3 , and any ranges between these values.

[0100] In a specific embodiment, the concentration of antimony in the silicon wafer is 4.3E+14 cm -3 to 1.9E+16cm -3 In a specific embodiment, the concentration of antimony in the silicon wafer is 4.45E+14cm -3 to 1.87E+16cm-3 .

[0101] Those skilled in the art will understand that the concentrations of antimony listed above may have certain detection deviations due to differences in the specific detection instruments used and the different detection batches. That is, for any of the values ​​listed above, it can be considered that they can fluctuate within the range of ±0.2. For example, 4E+14cm -3 , can be at 3.8E+14cm -3 to 4.2E+14cm -3 Floating within the range of 2E+16cm -3 Can be at 1.8E+16cm -3 to 2.2E+16cm -3 This applies to any range of values.

[0102] In a specific embodiment, the resistivity of the silicon wafer is 0.3 to 1000 Ω·cm, for example, 0.3 Ω·cm, 0.4 Ω·cm, 0.5 Ω·cm, 0.6 Ω·cm, 0.7 Ω·cm, 0.8 Ω·cm, 0.9 Ω·cm, 1 Ω·cm, 1.1 Ω·cm, 1.2 Ω·cm, 1.3 Ω·cm, 1.4 Ω·cm, 1.5 Ω·cm, 1.6 Ω·cm, 1.7 Ω·cm, 1.8 Ω·cm, 1.9 Ω·cm, 2 Ω·cm, 2 Ω·cm, 2.5 Ω·cm, 3 Ω·cm, 3.5 Ω·cm, 4 Ω·cm, 4.5 Ω·cm, 5 Ω·cm, 5.5 Ω·cm, 6 Ω·cm, 6.5 Ω·cm, 7Ω·cm, 7.5Ω·cm, 8Ω·cm, 8.5Ω·cm, 9Ω·cm, 9.5Ω·cm, 10Ω·cm, 15Ω·cm, 20Ω·cm, 25Ω·cm, 30Ω·cm, 35Ω·cm, 40Ω·cm, 45Ω·cm, 50Ω·cm, 55Ω·cm, 60Ω·cm, 65Ω·c m, 70Ω·cm, 75Ω·cm, 80Ω·cm, 85Ω·cm, 90Ω·cm, 95Ω·cm, 100Ω·cm, 150Ω·cm, 200Ω·cm, 250Ω·cm, 300Ω·cm, 350Ω·cm, 400Ω·cm, 450Ω·cm, 500Ω·cm, 550Ω·cm, 600Ω·cm, 650Ω·cm, 700Ω·cm, 750Ω·cm, 800Ω·cm, 850Ω·cm, 900Ω·cm, 950Ω·cm, 1000Ω·cm, and any range therebetween.

[0103] In a specific embodiment, the resistivity of the silicon wafer is 0.3 to 100 Ω·cm. The resistivity here can be the resistivity of any point on the silicon wafer. In a specific embodiment, the resistivity of the silicon wafer is 0.3 to 10 Ω·cm. In a specific embodiment, the resistivity of the silicon wafer is 0.4 to 8 Ω·cm. In a specific embodiment, the resistivity of the silicon wafer is 0.5 to 6 Ω·cm.

[0104] In a specific embodiment, the resistivity change rate of the silicon wafer can be, for example, 0.8, 0.79, 0.78, 0.77, 0.76, 0.75, 0.74, 0.73, 0.72, 0.71, 0.7, 0.69, 0.68, 0.67, 0.66, 0.65, 0.64, 0.63, 0.62, 0.61, 0.6, 0.59, 0.58, 0.57, 0.56, 0.55, 0.54, 0.53, 0.52, 0.51, 0.5, 0.49, 0.48, 0.47, 0.46, 0.45 , 0.44, 0.43, 0.42, 0.41, 0.4, 0.39, 0.38, 0.37, 0.36, 0.35, 0.34, 0.33, 0.32, 0.31, 0.3, 0.29, 0.28, 0.27, 0.26, 0.25, 0.24, 0.23, 0.22, 0.21, 0.2, 0.19, 0.18, 0.17, 0.16, 0.15, 0.14, 0.13, 0.12, 0.11, 0.1, 0.05, 0.02, 0.01, and any range therebetween.

[0105] In a specific embodiment, the resistivity change rate of the silicon wafer is ≤0.5. In a specific embodiment, the resistivity change rate of the silicon wafer is ≤0.4. In a specific embodiment, the resistivity change rate of the silicon wafer is 0.01-0.6. In a specific embodiment, the resistivity change rate of the silicon wafer is 0.01-0.5. In a specific embodiment, the resistivity change rate of the silicon wafer is 0.01-0.4. In a specific embodiment, the resistivity change rate of the silicon wafer is 0.1-0.6. In a specific embodiment, the resistivity change rate of the silicon wafer is 0.1-0.5. In a specific embodiment, the resistivity change rate of the silicon wafer is 0.1-0.4. In a specific embodiment, the resistivity change rate of the silicon wafer is 0.01-0.6. In a specific embodiment, the resistivity change rate of the silicon wafer is 0.01-0.5. In a specific embodiment, the resistivity change rate of the silicon wafer is 0.01-0.4.

[0106] In a specific embodiment, the average resistivity deviation rate of the silicon wafer is ≤8%, for example, it can be 5%, 4.9%, 4.8%, 4.7%, 4.6%, 4.5%, 4.3%, 4.2%, 4.1%, 4%, 3.9%, 3.8%, 3.7%, 3.6%, 3.5%, 3.3%, 3.2%, 3.1%, 3%, 2.9%, 2.8%, 2.7%, 2.6%, 2.5%, 2.3%, 2.2%, 2.1%, 2%, 1.9%, 1.8%, 1.7%, 1.6%, 1.5%, 1.3%, 1.2%, 1.1%, 1%, 0.9%, 0.8%, 0.7%, 0.6%, 0.5%, 0.3%, 0.2%, 0.1%, and any range therebetween. In a specific embodiment, the average offset rate of the resistivity of the silicon wafer is ≤5%. In a specific embodiment, the average offset rate of the resistivity of the silicon wafer is ≤4.5%. In a specific embodiment, the average offset rate of the resistivity of the silicon wafer is ≤4%. In a specific embodiment, the average offset rate of the resistivity of the silicon wafer is 0.1%-5%. In a specific embodiment, the average offset rate of the resistivity of the silicon wafer is 1%-5%. In a specific embodiment, the average offset rate of the resistivity of the silicon wafer is 0.1%-4.5%. In a specific embodiment, the average offset rate of the resistivity of the silicon wafer is 1%-4.5%. In a specific embodiment, the average offset rate of the resistivity of the silicon wafer is 0.1%-4%. In a specific embodiment, the average offset rate of the resistivity of the silicon wafer is 1%-4%.

[0107] In a specific embodiment, the concentration of antimony in the silicon wafer is 1E+12 cm -3 to 2E+16cm -3 , resistivity change rate ≤ 0.8, resistivity average deviation rate ≤ 8%. In a specific embodiment, the concentration of antimony in the silicon wafer is 4E+14cm -3 to 2E+16cm -3 , resistivity change rate ≤ 0.6, resistivity average deviation rate ≤ 5%. In a specific embodiment, the concentration of antimony in the silicon wafer is 4.30E+14cm -3 to 1.9E+16cm -3 , resistivity change rate ≤ 0.5, resistivity average deviation rate ≤ 4.5%. In a specific embodiment, the concentration of antimony in the silicon wafer is 4.45E+14cm -3 to 1.87E+16cm -3 , resistivity change rate ≤ 0.4, resistivity average deviation rate 4%. In a specific embodiment, the concentration of antimony in the silicon wafer is 4.45E+14cm -3 to 1.87E+16cm -3, the resistivity change rate is 0.1-0.4, and the average resistivity deviation rate is 1%-4%.

[0108] Because the excessively high doping concentration of antimony will lead to an increase in the recombination of carriers (electrons and holes), the minority carrier lifetime will be reduced, and the collection efficiency of the photocurrent will be reduced. The low doping concentration, that is, the poor conductivity of the high-resistivity material, will cause greater resistance to be encountered during the battery current transmission process, and the efficiency will be reduced. In the present application, by reasonably controlling the concentration of antimony in the above-mentioned silicon wafer, a balance between the minority carrier lifetime and the transmission resistance is achieved, combined with the uniform doping of antimony, so that the resistivity of the silicon wafer or the bare silicon wafer itself is uniform, the resistivity change rate is small, and the average offset rate of the resistivity is small. The battery prepared by such a silicon wafer can reduce the lateral and longitudinal transmission resistance of the carrier, thereby ultimately achieving an increase in battery efficiency. In addition, the silicon wafer of the present application has a high minority carrier lifetime, the short-circuit current of the prepared battery is improved, and the battery efficiency is further improved.

[0109] In a specific embodiment, the silicon wafer provided by the present application can be used as a silicon substrate for various types of solar cells. Various types of solar cells include aluminum back surface field cells (A1-BSF), passivated emitter and back contact cells (PERC), metal wrap-through cells (MWT); passivated emitter back localized diffused cells (PERL), passivated emitter back fully diffused cells (PERT), emitter wrap-through cells (EWT), tunneling oxide passivated cells (TOPCon), interdigitated back contact cells (IBC), crystalline silicon heterojunction cells (HJT / HIT), and full back electrode back contact heterojunction cells (HBC).

[0110] Another aspect of the present application relates to a solar cell, which includes the case where the silicon wafer described in detail in the present application is used in a solar cell, and the detailed description of the silicon wafer is basically applicable. Specifically, the solar cell of the present application includes a silicon substrate, wherein the silicon substrate is formed by the silicon wafer provided by the present application, and there is a doped region on at least one side surface of the silicon substrate, the silicon substrate contains antimony element, the doped region is doped with a doping element, the doping element is selected from the third main group element or the fifth main group element, and the concentration of the antimony element in the silicon substrate is 1E+12cm -3 to 2E+16cm -3 , preferably 4E+14cm -3 to 2E+16cm -3 , preferably 4.3E+14cm -3 to 1.9E+16cm -3 ; More preferably 4.45E+14cm -3 to 1.87E+16cm -3; The resistivity change rate of the silicon substrate is ≤0.8; the optional resistivity change rate is ≤0.6; the optional resistivity change rate is ≤0.5; the optional resistivity change rate is ≤0.4.

[0111] Those skilled in the art will understand that the above-mentioned silicon substrate is the structure formed after the silicon wafer provided in this application is prepared into a cell. Those skilled in the art will understand that the above-mentioned solar cell covers all solar cells that can be applied to the silicon wafer of this application, such as crystalline silicon heterojunction cells (HJT / HIT), full back electrode back contact heterojunction cells (HBC), TOPCon cells, partial TOPCon cells, back contact hybrid cells and TBC cells, as well as any cell form familiar to those skilled in the art.

[0112] In the above-mentioned battery form, at least one doped layer is provided on the surface of at least one side of the above-mentioned silicon substrate. Specifically, depending on the different battery forms, the doped layer can be selected based on the needs, for example, it can be an n-type amorphous or polycrystalline silicon carbide layer, such as phosphorus-doped silicon carbide or nitrogen-doped silicon carbide; it can be n-type amorphous or polycrystalline silicon, such as phosphorus-doped amorphous silicon or nitrogen-doped phosphorus-doped silicon; it can also be n-type amorphous or polycrystalline diamond-like carbon, such as nitrogen-doped diamond-like carbon. Those skilled in the art can make their selection based on their needs, and as long as the requirements of this application are met, at least a portion of the surface of at least one side of the silicon substrate can have one doped layer, and other regions can have another doped layer.

[0113] In the above-mentioned battery configuration, at least one passivation layer is provided between the above-mentioned doped layer and the doped region of the above-mentioned silicon substrate. Specifically, depending on the different battery configurations, the passivation layer can be selected based on requirements. Generally, the thickness of the passivation layer should be less than 10 nm. Due to the very small thickness, there is no requirement for the conductivity of the passivation layer. Due to the small thickness, there is no absorption limitation. Commonly used passivation layers include silicon oxide, silicon nitride, intrinsic amorphous silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride, etc. Those skilled in the art can fully select based on their needs, as long as the requirements of this application are met.

[0114] In one specific embodiment, the solar cell is a heterojunction cell, such as a crystalline silicon heterojunction cell (HJT / HIT) or a full back electrode back contact heterojunction cell (HBC). When the silicon wafer of the present application forms a silicon substrate for use as a heterojunction cell or a full back electrode back contact heterojunction cell, even after a heterojunction layer is stacked on the silicon substrate, the antimony concentration and resistivity change rate described in detail for the silicon wafer are still met, that is, after the heterojunction layer is stacked, the antimony concentration in the silicon substrate is 1E+12cm -3 to 2E+16cm -3, and the resistivity change rate of the light absorber is ≤0.8. All the above descriptions on the antimony concentration and resistivity change rate in the silicon wafer are applicable to this method.

[0115] For crystalline silicon heterojunction cells (HJT / HIT) and full back electrode back contact heterojunction cells (HBC), an intrinsic amorphous silicon layer and a doped amorphous silicon layer are usually further stacked on the silicon substrate of the present application, wherein the intrinsic amorphous silicon layer serves as a passivation layer. Due to the characteristics of the Sb element itself, the antimony element in the silicon substrate will not pass through the passivation layer into the doped amorphous silicon layer. The doped amorphous silicon layer basically does not contain Sb, that is, the silicon substrate contains antimony element, while the doped amorphous silicon layer or the intrinsic amorphous silicon layer contains doping elements but does not contain Sb.

[0116] More specifically, for crystalline silicon heterojunction cells (HJT / HIT) and full back electrode back contact heterojunction cells (HBC), the concentration of antimony in the silicon substrate is 4E+14cm -3 to 2E+16cm -3 , and the resistivity change rate of the light absorber is ≤0.6. More specifically, the concentration of antimony in the silicon substrate is 4.3E+14cm -3 to 1.9E+16cm -3 ; The resistivity change rate of the silicon substrate is ≤0.5. More specifically, the concentration of antimony in the silicon substrate is 4.45E+14cm -3 to 1.87E+16cm -3 ; The resistivity change rate of the above-mentioned silicon substrate is ≤0.4.

[0117] In a specific embodiment, when the solar cell is a TOPCon cell, a local TOPCon cell, a back contact hybrid cell, and a TBC cell, the solar cell of the present application includes a silicon substrate, a doped region is formed in at least one side surface of the silicon substrate, the entire silicon substrate contains antimony, and the doped region is doped with a doping element, the doping element is selected from the third main group element or the fifth main group element, and the concentration of the antimony element in the silicon substrate is 1E+12cm -3 to 2E+16cm -3 , preferably 4E+14cm -3 to 2E+16cm -3 , preferably 4.3E+14cm -3 to 1.9E+16cm -3 ; More preferably 4.45E+14cm -3 to 1.87E+16cm -3 ; The resistivity change rate of the above-mentioned silicon substrate is ≤0.8; the optional resistivity change rate is ≤0.6; the optional resistivity change rate is ≤0.5; the optional resistivity change rate is ≤0.4.

[0118] More specifically, for TOPCon cells, local TOPCon cells, back contact hybrid cells, and TBC cells, the concentration of antimony in the silicon substrate is 4.3E+14 cm -3 to 1.9E+16cm -3 ; The resistivity change rate of the silicon substrate is ≤0.5. More specifically, the concentration of antimony in the silicon substrate is 4.45E+14cm -3 to 1.87E+16cm -3 ; The resistivity change rate of the above-mentioned light absorber is ≤0.4.

[0119] In a specific embodiment, for TOPCon cells, local TOPCon cells, back contact hybrid cells and TBC cells, the doped region contains doping elements as described above, and the concentration of antimony elements in the doped region in the thickness direction of the silicon substrate is basically unchanged. In this way, the crystalline silicon lattice distortion caused by single element doping can be overcome, resulting in many defects in the heavily doped region, and light absorption can also be improved to improve cell efficiency. Those skilled in the art will understand that for TOPCon cells, local TOPCon cells, back contact hybrid cells and TBC cells, the doped region in this application refers to the region formed by direct doping inside the raw silicon wafer or indirectly doped through other layer structures. Therefore, in this case, the doped region is formed in the silicon substrate by the doping elements entering the silicon wafer. An interface passivation layer and a doped passivation layer can be further laminated on the surface of at least one side of the silicon substrate. In addition, those skilled in the art will also understand that as long as the solar cell structure has the structure described in detail in this application, the difference in its name also falls within the scope of protection of this application.

[0120] In this application, an interfacial passivation layer refers to a layer that has a passivating effect and allows the passage of dopant elements, such as a tunneling layer. A doped passivation layer is a layer that forms a PN junction or a high-low junction with the silicon substrate. Examples include a doped amorphous silicon layer and a doped polysilicon layer.

[0121] In the present application, essentially unchanged means that the concentration of antimony elements in the thickness direction of the silicon substrate of the present application is uniform. Although the specific values ​​may vary to a certain extent with the change of the detection site, the overall difference in antimony concentration in the thickness direction will not exceed 50%, 40%, 30%, or 20%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1%, that is, the difference between the maximum value and the minimum value will not exceed 50%, 40%, 30%, or 20%, 15%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1% of the minimum value.

[0122] Those skilled in the art will understand that, depending on the different application requirements of the silicon wafer, for example, when the silicon wafer is used in various solar cells, the silicon wafer can be further doped with multiple doping elements to form one or more doping regions. These doping elements can be Group III elements, such as boron, aluminum, gallium, indium, and thallium, or Group V elements, such as nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0123] In this application, the antimony concentration, resistivity, resistivity change rate, and resistivity average shift rate described for the above-mentioned silicon wafer are also applicable to the silicon substrate that has been installed in the solar cell as part of the light absorber. In this case, the above-mentioned parameters described for the antimony concentration, resistivity, resistivity change rate, and resistivity average shift rate in the silicon wafer are applicable to the entire silicon substrate, that is, they are applicable to the body region that contains only antimony doping, the doped region, and the entire body and doped regions. Those skilled in the art will understand that when the above-mentioned tests are performed only on the body region, the results of the antimony concentration, resistivity, resistivity change rate, and resistivity average shift rate measured or calculated are within the scope of the above-mentioned detailed description of this application. When the above-mentioned tests are performed only on the doped region, the results of the antimony concentration, resistivity, resistivity change rate, and resistivity average shift rate measured or calculated are within the scope of the above-mentioned detailed description of this application. When the boundaries between the doped region and the body region are ignored and the above-mentioned results are tested at any location on the entire silicon substrate, the above-mentioned results can also be obtained.

[0124] In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is ≤0.6. In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is ≤0.4. In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is ≤0.3. In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is ≤0.2. In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is 0.001-0.6. In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is 0.001-0.4. In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is 0.001-0.3. In a specific embodiment, the surface square resistance change rate of the optical silicon substrate surface is 0.001-0.2. In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is 0.01-0.6. In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is 0.01-0.4. In a specific embodiment, the surface square resistance change rate of the silicon substrate surface is 0.01-0.3. In a specific embodiment, the surface resistance change rate of the silicon substrate is 0.01-0.2.

[0125] In a specific embodiment, the doping element can be doped into the doping region by direct doping, that is, the doping element is doped directly into the doping region without passing through other layer structures of the battery. The direct doping method can also be various methods known in the art, such as thermal diffusion, ion implantation, or coating a slurry containing a dopant and incorporating the dopant by a driving force (such as heat treatment, laser, etc.). Those skilled in the art can choose according to their needs. It also includes the case where aluminum is diffused into the silicon wafer through aluminum grid lines through heat treatment.

[0126] In a specific manner, in addition to the above-mentioned direct doping, the doping element can be doped into the doping region in such a way that the doping element passes through the layer structure stacked on the silicon wafer or silicon substrate and is doped into the silicon wafer or silicon substrate to form the above-mentioned doping region. Those skilled in the art will understand that, according to different application scenarios of the silicon wafer, such as when used in different solar cells, the layer structure can be adjusted accordingly. For example, the layer structure may itself contain a dopant that provides the doping element, and the doping element is doped through the layer structure. The layer structure itself may also not contain a dopant, but the adjacent area has an atmosphere that can provide the doping element, and is doped into the silicon wafer through the layer structure to form a doping region by, for example, thermal diffusion, ion implantation, etc. The above-mentioned atmosphere that can provide the doping element can be a gas atmosphere (such as a gas containing a dopant), a liquid (such as a slurry containing a dopant), or a solid (such as a layer including a dopant, such as a doped passivation layer, especially a doped polysilicon layer).

[0127] The layer structure can be a single layer (e.g., a passivation layer or tunneling layer) or multiple layers, such as a passivation layer and a doped layer. The layer structure can be a natural oxide layer formed by natural oxidation on a silicon substrate. Alternatively, the layer structure can be made of intrinsic amorphous silicon, i.e., intrinsic amorphous silicon is provided on one side of the silicon wafer to provide passivation.

[0128] Taking the TOPCon battery structure as an example, the layer structure may be a doped polysilicon layer (doped passivation layer), a tunneling layer (interface passivation layer), or a doped polysilicon layer and a tunneling layer acting together as a layer structure. Those skilled in the art will fully understand that the above enumeration is only illustrative, and both direct doping and doping via a layer structure are optional, and direct doping and doping via a layer structure can be targeted at a local part of one side of the silicon wafer, such as doping elements by direct doping locally, while stacking TOPCon structures on other areas of the side surface to form a local TOPCon structure or a back-contact hybrid battery with a TOPCon structure. Or even one TOPCon structure can be used locally, and another TOPCon structure can be used in other locations to achieve doping separately, such as forming a TBC battery.

[0129] Those skilled in the art will understand that in the case of a TOPCon structure, a tunneling layer and a doped polysilicon layer are further stacked on the silicon substrate, and the concentration of antimony in the silicon substrate is 1E+12cm -3 to 2E+16cm -3 , preferably 4E+14cm -3 to 2E+16cm -3 , preferably 4.3E+14cm -3 to 1.9E+16cm -3 ; More preferably 4.45E+14cm -3 to 1.87E+16cm -3 ; The resistivity change rate of the silicon substrate is ≤0.8; the optional resistivity change rate is ≤0.6; the optional resistivity change rate is ≤0.5; the optional resistivity change rate is ≤0.4.

[0130] In a specific embodiment, in the case of direct doping, within a range of a thickness of h from the surface of the doped region away from the silicon substrate (i.e., the doping depth of the directly doped region), the concentration of the doping element is greater than the concentration of the antimony element on the surface and at the same depth from the surface. Furthermore, in the doped region, the sum of the concentration of the antimony element and the concentration of the doping element is less than or equal to 1.00E+21. The battery of the present application, because the range of the sum of the concentration of the antimony element and the concentration of the doping element in the doped region is controlled, is conducive to carrier separation, while reducing carrier recombination and improving short-circuit current and open-circuit voltage.

[0131] In a specific embodiment, the doping element is a third main group element, and the range of h is 30 to 650 nm. In a specific embodiment, the doping element is a third main group element, and the range of h is greater than or equal to 400 nm. In a specific embodiment, the doping element is a third main group element, and the range of h is 30 nm to 100 nm. In a specific embodiment, the doping element is a fifth main group element, and the range of h is 100 to 200 nm. As described above, the maximum range at the same depth from the surface should be the thickness h. For example, when the depth is 0, it is the concentration on the surface of the doping region. When the depth is 100 nm, for example, the concentration of the doping element is greater than the concentration of the antimony element at a position 100 nm from the surface. In a specific embodiment, as shown in FIG3 , the surface away from the silicon substrate side of the doping region is the front side of the doping region 2.

[0132] In a specific embodiment, the doping element is boron, and h is in the range of 30 to 650 nm or in the range of 30 nm to 100 nm. When only local doping is performed, only the location of the local doping needs to satisfy the above relationship.

[0133] In the present application, since the thickness of the doped region formed by direct doping in the silicon substrate of the solar cell is controlled, it is beneficial to the separation of carriers, while reducing carrier recombination and improving the short-circuit current and open-circuit voltage.

[0134] In some specific embodiments, if the thickness of the doping region formed by direct doping, for example, the thickness of the doping region in the case of doping the third main group elements, is further controlled to be even less than 100 nm or even less than 50 nm, the free carrier Auger recombination is further reduced and the short-circuit current is further improved.

[0135] In a specific embodiment, when diffusion is performed through a layer structure, within a range of a thickness of m from the surface of the doped region on the side remote from the silicon substrate (the depth of the doped region when diffusion is performed through a layer structure), the concentration of the doping element is greater than the concentration of the antimony element at the surface and at the same depth from the surface. In a specific embodiment, as shown in FIG3 , the surface of the doped region on the side remote from the silicon substrate is the back surface of the doped region 4.

[0136] In a specific manner, the doping element is a third main group element, and the range of m is 80 to 180 nm. In a specific embodiment, the doping element is a fifth main group element, and the range of m is 30 to 100 nm. As described above, the maximum range at the same depth from the surface should be less than or equal to m. For example, when the depth is 0, it is the concentration on the surface of the doped region. When the depth is 100 nm, for example, it can be at a position 100 nm from the surface, and the concentration of the doping element is greater than the concentration of the antimony element.

[0137] In a specific embodiment, the doping element is phosphorus, and m is in the range of 80 to 180 nm or in the range of 30 to 100 nm. When only local doping is performed, only the location of the local doping needs to satisfy the above relationship.

[0138] In the present application, the above-mentioned light absorber controls the thickness of the doped region formed by doping the layer structure, thereby retaining the passivation effect of the interface passivation layer and achieving effective doping of doped polysilicon, thereby increasing the short-circuit current and open-circuit voltage, and improving the efficiency of the battery.

[0139] In a specific embodiment, the solar cell of the present application is, for example, a tunneling oxide passivation cell (TOPCon cell), a local TOPCon cell, a back contact hybrid cell or a TBC cell.

[0140] In a specific embodiment, the typical structure of a TOPCon cell is shown in FIG3 , which includes, from the front to the back, a silicon substrate 1 (with a second doped region 2 and a first doped region 4 formed inside its two side surfaces), a tunneling layer 5, a doped polysilicon layer 6, a passivation layer or a high-transmission thin film layer 7, and an electrode 8. It is fully understood by those skilled in the art that although the structure of the TOPCon cell is described with the aid of FIG3 , the structure of the TOPCon cell is not limited to that of FIG3 , as long as a tunneling layer and a doped polysilicon layer are provided on the silicon substrate of the cell. The TOPCon structure can be formed on the entire silicon substrate or on at least a portion of the silicon substrate.

[0141] In a specific embodiment, the second doping region 2 is directly doped with boron, and the first doping region 4 is doped with phosphorus in the silicon substrate via the tunneling layer 5 and the doped polysilicon layer 6 .

[0142] A partial TOPCon cell refers to a cell in which a TOPCon structure (i.e., a first doped region, a tunneling layer, and a doped polysilicon layer) is formed in at least a portion of one side of the cell. The first doped region, the tunneling layer, and the doped polysilicon layer are located in the first partial region, while the rest of the cell is an additional doped region. The additional doped region and the first doped region are on the same surface, and the elements doped in the additional doped region and the first doped region have the same conductivity type. However, an element with an opposite conductivity type is doped on the other side to form a second doped region.

[0143] TBC battery refers to a battery with a TOPCon structure formed on the back side. There are two areas on the back side of this type of battery, each of which has a TOPCon structure with doping elements of opposite conductivity types.

[0144] A back-contact hybrid cell refers to a cell with a PERC or PERL structure in one region and a TOPCon structure in the other. For example, one region on the back has a TOPCon structure, and the other region has a PERL or PERC structure, and the two regions are doped with elements of opposite conductivity types. In some specific embodiments, when aluminum gate line doping is used, a metal layer is formed on the silicon substrate, and an alloy layer and a BSF layer are formed within the silicon substrate, where the BSF layer is the doped region. In this case, the surface of the BSF layer away from the silicon substrate on the side away from the doped region refers to the surface of the BSF layer away from the silicon substrate.

[0145] In a specific embodiment, the solar cell of the present application can be any one of the four types mentioned above, namely, TOPCon cells, local TOPCon cells, back-contact hybrid cells, and TBC cells. In these four types of cells, the doping element is doped into the silicon substrate through the layer structure on the silicon substrate to form the doped region. The doped region includes a first doping region and a second doping region. The layer structure on the silicon substrate includes a tunneling layer and a doped polysilicon layer stacked in sequence on the surface of the first doping region away from the silicon substrate. The first doping element is doped in the doped polysilicon layer, and the second doping region on the silicon substrate is also doped with the second doping element. The first doping region and the second doping region have opposite conductivity types.

[0146] In this application, the "first doping element" and the "second doping element" are different doping elements. For example, when the first doping element is a Group V element, the second doping element is a Group III element; when the first doping element is a Group III element, the second doping element is a Group V element.

[0147] In a specific embodiment, the first doping element is phosphorus, and the second doping element is boron.

[0148] When the solar cell of the present application is a TOPCon cell, a partial TOPCon cell, or a back-contact hybrid cell, the second doping region is a second doping element directly doped into the second doping region, wherein the first doping element is a Group V element (e.g., phosphorus) and the second doping element is a Group III element (e.g., boron).

[0149] In one specific embodiment, in the doped polysilicon layer, the concentration of the first doping element at a depth x (i.e., a first predetermined depth) from the surface of the doped polysilicon layer on the side away from the silicon substrate is greater than the concentration of the second doping element at a depth x (i.e., a first predetermined depth) from the surface of the second doping region. The thickness of the doped polysilicon layer ranges from 100 to 400 nm, where x is less than or equal to the thickness of the doped polysilicon layer. In this embodiment, since the concentration of the first doping element is greater than the concentration of the second doping element, free carrier Auger recombination can be further reduced, further improving short-circuit current. In one specific embodiment, in the tunneling layer, in the direction from the doped polysilicon layer to the tunneling layer, the concentration of the first doping element at a depth y (i.e., a second predetermined depth) from the surface of the doped polysilicon layer on the side away from the silicon substrate is greater than the concentration of the second doping element at a depth y (i.e., a second predetermined depth) from the surface of the second doping region. The thickness of the tunneling layer ranges from 0.5 to 5 nm, where y is less than or equal to the sum of the thicknesses of the doped polysilicon layer and the tunneling layer. In this method, since the concentration of the first doping element is greater than the concentration of the second doping element, the free carrier Auger recombination can be further reduced, and the short-circuit current can be further improved. On the other hand, the free carrier Auger recombination can be reduced without reducing the passivation effect of the tunneling layer, further improving the short-circuit current, open-circuit voltage, and improving battery efficiency. In a specific method, in the direction from the doped polysilicon layer to the surface of the above-mentioned first doping region, in the silicon substrate, the concentration of the first doping element at the z depth (i.e., the third preset depth) from the surface of the doped polysilicon layer away from the silicon substrate is greater than the concentration of the second doping element at the z depth (i.e., the third preset depth) from the surface of the second doping region, the thickness of the first doping region ranges from 30 to 100 nm, and z is less than or equal to the sum of the thicknesses of the doped polysilicon layer, the tunneling layer, and the first doping region. In this method, since the concentration of the first doping element is greater than the concentration of the second doping element, the free carrier Auger recombination can be further reduced, and the short-circuit current can be further improved. On the other hand, it can reduce the free carrier Auger recombination without reducing the passivation effect of the tunneling layer, further improve the short-circuit current, open-circuit voltage, and improve battery efficiency.

[0150] As described above, the element concentration distribution of the doped region of the battery silicon substrate is described in detail. With the help of the TOPCon battery shown in Figure 3, the positions of the above x, y and z are described. As shown in Figure 3, the surface of the doped polysilicon layer away from the silicon substrate is the surface shown as D, the maximum value of x is the distance between D and C; the maximum value of y is the distance between D and B; the maximum value of z is the distance between D and A.

[0151] When the solar cell of the present application is a TBC cell, the first doping element is a Group V element (for example, phosphorus), the second doping element is a Group III element (for example, boron), and the layer structure on the above-mentioned silicon substrate also includes a second layer structure, and the above-mentioned second layer structure includes a tunneling layer and a doped polysilicon layer stacked in sequence on the surface of the side of the above-mentioned second doping region away from the silicon substrate; the second doping region is a doping region formed by the second doping element passing through the second layer structure on the above-mentioned silicon substrate.

[0152] In a specific embodiment, in the doped polysilicon layer, the concentration of the first doping element at a depth x (i.e., a first preset depth) away from the surface of the silicon substrate side of the doped polysilicon layer in the first doping region is greater than the concentration of the second doping element at a depth x (i.e., a first preset depth) away from the surface of the silicon substrate side of the doped polysilicon layer in the second doping region, the thickness of the doped polysilicon layer on the first doping region is in the range of 100 to 400 nm, the thickness of the doped polysilicon layer on the second doping region is in the range of 100 to 400 nm, and x is less than or equal to the thickness of the doped polysilicon layer on the first doping region. In a specific embodiment, a first doping element is doped in the tunneling layer of the above-mentioned first doping region, and a second doping element is doped in the tunneling layer of the second doping region. In the direction from the doped polysilicon layer to the tunneling layer, in the tunneling layer, the concentration of the first doping element at a depth y (i.e., a second preset depth) from the surface of the doped polysilicon layer of the first doping region away from the silicon substrate is greater than the concentration of the second doping element at a depth y (i.e., a second preset depth) from the surface of the doped polysilicon layer of the second doping region away from the silicon substrate. The thickness of the tunneling layer on the first doping region ranges from 0.5 to 5 nm, and the thickness of the tunneling layer on the second doping region ranges from 0.5 to 5 nm, and y is less than or equal to the sum of the thicknesses of the doped polysilicon layer and the tunneling layer on the first doping region. In a specific embodiment, in the direction from the doped polysilicon layer to the surface of the above-mentioned first doped region, in the silicon substrate, the concentration of the first doping element at the depth z (i.e., the third preset depth) of the surface of the doped polysilicon layer of the first doped region away from the silicon substrate is greater than the concentration of the second doping element at the depth z (i.e., the third preset depth) of the surface of the doped polysilicon layer of the second doped region away from the silicon substrate, the thickness range of the first doped region is 30 to 100 nm, and z is less than or equal to the sum of the thicknesses of the doped polysilicon layer, the tunneling layer and the first doped region on the first doped region.

[0153] In this application, whether it is a TOPCon cell, a local TOPCon cell, a back contact hybrid cell, or a TBC cell, since the antimony element and the doping element in the silicon substrate are uniformly doped, the resistivity of the silicon substrate and the light absorber is very uniform, the resistivity change rate is small, and the average resistivity offset rate is small, it can effectively reduce the lateral transmission resistance of the carrier and improve the battery efficiency.

[0154] In a specific embodiment, the battery of the present application includes an electrode formed on a light absorber, the electrode includes a metal crystal portion in contact with the light absorber, the metal crystal portion includes antimony element, wherein the light absorber includes a silicon substrate and a region for separating carriers generated by the silicon substrate.

[0155] In the present application, the above-mentioned metal crystal refers to an alloy formed by the metal and silicon in the electrode during the electrode formation process.

[0156] In a specific embodiment, the metal crystal portion further includes a doping element, and the concentration of the doping element is greater than the concentration of the antimony element.

[0157] Since the metal crystal portion of the electrode of the battery of the present application contains antimony elements, the contact resistance of the solar cell can be reduced, and the contact resistance of the component can be further reduced.

[0158] In a specific embodiment, the mechanical strength of the solar cell of the present application is greater than or equal to 50 MPa.

[0159] The present application also includes a cell string structure, comprising a plurality of the above-mentioned solar cells of the present application interconnected by conductive interconnectors.

[0160] In a specific embodiment, the conductive interconnection member may be, for example, a conductive connection line (sometimes also referred to as a metal soldering ribbon), or a conductive line in a conductive backplane.

[0161] Specifically, before forming a photovoltaic module, cells need to go through a stringing (or string welding) step. Specifically, as shown in Figure 4, multiple cells are connected via multiple conductive wires, for example, in series. The wires can be metal wires with circular or triangular cross-sections, and can consist of a substrate and a bonding layer wrapped around the substrate.

[0162] In this application, whether the connection is made using a conductive connecting wire (metal welding ribbon) or a conductive circuit formed on a conductive backplane, as long as the battery is in contact with the conductive interconnect through the electrode and the contact part contains antimony elements, such a structure can further reduce the contact resistance of the battery string.

[0163] In the stringing step, welding is used for electrical connection, and the welding process requires a heating operation, the main purpose of which is to melt the bonding layer of the connecting wire to form an electrical connection with the battery. However, in the heating step, the stress of the battery may be uneven up and down, and this uneven pressure up and down will cause bending. However, the greater the bending during the stringing process, the greater the risk of hidden cracks and fragments in the battery during lamination. The mechanical strength of the battery involved in this application is greater than 50Mpa. Its large mechanical strength can suppress excessive bending of the battery cells when stringing, which can improve the yield of the component to a certain extent. Generally speaking, the curvature of the back-contact battery will be greater than that of the bifacial battery. This is because the stress difference between the upper and lower surfaces of the back contact will be greater. Among them, the back-contact battery refers to a battery having an electrical interconnection structure only on one side, while the bifacial battery refers to a battery having an electrical interconnection structure on both opposite sides.

[0164] Specifically, according to the test results of the inventors, referring to FIG4 , the curvature of the back-contact battery after being heated at 165-200 degrees Celsius and stringed together is less than or equal to 2 mm, and the curvature after being heated at a low temperature of 100-160 degrees Celsius and stringed together is less than or equal to 1.5 mm; referring to FIG5 , the curvature of the bifacial battery after being heated at 165-200 degrees Celsius and stringed together is less than or equal to 1.2 mm, and the curvature after being heated at a low temperature of 100-160 degrees Celsius and stringed together is less than or equal to 1 mm. It can be seen that the specially doped battery of the present invention has a smaller curvature, which can well control the problems of hidden cracks and fragments during lamination. It should be noted that the curvature involved in this application refers to the height or depth of the bulge or depression generated on the surface of the battery when the battery is bent, which can be obtained by measuring the curvature radius of the battery edge.

[0165] The present application also relates to a solar cell assembly, comprising a plurality of cells, an encapsulation layer, a cover plate and a back plate as described above. The sealing layer seals the plurality of cells, and the sealing layer is located between the cover plate and the back plate.

[0166] The battery strings of this application are formed into battery assemblies through layout, stacking, and lamination processes. The resulting battery assemblies are shown in Figures 6 and 7. During the lamination process, pressure and heat are applied to melt the encapsulation layer, sealing the battery string and bonding the cover and backsheets, with the encapsulation layer located between the cover and backsheets. During the lamination process, due to the aforementioned pressure and heating, some of the stress in the cells is released and suppressed. For back-contact cells, see Figure 6 , the cell curvature in the laminated battery assembly is less than or equal to 1.2 mm. For bifacial cells, see Figure 7 , the cell curvature in the laminated battery assembly is less than or equal to 0.8 mm. It has been verified that the laminated battery has significantly controlled the problems of hidden cracks and fragmentation. More specifically, for phosphorus-doped and antimony-doped bifacial cells, the inventors selected batch testing results of over 300 assemblies, showing that the fragmentation rates of phosphorus-doped and antimony-doped cells were 0.849% and 0.843%, respectively, and the crack-free rates were 98.18% and 98.20%, respectively. As can be seen from Figures 5 and 7, the bending direction of the battery is toward the cover plate, that is, the battery protrudes toward the cover plate to form a curved shape.

[0167] Specifically, the encapsulation layer can be at least one of EVA, POE, silicone, and PVB. The cover plate is close to the light-receiving surface of the battery and is transparent organic or inorganic. It can be preferably low-iron embossed glass, and its thickness is preferably 2.0 or 3.2 mm. The back plate can be transparent or non-transparent. For double-glass modules, the back plate is a transparent material, which is preferably glass, while for single-glass modules, the back plate can be non-transparent, such as a TPC board. Furthermore, the battery assembly also includes a frame, which has a groove-shaped mounting portion for accommodating the laminate, and the edges of the cover plate and the back plate are embedded in the mounting portion of the frame.

[0168] Example

[0169] This application provides general and / or specific descriptions of the materials and experimental methods used in the experiments. In the following examples, unless otherwise specified, % represents wt%, i.e., percentage by weight. All reagents or instruments used without manufacturer indication are commercially available conventional reagents.

[0170] Example 1

[0171] 1-1. Preparation of Antimony-Doped Bare Silicon Wafers

[0172] The polysilicon blocks are placed in the quartz crucible. For example, the solid silicon raw material is first piled into the quartz crucible, and then the quartz crucible filled with silicon material is placed in the single crystal furnace.

[0173] The single crystal furnace is vacuumed and argon is introduced. After reaching the set furnace pressure of 11 Torr, the single crystal furnace heater is turned on to gradually melt the solid silicon in the quartz crucible into a molten state.

[0174] Because the solid silicon material in the quartz crucible is stacked and placed, the actual volume of the silicon material in the quartz crucible decreases after being heated and melted. The melted silicon material does not reach the maximum loading capacity of the quartz crucible. Therefore, it is necessary to use an external feeder, such as a quartz tube feeding barrel, to fill the quartz crucible with silicon material for a second time. This experiment actually requires quartz tube filling 4 times. During the filling process, the heater simultaneously melts the silicon material in the quartz crucible.

[0175] 1.14 g of Sb-containing dopant was buried in the silicon material in the cylinder, and the silicon material was added into the quartz crucible together with the silicon material.

[0176] After all the silicon material in the quartz crucible is melted, it enters the temperature adjustment stage, inserts the seed crystal into the liquid surface, and controls the power parameters to reach the critical crystallization temperature of the liquid surface temperature.

[0177] After the seed crystal and the liquid level reach the crystallization temperature, the seed crystal is pulled upward.

[0178] When the seed crystal length reaches the required length of 15-20mm and the seed crystal diameter is within 5-10mm, the actual single crystal diameter is adjusted to the range of 252±1mm round rod diameter by adjusting parameters such as power and pulling speed; after the shoulder is placed, the shoulder rotation process is carried out to enter the silicon rod equalization process.

[0179] During the equal-diameter process, the furnace pressure was controlled below 11 Torr, and the equal-diameter length obtained was 3800 mm.

[0180] Silicon rod drawing is completed by reducing the diameter of the silicon rod.

[0181] The silicon rods are cut to the appropriate length by a cutting machine, and then transferred to a square cutting machine to be processed into square rods. The square rods are polished by a polishing machine and then transferred to a slicer. The silicon square rods are cut into silicon wafers (150μm) by diamond wire, i.e., antimony-doped bare silicon wafers.

[0182] 1-2 Detection of antimony concentration in antimony-doped bare silicon wafers

[0183] The antimony concentration of the silicon wafer of Example 1 was measured using ICP-MS. The average antimony concentration was calculated by taking the concentration at the center of the upper surface and the center of the lower surface of the silicon wafer. The average antimony concentration of the silicon wafer is shown in Table 1.

[0184] 1-3 Detection of resistivity of antimony-doped bare silicon wafers

[0185] The resistivity of the silicon wafer was tested using a terahertz offline two-dimensional imaging device (FalconWave-S), and the resistivity change rate and the average resistivity shift rate were calculated. A resistivity surface scan of the silicon wafer was performed (using a terahertz offline two-dimensional imaging device (FalconWave-S) for detection). As shown in Figure 1, the average resistivity value Rv on the black line (a line from the center point to the edge of the silicon wafer) was obtained. The maximum resistivity value Rmax and the minimum resistivity value Rmin on the black line were obtained, as well as the resistivity values ​​Ri per 1μm (i=1, 2, 3...). The resistivity change rate (Rmax-Rmin) / Rv and the resistivity shift rate were calculated. The resistivity change rate of the silicon wafer is shown in Table 1, and the average resistivity shift rate is shown in Table 1.

[0186] Example 2-10

[0187] Preparation of antimony-doped bare silicon wafers: Antimony-doped bare silicon wafers were prepared using exactly the same method as in Example 1, except for the amount of the Sb-containing dopant used in Example 1. The amount of the Sb-containing dopant used is shown in Table 1-1.

[0188] Detection of antimony concentration of antimony-doped bare silicon wafer: The method is similar to that of Example 1. The average antimony concentration of the above silicon wafer is shown in Table 1.

[0189] Detection of the resistivity of the antimony-doped bare silicon wafer: The method is similar to that of Example 1. The resistivity change rate of the above silicon wafer is shown in Table 1, and the resistivity average shift rate is shown in Table 1.

[0190] Comparative Example 1

[0191] Preparation of phosphorus-doped bare silicon wafers: A method identical to that of Example 1 was used, except that the Sb-containing dopant used in Example 1 was replaced with a phosphorus-doped master alloy as the dopant and the amount of the dopant was changed, while the rest remained unchanged, to prepare silicon wafers, i.e., phosphorus-doped bare silicon wafers. The amount of the dopant is shown in Table 1-1.

[0192] Detection of phosphorus concentration of phosphorus-doped bare silicon wafers: The method is similar to that of Example 1. The average phosphorus concentration of the above silicon wafers is shown in Table 1.

[0193] Detection of the resistivity of the phosphorus-doped bare silicon wafer: The method is similar to that of Example 1. The resistivity change rate of the above silicon wafer is shown in Table 1, and the resistivity average shift rate is shown in Table 1.

[0194] Comparative Example 2

[0195] Preparation of phosphorus-doped bare silicon wafers: A method identical to that of Example 1 was used, except that the Sb-containing dopant used in Example 1 was replaced with a phosphorus-doped master alloy as the dopant and the amount of the dopant was changed, while the rest remained unchanged, to prepare silicon wafers, i.e., phosphorus-doped bare silicon wafers. The amount of the dopant is shown in Table 1-1.

[0196] Detection of phosphorus concentration of phosphorus-doped bare silicon wafers: The method is similar to that of Example 1. The average phosphorus concentration of the above silicon wafers is shown in Table 1.

[0197] Detection of the resistivity of the phosphorus-doped bare silicon wafer: The method is similar to that of Example 1. The resistivity change rate of the above silicon wafer is shown in Table 1, and the resistivity average shift rate is shown in Table 1.

[0198] Table 1-1 Doping amount in Examples 1-10 and Comparative Examples 1 and 2

[0199] Table 1 compares Examples 1-5 with Comparative Example 1, and Examples 6-10 with Comparative Example 2, all with roughly the same average antimony concentration. It can be seen that the antimony-doped silicon wafers exhibit a lower resistivity change and a smaller average resistivity shift, resulting in better resistance uniformity. Uniform resistance distribution and concentration improve carrier transport and separation, increasing cell efficiency and light absorption. Therefore, subsequent boron diffusion can reduce differences in electric field distribution within the pn junction, thereby reducing carrier recombination losses and improving photoelectric conversion efficiency.

[0200] Example 11

[0201] Preparation of Antimony-Boron-Doped Silicon Wafers: The 150μm antimony-doped bare silicon wafers obtained in Example 1 were subjected to boron diffusion to produce 150μm antimony-doped boron-diffused silicon wafers. The purpose of the diffusion process is to form a PN junction on the silicon wafer, thereby converting light energy into electrical energy. The PN junction manufacturing equipment is a diffusion furnace. In this example, gaseous boron trichloride was used to diffuse the 150μm antimony-doped bare silicon wafers within the diffusion furnace. Boron atoms diffused into the silicon wafer, simultaneously forming a boron diffusion layer on the surface of the silicon wafer.

[0202] Detection of the resistivity of the antimony-doped boron silicon wafer: The method is similar to that of Example 1. The calculated resistivity change rate and resistivity average deviation rate are listed in Table 2.

[0203] Testing the square resistance of antimony-boron-doped silicon wafers: To characterize whether the boron concentration within the silicon wafer is uniform after boron diffusion, the square resistance of the silicon wafer was tested, with the square resistance change rate used as an indicator of boron concentration uniformity. The results are listed in Table 3. The specific testing method is as follows: Using a four-probe square resistance resistivity tester, as shown in Figure 2, the boron-doped surface was tested at five points on the graph, and the average square resistance Fv was calculated. The maximum square resistance Fmax and the minimum square resistance Fmin were obtained, and the square resistance change rate (Fmax-Fmin) / Fv was calculated. Those skilled in the art will understand that under ideal conditions, the boron concentration at each point on the silicon wafer is exactly the same. In this case, Fmax=Fmin=Fv, and the square resistance change rate is 1, indicating complete uniformity.

[0204] Examples 12 to 20

[0205] Preparation of antimony-boron-doped silicon wafers: The 150 μm antimony-doped bare silicon wafers obtained in Examples 2 to 10 were subjected to the same method as in Example 11 to obtain the 150 μm antimony-boron-doped silicon wafers after diffusion in Examples 12 to 20.

[0206] Detection of the resistivity of the antimony-doped boron silicon wafer: The method is similar to that of Example 1. The calculated resistivity change rate and resistivity average deviation rate are listed in Table 2.

[0207] Detection of the square resistance of the antimony-doped boron silicon wafer: The method is similar to that of Example 11. The calculated square resistance change rate is listed in Table 3.

[0208] Comparative Example 3

[0209] Preparation of phosphorus-doped boron silicon wafers: The 150μm phosphorus-doped bare silicon wafer obtained in Comparative Example 1 was subjected to boron diffusion treatment to obtain a 150μm phosphorus-doped boron-diffused silicon wafer. In this comparative example, gaseous boron trichloride was used to diffuse the 150μm phosphorus-doped bare silicon wafer in a diffusion furnace. Boron atoms diffused into the silicon wafer and formed a boron diffusion layer on the surface of the silicon wafer.

[0210] Detection of the resistivity of the phosphorus-doped boron silicon wafer: The method is similar to that of Example 1. The calculated resistivity change rate and resistivity average shift rate are listed in Table 2.

[0211] Detection of the square resistance of the phosphorus-doped boron silicon wafer: The method is similar to that of Example 11, and the calculated square resistance change rate is listed in Table 3.

[0212] Comparative Example 4

[0213] Preparation of phosphorus-doped boron silicon wafers: The 150μm phosphorus-doped bare silicon wafer obtained in Comparative Example 2 was subjected to boron diffusion treatment to obtain a 150μm phosphorus-doped boron-diffused silicon wafer. In this comparative example, gaseous boron trichloride was used to diffuse the 150μm phosphorus-doped bare silicon wafer in a diffusion furnace. Boron atoms diffused into the silicon wafer and formed a boron diffusion layer on the surface of the silicon wafer.

[0214] Detection of the resistivity of the phosphorus-doped boron silicon wafer: The method is similar to that of Example 1. The calculated resistivity change rate and resistivity average shift rate are listed in Table 2.

[0215] Detection of the square resistance of the phosphorus-doped boron silicon wafer: The method is similar to that of Example 11, and the calculated square resistance change rate is listed in Table 3.

[0216] The actual test results of Table 2 Examples 11 to 20 and Comparative Examples 3 and 4 are as follows

[0217] Table 2 compares Examples 11-15 with Comparative Example 3, where the average antimony concentrations are roughly the same order of magnitude, and Examples 16-20 with Comparative Example 4. It can be seen that the resistivity change rate of the antimony-doped boron silicon wafers is lower than that of the phosphorus-doped boron silicon wafers, and the average resistivity offset is smaller than that of the phosphorus-doped boron silicon wafers, indicating that the concentration distribution of the antimony-doped silicon wafers remains uniform after the boron diffusion process. Antimony atoms can be more evenly filled into the crystal during the crystal pulling process, resulting in a flatter doping profile. The antimony atoms in the antimony-doped silicon wafers can capture and neutralize radiation-induced defects, thereby reducing defect formation and diffusion. This helps reduce carrier capture and scattering, improving the transport efficiency of electrons and holes, and reducing the possibility of charge recombination, thereby improving the photovoltaic conversion efficiency and stability of the cell.

[0218] The actual test results of Table 3 Examples 11 to 20 and Comparative Examples 3 and 4 are as follows

[0219] Table 3 compares Examples 11-15 with Comparative Example 3, where the average antimony concentrations are roughly the same order of magnitude, and Examples 16-20 with Comparative Example 4. It can be seen that the antimony-doped silicon wafers have a lower rate of change in sheet resistance after boron diffusion. This indicates that the more uniform concentration of antimony-doped silicon wafers significantly reduces regional accumulation of boron doping sources on the silicon wafer surface, improving the uniformity of boron doping on the silicon wafer surface after deposition. The uniform distribution of resistivity and concentration can reduce the resistive loss of carriers throughout the silicon wafer. This can avoid localized areas of excessively high or low current density, reduce hot spots and current unevenness, and improve the efficiency and stability of the battery.

[0220] Therefore, the content of antimony is lower than that of phosphorus at the junction depth of boron diffusion. Moreover, compared with phosphorus doping, the self-doping effect of antimony is reduced, which will reduce the carrier recombination effect and is not easy to diffuse into the selection layer (tunneling layer and / or doped polysilicon), which will not affect the quality and efficiency of the tunnel junction. By reducing the self-doping effect, the original and expected characteristics of the electron and hole selection layer (i.e., the doped region or topcon structure) can be maintained, forming a good film quality, which is conducive to improving the battery conversion efficiency and improving the consistency and stability of the battery.

[0221] Example 21

[0222] A 150μm silicon wafer is first textured to form a pyramid texture surface, and boron is diffused on the front side to form a p+ layer. The boron diffusion layer on the back side is then removed while retaining the boron glass layer (BSG layer) on the front side. Subsequently, an oxide tunneling layer and a polysilicon passivation layer are deposited. The polysilicon on the back side is then P-doped, and the polysilicon, tunneling layer, and BSG layer on the front side and edges are etched away. The boron diffusion surface is then passivated with aluminum oxide, and the boron diffusion surface and phosphorus diffusion surface are passivated with silicon nitride. Finally, double-sided metallization is performed.

[0223] The electrical performance test results of TOPCon cells made from the silicon wafers of Examples 11 to 20 and Comparative Examples 3 and 4 as silicon substrates are shown in Table 4.

[0224] Table 4 TOPCon cell performance results (for cells prepared from silicon wafers of Examples 11 to 20 and Comparative Examples 3 and 4)

[0225] Table 4 compares cells made from silicon wafers of Examples 11-15 and Comparative Example 3, and from Examples 16-20 and Comparative Example 4, whose average antimony concentrations are roughly the same order of magnitude. It can be seen that, after undergoing the same cell process, the uniform concentration of the silicon wafers effectively improves their quality. When prepared into cell wafers, they exhibit superior short-circuit current, open-circuit voltage, and cell efficiency compared to phosphorus-doped silicon wafers.

[0226] Although the above description is based on the embodiments of the present application, the present application is not limited to the above specific embodiments and application fields. The above specific embodiments are merely illustrative and instructive, and not restrictive. A person of ordinary skill in the art, guided by this specification and without departing from the scope of protection of the claims of this application, may also devise various forms, all of which fall within the scope of protection of this application.

Claims

1. A silicon wafer, wherein: The concentration of antimony in the silicon wafer is 1E+12cm -3 To 2E+16cm -3 , preferably 4E+14cm -3 To 2E+16cm -3 , preferably 4.3E+14cm -3 To 1.9E+16cm -3 ; More preferably 4.45E+14cm -3 To 1.87E+16cm -3 ; The resistivity change rate of the silicon wafer is ≤0.8; the optional resistivity change rate is ≤0.6; the optional resistivity change rate is ≤0.5; the optional resistivity change rate is ≤0.

4.

2. The silicon wafer according to claim 1, wherein: The average resistivity offset rate of the silicon wafer is ≤8%; the average resistivity offset rate is optionally ≤5%, the average resistivity offset rate is optionally ≤4.5%; the average resistivity offset rate is further optionally ≤4%; the resistivity of the silicon wafer can be optionally 0.3-1000Ω·cm, can be optionally 0.3~100Ω·cm, can be optionally 0.3~10Ω·cm, can be optionally 0.4~8Ω·cm; can be optionally 0.5~6Ω·cm.

3. The silicon wafer according to claim 1 or 2, wherein: The resistivity change rate of the silicon wafer is ≥0.01, and the resistivity change rate can be selected to be ≥0.

1.

4. The silicon wafer according to any one of claims 1 to 3, wherein The resistivity average deviation rate is ≥0.1%, and the resistivity average deviation rate can be selected to be ≥1%.

5. A solar cell, comprising a silicon substrate, wherein the silicon substrate is formed by the silicon wafer according to any one of claims 1 to 4, wherein at least one side of the surface of the silicon substrate has a doping region, wherein the silicon substrate contains antimony, and wherein the doping region is doped with a doping element, wherein the doping element is selected from a third main group element or a fifth main group element, The antimony concentration in the silicon substrate is 1E+12cm -3 To 2E+16cm -3 , preferably 4E+14cm -3 To 2E+16cm -3 , preferably 4.3E+14cm -3 To 1.9E+16cm -3 ; More preferably 4.45E+14cm -3 To 1.87E+16cm -3 ; The resistivity change rate of the silicon substrate is ≤0.8; the resistivity change rate can be selected to be ≤0.6; the resistivity change rate can be selected to be ≤0.5; and the resistivity change rate can be selected to be ≤0.

4. The solar cell according to claim 5 , wherein at least one doping layer is provided on a surface of at least one side of the silicon substrate. 7 . The solar cell according to claim 6 , wherein at least one passivation layer is provided between the doping layer and the doping region. 8 . The solar cell according to claim 5 , wherein the concentration of antimony element in the doping region is substantially constant in the thickness direction of the silicon substrate.

9. The solar cell according to claim 5, wherein: In the doping region, the sum of the concentration of the antimony element and the concentration of the doping element is less than or equal to 1E+21cm -3 .

10. The solar cell according to claim 5, wherein: When the doping element is a third main group element, the thickness of the doping region is in the range of 30 to 650 mm; or When the doping element is a fifth main group element, the thickness of the doping region is in the range of 100 to 200 nm.

11. The solar cell according to claim 5, wherein: The doping region includes a first doping region and a second doping region, An interface passivation layer and a doping passivation layer are sequentially stacked on a surface of the first doped region on a side away from the silicon substrate, doping a first doping element in the doped passivation layer, The second doping region on the silicon substrate is further doped with a second doping element, The first doping region and the second doping region have opposite conductivity types.

12. The solar cell according to claim 11, wherein: The first doping element is a fifth main group element, the second doping element is a third main group element, In the doped passivation layer, the concentration of the first doping element at a first preset depth from the surface of the doped passivation layer on one side away from the silicon substrate is greater than the concentration of the second doping element at the same first preset depth from the surface of the second doping region, the thickness range of the doped passivation layer is 100 to 400 nm, and the first preset depth is less than or equal to the thickness of the doped passivation layer.

13. The solar cell according to claim 11, wherein: The first doping element is a fifth main group element, the second doping element is a third main group element, An interface passivation layer and a doping passivation layer are sequentially stacked on a surface of the second doped region on a side away from the silicon substrate; In the doped passivation layer, the concentration of the first doping element at a first preset depth from the surface of the doped passivation layer on the side away from the silicon substrate in the first doping region is greater than the concentration of the second doping element at a first preset depth from the surface of the doped passivation layer on the side away from the silicon substrate in the second doping region, the thickness of the doped passivation layer on the first doping region ranges from 100 to 400 nm, the thickness of the doped passivation layer on the second doping region ranges from 100 to 400 nm, and the first preset depth is less than or equal to the thickness of the doped passivation layer on the first doping region.

14. The solar cell according to claim 12, wherein: doping a first doping element in the interface passivation layer, In the direction from the doped passivation layer to the interface passivation layer, in the interface passivation layer, the concentration of the first doping element at a second preset depth from the surface of the doped passivation layer on a side away from the silicon substrate is greater than the concentration of the second doping element at a second preset depth from the surface of the second doping region, the thickness of the interface passivation layer ranges from 0.5 to 5 nm, and the second preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer and the interface passivation layer.

15. The solar cell according to claim 13, wherein: The interface passivation layer of the first doping region is doped with a first doping element, and the interface passivation layer of the second doping region is doped with a second doping element, In the direction from the doped passivation layer to the interface passivation layer, in the interface passivation layer, the concentration of the first doping element at a second preset depth from the surface of the doped passivation layer on the side away from the silicon substrate in the first doped region is greater than the concentration of the second doping element at a second preset depth from the surface of the doped passivation layer on the side away from the silicon substrate in the second doped region, the thickness of the interface passivation layer on the first doped region ranges from 0.5 to 5 nm, the thickness of the interface passivation layer on the second doped region ranges from 0.5 to 5 nm, and the second preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer and the interface passivation layer on the first doped region.

16. The solar cell according to claim 12, wherein: In the direction from the doped passivation layer to the surface of the first doped region, in the silicon substrate, the concentration of the first doping element at a third preset depth from the surface of the doped passivation layer away from the silicon substrate is greater than the concentration of the second doping element at a third preset depth from the surface of the second doping region, the thickness range of the first doping region is 30 to 100 nm, and the third preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer, the interface passivation layer and the first doping region.

17. The solar cell according to claim 13, wherein: In the direction from the doped passivation layer to the surface of the first doped region, in the silicon substrate, the concentration of the first doping element at a third preset depth from the surface of the doped passivation layer of the first doped region away from the silicon substrate is greater than the concentration of the second doping element at a third preset depth from the surface of the doped passivation layer of the second doped region away from the silicon substrate, the thickness of the first doped region ranges from 30 to 100 nm, and the third preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer, the interface passivation layer and the first doped region on the first doped region.

18. The solar cell according to claim 5, wherein: When the doping element is a third main group element, the thickness of the doping region ranges from 80 to 180 nm; When the doping element is a fifth main group element, the thickness of the doping region ranges from 30 to 100 nm.

19. The solar cell according to claim 5, wherein: The surface square resistance change rate of the silicon substrate surface is ≤0.6; the optional surface square resistance change rate is ≤0.4; the optional surface square resistance change rate is ≤0.3; the optional surface square resistance change rate is ≤0.

2.

20. The solar cell according to claim 19, wherein The surface square resistance variation rate of the silicon substrate surface is ≥0.001; the surface square resistance variation rate can be selected to be ≥0.

01.

21. The solar cell according to any one of claims 5 to 20, wherein The battery includes an electrode formed on a light absorber, the electrode including a metal crystal portion in contact with the light absorber, the metal crystal portion including antimony element, wherein the light absorber includes a silicon substrate and a region for separating carriers generated by the silicon substrate.

22. The battery according to claim 21, wherein The metal crystal portion further includes a doping element, and a concentration of the doping element is greater than a concentration of the antimony element.

23. The solar cell according to any one of claims 5 to 22, wherein the mechanical strength of the solar cell is greater than 50 MPa.

24. A cell string comprising a plurality of solar cells interconnected by conductive interconnectors, at least one of the solar cells being the solar cell according to any one of claims 5 to 23.

25. The battery string according to claim 24, wherein: The curvature of the solar cell is less than or equal to 2 mm.

26. The battery string according to claim 25, wherein: The connecting wire is connected to the solar cell by welding or conductive bonding.

27. The battery string according to claim 26, wherein: The welding includes a heating step.

28. The battery string according to claim 27, wherein: The temperature range of the heating step is 100-160 degrees Celsius, and the curvature of the solar cell is less than or equal to 1.5 mm.

29. The battery string according to claim 27, wherein: The temperature range of the heating step is 165-200 degrees Celsius, and the curvature of the solar cell is less than or equal to 2 mm.

30. The battery string according to any one of claims 24 to 29, wherein: The conductive interconnect includes an electrical contact portion contacting an electrode of the solar cell, the electrical contact portion including an antimony element.

31. A solar cell assembly, comprising a plurality of cells, a packaging layer, a cover plate and a back plate, wherein the sealing layer seals the plurality of cells and is located between the cover plate and the back plate; the cell is a solar cell according to any one of claims 5 to 23.

32. The solar module of claim 31, wherein: The curvature of the battery is less than or equal to 1.2 mm.

33. The solar module of claim 31, wherein: The battery protrudes toward the cover plate to form a curved shape.

34. The solar module according to any one of claims 31 to 33, wherein: It also includes a frame, and the edge of the cover plate and / or the back plate is embedded in the mounting portion of the frame.

35. The solar module according to any one of claims 31 to 33, wherein: The cover plate and / or back plate are transparent plates.

36. The solar module according to any one of claims 31 to 33, wherein: The back plate is a non-transparent plate.

37. The solar module according to any one of claims 31 to 36, wherein: A plurality of cells are interconnected by a conductive interconnector, wherein the conductive interconnector includes an electrical contact portion contacting an electrode of the solar cell, wherein the electrical contact portion includes an antimony element.

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