Display panel and display apparatus

Abstract

A display panel, which display panel comprises a light-shielding layer (13) and at least two pixel circuits. Each pixel circuit comprises at least two transistors for receiving different signals. The light-shielding layer (13) comprises first light-shielding structures (131) and second light-shielding structures (132). The orthographic projections of the first light-shielding structures (131) and the second light-shielding structures (132) on a drive circuit layer (12) respectively overlap active parts of different types of transistors, and two adjacent first light-shielding structures (131) are connected together, and / or two adjacent second light-shielding structures (132) are connected together, such that the electrostatic discharge area and path of the light-shielding layer (13) can be increased, and thus static electricity accumulated during a process is released in a timely manner or uniformly distributed, thereby preventing static electricity from damaging the light-shielding layer (13) or other film layers, and the display effect is good. Further provided is a display apparatus comprising the display panel.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311266462.3 filed on September 27, 2023, entitled “Display Panel and Display Device,” and the entire contents of this Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] Some display panels are provided with a light shielding layer to shield the thin film transistors in the pixel circuit. In order to prevent the light shielding layer from being suspended in the air, which may lead to poor uniformity of the characteristics of the thin film transistors, a voltage signal needs to be applied to the light shielding layer.

[0005] To avoid short circuits between shading structures connecting different signals, each pixel row uses two sets of independent shading structures. During the production process of the display panel, the static electricity accumulated in a single shading structure is not easy to release, which can easily cause static electricity damage to the shading layer or other film layers, affecting poor display.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0007] Summary of the Invention

[0008] The present disclosure provides a display panel and a display device.

[0009] According to one aspect of the present disclosure, a display panel is provided, which includes a base substrate, a driving circuit layer and a shading layer. The driving circuit layer is arranged on one side of the base substrate. The driving circuit layer includes at least two pixel circuits arranged along a row direction and arranged along a column direction. The column direction is perpendicular to the row direction. The pixel circuit includes at least two transistors for receiving different signals; the shading layer is arranged between the driving circuit layer and the base substrate. The shading layer includes at least two shading structure groups. Each shading structure group includes a first shading structure and a second shading structure. The first shading structure inputs a first signal, and the second shading structure inputs a second signal. The first shading structure and the second shading structure extend along the row direction. At least two first shading structures and at least two second shading structures are arranged along the column direction. One shading structure group shades one pixel circuit. The orthographic projections of the first shading structure and the second shading structure on the driving circuit layer overlap with active parts of different types of transistors respectively. Two adjacent first shading structures are connected together, and / or two adjacent second shading structures are connected together.

[0010] In one embodiment of the present disclosure, the pixel circuit includes a first reset transistor, a compensation transistor, a driving transistor, a write transistor, a first light-emitting control transistor, a second light-emitting control transistor, a second reset transistor, and a storage capacitor; the first electrode of the first reset transistor is used to receive a first reset signal, and the second electrode is connected to the gate of the driving transistor and the first plate of the storage capacitor; the first electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the gate of the driving transistor; the compensation transistor has two channels connected in series; the first electrode of the write transistor is connected to a data line, and the second electrode is connected to the first electrode of the driving transistor; the first light-emitting control transistor The first electrode of the tube and the second electrode plate of the storage capacitor are connected to the power line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting device; the first electrode of the second reset transistor is used to receive a second reset signal, and the second electrode is connected to the second electrode of the second light-emitting control transistor; the orthographic projection of the first shading structure on the driving circuit layer overlaps with the active part of the first reset transistor, the active part of the threshold compensation transistor, the active part of the write transistor and the active part of the second reset transistor, and the orthographic projection of the second light-shading structure on the driving circuit layer overlaps with the active part of the driving transistor.

[0011] In one embodiment of the present disclosure, the first light-shielding structure includes a first light-shielding portion and a second light-shielding portion, the first light-shielding portion and the second light-shielding portion extend in the row direction and are arranged in the column direction, the orthographic projection of the first light-shielding portion on the driving circuit layer overlaps with the active portion of the compensation transistor and the active portion of the write transistor, and the orthographic projection of the second light-shielding portion on the driving circuit layer overlaps with the active portion of the first reset transistor and the active portion of the second reset transistor of the pixel circuit in the previous row.

[0012] In one embodiment of the present disclosure, the first light-shielding portion and the second light-shielding portion of at least two first light-shielding structures are arranged alternately along the column direction, and the second light-shielding structure is arranged between the first light-shielding portion and the second light-shielding portion of the same first light-shielding structure, or between the first light-shielding portion and the second light-shielding portion of adjacent first light-shielding structures.

[0013] In one embodiment of the present disclosure, two adjacent first light-shielding structures are connected together, and two adjacent second light-shielding structures are connected together.

[0014] In one embodiment of the present disclosure, the first light-shielding portion and the second light-shielding portion of the same first light-shielding structure are connected by at least three first traces extending along the column direction, the first light-shielding portion located on one side of the light-shielding layer along the column direction is continuous and uninterrupted, the remaining first light-shielding portions and all the second light-shielding portions are provided with at least two discontinuities along the row direction, and a discontinuity is provided between every two adjacent first traces, the second light-shielding structure is provided between the first light-shielding portion and the second light-shielding portion of the same first light-shielding structure, the second light-shielding structure located on the other side of the light-shielding layer along the column direction is continuous and uninterrupted, and the remaining second light-shielding structures are interrupted into a sub-second light-shielding structure between every two first traces, and two adjacent sub-second light-shielding structures along the column direction are connected by a second trace, and the second trace is located in the discontinuity, the first light-shielding portion and the second light-shielding portion of different first light-shielding structures are connected by a third trace extending along the column direction, and the third trace is located between the first trace and the second trace.

[0015] In one embodiment of the present disclosure, the first light shading portion and the second light shading portion of the same first light shading structure are connected by a first routing line extending along the column direction, the second light shading structure is arranged between the first light shading portion and the second light shading portion of the same first light shading structure, the second light shading structure is connected by a second routing line extending along the column direction, the first routing line is located on one side of the light shading layer along the row direction, and the second routing line is located on the other side of the light shading layer along the row direction, and the first light shading portion and the second light shading portion of different first light shading structures are connected by a third routing line extending along the column direction.

[0016] In one embodiment of the present disclosure, the third routing line and the second routing line are located on the same straight line.

[0017] In one embodiment of the present disclosure, one end of the first light shading portion and one end of the second light shading portion of the same first light shading structure are connected through a first routing line extending along the column direction, the second light shading structure is arranged between the first light shading portion and the second light shading portion of the adjacent first light shading structure, different second light shading structures are connected end to end through the second routing line, the second routing line is arranged at one end of the first light shading structure away from the first routing line along the row direction, the first routing lines of adjacent first light shading structures are respectively located on different sides of the light shading layer along the row direction, a third routing line is respectively provided on the outside of the two first routing lines, and the third routing line is connected to the adjacent first routing lines.

[0018] In one embodiment of the present disclosure, the first light shading portion includes a plurality of first light shading units and a plurality of second light shading units connected by first connecting lines, the first light shading units and the second light shading units are alternately arranged along the row direction, at least one first light shading unit and at least one second light shading unit are provided between every two adjacent second lines, the orthographic projection of the first light shading unit on the driving circuit layer overlaps with the active part of the compensation transistor, and the orthographic projection of the second light shading unit on the driving circuit layer overlaps with the active part of the write transistor.

[0019] In one embodiment of the present disclosure, the active portion of the compensation transistor includes a first channel region and a second channel region, the first shading unit includes a first shading block and a second shading block connected to each other, the first shading block extends in a row direction, the second shading block extends in a column direction, the first shading block has an orthographic projection on the driving circuit layer that overlaps with the first channel region, and the second shading block has an orthographic projection on the driving circuit layer that overlaps with the second channel region.

[0020] In one embodiment of the present disclosure, the second light shielding portion includes a plurality of interconnected third light shielding units, and the orthographic projections of the third light shielding units on the driving circuit layer overlap with the active portion of the first reset transistor and the active portion of the second reset transistor of the upper row of pixel circuits.

[0021] According to another aspect of the present disclosure, a display device is provided, comprising the display panel provided by any one aspect of the present disclosure.

[0022] The display panel disclosed herein includes a light-shielding layer and at least two pixel circuits. The light-shielding layer includes at least two light-shielding structure groups. One light-shielding structure group blocks one pixel circuit. Each light-shielding structure group includes a first light-shielding structure for inputting a first signal and a second light-shielding structure for inputting a second signal. The pixel circuit includes at least two transistors for receiving different signals. The orthographic projections of the first light-shielding structure and the second light-shielding structure on the driving circuit layer overlap with the active parts of different types of transistors, respectively. Two adjacent first light-shielding structures are connected together, and / or two adjacent second light-shielding structures are connected together. By connecting all the first light-shielding structures and / or all the first light-shielding structures together, the electrostatic release area and path of the light-shielding layer can be increased, so that the static electricity accumulated during the process can be released in time or evenly distributed, preventing static electricity from damaging the light-shielding layer or other film layers, and achieving a good display effect.

[0023] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0025] FIG1 is a plan view of a light-shielding layer according to an embodiment of the present disclosure when adjacent light-shielding structure groups are independent of each other.

[0026] FIG2 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0027] FIG3 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0028] FIG4 is a plan view of the light-shielding layer according to an embodiment of the present disclosure when the light-shielding layer includes a first light-shielding section, a second light-shielding section, and a third light-shielding section.

[0029] FIG5 is a plan view of the light shielding layer according to an embodiment of the present disclosure when the first wiring and the second wiring are located at different sides of the light shielding layer along the row direction.

[0030] FIG6 is a plan view of the light shielding layer according to an embodiment of the present disclosure when the first pin is disposed on the third trace.

[0031] FIG7 is a plan view of the light-shielding layer involved in the embodiment of the present disclosure when two adjacent first light-shielding structures are connected together and two adjacent second light-shielding structures are independent of each other.

[0032] FIG8 is a planar schematic diagram of the light-shielding layer involved in an embodiment of the present disclosure when two adjacent second light-shielding structures are connected together and two adjacent first light-shielding structures are independent of each other.

[0033] In the figure: 1. driving backplane, 11. substrate, 12. driving circuit layer, 121. semiconductor layer, 122. gate insulating layer, 123. gate layer, 124. dielectric layer, 125. first source and drain layer, 126. passivation layer, 127. first planarization layer, 128. second source and drain layer, 129. second planarization layer, 13. light shielding layer, 131. first light shielding structure, 1310. sub-first light shielding portion, 1311. first light shielding portion, 1312. second light shielding portion, 1313. first trace, 1314. first light shielding unit, 1315. second light shielding unit, 1316. first connecting line, 1317. Third light-shielding unit, 1318. First pin, 1319. Sub-second light-shielding portion, 132. Second light-shielding structure, 1320. Sub-second light-shielding structure, 1321. Third light-shielding unit, 1322. Second connecting line, 1323. Second pin, 133. Second trace, 134. Third trace, 135. First light-shielding plate, 136. Second light-shielding plate, 137. Third light-shielding plate, 14. Buffer layer, 2. Light-emitting layer, 21. Light-emitting device, 211. First electrode, 212. Light-emitting material layer, 213. Second electrode, 3. Pixel definition layer, 31. Pixel pixel opening. DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0035] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0036] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0037] As shown in Figure 1, to prevent light from reaching the transistors and affecting their electrical characteristics, a light shielding layer 13 is gradually being introduced into the manufacturing process of the driver backplane 1 of an OLED display panel. Taking the driver backplane 1 employing a 7T1C pixel circuit as an example, the currently commonly used shielding method primarily involves using the light shielding layer 13 to shield the first reset transistor T1, compensation transistor T2, drive transistor T3, write transistor T4, and second reset transistor T7. The light shielding layer 13 can include a first light shielding structure 131 and a second light shielding structure 132. The first light shielding structure 131 shields the drive transistor T3, while the second light shielding structure 132 shields the first reset transistor T1, compensation transistor T2, write transistor T4, and second reset transistor T7. To prevent the light shielding layer 13 from floating, which could lead to poor transistor characteristic uniformity, a voltage signal must be applied to the light shielding layer 13. A first signal can be applied to the first light shielding structure 131, and a second signal can be applied to the second light shielding structure 132. It should be noted that the first signal can be a constant voltage signal Vdd, and the second signal can be a gate signal.

[0038] The first light-shielding structure 131 and the second light-shielding structure 132 form a light-shielding structure group. To prevent a short circuit between the first light-shielding structure 131 and the second light-shielding structure 132, which could cause signal anomalies, the current light-shielding layer 13 is configured to use a group of light-shielding structure groups for each pixel circuit. Each light-shielding structure group exists independently, and static electricity accumulated in a single light-shielding structure group during the manufacturing process is difficult to release in a timely manner. As the number of handling, cleaning, and other processes involved in the production of display panels increases, when static electricity accumulates to a certain level and cannot be released, it can easily cause static damage to the light-shielding layer 13 or other film layers, resulting in poor display effects.

[0039] Based on this, an embodiment of the present disclosure provides a display panel. As shown in Figures 2 to 8, the display panel includes a base substrate 11, a driving circuit layer 12, and a light shielding layer 13. The driving circuit layer 12 is provided on one side of the base substrate 11. The driving circuit layer 12 includes at least two pixel circuits arranged along the row direction and arranged along the column direction. The column direction is perpendicular to the row direction. The pixel circuit includes at least two transistors for receiving different signals. The light shielding layer 13 is provided between the driving circuit layer 12 and the base substrate 11. The light shielding layer 13 includes at least two light shielding structure groups. Each light shielding structure group includes a first light shielding structure 131 and a second light shielding structure 132. The first light shielding structure 131 and the second light shielding structure 132 are provided. A shading structure 131 inputs a first signal, and a second shading structure 132 inputs a second signal. The first shading structure 131 and the second shading structure 132 extend along the row direction, and at least two first shading structures 131 and at least two second shading structures 132 are arranged along the column direction; one shading structure group blocks one pixel circuit, and the orthographic projections of the first shading structure 131 and the second shading structure 132 on the driving circuit layer 12 overlap with the active parts of different types of transistors respectively, and two adjacent first shading structures 131 are connected together, and / or two adjacent second shading structures 132 are connected together.

[0040] Each shading structure group includes a first shading structure 131 for inputting a first signal and a second shading structure 132 for inputting a second signal. Two adjacent first shading structures 131 are connected together, and / or two adjacent second shading structures 132 are connected together, which can increase the electrostatic release area and path of the shading layer 13, so that the static electricity accumulated during the process can be released in time or evenly distributed, preventing static electricity from damaging the shading layer 13 or other film layers, and achieving a good display effect.

[0041] The display panel involved in the embodiments of the present disclosure will be described in detail below with reference to specific embodiments.

[0042] As shown in Figure 2, the display panel includes a driving backplane 1 and a light-emitting layer 2. The driving backplane 1 includes a base substrate 11 and a driving circuit layer 12. The driving circuit layer 12 is provided on one side of the base substrate 11, and the light-emitting layer 2 is provided on the side of the driving circuit layer 12 away from the base substrate 11. The base substrate 11 can support the circuit layer and can be a rigid or flexible structure. It can be a single-layer or multi-layer structure, which is not particularly limited here. The driving circuit layer 12 is used to drive the light-emitting devices 21 to emit light independently to display images. The driving circuit may include pixel circuits, which are connected to the light-emitting devices 21.

[0043] The base substrate 11 may be an inorganic material or an organic material. For example, in one embodiment of the present disclosure, the base substrate 11 may be made of a glass material such as soda-lime glass, quartz glass, or sapphire glass, or may be made of a metal material such as stainless steel, aluminum, or nickel.

[0044] In another embodiment of the present disclosure, the material of the base substrate 11 can be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terethalate (PET), polyethylene nathalate (PEN) or a combination thereof.

[0045] In another embodiment of the present disclosure, the substrate 11 may be a flexible substrate 11. For example, the substrate 11 may be made of polyimide (PI). The substrate 11 may also be a composite of multiple layers. For example, in one embodiment of the present disclosure, the substrate 11 may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0046] The driving circuit layer 12 includes multiple pixel circuits, and the light-emitting layer 2 includes multiple light-emitting devices 21. The number of pixel circuits can be multiple, and the array is distributed in multiple rows and columns. One pixel circuit can be connected to one light-emitting device 21. Of course, it is also possible to have one pixel circuit connected to multiple light-emitting devices 21. This article only uses the one-to-one connection between pixel circuits and light-emitting devices 21 as an example for description.

[0047] Each pixel circuit may include multiple transistors and storage capacitors. The channel regions of each transistor may be arranged in the same layer and all may be made of semiconductor materials such as polysilicon. A pixel circuit may include multiple transistors and capacitors, and may be a 2T1C, 3T1C, or 7T1C pixel circuit. For illustration, 7T1C is used as an example, indicating that a pixel circuit includes seven transistors and one capacitor.

[0048] The transistors in the pixel circuit of the present disclosure may be N-type transistors or P-type transistors, or both. The transistor may have a gate, a first electrode, and a second electrode. The gate may control the on / off state of the transistor. The first electrode and the second electrode may be used to input and output signals. The first electrode may be the source electrode of the transistor, and the second electrode may be the drain electrode of the transistor. However, when the operating state of the transistor changes, for example, when the direction of the current changes, the source and drain electrode of the transistor may be interchangeable.

[0049] The driving circuit layer 12 includes a semiconductor layer 121, a gate insulating layer 122, a gate layer 123, a dielectric layer 124, a first source and drain layer 125, a passivation layer 126, a first planarization layer 127, a second source and drain layer 128, and a second planarization layer 129, which are sequentially arranged in a direction away from the base substrate 11. The material of the first planarization layer 127 and the second planarization layer 129 can be an organic material such as a transparent resin, and the surface of the planarization layer facing away from the driving backplane 1 is flat so that the light-emitting device 21 can be disposed thereon.

[0050] As shown in FIG2 , a pixel definition layer 3 is provided on the side of the driving circuit layer 12 away from the base substrate 11. The pixel definition layer 3 is provided with a pixel opening 31. Each light-emitting device 21 can be arranged in an array within the pixel opening 31. The light-emitting device 21 can be an organic light-emitting diode, which includes a first electrode 211, a light-emitting material layer 212, and a second electrode 213 stacked in a direction away from the base substrate 11. A first electrode 211 is connected to a pixel circuit and serves as an anode. The first electrode 211 can be a single-layer or multi-layer structure, and its material can include one or more of a conductive metal, a metal oxide, and an alloy. The first electrode 211 can be a light-shielding structure. For example, the first electrode 211 can include three metal layers. The material of the middle metal layer can be silver, aluminum, etc., and the materials of the other two metal layers can be titanium or other metals, without special limitation.

[0051] As shown in FIG2 , the light-emitting material layer 212 is at least partially disposed within the pixel opening 31 and may include a hole injection layer, a hole transport layer, a light-emitting material layer 212, an electron transport layer, and an electron injection layer stacked sequentially in a direction away from the substrate 11. Visible light is generated by allowing holes and electrons to recombine into excitons in the light-emitting material layer 212, which then radiate photons. The specific light-emitting principle is not described in detail here. The light-emitting material layer 212 can be arranged in an array, with each light-emitting device 21 having an independently emitting light-emitting material layer 212, so that each light-emitting device 21 can emit light independently, and the light-emitting colors of different light-emitting devices 21 can be different. For example, there are multiple light-emitting material layers 212, which are arranged in an array in each pixel opening 31 and stacked with the first electrode 211 exposed by the pixel opening 31. Alternatively, each light-emitting material layer 212 may share at least a portion of the film layer other than the light-emitting material layer 212, but the light-emitting material layers 212 are independently arranged, thereby also obtaining light-emitting devices 21 with different light-emitting colors.

[0052] As shown in Figure 2 , the second electrode 213 can cover the light-emitting material layer 212 and serve as the cathode of the light-emitting device 21. The second electrode 213 can be a single-layer or multi-layer structure, and its material can include one or more of a conductive metal, metal oxide, and alloy. Each light-emitting device 21 can share the same second electrode 213. Specifically, the second electrode 213 is a continuous conductive layer that covers the light-emitting material layer 212 of each light-emitting device 21 and the pixel definition layer 3. In other words, the orthographic projection of the second electrode 213 on the pixel definition layer 3 covers each pixel opening 31.

[0053] As shown in FIG2 , to define the range of each light-emitting device 21, a pixel definition layer 3 may be provided on the surface of the planarization layer facing away from the base substrate 11. The pixel definition layer 3 may be used to separate the light-emitting devices 21, thereby preventing color crosstalk between adjacent light-emitting devices 21. Specifically, the pixel definition layer 3 may be provided with a plurality of pixel openings 31, each correspondingly exposing a first electrode 211, with the boundary of each pixel opening 31 located within the boundary of the exposed first electrode 211. The range defined by each pixel opening 31 constitutes the range of a light-emitting device 21.

[0054] As shown in Figure 3, the pixel circuit can be a 7T1C structure, that is, it can have 7 transistors and 1 capacitor, namely, a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a write transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7 and a storage capacitor Cst.

[0055] As shown in FIG3 , a first electrode of the first reset transistor T1 is connected to the first reset signal line VIL1 for receiving the first reset signal Vinit1 , and a second electrode is connected to the gate of the driving transistor T3 and the first plate of the storage capacitor Cst.

[0056] A first electrode of the compensation transistor T2 is connected to a second electrode of the driving transistor T3 , and a second electrode of the compensation transistor T2 is connected to a gate of the driving transistor T3 .

[0057] A first electrode of the write transistor T4 is connected to the data line DAL for receiving a data signal DA, and a second electrode is connected to a first electrode of the drive transistor T3 .

[0058] The first electrode of the first light emitting control transistor T5 and the second electrode of the storage capacitor Cst are connected to the power line VDL for receiving the first power signal VDD, and the second electrode is connected to the first electrode of the driving transistor T3.

[0059] A first electrode of the second light emitting control transistor T6 is connected to the second electrode of the driving transistor T3 , and a second electrode of the second light emitting control transistor T6 is connected to a first electrode 211 of a light emitting device 21 .

[0060] The first electrode of the second reset transistor T7 is connected to the second reset signal line VIL2 for receiving the second reset signal Vinit2, and the second electrode is connected to the second electrode of the second light emitting control transistor T6. The second electrode 213 of the light emitting device 21 can receive the second power signal VSS.

[0061] To control the on / off switching of each transistor, the gate of the first reset transistor T1 is connected to a first reset control line REL1 for inputting a first reset control signal RE1. The gate of the second reset transistor T7 is connected to a second reset control line REL2 for inputting a second reset control signal RE2. The gates of the compensation transistor T2 and the write transistor T4 are connected to a scan line GL for inputting a scan signal GA. The gates of the first and second emission control transistors T5 and T6 are connected to an emission control line EML for inputting an emission control signal EM. This pixel circuit can be used to drive the connected light-emitting device 21 to emit light in response to signals provided by the connected signal terminals.

[0062] The gate layer 123 may include a first plate Cst1 of the storage capacitor Cst, a scan line GL, a first reset control line REL1, a second reset control line REL2, and an emission control line EML. The region where the scan line GL overlaps with the semiconductor layer 121S serves as the gate of the write transistor T4 and the compensation transistor T2. The region where the first reset control line REL1 overlaps with the semiconductor layer 121S serves as the gate of the first reset transistor T1. The region where the second reset control line REL2 overlaps with the semiconductor layer 121S serves as the gate of the second reset transistor T7. The region where the emission control line EML overlaps with the semiconductor layer 121S serves as the gate of the first emission control transistor T5 and the second emission control transistor T6. The region where the first plate Cst1 overlaps with the semiconductor layer 121S serves as the gate of the drive transistor T3. In other words, the first plate Cst1 serves as the gate of the drive transistor T3. The scan line GL and the semiconductor layer 121S have a first channel region T1C1 and a second channel region T1C2 connected to each other. The first channel region T1C1 and the second channel region T1C2 are channels of the compensation transistor T2 .

[0063] As shown in FIG4 , the display panel further includes a light shielding layer 13, which is disposed between the drive circuit layer 12 and the base substrate 11. A buffer layer 14 may be disposed between the light shielding layer and the drive circuit layer. The light shielding layer 13 includes a plurality of light shielding structure groups arranged along the column direction. Each light shielding structure group includes a first light shielding structure 131 and a second light shielding structure 132. The first light shielding structure 131 inputs a first signal, and the second light shielding structure 132 inputs a second signal. The first light shielding structures 131 and the second light shielding structures 132 extend along the row direction, with at least two first light shielding structures 131 and at least two second light shielding structures 132 arranged along the column direction.

[0064] Each pixel circuit is arranged along the row direction, and multiple pixel circuits are arranged along the column direction. One light shielding structure group shields one pixel circuit. The orthographic projection of the first light shielding structure 131 on the drive circuit layer 12 covers the active portion of the drive transistor T3. The orthographic projection of the second light shielding structure 132 on the drive circuit layer 12 covers the active portion T1C of the first reset transistor T1, the active portion T2C of the threshold compensation transistor T2, the active portion T4C of the write transistor T4, and the active portion T7C of the second reset transistor T7 of the pixel circuit in the previous row.

[0065] The first light shielding structure 131 includes a first light shielding portion 1311. The first light shielding portion 1311 and the second light shielding portion 1312 extend in the row direction and are arranged in the column direction. The first light shielding portion 1311 includes a plurality of first light shielding units 1314 and a plurality of second light shielding units 1315 connected by first connecting lines 1316. The first light shielding units 1314 and the second light shielding units 1315 are arranged alternately in the row direction. At least one first light shielding unit 1314 and at least one second light shielding unit 1315 are provided between every two adjacent second traces 133. The orthographic projections of the first light shielding units 1314 on the drive circuit layer 12 cover the active portion T2C of the compensation transistor T2, and the orthographic projections of the second light shielding units 1315 on the drive circuit layer 12 cover the active portion T4C of the write transistor T4.

[0066] As mentioned above, the active portion T2C of the compensation transistor T2 may include a first channel region T2C1 and a second channel region T2C2. Therefore, the first light shielding unit 1314 may include a first light shielding block and a second light shielding block connected to each other. The first light shielding block extends in the row direction, and the second light shielding block extends in the column direction. The first light shielding block's orthogonal projection on the drive circuit layer 12 covers the first channel region, and the second light shielding block's orthogonal projection on the drive circuit layer 12 covers the second channel region. The second light shielding unit 1315 includes a third light shielding block extending in the row direction. The third light shielding block's orthogonal projection on the drive circuit layer 12 covers the channel region of the active portion T4C of the write transistor T4.

[0067] The first light-shielding structure 131 may further include a second light-shielding portion 1312, the second light-shielding portion 1312 includes a plurality of interconnected third light-shielding units 1317, the third light-shielding units 1317 are light-shielding line segments extending along the row direction and having substantially equal dimensions along the column direction, and one light-shielding line segment is projected on the driving circuit layer 12 to cover the active portion T1C of the first reset transistor T1 and the active portion T7C of the second reset transistor T7 of the pixel circuit in the previous row.

[0068] The second light shielding structure 132 may include a plurality of fourth light shielding units 1321 connected by second connection lines 1322 , and the orthographic projections of the fourth light shielding units 1321 on the driving circuit layer 12 cover the active portion T3C of the driving transistor T3 .

[0069] The first light-shielding portions 1311 and second light-shielding portions 1312 of the multiple first light-shielding structures 131 are arranged alternately along the column direction. The second light-shielding structures 132 are located between the first light-shielding portions 1311 and the second light-shielding portions 1312 of the same first light-shielding structure 131. The first light-shielding portions 1311 and the second light-shielding portions 1312 of the same first light-shielding structure 131 are connected via three first traces 1313 extending along the column direction. It should be noted that two of the first traces 1313 are located on the left and right sides of the light-shielding layer 13 along the row direction, respectively, and another first trace 1313 is located between the first two traces 1313. First pins 1318 for receiving first signals can be provided on the first traces 1313 located on the left and right sides of the light-shielding layer 13.

[0070] The second light-shielding structures 132 located along the bottom edge of the light-shielding layer 13 along the column direction are continuous and uninterrupted. The remaining second light-shielding structures 132 are divided into a sub-second light-shielding structure 1320 between every two first traces 1313. The three first traces 1313 divide the second light-shielding structure 132 into two sub-second light-shielding structures 1320. The first light-shielding portions 1311 located along the top edge of the light-shielding layer 13 along the column direction are continuous and uninterrupted. The remaining first light-shielding portions 1311 and all the second light-shielding portions 1312 are provided with two interruptions along the row direction. These two interruptions divide the first light-shielding portion 1311 into three sub-first light-shielding portions 1310 and the second light-shielding portion 1312 into three sub-second light-shielding portions 1319. A interruption can be provided between every two adjacent first traces 1313, with the interruption located at the location where the first connecting line 1316 is provided.

[0071] Two adjacent sub-second light-shielding structures 1320 along the column direction are connected by a second trace 133 to form a first light-shielding section 135. The second trace 133 is located within the discontinuity and typically connects the fourth light-shielding units 1321 of two adjacent sub-second light-shielding structures 1320. A second pin 1323 for inputting a second signal may be provided on the fourth light-shielding unit 1321 located on one side of the second trace 133 along the row direction of the sub-second light-shielding structure 1320, or the second pin 1323 for inputting a second signal may be provided on both fourth light-shielding units 1321 located on both sides of the second trace 133 along the row direction of the sub-second light-shielding structure 1320.

[0072] The first light shielding portions 1311 and the second light shielding portions 1312 of the different first light shielding structures 131 are connected via a third trace 134 extending along the column direction. The third trace 134 is located between the first trace 1313 and the second trace 133. In this embodiment, the third trace 134 is disposed at one end of the sub-first light shielding portion 1310 and the sub-second light shielding portion 1319 near the second trace 133, and the two third traces 134 are symmetrically disposed on either side of the second trace 133. Specifically, one of the third traces 134 may be connected to the first light shielding unit 1314 of one sub-first light shielding portion 1310, and the other third trace 134 may be connected to the second light shielding unit 1315 of the other sub-first light shielding portion 1310.

[0073] The sub-first light-shielding portion 1310 and the sub-second light-shielding portion 1319 located at both ends of the first light-shielding portion 1311 on the top edge have their ends away from the discontinuity connected to the first trace 1313, and their ends close to the discontinuity connected to the third trace 134. Therefore, the first light-shielding structure 131 forms a second light-shielding section 136 that is connected end to end and continuous at both ends of the first light-shielding portion 1311 on the top edge, and the two ends of the first light-shielding portion 1311 located in the middle are respectively connected to a third trace 134, and a plurality of rectangular light-shielding rings are formed in the middle of the first light-shielding portion 1311 on the top edge. The plurality of rectangular light-shielding rings are interconnected through the first trace 1313 to form a third light-shielding section 137.

[0074] As shown in FIG5 , the first light-shielding portion 1311 and the second light-shielding portion 1312 of the same first light-shielding structure 131 are connected via a first trace 1313 extending along the column direction. The second light-shielding structure 132 is disposed between the first light-shielding portion 1311 and the second light-shielding portion 1312 of the same first light-shielding structure 131. The second light-shielding structures 132 are connected via a second trace 133 extending along the column direction. The first trace 1313 is located on one side of the light-shielding layer 13 along the row direction, and the second trace 133 is located on the other side of the light-shielding layer 13 along the row direction. It will be understood that the first trace 1313 and the second trace 133 are located at either end of the first light-shielding structure 131 or the second light-shielding structure 132 along the row direction.

[0075] It should be noted that the arrangement of the first pin 1318 and the second pin 1323 in FIG5 remains unchanged from that in FIG4 : the first pin 1318 for inputting the first signal is provided on the first trace 1313, and the second pin 1323 for inputting the second signal is provided on the second light shielding structure 132. The first light shielding portion 1311 and the second light shielding portion 1312 of the different first light shielding structures 131 are connected by a third trace 134 extending along the column direction. In this embodiment, the third trace 134 and the second trace 133 are located on the same straight line. In other feasible embodiments, the third trace 134 may also be provided at an end of the first light shielding portion 1311 and the second light shielding portion 1312 in the row direction away from the first trace 1313, that is, multiple first light shielding portions 1311 and second light shielding portions 1312 are connected end to end.

[0076] As shown in FIG6 , the first light-shielding portion 1311 and the second light-shielding portion 1312 of the same first light-shielding structure 131 are connected via a first trace 1313 extending along the column direction. The first traces 1313 of adjacent first light-shielding structures 131 are located on different sides of the light-shielding layer 13 along the row direction. The second light-shielding structure 132 is located between the first light-shielding portion 1311 and the second light-shielding portion 1312 of adjacent first light-shielding structures 131. Different second light-shielding structures 132 are connected end-to-end via the second trace 133. A third trace 134 is located outside each of the two first traces 1313, and the third trace 134 is connected to both adjacent first traces 1313. The first pin 1318 can be located on the third trace 134.

[0077] In other embodiments, as shown in FIG7 , two adjacent first light-shielding structures 131 can be connected together, while two adjacent second light-shielding structures 132 remain independent of each other. This can also, to a certain extent, increase the static discharge area and path of the light-shielding layer 13, allowing static electricity accumulated during the process to be promptly released or evenly distributed. Alternatively, as shown in FIG8 , two adjacent second light-shielding structures 132 can be connected together, while two adjacent first light-shielding structures 131 remain independent of each other.

[0078] It should be noted that the row direction in FIG. 1 and FIG. 4 to FIG. 8 is the x direction, and the column direction is the y direction.

[0079] The present disclosure also provides a display device. The display device may include any of the display panels described above. The specific structure and beneficial effects of the display panel have been described in detail above and are therefore not further elaborated here.

[0080] It should be noted that, in addition to the display panel, the display device also includes other necessary components and components, such as circuit boards, power cords, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

[0081] When the display panel has the structure shown in the figure, the display device can be a traditional electronic device, such as a mobile phone, a computer, a television, and a camcorder, or it can be an emerging wearable device, such as a virtual reality device and an augmented reality device, which are not listed here one by one.

[0082] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that: include: substrate substrate; A driving circuit layer, disposed on one side of the base substrate, the driving circuit layer comprising at least two pixel circuits arranged along a row direction and arranged along a column direction, the column direction being perpendicular to the row direction, and the pixel circuit comprising at least two transistors for receiving different signals; A light shielding layer is provided between the driving circuit layer and the base substrate, the light shielding layer includes at least two light shielding structure groups, each light shielding structure group includes a first light shielding structure and a second light shielding structure, the first light shielding structure inputs a first signal, the second light shielding structure inputs a second signal, the first light shielding structure and the second light shielding structure extend along the row direction, and the at least two first light shielding structures and the at least two second light shielding structures are arranged along the column direction; One of the shading structure groups shades one of the pixel circuits, the orthographic projections of the first shading structure and the second shading structure on the driving circuit layer overlap with the active parts of different types of transistors respectively, two adjacent first shading structures are connected together, and / or two adjacent second shading structures are connected together.

2. The display panel according to claim 1, characterized in that: The pixel circuit includes a first reset transistor, a compensation transistor, a driving transistor, a writing transistor, a first light emission control transistor, a second light emission control transistor, a second reset transistor and a storage capacitor; The first electrode of the first reset transistor is used to receive a first reset signal, and the second electrode is connected to the gate of the driving transistor and the first electrode plate of the storage capacitor; The first electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the gate of the driving transistor; the compensation transistor has two channels connected in series; The first electrode of the write transistor is connected to a data line, and the second electrode is connected to the first electrode of the drive transistor; The first electrode of the first light emitting control transistor and the second electrode plate of the storage capacitor are connected to a power line, and the second electrode is connected to the first electrode of the driving transistor; The first electrode of the second light emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light emitting device; The first electrode of the second reset transistor is used to receive the second reset signal, and the second electrode is connected to the The second electrode of the second light emitting control transistor is connected; The orthographic projection of the first shading structure on the driving circuit layer overlaps with the active portion of the first reset transistor, the active portion of the threshold compensation transistor, the active portion of the write transistor and the active portion of the second reset transistor of the upper row of pixel circuits, and the orthographic projection of the second shading structure on the driving circuit layer overlaps with the active portion of the driving transistor.

3. The display panel according to claim 2, characterized in that: The first light-shielding structure includes a first light-shielding portion and a second light-shielding portion, the first light-shielding portion and the second light-shielding portion extend along the row direction and are arranged along the column direction, the orthographic projection of the first light-shielding portion on the driving circuit layer overlaps with the active portion of the compensation transistor and the active portion of the write transistor, and the orthographic projection of the second light-shielding portion on the driving circuit layer overlaps with the active portion of the first reset transistor and the active portion of the second reset transistor of the pixel circuit in the previous row.

4. The display panel according to claim 3, characterized in that: The first shading portions and the second shading portions of at least two first shading structures are alternately arranged along the column direction, and the second shading structure is arranged between the first shading portion and the second shading portion of the same first shading structure, or between the first shading portion and the second shading portion of adjacent first shading structures.

5. The display panel according to claim 4, characterized in that: Two adjacent first light-shielding structures are connected together, and two adjacent second light-shielding structures are connected together.

6. The display panel according to claim 5, characterized in that: The first light-shielding portion and the second light-shielding portion of the same first light-shielding structure are connected by at least three first routings extending along the column direction, the first light-shielding portion located on one side of the light-shielding layer along the column direction is continuous and uninterrupted, the remaining first light-shielding portions and all the second light-shielding portions are provided with at least two discontinuities along the row direction, one discontinuity is provided between every two adjacent first routings, the second light-shielding structure is provided between the first light-shielding portion and the second light-shielding portion of the same first light-shielding structure, the second light-shielding structure located on the other side of the light-shielding layer along the column direction is continuous and uninterrupted, the remaining second light-shielding structures are interrupted into a sub-second light-shielding structure between every two first routings, the two adjacent sub-second light-shielding structures along the column direction are connected by a second routing, the second routing is located in the discontinuity, the first light-shielding portion and the second light-shielding portion of different first light-shielding structures are connected by a third routing extending along the column direction, the third routing is located between the first routing and the second routing.

7. The display panel according to claim 5, characterized in that: The first light shading portion and the second light shading portion of the same first light shading structure are connected by a first routing extending along the column direction, the second light shading structure is arranged between the first light shading portion and the second light shading portion of the same first light shading structure, the second light shading structure is connected by a second routing extending along the column direction, the first routing is located on one side of the light shading layer along the row direction, and the second routing is located on the other side of the light shading layer along the row direction, and the first light shading portion and the second light shading portion of different first light shading structures are connected by a third routing extending along the column direction.

8. The display panel according to claim 7, characterized in that: The third routing line and the second routing line are located on the same straight line.

9. The display panel according to claim 5, characterized in that: One end of the first light shading portion of the same first light shading structure and one end of the second light shading portion are connected through a first routing extending along the column direction, the second light shading structure is arranged between the first light shading portion and the second light shading portion of the adjacent first light shading structure, different second light shading structures are connected end to end through the second routing, the second routing is arranged at one end of the first light shading structure away from the first routing along the row direction, the first routings of adjacent first light shading structures are respectively located on different sides of the light shading layer along the row direction, a third routing is respectively arranged on the outer side of two first routings, and the third routing is connected to adjacent first routings.

10. The display panel according to claim 6, 7 or 9, characterized in that: The first light-shielding portion includes a plurality of first light-shielding units and a plurality of second light-shielding units connected by first connecting lines, the first light-shielding units and the second light-shielding units are alternately arranged along the row direction, at least one first light-shielding unit and at least one second light-shielding unit are arranged between every two adjacent second wirings, the orthographic projection of the first light-shielding unit on the driving circuit layer overlaps with the active part of the compensation transistor, and the orthographic projection of the second light-shielding unit on the driving circuit layer overlaps with the active part of the write transistor.

11. The display panel according to claim 10, characterized in that: The active portion of the compensation transistor includes a first channel region and a second channel region, the first shading unit includes a first shading block and a second shading block connected to each other, the first shading block extends along the row direction, the second shading block extends along the column direction, the first shading block has an orthographic projection on the driving circuit layer that overlaps with the first channel region, and the second shading block has an orthographic projection on the driving circuit layer that overlaps with the second channel region.

12. The display panel according to claim 5, characterized in that: The second light shielding portion includes a plurality of interconnected third light shielding units, and the orthographic projections of the third light shielding units on the driving circuit layer overlap with the active portions of the first reset transistor and the active portions of the second reset transistors of the pixel circuits in an upper row.

13. A display device, characterized in that: A display panel comprising any one of claims 1 to 12.

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