Clock switching control circuit and control method

Abstract

Disclosed in the present invention are a clock switching control circuit and control method. The control circuit comprises: a plurality of clock sources, a clock source selection circuit, a clock source synchronization circuit, a switching control module and an output clock switching circuit, wherein the clock source selection circuit is used for selecting a clock source on the basis of input signal states and priorities of the plurality of clock sources, inputting a clock source selection signal into the switching control module, and inputting a selected clock source signal into the clock source synchronization circuit; the clock source synchronization circuit is used for synchronizing an input clock source with an output clock source, and outputting a jitter indication signal; the switching control module is used for outputting, on the basis of the jitter indication signal and the clock source selection signal, a logic control signal for controlling output clock switching; and the output clock switching circuit is used for switching an output clock on the basis of the logic control signal. The present solution can reduce jitter during a clock switching process, and realize seamless clock switching.

Description

Clock switching control circuit and control method Technical Field

[0001] The present invention relates to the technical field of digital circuits, and in particular to a clock switching control circuit and method. Background Art

[0002] Clock signals play a very important role in digital systems. In order to ensure system stability and data transmission accuracy, clock signals must be reliable and stable.

[0003] Clock switching circuits are used to switch clock signals in digital circuits, enabling data from one clock domain to be correctly processed in another. Clock switching circuits typically consist of a clock selector, a delay latch, and a handshake circuit. When a clock signal needs to be switched, a control signal triggers the clock selector, selecting the input clock source to be switched. The delayed clock signal is then delayed by the delay latch to meet timing requirements, and the delayed clock signal is then aligned through the handshake circuit.

[0004] The existing clock switching circuit can ensure that no additional burrs are generated during the clock switching process, but a large jitter will be generated during the clock switching process. Summary of the Invention

[0005] In order to reduce jitter during the clock switching process, this solution provides a clock switching control circuit and method. Through clock detection and fault detection, the clock source switching operation can be automatically triggered, and the phase of the currently selected clock source and the backup clock source can be adjusted and synchronized through the clock source synchronization circuit. When switching the clock source, various jitters can be reduced, and seamless switching of the signal source can be achieved. After the switching is completed, a feedback signal is sent to enable the normal operation of the system.

[0006] According to a first aspect of the present invention, a clock switching control circuit is provided, comprising: a plurality of clock sources, a clock source selection circuit, a clock source synchronization circuit, a switching control module, and an output clock switching circuit.

[0007] The clock source selection circuit is used to select a clock source according to the input signal state and priority of the clock source, input the clock source selection signal into the switching control module, and input the selected clock source signal into the clock source synchronization circuit;

[0008] The clock source synchronization circuit is used to synchronize the input clock source with the output clock source and output a jitter indication signal;

[0009] The switching control module is used to output a logic control signal for controlling the switching of the output clock according to the jitter indication signal of the clock source synchronization circuit and the clock source selection signal output by the clock source selection circuit;

[0010] The output clock switching circuit is used for switching the output clock according to the logic control signal.

[0011] Optionally, in the clock switching control circuit provided by the present invention, the clock source selection circuit may include a detection circuit, a priority determination circuit and a selection circuit.

[0012] The detection circuit is used to detect whether multiple clock sources have clock inputs and output a detection signal; the priority judgment circuit is used to determine the current clock source to be selected based on the preset priority and the detection signal, and output a clock source selection signal; the selection circuit is used to select the corresponding clock source as the output clock based on the clock source selection signal output by the priority judgment circuit.

[0013] Optionally, in the clock switching control circuit provided by the present invention, if the clock source has a clock input, the detection circuit outputs a detection signal of 1; if there is no clock input, the detection circuit outputs a detection signal of 0.

[0014] Optionally, in the clock switching control circuit provided by the present invention, the priority judgment circuit is used to determine the current clock source to be selected according to the priority binary code of each clock source and the digital logic gate calculation result of the detection signal of each clock source.

[0015] Optionally, in the clock switching control circuit provided by the present invention, when the detection circuit detects a current clock source failure, clock source switching is automatically triggered on the rising edge or falling edge of the clock source signal in descending order of clock source priority.

[0016] Optionally, in the clock switching control circuit provided by the present invention, the clock source synchronization circuit includes a clock buffer for slowly switching the current clock source to the alternative clock source.

[0017] Optionally, in the clock switching control circuit provided by the present invention, the clock source synchronization circuit includes a jitter indication circuit for measuring the phase difference between the clock input signal and the clock output signal, and converting the phase difference signal into a voltage signal for output.

[0018] Optionally, in the clock switching control circuit provided by the present invention, when the clock source synchronization circuit turns on the de-jitter function, the switching control module is used to control the output clock switching circuit to use the output clock of the clock source synchronization circuit as the system output clock.

[0019] Optionally, in the clock switching control circuit provided by the present invention, when the de-jitter function of the clock source synchronization circuit is disabled, the switching control module is used to control the output clock switching circuit to use the input clock of the clock source synchronization circuit as the system output clock.

[0020] According to a second aspect of the present invention, there is provided a clock switching control method, comprising: selecting a current clock source based on input signal states and priorities of a plurality of clock sources, automatically switching to a backup clock source in order of priority when a failure of the current clock source is detected, and outputting a clock source selection signal;

[0021] Synchronize the current clock source with the backup clock source and output a jitter indication signal; output a logic control signal for controlling the output clock switching according to the jitter indication signal and the clock source selection signal; and switch the output clock according to the logic control signal.

[0022] According to the clock switching control circuit and method provided by the present invention, the clock source switching operation can be automatically triggered through clock detection and fault detection, and the phase of the currently selected clock source and the backup clock source can be adjusted and synchronized through the clock source synchronization circuit. When switching the clock source, various jitters can be reduced to achieve seamless switching of the signal source. After the switching is completed, a feedback signal is sent to enable the system to operate normally.

[0023] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0025] FIG1 shows a schematic structural diagram of a clock switching control circuit according to an embodiment of the present invention;

[0026] FIG2 shows a schematic structural diagram of a clock source selection circuit according to an embodiment of the present invention;

[0027] FIG3 shows a schematic flow chart of a clock switching control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to reduce or avoid short-term jitter or interference during clock switching, this solution provides a clock switching control circuit and method that can smoothly switch to a backup clock source when the current clock source fails or needs to be switched, improve the various jitter and noise performance generated during the clock switching process, achieve seamless switching of the output clock, and improve the stability of system operation.

[0029] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] Figure 1 shows a schematic diagram of a clock switching control circuit according to one embodiment of the present invention. As shown in Figure 1 , the clock switching control circuit includes multiple clock sources (clock source 1, clock source 2, ..., clock source N), a clock source selection circuit, a clock source synchronization circuit, an output clock switching circuit, and a switching control module.

[0031] Among them, the clock source is used to provide the clock signal required by the system. Common clock sources include crystal oscillators, external clock generators, internal clock generators, etc. Different clock sources can be selected according to different application scenarios to meet the system's clock signal requirements.

[0032] The clock source selection circuit is used to select a clock source according to the input signal state and priority of the clock source, input the clock source selection signal into the switching control module, and input the selected clock source signal into the clock source synchronization circuit.

[0033] Specifically, the clock source selection circuit can detect whether the input clock source signal exists, and automatically select an available clock source as the output clock according to the priority set by the system or the custom priority.

[0034] Figure 2 shows a schematic diagram of the structure of a clock source selection circuit according to an embodiment of the present invention. As shown in Figure 2, the clock source selection circuit includes a detection circuit (detection circuit 1 ... detection circuit N), a priority determination circuit, and a selection circuit.

[0035] Detection circuits 1 through N are respectively configured to detect whether clock sources 1 through N are receiving clock inputs and output detection signals. If a clock source is receiving clock input, the detection circuit outputs a detection signal of 1; if not, the detection circuit outputs a detection signal of 0. This can also be achieved using a dedicated clock monitoring chip.

[0036] When the detection circuit detects a fault in the current clock source, it automatically triggers clock source switching at the rising or falling edge of the clock source signal in descending order of clock source priority, thereby maintaining a stable state of the clock signal.

[0037] The priority judgment circuit can determine the clock source to be selected based on the priority binary code of each clock source and the digital logic gate calculation result of the detection signal of each clock source.

[0038] In one embodiment of the present invention, the priority determination circuit first determines the number of input signals to be compared. Assuming there are n input clock signals, an encoder is used to encode the n input signals to generate a binary code output.

[0039] Based on the priority requirements, the binary codes output by the encoder should be ordered from high to low. That is, the code corresponding to the highest priority signal should be the smallest. Based on the output of the priority encoder, a digital logic circuit (such as an AND gate, OR gate, or NAND gate) is designed to determine the input signal with the highest priority. Finally, the output of the priority judgment logic determines the clock source to be selected.

[0040] The selection circuit is used to select the corresponding clock source as the output clock according to the clock source selection signal output by the priority judgment circuit. The output clock can be a direct clock source output or an optimized clock source output.

[0041] For example, if there are two clock sources, namely clock source 1 and clock source 2, and clock source 1 has a higher priority than clock source 2, when both clock sources 1 and 2 receive signals simultaneously, the clock source selection circuit outputs the clock source selection signal to the switching control module and simultaneously outputs the signal from clock source 1 to the clock source synchronization circuit. As shown in Figure 1, clock 1 is the signal from clock source 1.

[0042] The clock source synchronization circuit is used to synchronize the input clock source with the output clock source and output a jitter indication signal. It can be an analog phase-locked loop or a digital phase-locked loop.

[0043] For example, when an input clock source signal passes through a phase-locked loop (PLL), it serves as a reference signal, which is then compared in phase with the signal output by an oscillator within the PLL. Based on the phase difference output by the phase comparator, the PLL adjusts the oscillator's frequency and phase, causing the output signal's phase to gradually approach that of the reference signal, and its frequency to converge to that of the reference signal. This adjustment process is accomplished through control circuits within the PLL, such as a low-pass filter and a control voltage generator.

[0044] When the PLL reaches a stable state, the output signal has a frequency and phase close to that of the reference signal. Through phase comparison, frequency, and phase control, the PLL converts the input reference signal into a stable and accurate output signal, thereby adjusting the clock source signal.

[0045] The clock source synchronization circuit includes a clock buffer that is used to slowly switch the current clock source to the alternative clock source. During the switching process, the control voltage or delay of the buffer is gradually adjusted to achieve a smooth transition of the clock source.

[0046] 1 , after the signal of clock 1 passes through the clock source synchronization circuit, the output phase of clock 2 is the same as that of clock 1.

[0047] The clock source synchronization circuit also includes a jitter indication circuit for measuring the phase difference between the input clock signal and the output clock signal, and converting the phase difference signal into a voltage signal for output.

[0048] The switching control module is used to output a logic control signal for controlling the output clock switching according to the jitter indication signal of the clock source synchronization circuit and the clock source selection signal output by the clock source selection circuit. The output clock switching circuit is used to switch the output clock according to the logic control signal of the switching control module.

[0049] When the de-jitter function of the clock source synchronization circuit is enabled, the switching control module is used to control the output clock switching circuit to use the output clock of the clock source synchronization circuit as the system output clock. When the de-jitter function of the clock source synchronization circuit is disabled, the switching control module is used to control the output clock switching circuit to use the input clock of the clock source synchronization circuit as the system output clock.

[0050] In the above embodiment, if the de-jitter function is enabled in the clock source synchronization circuit, the jitter performance of clock 2 is higher than that of clock 1. At this time, the switching control module controls the output clock switching circuit to use clock 2 as the system output clock.

[0051] When the de-jitter function is disabled in the clock source synchronization circuit, clock 2 is used as the output clock during the phase-lock process based on the jitter indication signal from the clock source synchronization circuit and the clock source selection signal output by the clock source selection circuit. After the signal stabilizes, the switching control module controls the output clock switching circuit to switch the output clock to clock 1. In this way, the jitter performance of the output clock is the same as that of the clock source, achieving a seamless switching effect.

[0052] After that, if clock source 1 suddenly goes offline, the clock source selection circuit detects the change in the clock source input state and automatically switches the signal of clock 1 to clock source 2. At the same time, it outputs the clock source selection signal to the switching control module. Then, clock 2 slowly switches from the frequency of clock source 1 to the frequency of clock source 2.

[0053] FIG3 shows a flow chart of a clock switching control method 300 according to an embodiment of the present invention. As shown in FIG3 , the method includes:

[0054] Step S310 , selecting a current clock source according to the input signal states and priorities of multiple clock sources, automatically switching to a backup clock source according to the priority order when a failure of the current clock source is detected, and outputting a clock source selection signal.

[0055] Step S320: synchronize the input clock source with the output clock source, and output a jitter indication signal.

[0056] The clock source can be automatically switched through signal detection and fault detection. During the switch, the backup clock source is gradually transitioned to the main clock source through timing control and buffering operations, ensuring that no sudden changes or interference signals are generated during the switch.

[0057] Step S330 : Outputting a logic control signal for controlling output clock switching according to the jitter indication signal and the clock source selection signal.

[0058] Step S340: switching the output clock according to the logic control signal.

[0059] Jitter during clock switching can be minimized through jitter analysis and switching feedback control.

[0060] According to the clock switching control circuit and method provided by the present invention, by detecting the clock source signal input and fault detection, it is possible to automatically switch when a clock source fault occurs, and synchronize the alternative clock source with the current main clock source before switching to eliminate the phase and frequency differences between the alternative clock source and the main clock source. It can improve the various jitter and noise performance generated during the clock switching process, realize seamless switching of the output clock, and improve the stability of the system operation. It is suitable for application scenarios with strict timing requirements such as high-speed communication and data processing.

[0061] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0062] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0063] Those skilled in the art will appreciate that the modules, units, or components of the devices in the examples disclosed herein may be arranged in the device described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or further divided into multiple submodules.

[0064] Those skilled in the art will appreciate that the modules in the devices of the embodiments can be adaptively modified and installed in one or more devices different from the embodiments. The modules, units, or components in the embodiments can be combined into a single module, unit, or component, and furthermore, they can be divided into multiple sub-modules, sub-units, or sub-components. All features disclosed in this specification (including the accompanying claims, abstract, and drawings), and all processes or units of any method or device disclosed therein, can be combined in any combination, unless at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0065] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims below, any of the claimed embodiments may be used in any combination.

[0066] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions described. Thus, a processor having the necessary instructions for implementing the method or method element forms a device for implementing the method or method element. Furthermore, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0067] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved and are not intended to imply that the objects so described must have a given order in time, space, ranking, or in any other manner.

[0068] Although the present invention has been described with respect to a limited number of embodiments, it will be apparent to those skilled in the art, having benefit of the foregoing description, that other embodiments are contemplated within the scope of the invention thus described. Furthermore, it should be noted that the language used in this specification has been selected primarily for readability and didactic purposes, rather than for the purpose of explaining or limiting the subject matter of the present invention. Consequently, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is intended to be illustrative and not restrictive of the scope of the invention, which is defined by the appended claims.

Claims

1. A clock switching control circuit, characterized in that: include: Multiple clock sources, clock source selection circuit, clock source synchronization circuit, switching control module and output clock switching circuit, The clock source selection circuit is used to select an available clock source as an output clock according to the input signal state and priority of the clock source, input the clock source selection signal into the switching control module, and input the selected clock source signal into the clock source synchronization circuit; The clock source synchronization circuit is a phase-locked loop, and the clock source synchronization circuit includes a jitter indication circuit, which is used to measure the phase difference between the input clock and the output clock, and convert the phase difference signal into a voltage signal output, so as to synchronize the input clock source with the output clock source, and output a jitter indication signal; The switching control module is used to output a logic control signal for controlling the switching of the output clock according to the jitter indication signal of the clock source synchronization circuit and the clock source selection signal output by the clock source selection circuit; The output clock switching circuit is used to switch the output clock according to the logic control signal.

2. The clock switching control circuit according to claim 1, characterized in that: The clock source selection circuit includes a detection circuit, a priority judgment circuit and a selection circuit. The detection circuit is used to detect whether multiple clock sources have clock inputs and output a detection signal; The priority judgment circuit is used to judge the current clock source to be selected according to the preset priority and the detection signal, and output a clock source selection signal; The selection circuit is used to select a corresponding clock source as an output clock according to a clock source selection signal output by a priority judgment circuit.

3. The clock switching control circuit according to claim 2, characterized in that: If the clock source has a clock input, the detection circuit outputs a detection signal of 1; if there is no clock input, the detection circuit outputs a detection signal of 0.

4. The clock switching control circuit according to claim 3, characterized in that: The priority judgment circuit is used to determine the current clock source to be selected according to the binary priority code of each clock source and the digital logic gate calculation result of the detection signal of each clock source.

5. The clock switching control circuit according to claim 3, characterized in that: When the detection circuit detects that the current clock source fails, the clock source switching is automatically triggered at the rising edge or falling edge of the clock source signal in the order of clock source priority from high to low.

6. The clock switching control circuit according to claim 5, characterized in that: The clock source synchronization circuit includes a clock buffer for slowly switching the current clock source to the alternative clock source.

7. The clock switching control circuit according to claim 1, characterized in that: When the de-jitter function of the clock source synchronization circuit is turned on, the switching control module is used to control the output clock switching circuit to use the output clock of the clock source synchronization circuit as the system output clock.

8. The clock switching control circuit according to claim 1, characterized in that: When the de-jitter function of the clock source synchronization circuit is turned off, the switching control module is used to control the output clock switching circuit to use the input clock of the clock source synchronization circuit as the system output clock.

9. A clock switching control method, characterized in that: include: Select an available clock source as an output clock according to the input signal status and priority of multiple clock sources, automatically switch to a backup clock source according to the priority order when a current clock source failure is detected, output a clock source selection signal, input the clock source selection signal into a switching control module, and input the selected clock source signal into a clock source synchronization signal; The current clock source is synchronized with the backup clock source by measuring the phase difference between the input clock and the output clock, and a jitter indication signal is output; Outputting a logic control signal for controlling output clock switching according to the jitter indication signal and the clock source selection signal; The output clock is switched according to the logic control signal.

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