Oxide semiconductor film, thin-film transistor, and electronic device

Abstract

Provided is an oxide semiconductor film having crystallinity, said oxide semiconductor film comprising indium (In) and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanoid-based elements. The oxide semiconductor film contains a plurality of crystal grains which each include at least one of the <101> crystal orientation, the <111> crystal orientation, and the <001> crystal orientation that are measured by an electron backscatter diffraction method. The occupancy ratio of a first region in which the <101> crystal orientation is oriented within 15° with respect to the normal direction of the surface of the oxide semiconductor film is not less than 20%.

Description

Oxide semiconductor film, thin film transistor, and electronic device

[0001] One embodiment of the present invention relates to an oxide semiconductor film (Poly-OS film) having a polycrystalline structure. Another embodiment of the present invention relates to a thin film transistor including the Poly-OS film. Another embodiment of the present invention relates to an electronic device including the thin film transistor.

[0002] In recent years, development of thin film transistors using oxide semiconductor films as channels has been progressing, instead of silicon semiconductor films using amorphous silicon, low-temperature polysilicon, single-crystal silicon, etc. (see, for example, Patent Documents 1 to 6). Thin film transistors including oxide semiconductor films have a simple structure similar to thin film transistors including amorphous silicon films and can be formed by low-temperature processes. Thin film transistors including oxide semiconductor films are also known to have higher field-effect mobility than thin film transistors including amorphous silicon films.

[0003] JP 2021-141338 A JP 2014-099601 A JP 2021-153196 A JP 2018-006730 A JP 2016-184771 A JP 2021-108405 A

[0004] However, the field-effect mobility of a thin film transistor including a conventional oxide semiconductor film is not so high even when a crystalline oxide semiconductor film is used. Therefore, it has been desired to improve the crystalline structure of the oxide semiconductor film used in the thin film transistor and thereby increase the field-effect mobility of the thin film transistor.

[0005] In view of the above problems, an object of one embodiment of the present invention is to provide an oxide semiconductor film having a novel crystal structure. Another object of one embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor film having the novel crystal structure. Another object of one embodiment of the present invention is to provide an electronic device including a thin film transistor.

[0006] An oxide semiconductor film according to one embodiment of the present invention is a crystalline oxide semiconductor film, which contains indium (In) and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanoid elements, and which contains a plurality of crystal grains each having at least one of a <101> crystal orientation, a <111> crystal orientation, and a <001> crystal orientation, as measured by electron backscatter diffraction, and which has an occupancy rate of 20% or more of first regions in which the <101> crystal orientation is oriented within 15° with respect to a normal direction to a surface of the oxide semiconductor film.

[0007] An oxide semiconductor film according to one embodiment of the present invention is a crystalline oxide semiconductor film, the oxide semiconductor film comprising indium (In) and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and a lanthanoid element; the oxide semiconductor film comprises a plurality of crystal grains, each of which has at least one of a <101> crystal orientation, a <111> crystal orientation, and a <001> crystal orientation, as measured by electron backscatter diffraction. The oxide semiconductor film comprises a first region in which the <101> crystal orientation is oriented within 15° with respect to a direction normal to the surface of the oxide semiconductor film, a second region in which the <111> crystal orientation is oriented within 15° with respect to a direction normal to the surface of the oxide semiconductor film, and a third region in which the <001> crystal orientation is oriented within 15° with respect to a direction normal to the surface of the oxide semiconductor film, and the occupancy of the third region is smaller than that of the first region and that of the second region.

[0008] A thin film transistor according to one embodiment of the present invention includes the oxide semiconductor film.

[0009] An electronic device according to one embodiment of the present invention includes the thin film transistor.

[0010] FIG. 1 is a schematic diagram illustrating a method for measuring an oxide semiconductor film by EBSD. FIG. 2 is a schematic diagram illustrating a coordinate system used in EBSD. FIG. 3 is a schematic cross-sectional view illustrating the configuration of a thin film transistor according to an embodiment of the present invention. FIG. 4 is a schematic plan view illustrating the configuration of a thin film transistor according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG. 8 is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG. 9 is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG. 10 is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG. 11 is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor according to an embodiment of the present invention. 1 is an IPF map in ND of Example Sample 1-2 obtained by crystal orientation analysis using the EBSD method. 2 is an IPF map in ND of Example Sample 1-3 obtained by crystal orientation analysis using the EBSD method. 3 is an IPF map in ND of Example Sample 1-3 obtained by crystal orientation analysis using the EBSD method. 4 is an IPF map in ND of Example Sample 1-4 obtained by crystal orientation analysis using the EBSD method. 5 is an IPF map in ND of Example Sample 1-4 obtained by crystal orientation analysis using the EBSD method. 6 is a graph showing a distribution map of all adjacent point orientation changes of Example Sample 1-1. 7 is a graph showing a distribution map of KAM values ​​of Example Sample 1-1. 8 is a graph showing a distribution map of grain boundary orientation changes of Example Sample 1-1. 9 is a graph showing a distribution map of all adjacent point orientation changes of Example Sample 1-2.1 is a graph showing a distribution map of KAM values ​​for example sample 1-2. FIG. 2 is a graph showing a distribution map of grain boundary orientation change for example sample 1-2. FIG. 3 is a graph showing a distribution map of all adjacent point orientation change for example sample 1-3. FIG. 4 is a graph showing a distribution map of KAM values ​​for example sample 1-3. FIG. 5 is a graph showing a distribution map of grain boundary orientation change for example sample 1-3. FIG. 6 is a graph showing a distribution map of all adjacent point orientation change for example sample 1-4. FIG. 7 is a graph showing a distribution map of KAM values ​​for example sample 1-4. FIG. 8 is a graph showing a distribution map of grain boundary orientation change for example sample 1-4.

[0011] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily arrive at by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part more schematically than the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and drawings, components similar to those described above with reference to the previous figures are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0012] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below." For convenience of explanation, the terms "up" or "below" are used in the description. However, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be different from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When referring to a pixel electrode above a thin film transistor, the thin film transistor and the pixel electrode may not overlap in a planar view. On the other hand, when referring to a pixel electrode vertically above a thin film transistor, the thin film transistor and the pixel electrode may overlap in a planar view.

[0013] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0014] In this specification, the term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0015] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0016] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0017] First Embodiment An oxide semiconductor film according to one embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

[0018] [1. Composition of Oxide Semiconductor Film] The oxide semiconductor film according to this embodiment contains indium (In) and at least one or more metal elements (M) other than indium. The composition ratio of the oxide semiconductor film preferably satisfies formula (1) in terms of the atomic ratio of indium and at least one or more metal elements. In other words, the ratio of indium to all metal elements in the oxide semiconductor film is preferably 50% or more. By increasing the ratio of indium, an oxide semiconductor film having crystallinity can be formed. Furthermore, the crystal structure of the oxide semiconductor film preferably has a bixbyite structure. By increasing the ratio of indium, an oxide semiconductor film having a bixbyite structure can be formed.

[0019]

[0020] The at least one or more metal elements are preferably, for example, one or more metal elements selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanoid elements.

[0021] The first metal element included in the at least one metal element is preferably gallium. Gallium belongs to the same group 13 as indium, and therefore does not impair the crystallinity of the oxide semiconductor film. That is, even if the oxide semiconductor film contains gallium as the first metal element, it is possible to form an oxide semiconductor film having a bixbyite structure.

[0022] When the first metal element is gallium, the oxide semiconductor film may contain a second metal element (M2) selected from the group consisting of aluminum, yttrium, scandium, and lanthanoid elements. In this case, in the composition ratio of the oxide semiconductor film, the atomic ratio of indium, gallium, and the second metal element preferably satisfies formulas (2), (3), and (4). Because the ratio of the second metal element is lower than the ratio of indium or gallium, the second metal element does not impair the crystallinity of the oxide semiconductor film.

[0023]

[0024]

[0025]

[0026] Although the detailed manufacturing method of the oxide semiconductor film will be described later together with the manufacturing method of a thin film transistor, the oxide semiconductor film can be formed by a sputtering method. The composition of the oxide semiconductor film formed by the sputtering method depends on the composition of the sputtering target. With a sputtering target having the above-described composition, an oxide semiconductor film without compositional deviation of metal elements can be formed by the sputtering method. Therefore, the composition of the metal elements (e.g., indium or gallium) of the oxide semiconductor film may be the same as the composition of the metal elements of the sputtering target. For example, the composition of the metal elements of the oxide semiconductor film can be specified based on the composition of the metal elements of the sputtering target. Note that the oxygen contained in the oxide semiconductor film varies depending on the process conditions of the sputtering method, and is therefore not limited to this.

[0027] The composition of metal elements in the oxide semiconductor film can also be determined by X-ray fluorescence analysis, electron probe microanalyzer (EPMA) analysis, or the like. Furthermore, since the oxide semiconductor film has crystallinity, the composition of the oxide semiconductor film may be determined by X-ray diffraction (XRD). Specifically, the composition of metal elements in the oxide semiconductor film can be determined based on the crystal structure and lattice constant of the oxide semiconductor film obtained by XRD.

[0028] [2. Crystal Structure of Oxide Semiconductor Film] The oxide semiconductor film according to this embodiment has crystallinity. Specifically, the oxide semiconductor film has a polycrystalline structure including a plurality of crystal grains. Although the details will be described later, by using a Poly-crystalline Oxide Semiconductor (Poly-OS) technique, an oxide semiconductor film having a novel polycrystalline structure different from conventional oxide semiconductor films can be formed. Therefore, hereinafter, the oxide semiconductor film having a polycrystalline structure according to this embodiment may be referred to as a Poly-OS film to distinguish it from conventional oxide semiconductor films having a polycrystalline structure.

[0029] Each crystal grain in the Poly-OS film may be composed of a plurality of crystallites. The crystallite diameter is not particularly limited, but is preferably 1 nm or more, more preferably 10 nm or more, and further preferably 15 nm or more. The crystallite diameter can be measured by electron beam diffraction, XRD, or the like.

[0030] The crystal structure of the Poly-OS film is not limited to a particular structure, but is preferably a bixbyite structure. The crystal structure of the Poly-OS film can be identified by XRD or electron beam diffraction.

[0031] In the Poly-OS film, the crystal grains may have one type of crystal structure or may have multiple types of crystal structures. When the Poly-OS film has multiple types of crystal structures, one of the multiple types of crystal structures is preferably a bixbyite structure.

[0032] The crystal structure of a Poly-OS film is different from that of a conventional oxide semiconductor film having a polycrystalline structure. The inventors have found that crystal grains in a Poly-OS film have characteristics different from those in conventional oxide semiconductor films. Such characteristics of a Poly-OS film can be measured by electron backscatter diffraction (EBSD). Hereinafter, measurement of an oxide semiconductor film by EBSD will be described.

[0033] [2-1. EBSD Method] The EBSD method is an analytical method in which an object to be measured is irradiated with an electron beam, and electron backscatter diffraction generated on each crystal plane of the crystal structure of the object to be measured is analyzed to measure the crystal structure of a measurement region of the object to be measured. The EBSD method can obtain information such as the crystal orientation and crystal grains of an oxide semiconductor film in a measurement region by analyzing data obtained from an EBSD detector attached to a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0034] Fig. 1 is a schematic diagram illustrating a method for measuring an oxide semiconductor film by EBSD, and Fig. 2 is a schematic diagram illustrating a coordinate system used in the EBSD.

[0035] As shown in FIG. 1 , when an electron beam is irradiated onto the surface of an oxide semiconductor film 500 tilted at a predetermined angle (e.g., 70°), the electron beam is diffracted by each crystal plane of the crystalline structure of the oxide semiconductor film 500, and diffracted electron beams having an EBSD pattern corresponding to the crystal orientation are emitted. This EBSD pattern is detected by an EBSD detector 600 (e.g., a CCD sensor or a CMOS sensor), and crystal orientation analysis, such as indexing of the crystal orientation, is performed on the EBSD pattern to determine the crystal orientation. Furthermore, by scanning the electron beam and mapping the EBSD pattern, information such as the crystal orientation and crystal grains on the surface of the oxide semiconductor film 500 can be obtained. In crystal orientation analysis using the EBSD method, a coordinate system consisting of a rolling direction (RD), a transverse direction (TD), and a normal direction (ND) is used, as shown in FIG. 2 . When the surface of the oxide semiconductor film 500 is irradiated with an electron beam, RD and TD correspond to the in-plane directions of the oxide semiconductor film 500 , and ND corresponds to the normal direction to the surface of the oxide semiconductor film 500 .

[0036] Note that when the oxide semiconductor film 500 is provided on a flat substrate, the surface of the oxide semiconductor film 500 is approximately parallel to the surface of the substrate. In this case, ND may be described as corresponding to the normal direction to the surface of the substrate.

[0037] [2-2. IPF Map] Crystal orientation analysis of measurement data obtained by the EBSD method can be performed to create an IPF (Inverse Pole Figure) map. An IPF map is an image in which the crystal orientation in a specific direction (ND, RD, or TD) of the object being measured is divided according to a predetermined index. Generally, the crystal orientation is color-coded according to a color key. Measurement using the EBSD method can obtain crystal orientation information at each measurement point. Therefore, an IPF map can be created based on the crystal orientation information obtained at each measurement point. In addition, in an IPF map, the area of ​​each divided region can be obtained, and the ratio to the area of ​​the entire measurement region (hereinafter referred to as "occupancy rate") can be calculated and quantitatively compared.

[0038] An IPF map may be an image obtained by extracting data from measurement points where the crystal orientation difference with respect to the normal direction of the substrate surface (or the surface of the oxide semiconductor film) is within a predetermined angle range. In other words, an IPF map may be an image obtained by extracting regions where a specific crystal orientation is oriented within a predetermined angle range with respect to the normal direction of the substrate surface. For example, the predetermined angle range is 0° to 15°. Such an IPF map excludes measurement points with crystal orientations that are significantly tilted from the normal direction of the substrate surface, thereby revealing crystal orientations that tend to be oriented with respect to the normal direction of the substrate surface. Therefore, by comparing the occupancy rates of regions containing multiple crystal orientations, it is possible to more clearly identify crystal orientations that tend to be oriented with respect to the normal direction of the substrate surface.

[0039] When the oxide semiconductor film according to this embodiment has a bixbyite structure, the occupancy of the region where the crystal orientation <101> is oriented within 15° with respect to the normal direction (ND) of the substrate surface (hereinafter referred to as the "crystal orientation <101> region") is 20% or more, preferably 21% or more, more preferably 23% or more, and particularly preferably 26% or more. The occupancy of the region where the crystal orientation <111> is oriented within 15° with respect to the ND (hereinafter referred to as the "crystal orientation <111> region") is 15% or more, preferably 18% or more. Furthermore, the occupancy of the region where the crystal orientation <001> is oriented within 15° with respect to the ND (hereinafter referred to as the "crystal orientation <001> region") is less than 10%, preferably 8% or less. In other words, the occupancy rate of the region of the crystal orientation <001> is smaller than the occupancy rate of the region of the crystal orientation <101> and the occupancy rate of the region of the crystal orientation <111>. The occupancy rate of the region of the crystal orientation <101> is at least twice that of the region of the crystal orientation <001>. Furthermore, the occupancy rate of the region of the crystal orientation <111> is at least 1.5 times that of the region of the crystal orientation <001>. Note that the occupancy rate of the region of the crystal orientation <101> is preferably larger than that of the crystal orientation <111>. The effective mass of electrons in the conduction bands of the crystal orientations <101> and <111> is smaller than that of the conduction band of the crystal orientation <001>, resulting in higher electron mobility. Therefore, by using an oxide semiconductor film in which the occupancy rate of the region with the crystal orientation <101> and the occupancy rate of the region with the crystal orientation <111> are larger than the occupancy rate of the region with the crystal orientation <001> as a channel, the field-effect mobility of the thin film transistor can be improved.

[0040] Here, the crystal orientation <001> represents

[001] and its equivalents

[100] and

[010] . The crystal orientation <101> represents

[101] and its equivalents

[110] and

[011] . The crystal orientation <111> represents

[111] . Furthermore, in each orientation, "1" may be "-1" and is considered to be an axis equivalent to each orientation.

[0041] In addition to <001>, <101>, and <111>, other crystal orientations include <hk0> (h≠k, h and k are natural numbers), <hhl> (h≠l, h and l are natural numbers), and <hkl> (h≠k≠l, h, k, and l are natural numbers).

[0042] [2-3. Crystal Grains] A crystal grain is a crystalline region surrounded by a crystal grain boundary. Since EBSD provides information about the crystal orientation, a crystal grain boundary can be defined based on the crystal orientation. Generally, when the difference in crystal orientation between two adjacent measurement points exceeds 5°, it is defined that a crystal grain boundary exists between the two measurement points. Therefore, the above definition also applies to Poly-OS films.

[0043] [2-4. Grain size] The grain size is a value indicating the size of a grain. Since the EBSD method can calculate the area S of a grain, the diameter of a circle corresponding to the area S is defined as the grain size d.

[0044] [2-5. Average Crystal Grain Size] The average crystal grain size is the average value of the crystal grain sizes of a plurality of crystal grains. Since a Poly-OS film contains a plurality of crystal grains, the Poly-OS film can be evaluated using the average crystal grain size. Average crystal grain size d ＡＶＥ is calculated by the formula (5). ｊ is the area ratio of the jth grain (the ratio of the area of ​​the grain to the area of ​​the entire EBSD measurement area (measurement area)), and d ｊ is the grain size of the jth grain, and N is the number of grains. As shown in equation (5), the average grain size d ＡＶＥ is the area average within the measurement area weighted by the area of ​​the grains. ＡＶＥ When the crystal grain size is large, it can be said that many crystal grains with large grain sizes are present in the oxide semiconductor film.

[0045]

[0046] The average crystal grain size of the plurality of crystal grains included in the Poly-OS film is, for example, 0.1 μm or more, preferably 0.3 μm or more, and further preferably 0.5 μm or more.

[0047] [2-6. KAM Value] The KAM (Kernel Average Misorientation) value is the average value of the crystal orientation misorientation between one measurement point within a crystal grain and all measurement points adjacent to that measurement point. The KAM value is calculated based on two adjacent measurement points within a crystal grain. Therefore, the crystal orientation misorientation between two adjacent measurement points across a grain boundary is excluded from the calculation of the KAM value.

[0048] The KAM value is a value that represents the change in crystal orientation within a crystal grain. As mentioned above, if the difference in crystal orientation between one measurement point and another measurement point adjacent to that measurement point exceeds 5°, it is considered to be a grain boundary. Therefore, the range of the KAM value calculated based on adjacent measurement points within a crystal grain is 0° or more and 5° or less. A large KAM value means that the local change in crystal orientation within the crystal grain is large, and the crystal grain has a large strain.

[0049] The KAM value is calculated at each of the multiple measurement points. Therefore, a distribution map of the KAM values ​​within the crystal grains can be created. Furthermore, the average KAM value can be calculated based on the distribution map of the KAM values. The average KAM value represents one of the properties of the crystal grains contained in the Poly-OS film. The Poly-OS film has a large change in crystal orientation and contains many crystals with large strain, so the average KAM value is larger than that of a conventional oxide semiconductor film having a polycrystalline structure. The average KAM value of the Poly-OS film is 1.0° or more, preferably 2.0° or more, and more preferably 3.0° or more. A large KAM value in the Poly-OS film means a large deviation in crystal orientation within the crystal grains, which results in a small crystal orientation difference at the crystal grain boundaries. This results in high lattice matching and few defects at the crystal grain boundaries, which suppresses grain boundary scattering and improves bulk mobility. Therefore, in a thin film transistor including a Poly-OS film as a channel, grain boundary scattering is suppressed and field-effect mobility is improved.

[0050] [2-7. Grain Boundary Orientation Change] The grain boundary orientation change is the difference in crystal orientation between two adjacent measurement points across a grain boundary. In other words, the grain boundary orientation change corresponds to the crystal orientation difference excluded from the calculation of the KAM value.

[0051] The grain boundary orientation change is a value that represents the change in crystal orientation at the grain boundary. As mentioned above, at the grain boundary, the crystal orientation difference exceeds 5°, so the grain boundary orientation change is in the range of more than 5°. A large grain boundary orientation change means that the change in crystal orientation between two adjacent crystal grains at the grain boundary is large, and the degree of coincidence of the crystal orientations of the two adjacent crystal grains at the grain boundary is low. In other words, a large grain boundary orientation change means that the lattice coherence is low and there is a grain boundary with many defects. Conversely, a small grain boundary orientation change means that the lattice coherence at the grain boundary is high and there is a grain boundary with few defects. Here, lattice coherence is defined as the degree of coincidence of the lattice constant and crystal orientation between two crystal grains.

[0052] The average value of the grain boundary orientation change can be calculated based on the distribution map of the grain boundary orientation change. The average value of the grain boundary orientation change represents one of the properties of the crystal grains contained in the Poly-OS film. A small average value of the grain boundary orientation change means that the Poly-OS film has high lattice matching and contains many grain boundaries with few defects. In the Poly-OS film, the average value of the grain boundary orientation change is 50° or less, preferably 40° or less, and more preferably 30° or less.

[0053] As described above, the oxide semiconductor film according to one embodiment of the present invention, i.e., the Poly-OS film, has a novel crystal structure. The Poly-OS film has high lattice matching and few defects at the grain boundaries, which suppresses grain boundary scattering and improves bulk mobility. Therefore, in a thin film transistor including the Poly-OS film as a channel, grain boundary scattering is suppressed and field-effect mobility is improved.

[0054] 3 to 12, a thin film transistor 10 according to one embodiment of the present invention will be described. The thin film transistor 10 can be used in, for example, a display device, an integrated circuit (IC) such as a microprocessor (MPU), or a memory circuit.

[0055] [1. Configuration of Thin Film Transistor 10] The configuration of a thin film transistor 10 according to one embodiment of the present invention will be described with reference to Figures 3 and 4. Figure 3 is a schematic cross-sectional view showing the configuration of a thin film transistor 10 according to one embodiment of the present invention. Figure 4 is a schematic plan view showing the configuration of a thin film transistor according to one embodiment of the present invention. Specifically, Figure 3 is a cross-sectional view taken along line AA' in Figure 4.

[0056] As shown in FIG. 3 , the thin film transistor 10 includes a substrate 100, a light-shielding layer 105, a first insulating layer 110, a second insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a fourth insulating layer 180, a source electrode 201, and a drain electrode 203. The light-shielding layer 105 is provided on the substrate 100. The first insulating layer 110 covers the upper surface and end surfaces of the light-shielding layer 105 and is provided on the substrate 100. The second insulating layer 120 is provided on the first insulating layer 110. The oxide semiconductor layer 140 is provided on the second insulating layer 120. The oxide semiconductor layer 140 is in contact with the second insulating layer 120. The gate insulating layer 150 covers the upper surface and end surfaces of the oxide semiconductor layer 140 and is provided on the second insulating layer 120. The gate electrode 160 overlaps the oxide semiconductor layer 140 and is provided on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end surfaces of the gate electrode 160 and is provided on the gate insulating layer 150. The fourth insulating layer 180 is provided on the third insulating layer 170. The gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 have openings 171 and 173 through which part of the upper surface of the oxide semiconductor layer 140 is exposed. The source electrode 201 is provided on the fourth insulating layer 180 and in the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the fourth insulating layer 180 and in the opening 173, and is in contact with the oxide semiconductor layer 140. Note that hereinafter, when the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrodes 200.

[0057] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH with respect to the gate electrode 160. That is, the oxide semiconductor layer 140 includes the channel region CH overlapping with the gate electrode 160, as well as the source region S and the drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has semiconductor properties. The source region S and the drain region D each have conductor properties. Therefore, the electrical conductivities of the source region S and the drain region D are greater than that of the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may have a single-layer structure or a stacked-layer structure.

[0058] 4 , each of the light-shielding layer 105 and the gate electrode 160 has a constant width in the D1 direction and extends in the D2 direction perpendicular to the D1 direction. In the D1 direction, the width of the light-shielding layer 105 is larger than the width of the gate electrode 160. The channel region CH completely overlaps with the light-shielding layer 105. In the thin-film transistor 10, the D1 direction corresponds to the direction in which current flows from the source electrode 201 to the drain electrode 203 through the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0059] The substrate 100 can support each layer constituting the thin film transistor 10. The substrate 100 can be, for example, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate. Alternatively, a rigid substrate having no light-transmitting properties, such as a silicon substrate, can also be used. Alternatively, a flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, can also be used. Impurities may be introduced into the resin substrate in order to improve the heat resistance of the substrate 100. A substrate in which a silicon oxide film or a silicon nitride film is formed on the rigid or flexible substrate described above can also be used as the substrate 100.

[0060] The light-shielding layer 105 can reflect or absorb external light. As described above, the light-shielding layer 105 has an area larger than the channel region CH of the oxide semiconductor layer 140, and therefore can block external light from entering the channel region CH. The light-shielding layer 105 can be made of, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy or compound thereof. Furthermore, if electrical conductivity is not required, the light-shielding layer 105 does not necessarily need to contain a metal. For example, a black matrix made of a black resin can also be used as the light-shielding layer 105. The light-shielding layer 105 may have a single-layer structure or a multilayer structure. For example, the light-shielding layer 105 may have a multilayer structure of red, green, and blue color filters.

[0061] The first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can prevent impurities from diffusing into the oxide semiconductor layer 140. Specifically, the first insulating layer 110 and the second insulating layer 120 can prevent the diffusion of impurities contained in the substrate 100, and the third insulating layer 170 and the fourth insulating layer 180 can prevent the diffusion of impurities (e.g., water) entering from the outside. Each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can be made of, for example, silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), silicon nitride (SiN ｘ ), silicon oxynitride (SiN ｘ O ｙ ), aluminum oxide (AlO ｘ ), aluminum oxynitride (AlO ｘ N ｙ ), aluminum oxide nitride (AlN ｘ O ｙ ), aluminum nitride (AlN ｘ ) is used. Here, silicon oxynitride (SiO ｘ N ｙ ) and aluminum oxynitride (AlO ｘ N ｙ ) are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than oxygen (O) (x>y), respectively. Silicon oxynitride (SiN ｘ O ｙ ) and aluminum oxide nitride (AlN ｘ O ｙ ) is a silicon compound and an aluminum compound containing a smaller ratio of oxygen than nitrogen (x>y). Furthermore, the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may each have a single-layer structure or a multilayer structure.

[0062] The second insulating layer 120 is made of silicon oxide (SiO ｘ ) and silicon oxynitride (SiO ｘ N ｙThat is, when the second insulating layer 120 has a single layer structure, the second insulating layer 120 is preferably an insulating layer containing oxygen such as silicon oxide (SiO ｘ ) or silicon oxynitride (SiO ｘ N ｙ When the second insulating layer 120 has a stacked structure, a layer in contact with the oxide semiconductor layer 140 included in the second insulating layer 120 is made of silicon oxide (SiO ｘ ) or silicon oxynitride (SiO ｘ N ｙ ) is used.

[0063] Each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may have a planarizing function or a function of releasing oxygen by heat treatment. For example, if the second insulating layer 120 has a function of releasing oxygen by heat treatment, oxygen is released from the second insulating layer 120 by the heat treatment performed in the manufacturing process of the thin film transistor 10, and the released oxygen can be supplied to the oxide semiconductor layer 140.

[0064] For the sake of convenience, silicon oxide (SiO ｘ ) and silicon oxynitride (SiO ｘ N ｙ ) may be referred to simply as "silicon oxide." ｘ ) and silicon oxynitride (SiN ｘ O ｙ ) may be referred to simply as "silicon nitride."

[0065] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof, may be used for each of the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a multilayer structure.

[0066] The gate insulating layer 150 includes an oxide having insulating properties. Specifically, the gate insulating layer 150 includes silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), aluminum oxide (AlO ｘ ), or aluminum oxynitride (AlO ｘ N ｙ ) is used. The gate insulating layer 150 preferably has a composition close to the stoichiometric ratio. The gate insulating layer 150 also preferably has few defects. For example, the gate insulating layer 150 may be made of an oxide in which no defects are observed when evaluated by electron spin resonance (ESR).

[0067] The oxide semiconductor film having a polycrystalline structure (Poly-OS film) described in the first embodiment can be used as the oxide semiconductor layer 140. For example, the thickness of the oxide semiconductor layer 140 is 5 nm to 50 nm, preferably 10 nm to 40 nm, and further preferably 10 nm to 30 nm.

[0068] The configuration of the thin-film transistor 10 has been described above. The thin-film transistor 10 described above is a so-called top-gate transistor. Various modifications of the thin-film transistor 10 are possible. For example, if the light-shielding layer 105 is conductive, the thin-film transistor 10 may be configured such that the light-shielding layer 105 functions as a gate electrode, and the first insulating layer 110 and the second insulating layer 120 function as gate insulating layers. In this case, the thin-film transistor 10 is a so-called dual-gate transistor. Furthermore, if the light-shielding layer 105 is conductive, the light-shielding layer 105 may be a floating electrode or may be connected to the source electrode 201. Furthermore, the thin-film transistor 10 may be a so-called bottom-gate transistor in which the light-shielding layer 105 functions as a main gate electrode.

[0069] 5 to 12, a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention will be described. Fig. 5 is a flowchart showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention. Figs. 6 to 12 are schematic cross-sectional views showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention.

[0070] 5, the method for manufacturing the thin-film transistor 10 includes steps S1010 to S1110. Steps S1010 to S1110 will be described in order below, but the order of the steps may be reversed in the method for manufacturing the thin-film transistor 10. Furthermore, the method for manufacturing the thin-film transistor 10 may include additional steps.

[0071] In step S1010, a light-shielding layer 105 having a predetermined pattern is formed on the substrate 100. The light-shielding layer 105 is patterned using photolithography. A first insulating layer 110 and a second insulating layer 120 are formed on the light-shielding layer 105 (see FIG. 6 ). The first insulating layer 110 and the second insulating layer 120 are formed using CVD. For example, silicon nitride and silicon oxide are formed as the first insulating layer 110 and the second insulating layer 120, respectively. When silicon nitride is used as the first insulating layer 110, the first insulating layer 110 can block impurities diffusing from the substrate 100 side into the oxide semiconductor layer 140. When silicon oxide is used as the second insulating layer 120, the second insulating layer 120 can release oxygen by heat treatment.

[0072] In step S1020, an oxide semiconductor film 145 is formed over the second insulating layer 120 (see FIG. 7 ). The oxide semiconductor film 145 is formed by a sputtering method. The thickness of the oxide semiconductor film 145 is, for example, 5 nm to 50 nm, preferably 10 nm to 40 nm, and more preferably 10 nm to 30 nm.

[0073] The oxide semiconductor film 145 in step S1020 is amorphous. In the Poly-OS technology, in order for the oxide semiconductor layer 140 to have a uniform polycrystalline structure in the substrate plane, the oxide semiconductor film 145 is preferably amorphous after deposition and before heat treatment. Therefore, the deposition conditions for the oxide semiconductor film 145 are preferably such that the oxide semiconductor layer 140 immediately after deposition is as little crystallized as possible. When the oxide semiconductor film 145 is deposited by a sputtering method, the oxide semiconductor film 145 is deposited while controlling the temperature of the deposition target (the substrate 100 and the layer formed on the substrate 100) to 100° C. or lower, preferably 80° C. or lower, and more preferably 50° C. or lower. The oxide semiconductor film 145 is deposited under a low oxygen partial pressure condition. The oxygen partial pressure is 1% to 20%, preferably 3% to 15%, and more preferably 3% to less than 10%.

[0074] In step S1030, the oxide semiconductor film 145 is patterned (see FIG. 8 ). The oxide semiconductor film 145 is patterned by photolithography. The oxide semiconductor film 145 may be etched by wet etching or dry etching. In the wet etching, an acidic etchant may be used. Examples of the etchant that may be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide, and hydrofluoric acid.

[0075] In step S1040, the oxide semiconductor film 145 is subjected to heat treatment. Hereinafter, the heat treatment performed in step S1040 is referred to as "OS annealing." In the OS annealing, the oxide semiconductor film 145 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 250° C. or higher and 500° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 350° C. or higher and 450° C. or lower. The holding time at the temperature is 15 minutes or higher and 120 minutes or lower, preferably 30 minutes or higher and 60 minutes or lower. The OS annealing crystallizes the oxide semiconductor film 145, and the oxide semiconductor layer 140 having a polycrystalline structure (i.e., the oxide semiconductor layer 140 including a Poly-OS film) is formed.

[0076] In step S1050, a gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see FIG. 9 ). The gate insulating layer 150 is formed using a CVD method. For example, silicon oxide is formed as the gate insulating layer 150. In order to reduce defects in the gate insulating layer 150, the gate insulating layer 150 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm. After the gate insulating layer 150 is formed, a process of introducing oxygen into a part of the gate insulating layer 150 may be performed.

[0077] In step S1060, a heat treatment is performed on the oxide semiconductor layer 140. Hereinafter, the heat treatment performed in step S1060 is referred to as "oxidation annealing." When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen defects are generated on the top surface and side surfaces of the oxide semiconductor layer 140. When the oxidation annealing is performed, oxygen is supplied from the second insulating layer 120 and the gate insulating layer 150 to the oxide semiconductor layer 140, and the oxygen defects are repaired.

[0078] In step S1070, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see FIG. 10). The gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned using photolithography.

[0079] In step S1080, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see FIG. 10 ). The source region S and the drain region D are formed by ion implantation. Specifically, impurities are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150 using the gate electrode 160 as a mask. Examples of the implanted impurities include argon (Ar), phosphorus (P), and boron (B). In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen vacancies are generated by the ion implantation, and hydrogen is trapped in the generated oxygen vacancies. This reduces the resistance of the source region S and the drain region D. On the other hand, in the channel region that overlaps with the gate electrode 160, impurities are not implanted, so no oxygen vacancies are generated and the resistance of the channel region CH does not decrease.

[0080] In the thin-film transistor 10, impurities are injected into the oxide semiconductor layer 140 through the gate insulating layer 150, and therefore the gate insulating layer 150 may also contain impurities such as argon (Ar), phosphorus (P), or boron (B).

[0081] In step S1090, a third insulating layer 170 and a fourth insulating layer 180 are formed on the gate insulating layer 150 and the gate electrode 160 (see FIG. 11 ). The third insulating layer 170 and the fourth insulating layer 180 are formed using a CVD method. For example, silicon oxide and silicon nitride are formed as the third insulating layer 170 and the fourth insulating layer 180, respectively. The thickness of the third insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the fourth insulating layer 180 is also 50 nm or more and 500 nm or less.

[0082] In step S1100, openings 171 and 173 are formed in the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 (see FIG. 12 ). By forming the openings 171 and 173, the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0083] In step S1110, a source electrode 201 is formed on the fourth insulating layer 180 and inside the opening 171, and a drain electrode 203 is formed on the fourth insulating layer 180 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning a single conductive film that has been deposited. Through the above steps, the thin film transistor 10 shown in FIG. 2 is manufactured.

[0084] Although the method for manufacturing the thin film transistor 10 has been described above, the method for manufacturing the thin film transistor 10 is not limited to this.

[0085] In the thin film transistor 10 according to this embodiment, the oxide semiconductor layer 140 includes a Poly-OS film having a novel crystal structure. The Poly-OS film has high lattice matching and contains many crystal grain boundaries with few defects, which suppresses grain boundary scattering. As a result, the field-effect mobility of the thin film transistor 10 is improved.

[0086] Third Embodiment An electronic device according to a third embodiment of the present invention will be described with reference to FIG.

[0087] FIG. 13 is a schematic diagram showing an electronic device 1000 according to an embodiment of the present invention. Specifically, FIG. 13 shows a smartphone as an example of the electronic device 1000. The electronic device 1000 includes a display device 1100 having curved sides. The display device 1100 includes a plurality of pixels for displaying an image. The plurality of pixels are controlled by a pixel circuit, a drive circuit, and the like. The pixel circuit and the drive circuit include the thin-film transistor 10 described in the second embodiment. The thin-film transistor 10 has high field-effect mobility, which improves the responsiveness of the pixel circuit and the drive circuit, thereby improving the performance of the electronic device 1000.

[0088] The electronic device 1000 according to this embodiment is not limited to a smartphone. The electronic device 1000 also includes electronic devices having a display device, such as a watch, a tablet, a laptop computer, a car navigation system, or a television. The thin-film transistor 10 described in the second embodiment can be applied to any electronic device, regardless of whether or not it has a display device.

[0089] The Poly-OS film will be described in more detail based on the fabricated example samples.

[0090] [1. Crystal Orientation Analysis] [1-1. Fabrication of Example Samples] As example samples, oxide semiconductor films (Poly-OS films) were fabricated on glass substrates using the sputtering process and OS annealing process described in the second embodiment. In the sputtering process, a sputtering target was used, which contained indium (In) and gallium (Ga) as the first metal element (M1) in a sintered body, with the indium content being 70% of all metal elements in the sintered body. Note that the first metal element (M1) contained in the example sintered body is not limited to gallium (Ga); aluminum (Al), yttrium (Y), scandium (Sc), and lanthanoid elements also exhibit similar effects. In the OS annealing process, the ultimate temperature was controlled to 450°C in an air atmosphere and maintained at that temperature for 60 minutes. In all example samples, the chemical composition of the oxide semiconductor film after the OS annealing process was similar to that of the sputtering target.

[0091] Example Samples 1-1 to 1-4 were prepared under different preparation conditions. The preparation conditions for each example sample are shown in Table 1.

[0092]

[0093] [1-2. Crystal structure analysis by XRD method] The crystal structure of the oxide semiconductor film of each example sample was analyzed by XRD method. All oxide semiconductor films were crystalline and had a bixbyite-type crystal structure.

[0094] [1-3. Crystal Orientation Analysis by EBSD Method] The crystal orientation of the oxide semiconductor film of each sample was analyzed by EBSD method. The measurement conditions for EBSD method are shown in Table 2. The crystal orientation analysis was performed using OIM-Analysis (ver. 7.1) manufactured by TSL Solutions, Inc. Crystal structure file 14388 of the bixbyite-type structure in the Inorganic Crystal Structure Database (ICSD: Chemical Information Association) was used for orientation of the crystal structure. As a result of the measurement and analysis, when the CI value was 0.6 or more, the obtained pattern was sufficiently clear, and it was determined that the crystal orientation was identified as a bixbyite-type structure.

[0095]

[0096] IPF maps in the normal direction (ND) relative to the film surface of the oxide semiconductor film of Example Sample 1-1 are shown in FIGS. 14 and 15 . IPF maps in the ND direction of Example Sample 1-2 are shown in FIGS. 16 and 17 . IPF maps in the ND direction of Example Sample 1-3 are shown in FIGS. 18 and 19 . IPF maps in the ND direction of Example Sample 1-4 are shown in FIGS. 20 and 21 . In FIGS. 14 to 21 , the crystal orientation at each measurement point in the ND direction is classified by an index. Specifically, the crystal orientation at each measurement point in the ND direction is classified based on the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111>. In each IPF map, a crystal grain boundary is considered to exist when the difference in crystal orientation between two adjacent measurement points exceeds 5°, and the crystal grain boundary is indicated by a black line. 15, 17, 19, and 21, regions in which the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111> are oriented within 15° with respect to ND are extracted and classified. In other words, Figures 15, 17, 19, and 21 are IPF maps in which regions in Figures 14, 16, 18, and 20, respectively, in which the crystal orientation difference between the crystal orientation <001>, the crystal orientation <101>, or the crystal orientation <111> with respect to ND exceeds 15° are excluded.

[0097] As shown in FIGS. 14 to 20 , the oxide semiconductor films of Example Sample 1-1 to Example Sample 1-4 all include multiple crystal grains separated by grain boundaries. The average crystal grain sizes of the oxide semiconductor films of Example Sample 1-1 to Example Sample 1-4 were 2.7 μm, 1.5 μm, 1.1 μm, and 1.2 μm, respectively, which were larger than the thicknesses of the oxide semiconductor films. In FIGS. 14 , 16 , 18 , and 20 , multiple crystal orientations can be seen within the crystal grains. Therefore, the oxide semiconductor films of Example Sample 1-1 to Example Sample 1-4 are all Poly-OS films in which the crystal orientation changes within the crystal grains. Furthermore, in the oxide semiconductor films of Example Sample 1-1 to Example Sample 1-4, regions separated into the <001> crystal orientation, the <101> crystal orientation, and the <111> crystal orientation can be seen within one crystal grain. That is, at least one crystal grain in each of the oxide semiconductor films of Example Sample 1-1 to Example Sample 1-4 includes a region with a crystal orientation <001>, a region with a crystal orientation <101>, and a region with a crystal orientation <111>, and the crystal orientation changes significantly within the crystal grain.

[0098] Based on the IPF maps shown in Figures 15, 17, 19, and 21, the occupancy rates of the region with the crystal orientation <101>, the region with the crystal orientation <101>, and the region with the crystal orientation <111> were calculated (the measured region is set to 100%). The occupancy rates for Example Samples 1-1 to 1-4 are shown in Table 3.

[0099]

[0100] In all of Example Sample 1-1 to Example Sample 1-4, the occupancy rate of the region with the crystal orientation <101> was 20% or more. In Example Sample 1-1 to Example Sample 1-3, which had the same oxide semiconductor film thickness, the occupancy rate of the region with the crystal orientation <101> increased as the oxygen partial pressure during film formation of the oxide semiconductor film decreased. In addition, in all of Example Sample 1-1 to Example Sample 1-4, the occupancy rate of the region with the crystal orientation <111> was 15% or more. In Example Sample 1-1 to Example Sample 1-3, which had the same oxide semiconductor film thickness, the occupancy rate of the region with the crystal orientation <111> increased as the oxygen partial pressure during film formation of the oxide semiconductor film decreased. On the other hand, in all of Example Sample 1-1 to Example Sample 1-4, the occupancy rate of the region with the crystal orientation <001> was less than 10%. In Example Samples 1-1 to 1-3, in which the oxide semiconductor films had the same thickness, the occupancy rate of the regions with the <001> crystal orientation decreased as the oxygen partial pressure in the deposition of the oxide semiconductor films decreased.

[0101] In other words, the occupancy rate of the region with the crystal orientation <001> is smaller than the occupancy rate of the region with the crystal orientation <101> and the occupancy rate of the region with the crystal orientation <111>. The occupancy rate of the region with the crystal orientation <101> is at least twice the occupancy rate of the region with the crystal orientation <001>. Furthermore, the occupancy rate of the region with the crystal orientation <111> is at least 1.5 times the occupancy rate of the region with the crystal orientation <001>. In Example Samples 1-1 to 1-3 in which the thickness of the oxide semiconductor film is less than 30 nm, the occupancy rate of the region with the crystal orientation <101> is larger than the occupancy rate of the region with the crystal orientation <111>.

[0102] The total occupancy of the regions with the <101> crystal orientation and the <111> crystal orientation is 40% or more. In this way, in the Poly-OS film, the <101> crystal orientation and the <111> crystal orientation are preferentially oriented in the film thickness direction.

[0103] Next, an analysis based on the crystal orientation difference between two adjacent measurement points will be described. Note that, hereinafter, the crystal orientation difference between two measurement points may be simply referred to as "orientation difference."

[0104] Graphs relating to the distribution of crystal orientation misorientation of the oxide semiconductor films of Example Samples 1-1 to 1-4 are shown in FIGS. 22A to 25C. FIGS. 22A, 23A, 24A, and 25A show graphs representing distribution maps of all adjacent point orientation changes in Example Samples 1-1 to 1-4, respectively. FIGS. 22B, 23B, 24B, and 25B show graphs representing distribution maps of KAM values ​​in Example Samples 1-1 to 1-4, respectively. FIGS. 22C, 23C, 24C, and 25C show graphs representing distribution maps of grain boundary orientation changes in Example Samples 1-1 to 1-4, respectively. The distribution maps of all adjacent point orientation changes show all crystal orientation misorientation between two adjacent measurement points.

[0105] 22C , 23C , 24C , and 25C , peaks can be seen in the distribution diagrams of the change in grain boundary orientation at misorientation angles of approximately 10° and 45°. When the thickness of the oxide semiconductor film is reduced or the oxygen partial pressure during deposition of the oxide semiconductor film is reduced, the peak at approximately 10° becomes larger than the peak at approximately 45°.

[0106] 22B, 23B, and 24B, the distribution of KAM values ​​clearly shows KAM values ​​of 3° or more. Also, according to Fig. 22B, 23B, and 24B, KAM values ​​are also present around 5°. On the other hand, in the distribution of KAM values ​​in Fig. 25B, KAM values ​​of 3° or more are hardly observed.

[0107] Here, the ratio of the average value of the grain boundary orientation change to the average value of the KAM value is defined as the grain boundary parameter P ＧＢ The grain boundary parameter P ＧＢ ) = (average value of grain boundary orientation change) / (average value of KAM value)) Grain boundary parameter P ＧＢ is a parameter that represents the ratio of the amount of change in crystal orientation at the grain boundary to the amount of change in crystal orientation within the grain. ＧＢWhen the grain boundary parameter P is large, it means that the local change in crystal orientation within the grain is small and the difference in crystal orientation between two adjacent measurement points across the grain boundary is large. ＧＢ The smaller the grain boundary parameter P is and the closer it is to 1, the greater the change in local crystal orientation within the grain, and the higher the lattice matching between two measurement points adjacent to each other across the grain boundary. ＧＢ As the value of σ approaches 1, the oxide semiconductor film has higher lattice matching and contains more crystal grain boundaries with fewer defects.

[0108] The average KAM value, the average grain boundary orientation change, and the grain boundary parameter P ＧＢ is shown in Table 4.

[0109]

[0110] As shown in Table 4, the average value of the KAM value was 1.0° or more in the oxide semiconductor films of Example Sample 1-1 to Example Sample 1-4. In particular, the average value of the KAM value was 3.0° or more in the oxide semiconductor films of Example Sample 1-1 to Example Sample 1-3, in which the thickness of the oxide semiconductor film was less than 30 nm. Furthermore, the average value of the grain boundary orientation change was 50° or less in the oxide semiconductor films of Example Sample 1-1 to Example Sample 1-4. Furthermore, the grain boundary parameter P ＧＢ In particular, in Example Samples 1-1 to 1-3 in which the thickness of the oxide semiconductor film was less than 30 nm, the grain boundary parameter P ＧＢ As mentioned above, the grain boundary parameter P ＧＢ As ρ becomes smaller and approaches 1, the oxide semiconductor film has more grain boundaries with higher lattice matching and fewer defects. In the Poly-OS film, the crystal orientations in two adjacent crystal grains change so that the lattice matching at the grain boundaries is higher, resulting in higher lattice matching at the grain boundaries and fewer defects.

[0111] [2. Electrical Characteristics] Thin film transistors including oxide semiconductor films of Example Samples 1-1 to 1-4 were fabricated using the manufacturing method described in the second embodiment, and their electrical characteristics were measured. Table 5 shows the field-effect mobility (field-effect mobility in the saturation region) calculated from the electrical characteristics.

[0112]

[0113] As shown in Table 5, in all of the thin film transistors of Example Sample 1-1 to Example 1-4, ２ In particular, in Example Samples 1-1 to 1-3 in which the thickness of the oxide semiconductor film was less than 30 nm, a field-effect mobility of 40 cm ２ As can be seen from this result, when a Poly-OS film is used for a channel of a thin film transistor, the field-effect mobility is improved.

[0114] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0115] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0116] 10: Thin film transistor, 100: Substrate, 105: Light-shielding layer, 110: First insulating layer, 120: Second insulating layer, 140: Oxide semiconductor layer, 145: Oxide semiconductor film, 150: Gate insulating layer, 160: Gate electrode, 170: Third insulating layer, 171: Opening, 173: Opening, 180: Fourth insulating layer, 200: Source / drain electrode, 201: Source electrode, 203: Drain electrode, 500: Oxide semiconductor film, 600: EBSD detector, 1000: Electronic device, 1100: Display device

Claims

1. A crystalline oxide semiconductor film, comprising: indium (In); and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and a lanthanoid element; the oxide semiconductor film comprises a plurality of crystal grains each having at least one of a crystal orientation <101>, a crystal orientation <111>, and a crystal orientation <001>, as measured by an electron backscatter diffraction method; and an occupancy rate of a first region in which the crystal orientation <101> is oriented within 15° with respect to a normal direction to a surface of the oxide semiconductor film is 20% or more.

2. The oxide semiconductor film according to claim 1, wherein an average KAM value calculated by the electron backscatter diffraction method is 1.0° or more.

3. The oxide semiconductor film according to claim 1, wherein the occupancy rate of a second region in which the crystal orientation <111> is oriented within 15° with respect to the normal direction of the surface of the oxide semiconductor film is 15% or more.

4. The oxide semiconductor film according to claim 3, wherein a total occupancy rate of the first region and the second region is 40% or more.

5. The oxide semiconductor film according to claim 1, wherein the occupancy rate of a third region in which the crystal orientation <001> is oriented within 25° relative to the normal direction of the surface of the oxide semiconductor film is less than 10%.

6. The oxide semiconductor film according to claim 1, wherein the oxide semiconductor film contains at least one or more metal elements including the first metal element excluding the indium, the first metal element being the gallium, and a second metal element (M2) contained in the at least one or more metal elements being one metal element selected from the group consisting of the aluminum, the yttrium, the scandium, and the lanthanoid elements, and an atomic ratio of the indium, the gallium, and the second metal element satisfies formulas (1), (2), and (3).

7. The oxide semiconductor film according to claim 1, wherein the crystal structure of the oxide semiconductor film is a bixbyite structure.

8. An oxide semiconductor film having crystallinity, the oxide semiconductor film comprising indium (In) and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and a lanthanoid element, the oxide semiconductor film comprising a plurality of crystal grains each having at least one of a crystal orientation <101>, a crystal orientation <111>, and a crystal orientation <001> measured by an electron backscatter diffraction method, the oxide semiconductor film comprising: a first region in which the crystal orientation <101> is oriented within 15° with respect to a normal direction to a surface of the oxide semiconductor film; a second region in which the crystal orientation <111> is oriented within 15° with respect to the normal direction to the surface of the oxide semiconductor film; and a third region in which the crystal orientation <001> is oriented within 15° with respect to the normal direction to the surface of the oxide semiconductor film, an occupancy rate of the third region is smaller than an occupancy rate of the first region and an occupancy rate of the second region; 9. The oxide semiconductor film according to claim 8, wherein an average value of the KAM value calculated by the electron backscatter diffraction method is 1.0° or more.

10. The oxide semiconductor film according to claim 8, wherein the occupancy rate of the first region is greater than the occupancy rate of the second region.

11. The oxide semiconductor film according to claim 8, wherein the occupancy rate of the first region is 2.0 times or more that of the third region.

12. The oxide semiconductor film according to claim 8, wherein the occupancy rate of the second region is 1.5 times or more that of the third region.

13. The oxide semiconductor film according to claim 8, wherein an average change in grain boundary orientation calculated by the electron backscatter diffraction method is 50° or less.

14. The oxide semiconductor film according to claim 8, wherein the oxide semiconductor film has a thickness of less than 30 nm.

15. The oxide semiconductor film according to claim 8, wherein the oxide semiconductor film contains at least one or more metal elements including the first metal element excluding the indium, the first metal element being the gallium, and a second metal element (M2) contained in the at least one or more metal elements being one metal element selected from the group consisting of the aluminum, the yttrium, the scandium, and the lanthanoid elements, and an atomic ratio of the indium, the gallium, and the second metal element satisfies formulas (1), (2), and (3).

16. The oxide semiconductor film according to claim 8, wherein the crystal structure of the oxide semiconductor film is a bixbyite structure.

17. A thin film transistor comprising the oxide semiconductor film according to any one of claims 1 to 16 as a channel.

18. An electronic device comprising the thin film transistor according to claim 17.

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