Semiconductor substrate, production method and production apparatus for same, and semiconductor device

Abstract

In this semiconductor substrate, a first semiconductor part is located from above a first seed region to above a growth suppression region, a second semiconductor part is located from above a second seed region to above the growth suppression region, a third semiconductor part is located from above a third seed region to above the growth suppression region, the upper surface of each of the first to third semiconductor parts has a shape having a short axis and a long axis, the first semiconductor part includes a first portion that is located between the second semiconductor part and the third semiconductor part and a second portion that is not located between the second semiconductor part and the third semiconductor part, and the ratio of the length of the second semiconductor part in the long axis direction to the length of the first semiconductor part in the long axis direction is 0.8-1.2.

Description

Semiconductor substrate, manufacturing method and manufacturing apparatus thereof, and semiconductor device

[0001] The present disclosure relates to semiconductor substrates and the like.

[0002] A mask pattern that prevents the growth of a nitride semiconductor layer is formed on a template substrate including a heterogeneous substrate and a seed layer, and the nitride semiconductor layer is grown laterally on the mask portion, starting from the seed layer exposed in the opening where there is no mask portion, thereby reducing the defect density of the nitride semiconductor layer on the mask portion (Patent Document 1).

[0003] Japanese Patent Publication No. 2013-251304

[0004] The semiconductor substrate comprises a template substrate including a first seed region, a second seed region, a third seed region, and a growth inhibition region, and a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion, each including a nitride semiconductor, wherein the first semiconductor portion is located above the first seed region and above the growth inhibition region, the second semiconductor portion is located above the second seed region and above the growth inhibition region, and the third semiconductor portion is located above the third seed region and above the growth inhibition region, the top surfaces of the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion each have a shape having a minor axis and a major axis, the first semiconductor portion includes a first portion located between the second semiconductor portion and the third semiconductor portion, and a second portion not located between the second semiconductor portion and the third semiconductor portion, and the ratio of the length in the major axis direction of the second semiconductor portion to the length in the major axis direction of the first semiconductor portion is 0.8 to 1.2.

[0005] 20 is a plan view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 21 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 22 is a plan view showing a portion of FIG. 1. FIG. 23 is a plan view showing the configuration of first to third semiconductor portions. FIG. 24 is a cross-sectional view showing the configuration of a semiconductor substrate. FIG. 25 is a cross-sectional view showing the configuration of a semiconductor substrate. FIG. 26 is a plan view and a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 27 is a plan view showing a method for manufacturing a semiconductor substrate according to the present embodiment. FIG. 28 is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment. FIG. 29 is a block diagram showing a semiconductor substrate manufacturing apparatus according to the present embodiment. FIG. 30 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment. FIG. 31 is a plan view showing the configuration of a semiconductor device according to the present embodiment. FIG. 32 is a cross-sectional view showing the configuration of a semiconductor device according to the present embodiment. FIG. 33 is a cross-sectional view showing the configuration of a semiconductor device according to the present embodiment. FIG. 34 is a plan view showing the configuration of a semiconductor device according to the present embodiment. FIG. 35 is a cross-sectional view showing the configuration of a semiconductor device according to the present embodiment. FIG. 36 is a plan view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 37 is a cross-sectional view showing the configuration of a semiconductor device according to the present embodiment. FIG. 38 is a plan view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 39 is a plan view showing the configuration of a semiconductor substrate according to the present embodiment. 8A to 8C are plan views illustrating a method for manufacturing the semiconductor substrate shown in FIG. 7.

[0006] FIG. 1 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. FIG. 2 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. FIG. 3 is a plan view showing a portion of FIG. 1. FIG. 4 is a plan view showing the configuration of first to third semiconductor portions. FIG. 5 is a cross-sectional view showing the configuration of the first to third semiconductor portions. As shown in FIGS. 1 to 5, the semiconductor substrate 10 includes a template substrate TS including a first seed region S1, a second seed region S2, a third seed region S3, and a growth inhibition region DA, and a first semiconductor portion H1, a second semiconductor portion H2, and a third semiconductor portion H3 each including a nitride semiconductor.

[0007] The first semiconductor part H1 is located above the first seed region S1 and above the growth inhibition region DA, the second semiconductor part H2 is located above the second seed region S2 and above the growth inhibition region DA, and the third semiconductor part H3 is located above the third seed region S3 and above the growth inhibition region DA.

[0008] The top surface UF of each of the first to third semiconductor parts (H1, H2, H3) has a shape with a minor axis X and a major axis Y, and the first semiconductor part H1 includes a first part B1 located between the second semiconductor part H2 and the third semiconductor part H3, and a second part B2 not located between the second semiconductor part H2 and the third semiconductor part H3.

[0009] The ratio of the length of the second semiconductor portion H2 in the major axis direction (Y direction) to the length of the first semiconductor portion H1 in the major axis direction (Y direction) is 0.8 to 1.2. This ratio (ratio value) may be 0.9 to 1.1 or 0.95 to 1.05. The first semiconductor portion H1 and the second semiconductor portion H2 may be adjacent to each other with a gap GA ( FIG. 3 ) between them, and the first semiconductor portion H1 and the third semiconductor portion H3 may be adjacent to each other with a gap GB ( FIG. 3 ) between them.

[0010] By configuring the first to third semiconductor portions H1 to H3 in this manner, warping of the semiconductor substrate can be reduced. Furthermore, bias in the supply of raw materials (e.g., excessive supply near the tip of the first semiconductor portion H1) is reduced, and abnormal growth of the first semiconductor portion H1 (e.g., growth near the tip of H1 thicker than the surrounding area) can be suppressed. Each of the first and second semiconductor portions H1 and H2 can be used as a base semiconductor portion for forming an upper layer portion (device layer) including an active layer.

[0011] The first to third seed regions S1 to S3 may have the same longitudinal shape and the same longitudinal direction, and the triangle connecting the center of gravity (geometric center of gravity) of the first seed region S1, the center of gravity of the second seed region S2, and the center of gravity of the third seed region S3 may be an isosceles triangle or an equilateral triangle with the side connecting the center of gravity of the second seed region S2 and the center of gravity of the third seed region S3 as its base. In the case of an isosceles triangle, its apex angle may be 40° or more and less than 60°, or 50° or more and less than 60°.

[0012] The first to third semiconductor portions H1 to H3 contain a nitride semiconductor as a main component. The nitride semiconductor can be expressed, for example, as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The nitride semiconductor may be doped (e.g., n-type containing donors) or undoped.

[0013] A semiconductor substrate means a substrate that includes a semiconductor, and the main substrate 1 included in the template substrate TS may or may not include a semiconductor (e.g., silicon or silicon carbide). An example of a main substrate 1 that does not include a semiconductor is a sapphire substrate. The template substrate TS is also sometimes called a growth substrate. In the following, expressions such as "equal," "same or identical," "parallel," and "orthogonal" may be used with an allowance of error of approximately 10%.

[0014] In the first to third semiconductor portions H1 to H3, the a-axis direction of the nitride semiconductor is, for example, the <11-20> direction, and the m-axis direction is, for example, the <1-100> direction. The thickness direction of the first to third semiconductor portions H1 to H3 may be the c-axis direction of the nitride semiconductor (for example, the <0001> direction). In a hexagonal nitride semiconductor, on the c-plane, the three directions of 0° and 180°, 60° and 240°, and 120° and 300° may be the a-axis directions, and the three directions of 30° and 210°, 90° and 270°, and 150° and 330° may be the m-axis directions.

[0015] For example, the first semiconductor portion H1 can be formed by ELO (Epitaxial Lateral Overgrowth) of a nitride semiconductor crystal starting from the first seed portion S1. The top surface UF of each of the first to third semiconductor portions H1 to H3 may include a longitudinal region (longitudinal high dislocation density region) FA overlapping the longitudinal axis Y and including a plurality of threading dislocations, and low dislocation regions LA and LB having a threading dislocation density lower than that of the longitudinal region FA. The threading dislocation density of the low dislocation regions LA and LB may be 1 / 5 or less, 1 / 10 or less, or 1 / 100 or less of the threading dislocation density of the longitudinal region FA. The threading dislocation density of the low dislocation regions LA and LB may be 5×10 ６ / cm ２ It may be the following:

[0016] The long axis directions (Y directions) of the first and second semiconductor portions H1 and H2 may be the same (for example, the same m-axis direction). The top surface UF of each of the first to third semiconductor portions H1 to H3 may include two adjacent sides CA and CB ( FIG. 4 ), and the two sides may be along two a-axis directions of the nitride semiconductor that form an angle of 60°. The top surface UF of each of the first to third semiconductor portions H1 to H3 may be a quadrangle (for example, a rhombus) with two pairs of parallel sides. The first to third semiconductor portions H1 to H3 may have the same shape.

[0017] The width of the gap GA between the first and second semiconductor portions H1 and H2 may be equal to the width of the gap GB between the first and third semiconductor portions H1 and H3. In a plan view, the gap GA between the first and second semiconductor portions H1 and H3 and the gap GB between the first and third semiconductor portions H1 and H3 may form a V-shape. In a plan view, the first portion B1 may form an acute triangle. In a plan view, the first portion B1 and the second portion B2 may be line-symmetric.

[0018] In nitride semiconductor crystals (e.g., GaN-based semiconductor crystals), growth autonomously stops at the location where a plane parallel to the a-axis occurs. Therefore, by using the template substrate TS of FIG. 1 , first to third semiconductor portions H1 to H3 surrounded by planes along the a-axis are autonomously formed (e.g., the upper surface UF of each of H1 to H3 autonomously becomes a diamond shape). That is, in the semiconductor substrate 10, the shape of the semiconductor portion group (including H1 to H3) formed by ELO can be determined by the pattern of the seed group (including S1 to S3) of the template substrate TS. This has the advantage that the ELO-formed nitride semiconductor crystal does not need to be divided into multiple semiconductor portions by etching or the like. The timing of stopping the raw material supply is also easily controlled. Because an etching process (RIE process) for division is not required, side surface degradation (e.g., the formation of a current leakage path on the side of the etched region) can be avoided.

[0019] 1, in the template substrate TS, a group of seeds (including first to third seed portions S1 to S3) having the same longitudinal shape may be arranged in a staggered pattern. In the semiconductor substrate 10, a plurality of semiconductor portions having the same shape, including a first semiconductor portion H1, may be aligned in the a-axis direction of the nitride semiconductor, and a plurality of semiconductor portions having the same shape, including second and third semiconductor portions H2 and H3, may be aligned in the a-axis direction of the nitride semiconductor.

[0020] By autonomously dividing and forming the semiconductor portion group (including H1 to H3), distortion of the semiconductor portion group (including H1 to H3) is reduced both at room temperature and at the growth temperature (for example, 1000°C or higher), and further, stress generated between the semiconductor portion group and the template substrate TS is alleviated, reducing warpage of the semiconductor substrate 10 itself. This facilitates subsequent processes using the semiconductor substrate 10 (such as the process of forming a device layer). In addition, the main substrate (wafer) included in the template substrate TS can be made thinner, thereby reducing costs. Furthermore, the reduced stress in the semiconductor portion group even at the growth temperature makes it easier to incorporate indium (In), facilitating the formation of an active layer for long wavelengths (for example, red light emission).

[0021] The semiconductor substrate 10 may include a fourth semiconductor portion H4 that has the same shape as the first to third semiconductor portions H1 to H3 and is adjacent to at least one of the second and third semiconductor portions H2 and H3. As shown in Figures 4 and 5, the first to third semiconductor portions H1 to H3 may each have a plurality of side surfaces (VA, VB, KA, KB) that are aligned with the a-axis of the nitride semiconductor. The areas of the upper surface UF and the lower surface BT may differ among the first to third semiconductor portions H1 to H3.

[0022] The nitride semiconductors included in the first to third semiconductor portions H1 to H3 may be GaN-based semiconductors. Each of the first to third semiconductor portions H1 to H3 may be a nitride semiconductor crystal (for example, a GaN-based semiconductor crystal).

[0023] 6 and 7 are cross-sectional views showing the configuration of a semiconductor substrate. As shown in FIGS. 6 and 7 , the template substrate TS may include a main substrate 1 (heterogeneous wafer) having a lattice constant different from that of a GaN-based semiconductor and a seed layer 4 located above the main substrate 1. Here, the first semiconductor portion H1 and the growth inhibition region DA may be in contact with each other, or, as shown in FIG. 7 , a gap JD may be located between the first semiconductor portion H1 and the growth inhibition region DA. As shown in FIG. 6 , the growth inhibition region DA may be a mask portion 5 (the first seed region S1 is exposed in an opening K1 where there is no mask portion), or as shown in FIG. 7 , the growth inhibition region DA may be a modified region obtained by modifying the seed layer 4 (e.g., an aluminum nitride layer).

[0024] 8 is a plan view and a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in FIG. 8, the semiconductor substrate 10 may have an upper layer portion UL including an active layer above each of the first to third semiconductor portions H1 to H3. In this case, each of the first to third semiconductor portions H1 to H3 serves as a base semiconductor portion when forming the upper layer portion UL. The upper layer portion UL may include at least one of an insulating layer and an electrode in addition to a nitride semiconductor layer including an active layer.

[0025] 9A and 9B are plan views showing the method for manufacturing a semiconductor substrate according to this embodiment, and FIG. 10 is a flowchart showing the method for manufacturing a semiconductor substrate according to this embodiment. 3 and 9 and 10 , the method for manufacturing the semiconductor substrate includes: a step S10 of preparing a template substrate TS including first to third seed regions S1 to S3 and a growth inhibition region DA; a step S20 of growing first to third semiconductor portions H1 to H3 corresponding to the first to third seed regions S1 to S3 by supplying nitride semiconductor raw materials to the template substrate TS; and a step S30 of stopping the supply of raw materials after the top surfaces of the first to third semiconductor portions H1 to H3, which are independent of one another, have a shape having a minor axis X and a major axis Y, and the first semiconductor portion H1 has a shape including a first portion B1 located between the second semiconductor portion H2 and the third semiconductor portion H3 and a second portion B2 not located between the second semiconductor portion H2 and the third semiconductor portion H3, and 3 and 9 , over time, the surfaces along the a-axis grow while the surfaces along the m-axis disappear, and the first to third semiconductor portions H1 to H3, each surrounded only by surfaces along the a-axis, are formed autonomously. That is, when the supply of raw materials is stopped, the gap GA between the first and second semiconductor portions H1 and H2 and the gap GB between the first and third semiconductor portions H1 and H3 may form a V-shape in plan view. Step S30 of stopping the supply of raw materials may be performed when the first and second portions B1 and B2 approach an acute triangle, or may be performed at the timing when the first and second portions B1 and B2 become an acute triangle.

[0026] Fig. 11 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M10 that performs step S10 in Fig. 10, an apparatus M40 (e.g., an MOCVD apparatus) that performs steps S20 and S30 in Fig. 10, and a control device MC that controls the apparatuses M10 and M40.

[0027] 12 is a flowchart showing a method for manufacturing a semiconductor device according to this embodiment. As shown in FIG. 11, the method for manufacturing a semiconductor device includes a step S60 of preparing a semiconductor substrate 10, a step S70 of forming upper layer portions UL including active layers above the first to third semiconductor portions H1 to H3, and a step S80 of separating the first to third semiconductor portions H1 to H3 from the template substrate TS.

[0028] 13 and 14 are plan views showing the configuration of a semiconductor device according to this embodiment. FIGS. 15 and 16 are cross-sectional views showing the configuration of a semiconductor device separated from a template substrate TS according to this embodiment. As shown in FIGS. 13 to 16, a semiconductor device 15 (semiconductor chip) includes a semiconductor portion (base semiconductor portion) H containing a nitride semiconductor and an upper layer portion UL located on the semiconductor portion H. The semiconductor portion H has a shape with a minor axis X and a major axis Y and a first face UF (main surface) including two adjacent sides CA and CB that form an acute angle. The first face UF includes a longitudinal region FA that overlaps the major axis and includes a plurality of threading dislocations, and first and second low-dislocation regions LA and LB that are adjacent to each other in the a-axis direction of the nitride semiconductor via the longitudinal region FA and have a lower threading dislocation density than the longitudinal region FA. The upper layer portion UL includes an active layer 9 a and an anode EA that overlap the first low-dislocation region LA in a planar view.

[0029] The two sides CA and CB may be along two a-axis directions that form an angle of 60° in the nitride semiconductor. The first face UF may be rhombic. The semiconductor portion H may have a plurality of side faces KA, KB, VA, and VB that are along the a-axis of the nitride semiconductor. The plurality of side faces may include faces VA and VB that are perpendicular to the first face UF and faces KA and KB that are non-perpendicular to the first face UF.

[0030] The upper layer portion UL may include an n-type nitride semiconductor layer 9n, an active layer 9a, and a p-type nitride semiconductor layer 9p. The upper layer portion UL may include an insulating layer ZL overlapping the n-type contact layer Cn and the p-type contact layers PA and PB. A functional layer FL including the n-type nitride semiconductor layer 9n, the active layer 9a, and the p-type nitride semiconductor layer 9p may cover the semiconductor portion H.

[0031] The semiconductor device 15 has a second surface BT located opposite the first surface UF, and the second surface BT may have a separation trace RS at a position facing the longitudinal region FA. The separation trace RS is a trace of separation from the template substrate TS, and may be, for example, a region having at least one of a random surface morphology with a surface roughness Ra of 100 nm or more and a surface morphology with a threading dislocation density 10 times or more that of other regions. The areas of the second surface BT and the first surface UF may be different.

[0032] The upper layer portion UL may include a cathode EC overlapping the longitudinal region FA in a planar view. The upper layer portion UL may include a first p-type contact layer PA overlapping the first low dislocation region LA in a planar view, and a second p-type contact layer PB overlapping the second low dislocation region LB in a planar view. The anode EA and the cathode EC may be aligned in a direction (m-axis direction) perpendicular to the a-axis direction.

[0033] The semiconductor device 15 may be a light-emitting element (e.g., a micro-LED or a laser). In this case, the naturally formed oblique side surfaces of the semiconductor portion H during growth (ELO) produce a light reflection effect, improving the light extraction efficiency from the bottom surface BT (back surface). Furthermore, by disposing the cathode EC on the longitudinal region FA (defect concentration region) and the anode EA on the low-dislocation regions LA and LB, the active layer 9a on the low-dislocation regions LA and LB can be utilized to the maximum extent as a light-emitting region, thereby improving the light-emitting efficiency.

[0034] 13 and 14, both the anode EA and the cathode EC are formed above the first surface UF, but this is not limiting. The anode may be formed above the first surface UF and the cathode may be formed below the second surface BT.

[0035] 17 and 18 are plan views showing the configuration of a semiconductor device according to this embodiment. FIG. 19 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment. As shown in FIGS. 17, 18, and 19, a semiconductor device 25 (semiconductor element substrate) includes a transfer substrate PS, first to third semiconductor portions H1 to H3 that are located above the transfer substrate PS and include nitride semiconductors, and active layers 9a that are located between the transfer substrate PS and the first to third semiconductor portions H1 to H3, respectively. A first surface UF (main surface) of each of the first to third semiconductor portions H1 to H3 has a shape having a minor axis X and a major axis Y, and overlaps with the major axis X, and has a plurality of through holes. The substrate PS includes a longitudinal region FA including threading dislocations TD and low-dislocation regions LA and LB having a lower threading dislocation density than the longitudinal region FA, the first semiconductor portion H1 includes a first portion B1 located between the second semiconductor portion H2 and the third semiconductor portion H3 and a second portion B2 not located between the second semiconductor portion H2 and the third semiconductor portion H3, and the ratio of the length of the second semiconductor portion H2 in the longitudinal axis direction (Y direction) to the length of the first semiconductor portion H1 in the longitudinal axis direction (Y direction) is 0.8 to 1.2. The substrate PS may be a submount substrate connected to at least one of the anode EA and the cathode EC.

[0036] Fig. 20 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. Fig. 21 is a plan view showing a portion of Fig. 20. As shown in Figs. 20 and 21, the semiconductor substrate 10 comprises a template substrate TS including first to third seed regions S1 to S3 and a growth inhibition region DA, and first to third semiconductor portions H1 to H3 including nitride semiconductors.

[0037] The first semiconductor part H1 is located above the first seed region S1 and above the growth inhibition region DA, the second semiconductor part H2 is located above the second seed region S2 and above the growth inhibition region DA, and the third semiconductor part H3 is located above the third seed region S3 and above the growth inhibition region DA.

[0038] The top surface UF of each of the first to third semiconductor portions H1 to H3 has a shape with a minor axis X and a major axis Y, the first semiconductor portion H1 includes a first portion B1 located between the second semiconductor portion H2 and the third semiconductor portion H3 and a second portion B2 not located between the second semiconductor portion H2 and the third semiconductor portion H3, and the ratio of the length of the second semiconductor portion H2 in the major axis direction (Y direction) to the length of the first semiconductor portion H1 in the major axis direction (Y direction) is 0.8 to 1.2. The first semiconductor portion H1 and the second semiconductor portion H2 may be adjacent to each other with a gap GA ( FIG. 20 ) interposed therebetween, and the first semiconductor portion H1 and the third semiconductor portion H3 may be adjacent to each other with a gap GB ( FIG. 20 ). The major axis direction Y of the first and second semiconductor portions H1 and H2 may form an angle of 60°.

[0039] 20 and 21, uniaxial strain (e.g., strain in the m-axis direction) is effectively suppressed, reducing the anisotropy of warpage and thereby reducing the warpage itself of the semiconductor substrate 10. Each of the first and second semiconductor portions H1 and H2 can be used as a base semiconductor portion for forming an upper layer portion (device layer) including an active layer.

[0040] The top surface UF of each of the first to third semiconductor portions H1 to H3 may include two adjacent sides, and these two sides may be along two a-axis directions of the nitride semiconductor that form an angle of 60°. The top surface UF of each of the first to third semiconductor portions H1 to H3 may be a quadrangle (e.g., a rhombus) having two pairs of parallel sides. The first to third semiconductor portions H1 to H3 may have the same shape.

[0041] The width of the gap GA between the first and second semiconductor portions H1 and H2 may be equal to the width of the gap GB between the first and third semiconductor portions H1 and H3. In a plan view, the gap GA between the first and second semiconductor portions H1 and H3 and the gap GB between the first and third semiconductor portions H1 and H3 may form a V-shape. In a plan view, the first portion B1 may form an acute triangle. In a plan view, the first portion B1 and the second portion B2 may be line-symmetric.

[0042] Fig. 22 is a plan view showing the method for manufacturing the semiconductor substrate according to Fig. 20. As shown in Fig. 22, in a nitride semiconductor crystal (for example, a GaN-based semiconductor crystal), growth autonomously stops at a portion where a plane parallel to the a-axis occurs (for example, the upper surface UF of each of H1 to H3 autonomously becomes diamond-shaped), and therefore, in the semiconductor substrate 10, the shape of the semiconductor portion group (including H1 to H3) to be formed by ELO can be determined by the pattern of the seed group (including S1 to S3) of the template substrate TS.

[0043] This has the advantage that it is not necessary to divide the nitride semiconductor crystal formed by ELO into multiple semiconductor parts by etching or the like. The timing of stopping the supply of raw materials can also be easily controlled. Since an etching process (RIE process) for division is not required, side surface deterioration can be avoided.

[0044] By autonomously dividing and forming the semiconductor portion group (including H1 to H3), distortion of the semiconductor portion group (including H1 to H3) is reduced both at room temperature and at the growth temperature. This relieves the stress generated between the semiconductor portion group and the template substrate TS, reducing the anisotropy of warpage and reducing the warpage of the semiconductor substrate 10 itself. This facilitates subsequent processes using the semiconductor substrate 10 (such as the process of forming a device layer). In addition, the main substrate (wafer) included in the template substrate TS can be made thinner, thereby reducing costs. Furthermore, the reduced stress in the semiconductor portion group even at the growth temperature makes it easier to incorporate indium (In), facilitating the formation of an active layer for long wavelengths (e.g., red light emission).

[0045] Fig. 23 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. Fig. 24 is a plan view showing a portion of Fig. 23. As shown in Figs. 23 and 24, the semiconductor substrate 10 comprises a template substrate TS including first to third seed regions S1 to S3 and a growth inhibition region DA, and first to third semiconductor portions H1 to H3 including nitride semiconductors.

[0046] The first semiconductor part H1 is located above the first seed region S1 and above the growth inhibition region DA, the second semiconductor part H2 is located above the second seed region S2 and above the growth inhibition region DA, and the third semiconductor part H3 is located above the third seed region S3 and above the growth inhibition region DA.

[0047] The top surface UF of each of the first to third semiconductor portions H1 to H3 has a shape having a minor axis X and a major axis Y, the first semiconductor portion H1 includes a first portion B1 located between the second semiconductor portion H2 and the third semiconductor portion H3, and a second portion B2 not located between the second semiconductor portion H2 and the third semiconductor portion H3, and the ratio of the length of the second semiconductor portion H2 in the major axis direction (Y direction) to the length of the first semiconductor portion H1 in the major axis direction (Y direction) is 0.8 to 1.2.

[0048] The first semiconductor portion H1 and the second semiconductor portion H2 may be adjacent to each other with a gap GA (FIG. 24) therebetween, and the first semiconductor portion H1 and the third semiconductor portion H3 may be adjacent to each other with a gap GB (FIG. 24) therebetween. The long axis directions (Y directions) of the first and second semiconductor portions H1 and H2 may be the same (for example, the same m-axis direction).

[0049] The top surface UF of each of the first to third semiconductor portions H1 to H3 may include two adjacent sides, and these two sides may be along two a-axis directions of the nitride semiconductor that form a 60° angle. The top surface UF of each of the first to third semiconductor portions H1 to H3 may be a hexagon (e.g., diamond shape) having three pairs of parallel sides. The first to third semiconductor portions H1 to H3 may each have a side surface that is along the m-axis of the nitride semiconductor. The first to third semiconductor portions H1 to H3 may have the same shape. In a plan view, the area of ​​the first portion B1 may be smaller than the area of ​​the second portion B2.

[0050] 23 and 24, the first to third semiconductor portions H1 to H3 can be configured to reduce warpage of the semiconductor substrate. Furthermore, uneven supply of raw materials (e.g., excessive supply near the tip of the first semiconductor portion H1) can be reduced, and abnormal growth of the first semiconductor portion H1 can be suppressed. Each of the first and second semiconductor portions H1 and H2 can be used as a base semiconductor portion for forming an upper layer portion (device layer) including an active layer.

[0051] FIG. 25 is a plan view showing a semiconductor portion having a diamond shape. In a semiconductor portion (hexagonal crystal) having a diamond shape, when the ratio of the length in the long axis direction to the length in the short axis direction is large, slip (dislocations along the a-axis in a plan view, which are thought to be caused by stress within the crystal) occurs frequently. This occurs when the oblique m-planes cross the left and right m-axis parallel sides (two sides in the long axis direction) of the diamond shape. It has also been found that if the vertical length (size in the long axis direction) of the diamond shape is small, the oblique m-planes do not cross the left and right m-axis parallel sides, and slip is significantly reduced. From these findings, as shown in FIG. 25, for the first to third semiconductor portions H1 to H3 of a hexagonal crystal having a diamond shape (a hexagon with four interior angles of 150° and two interior angles of 60°), the ratio of the length Y in the long axis direction to the length X in the short axis direction on the top surface UF is set to 2×3. １／２ By making it equal to or less than 2 times the square root of 3, the occurrence of slippage can be significantly reduced. １／２ = (1 / 2) x 3 １／２ +1 x 3 １／２ + (1 / 2) x 3 １／２ is.

[0052] 26 is a plan view showing the method for manufacturing the semiconductor substrate shown in FIG. 23. As shown in FIG. 26, in nitride semiconductor crystals (e.g., GaN-based semiconductor crystals), growth autonomously stops at the locations where planes parallel to the a-axis are generated. Therefore, by controlling the timing of stopping the supply of raw materials so that adjacent semiconductor portions do not meet in the direction of the arrangement of the seed regions, the shape of the semiconductor portion group (including H1 to H3) formed by ELO can be determined by the pattern of the seed group (including S1 to S3) on the template substrate TS. This has the advantage that it is not necessary to divide the nitride semiconductor crystal formed by ELO into multiple semiconductor portions by etching or the like. Since an etching step (RIE step) for division is not required, side surface degradation can be avoided.

[0053] By dividing and forming the semiconductor portion group (including H1 to H3), the stress generated between the semiconductor portion group and the template substrate TS is alleviated both at room temperature and at the growth temperature, and the warpage caused by the semiconductor portion group is small and close to central symmetry, so that the warpage of the semiconductor substrate 10 itself approaches the warpage of the template substrate TS itself. This improves the temperature distribution of the template substrate TS during the growth process of the semiconductor portion group, improving yield. Furthermore, post-processing using the semiconductor substrate 10 (such as the device layer formation process) becomes easier. Furthermore, the main substrate (wafer) included in the template substrate TS can be made thinner, thereby reducing costs. Furthermore, the reduced stress in the semiconductor portion group, even at the growth temperature, makes it easier to incorporate indium (In), facilitating the formation of an active layer for long wavelengths (e.g., red light emission).

[0054] Fig. 27 is a plan view showing a method for manufacturing the semiconductor substrate shown in Fig. 6. As shown in Fig. 27, starting from a part (first seed portion S1) of the seed layer 4 exposed in the opening of the mask portion 5 (growth suppression region DA), a first semiconductor portion H1 which is a nitride semiconductor crystal (for example, a GaN crystal) is grown by ELO (epi-lateral overgrowth).

[0055] FIG. 28 is a plan view illustrating a method for manufacturing the semiconductor substrate shown in FIG. As shown in FIG. 28 , the template substrate TS includes a growth-inhibited region DA, which is a modified region (e.g., an AlN crystal modified region using argon plasma) of the seed layer 4 (e.g., an AlN layer), and a first seed portion S1 (AlN region), which is an unmodified region of the seed layer 4. Starting from the first seed portion S1, a nitride semiconductor crystal (e.g., a GaN crystal) is first grown vertically, followed by the formation of a growth-inhibited film 7. The first semiconductor portion H1 is then grown by ELO (lateral overgrowth) above the growth-inhibited region DA. This allows the first semiconductor portion H1 to be suspended (i.e., a gap JD is formed between the first semiconductor portion H1 and the growth-inhibited region DA). The growth-inhibited region DA may have a higher concentration of argon as an impurity than the first seed portion S1. The growth-inhibited region DA may also contain an oxide of the seed layer 4.

[0056] (Notes) The above disclosure is for the purpose of illustration and explanation, not for the purpose of limitation. Based on these examples and explanations, many variations will be obvious to those skilled in the art, and it should be noted that these variations are also included in the embodiments. In the summary description below, the term "above" also includes the contents of Figures 1 to 28.

[0057] [Summary] A semiconductor substrate comprising: a template substrate including first to third seed regions and a growth inhibition region; and first to third semiconductor parts including a nitride semiconductor; the first semiconductor part is located from above the first seed region to above the growth inhibition region; the second semiconductor part is located from above the second seed region to above the growth inhibition region; the third semiconductor part is located from above the third seed region to above the growth inhibition region; the top surfaces of the first to third semiconductor parts have a shape with a minor axis and a major axis; the first semiconductor part includes a first part located between the second semiconductor part and the third semiconductor part, and a second part not located between the second semiconductor part and the third semiconductor part; and the ratio of the length in the major axis direction of the second semiconductor part to the length in the major axis direction of the first semiconductor part is 0.8 to 1.2.

[0058] The semiconductor substrate described above, wherein the first semiconductor portion is adjacent to the second and third semiconductor portions, and the long axis directions of the first and second semiconductor portions are the same.

[0059] The semiconductor substrate described above, wherein the top surface of each of the first to third semiconductor portions includes two sides, and the two sides are along two a-axis directions of the nitride semiconductor that form an angle of 60°.

[0060] The semiconductor substrate described above, wherein the first semiconductor portion is adjacent to the second and third semiconductor portions, and the major axis directions of the first and second semiconductor portions form an angle of 60°.

[0061] The semiconductor substrate described above, wherein the upper surfaces of the first to third semiconductor portions each include a longitudinal region that overlaps the longitudinal axis and includes a plurality of threading dislocations, and a low-dislocation region that has a threading dislocation density lower than that of the longitudinal region.

[0062] The semiconductor substrate described above, wherein the top surface of each of the first to third semiconductor portions is a rectangle having two pairs of parallel sides.

[0063] The semiconductor substrate described above, wherein the top surface of each of the first to third semiconductor portions is a hexagon having three pairs of parallel sides.

[0064] The semiconductor substrate described above, wherein the long axis direction of the first semiconductor portion is the m-axis direction of the nitride semiconductor.

[0065] The semiconductor substrate described above, wherein the first to third semiconductor portions have the same shape.

[0066] The semiconductor substrate described above further comprises a fourth semiconductor portion having the same shape as the first to third semiconductor portions and adjacent to at least one of the second and third semiconductor portions.

[0067] The semiconductor substrate described above, wherein each of the first to third semiconductor portions has a plurality of side surfaces along the a-axis of the nitride semiconductor.

[0068] The semiconductor substrate described above, wherein each of the first to third semiconductor portions has a side surface along the m-axis of the nitride semiconductor.

[0069] The ratio of the length in the major axis direction to the length in the minor axis direction of each of the upper surfaces of the first to third semiconductor portions is 2×3 １／２ The semiconductor substrate as described above, wherein:

[0070] The above-mentioned semiconductor substrate, wherein the width of the gap between the first and second semiconductor portions is equal to the width of the gap between the first and third semiconductor portions.

[0071] The semiconductor substrate described above, wherein the gap between the first and second semiconductor portions and the gap between the first and third semiconductor portions form a V-shape in plan view.

[0072] The aforementioned semiconductor substrate, wherein the first portion forms an acute triangle in plan view.

[0073] The semiconductor substrate described above, wherein each of the first to third seed regions has a shape whose longitudinal direction is the m-axis direction of the nitride semiconductor.

[0074] The semiconductor substrate described above, wherein the first to third semiconductor portions have different areas of the upper and lower surfaces.

[0075] The semiconductor substrate described above, wherein a gap is located between the first semiconductor portion and the growth inhibiting region.

[0076] The above-mentioned semiconductor substrate, wherein a plurality of semiconductor portions of the same shape including the first semiconductor portion are aligned in the a-axis direction of the nitride semiconductor, and a plurality of semiconductor portions of the same shape including the second and third semiconductor portions are aligned in the a-axis direction of the nitride semiconductor.

[0077] The semiconductor substrate described above, wherein the first to third semiconductor portions each serve as a base semiconductor portion when an upper layer portion including an active layer is formed.

[0078] The semiconductor substrate described above has upper layer portions including active layers above the first to third semiconductor portions.

[0079] The above-mentioned semiconductor substrate, wherein the template substrate has a seed group including the first to third seed portions arranged in a staggered pattern.

[0080] The aforementioned semiconductor substrate, wherein the nitride semiconductor is a GaN-based semiconductor, and the template substrate includes a heterogeneous substrate having a lattice constant different from that of the GaN-based semiconductor, and a seed layer located above the heterogeneous substrate.

[0081] a step of growing first to third semiconductor portions corresponding to the first to third seed regions by supplying a nitride semiconductor raw material onto the template substrate; and a step of stopping the supply of the raw material after the first to third semiconductor portions, which are independent of one another, have a shape having a short axis and a long axis, and the first semiconductor portion has a shape including a first portion located between the second semiconductor portion and the third semiconductor portion and a second portion not located between the second semiconductor portion and the third semiconductor portion, and

[0082] The aforementioned method for manufacturing a semiconductor substrate, wherein when the supply is stopped, the gap between the first and second semiconductor portions and the gap between the first and third semiconductor portions form a V-shape in plan view.

[0083] The above-mentioned method for manufacturing a semiconductor substrate does not include a step of dividing the first semiconductor portion by etching or cleaving, a step of dividing the second semiconductor portion by etching or cleaving, and a step of dividing the third semiconductor portion by etching or cleaving.

[0084] A semiconductor substrate manufacturing device that performs each of the above steps.

[0085] A method for manufacturing a semiconductor device, comprising: a step of preparing the above-mentioned semiconductor substrate; a step of forming upper layer portions including active layers above the first to third semiconductor portions, respectively; and a step of separating the first to third semiconductor portions from the template substrate.

[0086] a transfer substrate; first to third semiconductor portions located above the transfer substrate and including a nitride semiconductor; and active layers located between the transfer substrate and each of the first to third semiconductor portions; a main surface of each of the first to third semiconductor portions has a shape having a short axis and a long axis, and includes a longitudinal region overlapping the long axis and including a plurality of threading dislocations, and a low-dislocation region having a threading dislocation density lower than that of the longitudinal region; the first semiconductor portion includes a first portion located between the second semiconductor portion and the third semiconductor portion, and a second portion not located between the second semiconductor portion and the third semiconductor portion; and a ratio of the length of the second semiconductor portion in the long axis direction to the length of the first semiconductor portion in the long axis direction is 0.8 to 1.2.

[0087] a semiconductor device comprising: a semiconductor portion including a nitride semiconductor; and an upper layer portion located on the semiconductor portion; wherein the semiconductor portion has a shape with a short axis and a long axis, and has a first surface including two adjacent sides that form an acute angle; the first surface includes a longitudinal region that overlaps the long axis and includes a plurality of threading dislocations, and first and second low dislocation regions that are adjacent to each other in an a-axis direction of the nitride semiconductor via the longitudinal region and have a lower threading dislocation density than the longitudinal region; and the upper layer portion includes an active layer and an anode that overlap the first low dislocation region in a planar view.

[0088] The semiconductor device described above, wherein the two sides are along two a-axis directions in the nitride semiconductor that form an angle of 60°.

[0089] The semiconductor device as described above, wherein the first surface is diamond-shaped.

[0090] The semiconductor device described above, wherein the semiconductor portion has a plurality of side surfaces along the a-axis of the nitride semiconductor.

[0091] The aforementioned semiconductor device, wherein the plurality of side surfaces include surfaces perpendicular to the first surface and surfaces non-perpendicular to the first surface.

[0092] The semiconductor device as described above, further comprising a second surface located opposite the first surface, wherein the second surface has a peeling trace at a position facing the longitudinal region.

[0093] The semiconductor device as described above, further comprising a second surface located opposite the first surface, wherein the second surface and the first surface have different areas.

[0094] The semiconductor device described above, wherein the upper layer portion includes a cathode that overlaps the longitudinal region in a plan view.

[0095] The semiconductor device described above, wherein the upper layer portion includes a first p-type contact layer overlapping the first low dislocation region in a planar view, and a second p-type contact layer overlapping the second low dislocation region in a planar view.

[0096] The aforementioned semiconductor device, wherein the anode and the cathode are aligned in a direction perpendicular to the a-axis direction.

[0097] H1 First semiconductor portion H2 Second semiconductor portion H3 Third semiconductor portion S1 First seed portion S2 Second seed portion S3 Third seed portion B1 First portion B2 Second portion JD Void DA Growth inhibition region TS Template substrate UF Upper surface (main surface) 10 Semiconductor substrate 15 Semiconductor device 25 Semiconductor device

Claims

1. A semiconductor substrate comprising: a template substrate including a first seed region, a second seed region, a third seed region, and a growth inhibition region; and a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion each including a nitride semiconductor, wherein the first semiconductor portion is located from above the first seed region to above the growth inhibition region, the second semiconductor portion is located from above the second seed region to above the growth inhibition region, and the third semiconductor portion is located from above the third seed region to above the growth inhibition region, the top surfaces of the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion each have a shape having a short axis and a long axis, the first semiconductor portion includes a first portion located between the second semiconductor portion and the third semiconductor portion, and a second portion not located between the second semiconductor portion and the third semiconductor portion, and a ratio of the length in the long axis direction of the second semiconductor portion to the length in the long axis direction of the first semiconductor portion is 0.8 to 1.

2.

2. The semiconductor substrate according to claim 1, wherein the first semiconductor portion is adjacent to the second and third semiconductor portions, and the major axis directions of the first and second semiconductor portions are the same.

3. The semiconductor substrate according to claim 2, wherein the top surface of each of the first to third semiconductor portions includes two sides, and the two sides are aligned along two a-axis directions of the nitride semiconductor that form an angle of 60°.

4. The semiconductor substrate according to claim 1, wherein the first semiconductor portion is adjacent to the second and third semiconductor portions, and the major axis directions of the first and second semiconductor portions form an angle of 60°.

5. A semiconductor substrate according to any one of claims 1 to 4, wherein the upper surfaces of the first to third semiconductor portions each include a longitudinal region overlapping the longitudinal axis and including a plurality of threading dislocations, and a low-dislocation region having a lower threading dislocation density than the longitudinal region.

6. The semiconductor substrate according to claim 1, wherein the top surface of each of the first to third semiconductor portions is a rectangle having two pairs of parallel sides.

7. The semiconductor substrate according to claim 1, wherein the top surface of each of the first to third semiconductor portions is a hexagon having three pairs of parallel sides.

8. The semiconductor substrate according to any one of claims 1 to 7, wherein the long axis direction of said first semiconductor portion is the m-axis direction of said nitride semiconductor.

9. The semiconductor substrate according to claim 1, wherein the first, second and third semiconductor portions have the same shape.

10. The semiconductor substrate according to claim 9, further comprising a fourth semiconductor portion having the same shape as said first to third semiconductor portions and adjacent to at least one of said second and third semiconductor portions.

11. The semiconductor wafer according to claim 1, wherein each of the first to third semiconductor portions has a plurality of side surfaces aligned along the a-axis of the nitride semiconductor.

12. The semiconductor wafer according to claim 7, wherein each of the first to third semiconductor portions has a side surface along the m-axis of the nitride semiconductor.

13. With respect to the upper surfaces of the first to third semiconductor portions, the ratio of the length in the major axis direction to the length in the minor axis direction is 2×3 １／２ The semiconductor substrate according to any one of claims 1 to 12, wherein:

14. The semiconductor substrate according to any one of claims 1 to 13, wherein the width of the gap between the first and second semiconductor portions is equal to the width of the gap between the first and third semiconductor portions.

15. The semiconductor substrate according to any one of claims 1 to 14, wherein in a plan view, the gap between the first and second semiconductor portions and the gap between the first and third semiconductor portions form a V shape.

16. The semiconductor substrate according to any one of claims 1 to 15, wherein the first portion forms an acute triangle in a plan view.

17. The semiconductor wafer according to any one of claims 1 to 16, wherein each of the first to third seed regions has a shape whose longitudinal direction is the m-axis direction of the nitride semiconductor.

18. The semiconductor substrate according to any one of claims 1 to 17, wherein the areas of the upper surface and the lower surface of each of the first to third semiconductor portions are different.

19. The semiconductor substrate according to any one of claims 1 to 18, wherein a gap is located between the first semiconductor portion and the growth inhibition region.

20. A semiconductor substrate according to any one of claims 1 to 19, wherein a plurality of semiconductor portions of the same shape including the first semiconductor portion are aligned in the a-axis direction of the nitride semiconductor, and a plurality of semiconductor portions of the same shape including the second and third semiconductor portions are aligned in the a-axis direction of the nitride semiconductor.

21. The semiconductor substrate according to any one of claims 1 to 20, wherein each of the first to third semiconductor portions serves as a base semiconductor portion when forming an upper layer portion including an active layer.

22. The semiconductor substrate according to claim 21, further comprising an upper layer portion including an active layer above each of the first to third semiconductor portions.

23. The semiconductor substrate according to any one of claims 1 to 22, wherein on the template substrate, a seed group including the first to third seed portions is arranged in a staggered pattern.

24. The semiconductor substrate according to any one of claims 1 to 23, wherein the nitride semiconductor is a GaN-based semiconductor, and the template substrate includes a heterogeneous substrate having a lattice constant different from that of the GaN-based semiconductor, and a seed layer located above the heterogeneous substrate.

25. A method for manufacturing a semiconductor substrate, comprising: preparing a template substrate including a first seed region, a second seed region, a third seed region, and a growth inhibition region; supplying a nitride semiconductor source to the template substrate to grow a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion corresponding to the first seed region, the second seed region, and the third seed region; and stopping the supply of the source after the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion each have a short axis and a long axis that are independent of one another, and the first semiconductor portion has a shape including a first portion located between the second semiconductor portion and the third semiconductor portion and a second portion not located between the second semiconductor portion and the third semiconductor portion, wherein at the time of stopping the supply, a ratio of the length of the second semiconductor portion in the long axis direction to the length of the first semiconductor portion in the long axis direction is 0.8 to 1.

2.

26. The method for manufacturing a semiconductor substrate according to claim 25, wherein when the supply is stopped, the gap between the first and second semiconductor portions and the gap between the first and third semiconductor portions form a V-shape in a plan view.

27. A method for manufacturing a semiconductor substrate according to claim 25, which does not include a step of dividing the first semiconductor portion by etching or cleaving, a step of dividing the second semiconductor portion by etching or cleaving, and a step of dividing the third semiconductor portion by etching or cleaving.

28. A semiconductor substrate manufacturing apparatus which performs each of the steps recited in claim 25.

29. A method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate as described in claim 1; forming upper layer portions including active layers above the first to third semiconductor portions, respectively; and separating the first to third semiconductor portions from the template substrate.

30. A semiconductor device comprising: a transfer substrate; a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion located above the transfer substrate and including a nitride semiconductor; and an active layer located between the transfer substrate and each of the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion, wherein a main surface of each of the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion has a shape having a short axis and a long axis and includes a longitudinal region overlapping the long axis and including a plurality of threading dislocations, and a low-dislocation region having a lower threading dislocation density than the longitudinal region, the first semiconductor portion includes a first portion located between the second semiconductor portion and the third semiconductor portion, and a second portion not located between the second semiconductor portion and the third semiconductor portion, and a ratio of the length of the second semiconductor portion in the long axis direction to the length of the first semiconductor portion in the long axis direction is 0.8 to 1.

2.

31. A semiconductor device comprising: a semiconductor section including a nitride semiconductor; and an upper layer section located on the semiconductor section; the semiconductor section having a shape with a short axis and a long axis, and a first surface including two adjacent sides forming an acute angle; the first surface including a longitudinal region overlapping the long axis and including a plurality of threading dislocations, and first and second low dislocation regions adjacent to each other in the a-axis direction of the nitride semiconductor via the longitudinal region and having a lower threading dislocation density than the longitudinal region; and the upper layer section including an active layer and an anode overlapping with the first low dislocation region in a planar view.

32. The semiconductor device according to claim 31, wherein the two sides are aligned along two a-axis directions of the nitride semiconductor that form an angle of 60°.

33. The semiconductor device of claim 31 or 32, wherein the first surface is diamond shaped.

34. The semiconductor device according to claim 31 or 32, wherein the semiconductor portion has a plurality of side surfaces aligned along the a-axis of the nitride semiconductor.

35. The semiconductor device of claim 34, wherein the plurality of side surfaces include surfaces that are perpendicular to the first surface and surfaces that are non-perpendicular to the first surface.

36. The semiconductor device according to claim 31 or 32, further comprising a second surface located opposite the first surface, the second surface having a peeling mark at a position facing the longitudinal region.

37. The semiconductor device of claim 31 or 32, further comprising a second surface located opposite said first surface, said second surface and said first surface being different in area.

38. The semiconductor device according to claim 31 or 32, wherein the upper layer portion includes a cathode overlapping the longitudinal region in a plan view.

39. The semiconductor device of claim 38, wherein the upper layer portion includes a first p-type contact layer overlapping the first low dislocation region in a planar view, and a second p-type contact layer overlapping the second low dislocation region in a planar view.

40. The semiconductor device of claim 39, wherein the anode and the cathode are aligned in a direction perpendicular to the a-axis direction.

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