Power conversion device

Abstract

Provided is a power conversion device provided with a wiring board in which a plurality of upper arm semiconductor elements and a plurality of lower arm semiconductor elements are connected in parallel and that has a plurality of wiring layers. The plurality of wiring layers include: positive electrode wiring that extends along the array direction of the plurality of upper arm semiconductor elements; negative electrode wiring that extends along the array direction of the plurality of lower arm semiconductor elements; and output wiring that connects the plurality of upper arm semiconductor elements and the plurality of lower arm semiconductor elements with each other. The positive electrode wiring and the negative electrode wiring form: a first positive / negative electrode wiring pair, in which the positive electrode wiring and the negative electrode wiring are arranged in parallel and are arranged as stacked on the output wiring; and a second positive / negative electrode wiring pair, in which the positive electrode wiring and the negative electrode wiring are arranged as stacked on each other.

Description

Power Conversion Device

[0001] The present invention relates to a power conversion device.

[0002] For card-type inverters incorporating small semiconductor packages, parallel mounting of multiple small semiconductor packages is required to improve productivity and expand the output lineup. At the same time, reduction of inductance that occurs when a large current is generated by parallel mounting of multiple small semiconductor packages is also required. For example, Patent Document 1 listed below describes the configuration of a semiconductor module in which the wiring structure within the wiring board changes along the arrangement direction of the semiconductor elements, thereby reducing inductance.

[0003] Patent No. 6269296

[0004] While Patent Document 1 achieves the goal of reducing inductance, it focuses only on reducing the inductance of the short-circuit loop paths of the upper and lower arms of the semiconductor element, and does not take into account the inductance variation that occurs when multiple semiconductor chips are connected in parallel. Furthermore, in order to achieve the goal of miniaturizing the main circuit board on which a small semiconductor package is mounted, it is difficult to equalize the wiring lengths connecting the film capacitor and each semiconductor device. This configuration poses the problem of current variation in each semiconductor device due to inductance differences. In light of this, the present invention aims to provide a power conversion device that achieves both low inductance and equal inductance.

[0005] A power conversion device including a wiring board having a plurality of wiring layers on which a plurality of upper arm semiconductor elements and a plurality of lower arm semiconductor elements are connected in parallel, wherein the plurality of wiring layers include positive wiring extending along the arrangement direction of the plurality of upper arm semiconductor elements, negative wiring extending along the arrangement direction of the plurality of lower arm semiconductor elements, and output wiring connecting the plurality of upper arm semiconductor elements and the plurality of lower arm semiconductor elements, and the positive wiring and the negative wiring form a first pair of positive and negative wiring that are each arranged in parallel and stacked on the output wiring, and a second pair of positive and negative wiring that are each arranged stacked on top of each other.

[0006] A power conversion device that achieves both low inductance and uniform inductance can be provided.

[0007] A circuit diagram of a power conversion device of the present invention. An overall external view of a power conversion device of the present invention. A cross-sectional view of a wiring board according to an embodiment of the present invention. A diagram of a semiconductor device according to an embodiment of the present invention. A diagram of the wiring board from the second layer to the fourth layer according to an embodiment of the present invention. A diagram of a wiring board on which a second capacitor is arranged according to an embodiment of the present invention.

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and some omissions and simplifications have been made as appropriate for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0009] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0010] (One embodiment of the present invention and overall configuration) (FIG. 1) A power conversion device 1 is configured with three-phase semiconductor devices: U-phase, V-phase, and W-phase. Each semiconductor device is configured with an upper arm semiconductor element 4 and a lower arm semiconductor element 5. The upper arm semiconductor element 4 and the lower arm semiconductor element 5 may be, for example, an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0011] A plurality of upper arm semiconductor elements 4 and lower arm semiconductor elements 5 are formed and connected in parallel to each other, thereby increasing the output current of the power conversion device 1. In the power conversion circuit for one of the U, V, and W phases, a series-connected upper arm semiconductor element 4 and lower arm semiconductor element 5 are paired with a capacitor 8. A small ceramic capacitor 7 is connected in parallel to each phase.

[0012] The output wiring 6 for each phase is connected to a load such as a motor (not shown). The output wiring 6 also connects a plurality of upper arm semiconductor elements 4 and a plurality of lower arm semiconductor elements 5. The capacitors 8 are, for example, film capacitors or electrolytic capacitors with large capacitance. By arranging such capacitors 8 near the upper arm semiconductor elements 4 and the lower arm semiconductor elements 5, the wiring inductance of the positive electrode wiring 2 and the negative electrode wiring 3 is reduced.

[0013] The positive wiring 2 is connected to the positive terminal of a DC power supply such as a battery (not shown), and the negative wiring 3 is connected to the negative terminal of the DC power supply such as a battery, thereby supplying a DC voltage to the power conversion circuit of each phase.

[0014] (FIG. 2) Power conversion device 1 includes a wiring board 13 having a plurality of upper arm semiconductor elements 4 and a plurality of lower arm semiconductor elements 5 connected in parallel and having a plurality of wiring layers. Capacitor 8 is connected to positive electrode wiring 2 and negative electrode wiring 3 provided on wiring board 13. Capacitor 8 is disposed adjacent to one side (side) of wiring board 13 and electrically connected thereto, which facilitates fixing to a housing (not shown) of power conversion device 1. This improves vibration resistance.

[0015] The output terminal 6a is arranged on the other side of the wiring board 13 opposite to the side on which the capacitor 8 is arranged, and is electrically connected to the output wiring 6. By arranging the upper arm semiconductor element 4 and the lower arm semiconductor element 5 side by side and extending them from the capacitor 8 toward the output terminal 6a, it is possible to shorten the positive wiring 2, the negative wiring 3, and the output wiring 6, and to reduce the size of the power conversion device 1. By arranging the multiple upper arm semiconductor elements 4 and the multiple lower arm semiconductor elements 5 in a row, it becomes easy to attach a cooler (not shown) to this portion, and it also becomes possible to reduce the size of the cooler.

[0016] Three-phase semiconductor devices, U-phase, V-phase, and W-phase, are arranged on wiring board 13. Positive wiring 2 and negative wiring 3 are formed in parallel between the respective semiconductor devices. A plurality of capacitors 8 are arranged on wiring board 13 along the arrangement of the U-phase, V-phase, and W-phase semiconductor devices.

[0017] (FIG. 3) Wiring board 13 has multiple wiring layers between the row of upper arm semiconductor elements 4 and the row of lower arm semiconductor elements 5. These multiple wiring layers include positive wiring 2 extending in the arrangement direction of the multiple upper arm semiconductor elements 4, negative wiring 3 extending in the arrangement direction of the multiple lower arm semiconductor elements 5, and output wiring 6 connecting the multiple upper arm semiconductor elements 4 and the multiple lower arm semiconductor elements 5.

[0018] The wiring board 13 is configured by stacking four layers of wiring. Starting from the top in Fig. 3, the layers are designated as the first layer, the second layer, etc. In the first layer, the positive electrode wiring 2 and the negative electrode wiring 3 are arranged in parallel. In the second layer, the output wiring 6 is arranged. In the third layer, the negative electrode wiring 3 is arranged between the output wiring 6. In the fourth layer, the positive electrode wiring 2 is arranged between the output wiring 6. An insulating material such as resin is filled between each layer of the wiring board 13, so that the wiring 2, 3, and 6 formed on each layer are electrically insulated from one another.

[0019] A wiring pair in which the positive electrode wiring 2 and the negative electrode wiring 3 are formed in parallel and stacked on the output wiring 6 is referred to as a first positive / negative electrode wiring pair 13a, and a wiring pair in which the positive electrode wiring 2 and the negative electrode wiring 3 are stacked on top of each other is referred to as a second positive / negative electrode wiring pair 13b.

[0020] In this way, assuming a structure in which the chips of the upper and lower arms are arranged in multiple parallel arrangements, two types of stacked wiring pair structures with different opposing partners are provided for the positive wiring 2 and negative wiring 3 that run along the arrangement direction of the multiple upper arm semiconductor elements 4 and lower arm semiconductor elements 5 arranged in parallel, thereby making it possible to achieve both low inductance and equal inductance.

[0021] (Fig. 4) By widely opposing the current flowing from capacitor 8 (see Fig. 2) located on the upper side of the page to each semiconductor device (upper arm semiconductor element 4, lower arm semiconductor element 5), an increase in inductance caused by extending wiring 2, 3, 6 is suppressed. Furthermore, by achieving both low inductance and equal inductance, it is possible to realize a large current by driving a large number of semiconductor devices arranged in parallel in parallel.

[0022] Wiring board 13 is electrically connected to terminals of upper arm semiconductor element 4 and lower arm semiconductor element 5. Control terminals 10 of upper arm semiconductor element 4 and lower arm semiconductor element 5 are connected to a control circuit (not shown), and are turned on or off based on a signal input from a higher-level control device such as a microcomputer, thereby outputting an AC voltage to a load such as a motor.

[0023] The terminals of the upper arm semiconductor element 4 and the lower arm semiconductor element 5 will be described. The upper arm semiconductor element 4 has three terminals: a main circuit high-voltage side terminal 12, a main circuit low-voltage side terminal 12a, and a control terminal 10. The lower arm semiconductor element 5 has three terminals: a main circuit high-voltage side terminal 11, a main circuit low-voltage side terminal 11a, and a control terminal 10. In the upper arm semiconductor element 4 and the lower arm semiconductor element 5 connected to the wiring board 13, the main circuit high-voltage side terminals 11, 12 and the main circuit low-voltage side terminals 11a, 12a are alternately arranged and electrically connected to the wiring board 13.

[0024] The main circuit high-voltage side terminals 11 and 12 are collector terminals for IGBTs and drain terminals for MOSFETs. The main circuit low-voltage side terminals 11a and 12a are emitter terminals for IGBTs and source terminals for MOSFETs. The control terminal 10 is a gate terminal or the like.

[0025] The main circuit high-voltage side terminal 12 and main circuit low-voltage side terminal 12a of the upper arm semiconductor element 4, the main circuit high-voltage side terminal 11 and main circuit low-voltage side terminal 11a of the lower arm semiconductor element 5, and the control terminal 10 are connected to the positive electrode wiring 2 and negative electrode wiring 3 formed on the first layer (outermost layer) of the wiring board 13 via a bonding material such as solder.

[0026] The positive electrode wiring 2, the negative electrode wiring 3, and the output wiring 6 formed in the first layer are electrically connected to other layers stacked on the wiring board 13 by interlayer connections 9 formed by through-hole vias or the like.

[0027] A plurality of interlayer connectors 9 are formed on the positive wiring 2 and the negative wiring 3 along the arrangement direction of the plurality of upper arm semiconductor elements 4 and the plurality of lower arm semiconductor elements 5. The interlayer connectors 9 electrically connect the positive wirings 2 and the negative wirings 3 of the first positive / negative wiring pair 13a and the second positive / negative wiring pair 13b, thereby increasing the cross-sectional area of ​​the current flowing in the cross-sectional direction of the wiring board 13 (the stacking direction of the wiring). This reduces electrical resistance and reduces heat generation in the positive wiring 2 and the negative wiring 3. Furthermore, the interlayer connectors 9 improve the heat transfer in the cross-sectional direction of the wiring board 13, thereby suppressing an increase in wiring temperature.

[0028] The positive terminal of capacitor 8 is connected to the main circuit high-voltage side terminal 12 of the upper arm semiconductor element 4 by a positive wiring 2. The negative terminal of capacitor 8 is connected to the main circuit low-voltage side terminal 11a of the lower arm semiconductor element 5 by a negative wiring 3. The main circuit low-voltage side terminal 12a of the upper arm semiconductor element 4 is connected to the main circuit high-voltage side terminal 11 of the lower arm semiconductor element 5 by output wiring 6 of each phase.

[0029] The positive wiring 2 is connected to the positive terminal of the capacitor 8 of the other phase and to the main circuit high-voltage side terminal 11 of the upper arm semiconductor element 4 of the other phase. The negative wiring 3 is connected to the negative terminal of the capacitor 8 of the other phase and to the main circuit low-voltage side terminal 11a of the lower arm semiconductor element 5 of the other phase. This makes it possible to configure a multi-phase circuit.

[0030] (FIG. 5) Fig. 5(a) is a diagram illustrating the second layer of wiring board 13, Fig. 5(b) is a diagram illustrating the third layer of wiring board 13, and Fig. 5(c) is a diagram illustrating the fourth layer of wiring board 13. As described above, wiring board 13 has multiple wiring layers in the thickness direction of wiring board 13. For example, if wiring board 13 is a four-layer board, the first layer is arranged on the front surface of the board and the fourth layer is arranged on the back surface of the board.

[0031] The output wiring 6 is arranged on the second layer, which makes it possible to shorten the length of the wiring connecting the main circuit low-voltage side terminal 12 a of the upper arm semiconductor element 4 and the main circuit high-voltage side terminal 11 of the lower arm semiconductor element 5, thereby reducing the wiring inductance.

[0032] In the third layer, the positive wires 2 are arranged so as to be formed between the output wires 6. The capacitors 8 are arranged on one side (upper side of the drawing) of the wiring board 13, and are electrically connected to the second positive and negative wire pair 13b (see FIG. 3). The second positive and negative wire pair 13b, including the positive wires 2 in the third layer, is formed along an extension direction perpendicular to one side of the wiring board 13, and the cross-sectional area (conduction cross-sectional area) in the direction perpendicular to the extension direction becomes smaller the further away from the capacitor 8.

[0033] The output wiring 6 is formed along an extension direction perpendicular to the other side of the wiring board 13. The output wiring 6 is configured so that the cross-sectional area in a direction perpendicular to the extension direction becomes smaller the farther away from the output terminal 6a. This makes it possible to adjust the balance of the current densities on the DC and AC sides, uniformize the current densities of the wiring, and suppress local temperature increases on the wiring board 13.

[0034] (FIG. 6) In the first layer (outermost layer) of wiring board 13, ceramic capacitor 7 (second capacitor) is disposed between positive electrode wiring 2 and negative electrode wiring 3 formed in parallel. Ceramic capacitor 7 is a second capacitor provided separately from capacitor 8, and is disposed equidistant from each semiconductor device. The direction of current through ceramic capacitor 7 is determined by the formation of a wiring layer between upper arm semiconductor element 4 and lower arm semiconductor element 5.

[0035] The distance between the capacitor 8 and each semiconductor device is different, and the positive wire 2 and the negative wire 3 of the second positive / negative wire pair 13b connecting the capacitor 8 to each semiconductor device are stacked. By opposing the switching transient current flowing from the ceramic capacitor 7 to each semiconductor device between the layers of the second positive / negative wire pair 13b, inductance can be reduced and the transient current supplied from the capacitor 8 can be suppressed. Furthermore, with the above configuration, the currents flowing from the capacitor 8 to each semiconductor device are widely opposed, thereby suppressing inductance differences due to unequal length wires.

[0036] Since ceramic capacitors 7 are arranged at equal distances from corresponding elements among the many upper arm semiconductor elements 4 and lower arm semiconductor elements 5 connected in parallel, variations in wiring inductance are suppressed.

[0037] The ceramic capacitor 7 is connected to the upper arm semiconductor element 4 and the lower arm semiconductor element 5 by the positive wiring 2 and negative wiring 3 which have low inductance, thereby reducing the current supplied from the capacitor 8 during switching, and therefore reducing the effect of the inductance difference on the positive wiring 2 and negative wiring 3 which connect the capacitor 8 to the upper arm semiconductor element 4 and the lower arm semiconductor element 5.

[0038] Ceramic capacitor 7 is disposed near upper arm semiconductor element 4 and lower arm semiconductor element 5, so that transient current during switching is supplied not only from capacitor 8 but also from ceramic capacitor 7. Furthermore, first positive / negative wiring pair 13a causes currents flowing through positive wiring 2 and negative wiring 3 connecting ceramic capacitor 7 to upper arm semiconductor element 4 and lower arm semiconductor element 5 to oppose each other. This cancels out magnetic flux, reducing the inductance of the wiring connecting ceramic capacitor 7 to upper arm semiconductor element 4 and lower arm semiconductor element 5, and enabling the transient current supplied from ceramic capacitor 7 to be increased.

[0039] In the first positive / negative wiring pair 13a, which is a closed loop path passing through the ceramic capacitor 7, the positive wiring 2, the negative wiring 3, and the output wiring 6 are arranged in a stacked configuration, and transient currents flow in opposite directions, reducing inductance. Furthermore, the main circuit current flowing from the capacitor 8 cancels out magnetic fluxes in the positive wiring 2 and the negative wiring 3, reducing position-dependent inductance differences between the semiconductor devices.

[0040] Even for semiconductor devices located far from capacitor 8, an increase in wiring inductance due to wiring extension is suppressed, so the difference in wiring inductance is reduced and current variations are suppressed. By opposing the switching transient current flowing from ceramic capacitor 7 to each semiconductor device between layers, inductance is reduced and the transient current supplied from capacitor 8 can be suppressed.

[0041] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0042] (1) A power conversion device 1 includes a wiring substrate 13 having a plurality of wiring layers, in which a plurality of upper arm semiconductor elements 4 and a plurality of lower arm semiconductor elements 5 are connected in parallel, and the plurality of wiring layers include positive wiring 2 extending along the arrangement direction of the plurality of upper arm semiconductor elements 4, negative wiring 3 extending along the arrangement direction of the plurality of lower arm semiconductor elements 5, and output wiring 6 connecting the plurality of upper arm semiconductor elements 4 and the plurality of lower arm semiconductor elements 5. The positive wiring 2 and the negative wiring 3 form a first positive / negative wiring pair 13a that are arranged in parallel and stacked with respect to the output wiring 6, and a second positive / negative wiring pair 13b that are arranged stacked with respect to each other. This makes it possible to provide a power conversion device that achieves both low inductance and equal inductance.

[0043] (2) The capacitor 8 is disposed on one side of the wiring board 13 and is electrically connected to the second positive and negative wiring pair 13b, and the second positive and negative wiring pair 13b is formed along an extension direction perpendicular to the one side of the wiring board 13, and the cross-sectional area in the direction perpendicular to the extension direction decreases the farther away from the capacitor 8. This makes it possible to adjust the balance of the current densities on the DC side and the AC side, uniformize the current densities of the wiring, and suppress local temperature increases in the wiring board 13.

[0044] (3) The output terminal 6a is disposed on the other side of the wiring board 13 opposite to the one side and electrically connected to the output wiring 6, and the output wiring 6 is formed along an extension direction perpendicular to the other side of the wiring board 13, and the cross-sectional area of ​​the output wiring 6 in the direction perpendicular to the extension direction becomes smaller the farther away from the output terminal 6a. This makes it possible to adjust the balance of the current density on the DC side and the AC side, uniformize the current density of each wiring, and suppress local temperature rises in the wiring board 13.

[0045] (4) On the outermost layer of the wiring board 13, the positive electrode wiring 2 and the negative electrode wiring 3 are formed in parallel, and a second capacitor is disposed between the positive electrode wiring 2 and the negative electrode wiring 3. This configuration suppresses variations in wiring inductance.

[0046] (5) The drain terminals and source terminals, or collector terminals and emitter terminals, of the plurality of upper arm semiconductor elements 4 and the plurality of lower arm semiconductor elements 5 are alternately arranged and connected to the wiring substrate 13. In this way, the configuration of the present invention can be realized in either the IGBT or MOSFET system.

[0047] (6) The wiring board 13 has a plurality of wiring layers between the arrangement of the plurality of upper arm semiconductor elements 4 and the plurality of lower arm semiconductor elements 5. This makes it possible to achieve low inductance.

[0048] (7) The wiring board 13 has through holes 9 for electrically connecting the first positive and negative wiring pair 13a and the second positive and negative wiring pair 13b, and a plurality of through holes 9 are formed along the arrangement direction of the upper arm semiconductor elements 4 and the lower arm semiconductor elements 5, and connect the positive wirings 2 and the negative wirings 3 of the first positive and negative wiring pair 13a and the second positive and negative wiring pair 13b of the wiring board 13. This reduces electrical resistance and reduces heat generation in the positive wirings 2 and the negative wirings 3.

[0049] The present invention is not limited to the above-described embodiments, and various modifications and combinations of other configurations are possible without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiments, and includes those in which some of the configurations are omitted.

[0050] REFERENCE SIGNS LIST 1 Power conversion device 2 Positive electrode wiring 3 Negative electrode wiring 4 Upper arm semiconductor element 5 Lower arm semiconductor element 6 Output wiring 6a Output terminal 7 Ceramic capacitor 8 Capacitor 9 Interlayer connection (through hole) 10 Control terminal 11 High voltage side terminal for main circuit (lower arm semiconductor element) 11a Low voltage side terminal for main circuit (lower arm semiconductor element) 12 High voltage side terminal for main circuit (upper arm semiconductor element) 12a Low voltage side terminal for main circuit (upper arm semiconductor element) 13 Wiring board 13a First positive and negative electrode wiring pair 13b Second positive and negative electrode wiring pair

Claims

1. A power conversion device comprising a wiring board having a plurality of wiring layers on which a plurality of upper arm semiconductor elements and a plurality of lower arm semiconductor elements are connected in parallel, the plurality of wiring layers including positive wiring extending along the arrangement direction of the plurality of upper arm semiconductor elements, negative wiring extending along the arrangement direction of the plurality of lower arm semiconductor elements, and output wiring connecting the plurality of upper arm semiconductor elements and the plurality of lower arm semiconductor elements, the positive wiring and the negative wiring forming a first pair of positive and negative wiring arranged in parallel and stacked on the output wiring, and a second pair of positive and negative wiring arranged stacked on top of each other.

2. A power conversion device as claimed in claim 1, further comprising a capacitor arranged on one side of the wiring board and electrically connected to the second positive and negative wiring pair, the second positive and negative wiring pair being formed along an extension direction perpendicular to the one side of the wiring board, and the farther away from the capacitor the position of the second positive and negative wiring pair is, the smaller the cross-sectional area in the direction perpendicular to the extension direction becomes.

3. A power conversion device as claimed in claim 2, comprising an output terminal arranged on the other side of the wiring board opposite to the one side and electrically connected to the output wiring, the output wiring being formed along an extension direction perpendicular to the other side of the wiring board, and the farther away from the output terminal the output wiring is, the smaller its cross-sectional area in a direction perpendicular to the extension direction becomes.

4. A power conversion device according to claim 1, wherein the positive wiring and the negative wiring are formed in parallel on the outermost layer of the wiring board, and a second capacitor is disposed between the positive wiring and the negative wiring.

5. A power conversion device as claimed in claim 1, wherein the drain terminals and source terminals, or collector terminals and emitter terminals, of the plurality of upper arm semiconductor elements and the plurality of lower arm semiconductor elements are alternately arranged and connected to the wiring board.

6. A power conversion device according to claim 4, wherein the wiring board has the plurality of wiring layers between an arrangement of the plurality of upper arm semiconductor elements and the plurality of lower arm semiconductor elements.

7. A power conversion device as claimed in claim 1, wherein the wiring board has through holes for electrically connecting the first pair of positive and negative wiring and the second pair of positive and negative wiring, the through holes being formed in plurality along the arrangement direction of the upper arm semiconductor elements and the lower arm semiconductor elements, and connecting the positive wires of the first pair of positive and negative wiring and the negative wires of the second pair of positive and negative wiring of the wiring board together.

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