Optoelectronic device with reflector structure and method for manufacturing the optoelectronic device

Abstract

The invention concerns an optoelectronic device comprising a semiconductor layer stack of at least a first layer of a first conductivity type, a second layer of a second conductivity type as well as an active region between the first and second layer, the semiconductor layer stack comprising first side surfaces connecting a bottom surface and a top surface. The optoelectronic device further comprises a bottom contact element arranged on the bottom surface, a dielectric layer arranged on the first side surfaces and in particular extending partially onto the bottom surface, and a reflective contact layer arranged on the dielectric layer electrically contacting the bottom contact element. The dielectric layer thereby comprises second side surfaces opposite the first side surfaces with the second side surfaces having at least in portions a different angle relative to the bottom surface than the first side surfaces.

Description

[0001] OPTOELECTRONIC DEVICE WITH REFLECTOR STRUCTURE AND METHOD FOR MANUFACTURING THE OPTOELECTRONIC DEVICE

[0002] The present application claims priority from German patent application DE 10 2023 127 202 . 0 filed on October 05 , 2023 , the disclosure of which is incorporated by way for reference in its entirety .

[0003] The present invention concerns a method for manufacturing an optoelectronic device , in particular p-LED, that are decoupled in their electrical and optical properties and manufactured by self-aligning processes as well as an optoelectronic device .

[0004] BACKGROUND

[0005] In order to increase the external quantum efficiency ( EQE ) of for example p-LEDs , or more general light emitting nanostructures , one can engineer the geometry, shape and surroundings (passivation, reflective mirror , ...) of the p-LEDs in a way that the light extraction efficiency (LEE ) in a specific solid angle is maximized . Apart from the LEE the internal quantum efficiency ( IQE ) is as important , where a main loss factor originates from non-radiative recombination of charge carriers within the p-LED .

[0006] Plasma etching is a common and standard process for pixel etching ( etching through the active region and physical separation of individual pixels ) , but introduces plasma damage to the surface and underlying layers dependent on the specific process and parameters used . Plasma damage in this case means the creation of defect centres in the crystal lattice caused by Ion bombardment . Especially for small pixels such as for the case of p-LEDs with a high surf ace-to-volume ratio , in particular a high ratio of the exposed active region surface on the pixel' s sidewall vs . the total active region volume , this is a maj or challenge . Defects created on the surface and below of the active region - which is exposed during and after pixel etching by means of plasma etching - act as non-radiative recombination channels and dramatically reduce the IQE of the p-LED leading to a bad overall performance . The same applies to laser devices such as vertical-cavity surfaceemitting lasers (VCSEL ) and edge-emitting lasers . They also face a high surf ace-to-volume ratio . In addition to p-LEDs , some of the etched side surfaces of the lasers are within the light path of the light to be emitted and therefor have to be optically perfect . This can mean that the etched side surface ( s ) need to comprise a lower / no absorption resulting in higher COD-levels .

[0007] A common approach to remove plasma damage is a subsequent so-called defect etching step, where defects are reduced or even removed while not creating new defects . Therefore , usually wet chemistry is used, mostly aqueous KOH . The KOH wet etching behaviour of GaN is highly anisotropic due to the different etch rates in different crystallographic directions . Therefore , by starting from a certain p- LED shape formed by plasma etching e . g . , with inclined and smooth side surfaces , the defect etching will change the shape of the p-LED completely . This includes the formation of micro crystal facets with different orientations ( surface patterning ) as well as the loss of the overall shape and / or the smoothness . Smooth vertical sidewalls can be etched with KOH for long etching times due to the specific crystal plane etching selectivity, however it is not possible to preserve at the same time inclined side surfaces with a smooth surface . However , inclined side surfaces in particular may be preferred in order to obtain a desired light extraction / far field properties of the light generated in the p-LED in combination with an appropriately applied mirror structure .

[0008] A further challenge in the manufacturing process of p-LEDs in the order of a few pm and smaller is the alignment accuracy in the lithography process for electrically contacting the p-LEDs . Common processes have a placement / contacting accuracy in the order of ± 200 nm, which is far from what is required . This can result in varying brightness and far- field shapes from one p-LED to another . Furthermore , alignment errors of different layers used for the known processes add up , so that even small alignment errors lead to strongly asymmetrical p-LEDs in some cases . Thus with state-of-the-art lithography processes , alignment errors lead to problems with p-LED uniformity and asymmetry . This may not be a problem for p-LEDs on the order of a few tens of pm or larger structures allowing a higher tolerance , but it is crucial for p-LEDs a few pm and smaller in size and thus lower tolerances . Wave optical effects inside the pixel dominate the light extraction properties and are sensible to small changes in the geometry in the 10 nm regime .

[0009] It is an obj ect of the present application to provide an enhanced method for manufacturing an optoelectronic device and p-LED in particular , by means of which at least some of aforementioned problems can be overcome . It is further an obj ect to provide a respective optoelectronic device and in particular p-LED .

[0010] SUMMARY OF THE INVENTION

[0011] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0012] The idea of the inventors is a manufacturing of an optoelectronic device , for example a nitride-based micro-LED, that is decoupled in its electrical and optical properties and manufactured by self-aligning process ( es ) . A decoupling of the electrical and optical properties can be understood in this context in such a way that the problem of a reduced IQE can be solved detached from the problem of a reduced LEE by an appropriate design, in particular the design of a dielectric layer between the semiconductor stack and a reflector structure . In addition, process steps for the generation of the dielectric layer and for the generation of a contact element on the semiconductor layer stack are chosen and sequenced in such a way that they are selfaligning and thus placement inaccuracies do not or barely occur during their manufacture .

[0013] According to a first aspect , an optoelectronic device , in particular p-LED, is provided . The optoelectronic device comprises a semiconductor layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region between the first and second layer . The semiconductor layer stack comprises first side surfaces connecting a bottom surface and a top surface opposite the bottom surface .

[0014] The optoelectronic device further comprises a bottom contact element arranged on a bottom surface of the semiconductor layer stack electrically coupled to the second layer .

[0015] A dielectric layer is arranged on the first side surfaces and in particular also extends partially onto the bottom surface adj acent to the bottom contact element . Further a reflective contact layer is arranged on the dielectric layer covering the dielectric layer and electrically contacts the bottom contact element and thus the second layer . The dielectric layer thereby comprises second side surfaces opposite the first side surfaces with the second side surfaces having at least in portions a different angle relative to the bottom surface than the first side surfaces .

[0016] The first side surfaces having at least in portions a different angle relative to the bottom surface than the first side surfaces can in particular result from the dielectric layer being structured / treated after being disposed on the contour of the semiconductor layer stack . By means of only disposing the dielectric layer by for example sputtering , spinning, or spraying the dielectric layer would substantially follow the contour of the semiconductor layer stack with a substantially equal thickness and second side surfaces of the dielectric layer opposite the first side surfaces of the semiconductor layer stack would substantially have the same angle relative to the bottom surface . By however structuring / treating the dielectric layer to a specific need after being disposed on the contour of the semiconductor layer stack, the dielectric layer has at least in portions a different angle relative to the bottom surface than the first side surfaces .

[0017] In this way, a correspondingly desired contour for the reflective contact layer later placed on the dielectric layer can be achieved in order to increase the LEE of the device . At the same time , efforts to improve the shape / contour of the semiconductor layer stack to increase the LEE can be deferred and with regard to the semiconductor layer stack, the focus can be placed on improving the IQE .

[0018] The term "having at least in portions a different angle relative to the bottom surface" shall in this regard be understood in such that the first and opposing second surfaces comprise a different angle at least in one laterally opposing point . By latterly opposing it can in particular be understood opposing points of the first and second side surfaces that lay within a plane hat is parallel shifted with regard to the bottom surface . In case the surfaces or one of the surfaces is curved, a different angle shall in particular be regarded to the tangents which lie on the side surfaces at the laterally opposing points of the opposing side surfaces .

[0019] In some aspects , the semiconductor layer stack and in particular the first and second layer as well as the active region are of a nitride based semiconductor material system . For example , the semiconductor layer stack and in particular the first and second layer as well as the active region are of a gallium nitride ( GaN) semiconductor material system . For example , in case of nitride based semiconductor material systems , the creation of non-radiative recombination centres along etched side surface of the optoelectronic device can be very critical . However, the semiconductor layer stack can be of a different Epi structure as well .

[0020] The semiconductor layer stack comprises at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region between the first and second layer . The first layer can for example be a semiconductor layer that is p-doped, whereas the second layer can for example be a semiconductor layer that is n-doped . The two layers can thus form a pn- j unction with the active region arranged in-between . The active region can for example comprise a quantum well or multi quantum well structure , or can for example comprise quantum dots . According to some aspects , the reflective contact layer is reflective . By means of a reflective contact layer , the outcoupling efficiency and light directionality of the light emitted by the p-LED can for example be improved, as light generated in the active region gets reflected into a desired direction .

[0021] In some aspects , the bottom contact element comprises a transparent conductive oxide , such as for example indium tin oxide ( ITO ) , IZO or IGZO .

[0022] The proposed solution works for any nitride based p-LED shapes or more general light emitting nanostructures for example etched by plasma or grown by selective area growth with exposed active regions . Also , for laser devices like VCSELs or edge-emitting lasers the solution is very promising, as it could further be used to improve etched facets not only for electrical , but also for optical reasons .

[0023] In some aspects , the first side surfaces are substantially perpendicular with respect to the bottom surface . This can in particular result from a surface treating of pre-etched side surfaces using a wet etchant , for example KOH , thereby forming the etched first side surfaces . The KOH wet etching behaviour of for example GaN is highly anisotropic due to the different etch rates in different crystallographic directions . Therefore , by starting from a certain p- LED shape formed by for example plasma etching e . g . , a mesa shape with inclined side surfaces , the defect etching will change the shape of the p-LED resulting in substantially perpendicular first side surfaces with respect to the bottom surface . Smooth vertical sidewalls can be etched with KOH for long etching times due to the specific crystal plane etching selectivity and most of the non-radiative recombination channels generated during plasma etching of the semiconductor layer stack can be removed .

[0024] In some aspects , the dielectric layer comprises an increasing thickness in a lateral direction from the bottom surface to the top surface . The thickness may be constant or steadily increasing . In particular , the term thickness may be understood to mean the lateral distance between the opposing first and second side surfaces that increases from the bottom surface to the top surface .

[0025] In some aspects , at least portions of the second side surfaces are inclined with respect to the bottom surface and / or at least portions of the second side surfaces are curved . However, it is also possible that the second side surface is inclined or curved over the entire surface thereof , or that portions of the side surface are vertical or horizontal .

[0026] In some aspects , a circumference of the dielectric layer increases from the bottom surface to the top surface , in particular when viewed in a direction perpendicular to the bottom surface . The second surfaces of the dielectric layer can in particular form a parabolic, conical , or pyramidal surface surrounding the semiconductor layer stack .

[0027] In some aspects , the material of the semiconductor layer stack and the material of the dielectric layer can be index matched and in particular differs by no more than 0 . 1 . For example the dielectric layer can be of Nb2O5whereas the semiconductor layer stack can be of a GaN material system . By means of this , it can be achieved that light , generated within the semiconductor layer stack, is not or at least hardy reflected at the interface between the dielectric layer and the semiconductor layer stack . The light generated within the semiconductor layer stack can thus propagate through the dielectric layer and be reflected at the reflective contact layer arranged on the dielectric layer .

[0028] In some aspects , the material of the dielectric layer can have a different refractive index , in particular lower refractive index , compared to the material of the semiconductor layer stack . For example the dielectric layer can be of SiO2 whereas the semiconductor layer stack can be of a GaN material system . By means of this , it can be achieved that light , generated within the semiconductor layer stack is outcoupled ideally when the overall geometry is optimized with respect to internal wave optical effects . In some aspects , the material of the dielectric layer can comprise several layers of the same or different materials which can be deposited right one after the other or which can be applied after the underlying dielectric layer ( s ) have already been plasma etched / structured . By means of this , already the dielectric layers can form a mirror for the optoelectronic device .

[0029] In some aspects , the optoelectronic device further comprises a passivation layer at least arranged between the first side surfaces and the dielectric layer . In particular a passivation layer for chemical surface passivation can be applied at least to the first side surfaces . The passivation layer can be applied by Atomic Layer Deposition, CVD, PECVD or Sputtering, ( e . g . ALD A12O3, ALD AIN, SiO2) with for example a thickness of a single monolayer up to hundreds of nanometres . Also other passivation methods are thinkable like hydrogen passivation, 02ashing , plasma exposure or a combination thereof . The passivation layer can in particular be arranged all over between the semiconductor layer stack and the dielectric layer .

[0030] In some aspects , the first layer and in particular an upper portion of the first layer forms the top surface .

[0031] In some aspects , the optoelectronic device further comprises an optical element arranged on the top surface or further comprises an optical element formed of the first layer . For example a lens or p-lens can be arranged on the top surface or the first layer can be structured such that it forms an optical element forming the top surface of the semiconductor layer stack .

[0032] In some aspects , the optoelectronic device further comprises a top contact element electrically coupled to the first layer, wherein optionally the top contact element is of a reflective material and surrounds the semiconductor layer stack in a circumferential direction .

[0033] The optoelectronic device can in particular comprise a reflective structure surrounding the semiconductor layer stack in a circumferential direction, wherein the reflective structure exposes a portion of the top surface and extends from a level below the top surface to a level above the top surface . The reflective structure in particular provides a reflector surrounding the semiconductor layer stack in circumferential direction, which exposes a portion of the top surface and extends from a level below the top surface to a level above the top surface to reflect light generated within the semiconductor layer stack and in particular within the active region of the semiconductor layer stack into a desired direction . The reflective structure in addition can be used to electrically contact the first layer, on / in which the reflective structure is arranged .

[0034] According to some aspects , the reflective structure together with the reflective contact layer and / or the bottom contact element forms a mirror , for example parabolic-like or parabolic mirror , for light generated in the semiconductor layer stack . By means of the combined mirror , light generated within the semiconductor layer stack can be outcoupled of the optoelectronic device in an enhanced way, as well as a focusing of the light into a smaller solid angle is possible .

[0035] According to some aspects , the reflective structure is a metallic grid surrounding the semiconductor layer stack in the circumferential direction . The reflective structure can in particular be in form of a metallic grid comprising an element surrounding the semiconductor layer stack in the circumferential direction and comprising bars or residues of bars connecting elements surrounding the semiconductor layer stack in the circumferential direction . Due to its conductivity, the metallic grid can together with the bottom contact element and the reflective contact layer in particular be used to electrically connect the semiconductor layer stack to a current source .

[0036] According to some aspects , the reflective contact layer comprises a through contact through the dielectric layer electrically contacting the bottom contact element . The through contact can in particular be substantially centred with respect to the semiconductor layer stack . This can in particular result from a respective self-aligned manufacturing of the through contact , which is explained later on . According to some aspects , the dielectric layer and in particular the centre of gravity of the dielectric layer with regard to the lateral direction is substantially centred with respect to the semiconductor layer stack , n particular the second side surfaces can be arranged symmetrically around the semiconductor layer stack .

[0037] According to some aspects , the optoelectronic device further comprises an intermediate layer arranged on the reflective contact layer covering the reflective contact layer . The intermediate layer can in particular form a substantially even surface on a surface opposite the reflective contact layer . On the intermediate layer and in particular on the substantially even surface of the intermediate layer, in addition a carrier layer can be arranged . The carrier layer can for example be or comprise an integrated circuit for controlling the optoelectronic device and can thus for example be electrically connected to the reflective contact layer by means of through contact ( s ) through the intermediate layer .

[0038] According to a further aspect , a method for manufacturing an optoelectronic device is provided . The optoelectronic device can for example be a light emitting device comprising one or more light emitting components such as a small LED or pLED configured to emit light when powered and can in particular be an optoelectronic device according to one or some of aforementioned aspects .

[0039] The method comprises the steps :

[0040] Providing a semiconductor layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region between the first and second layer ;

[0041] Structuring the semiconductor layer stack such that at least a first portion of the semiconductor layer stack is retained and at least a second portion of the semiconductor layer stack adj acent to the first portion is removed, thereby forming an etched first side surface of the first portion comprising the first layer , the second layer and the active region and extending from a bottom surface of the semiconductor layer stack into the direction of a top surface of the semiconductor layer stack opposite the bottom surface ; Providing a dielectric layer at least on the first side surface ;

[0042] Structuring the dielectric layer such that at least a first portion of the dielectric layer is retained and at least a second portion of the dielectric layer adj acent to the first portion is removed, thereby forming an etched second side surface of the dielectric layer; and

[0043] Providing a reflective contact layer on the dielectric layer electrically contacting the semiconductor layer stack .

[0044] The second side surface thereby has at least in portions a different angle relative to the bottom surface than the first side surface .

[0045] The steps of providing and structuring the dielectric layer can thereby in particular be due to the underlying structure self-aligning process steps . The step of providing the dielectric layer can in particular comprise a sputtering of the material of the dielectric layer such that the dielectric material layer so that the dielectric material layer substantially replicates the underlying contour with a substantially constant thickness . The step of structuring the dielectric layer can then in particular comprise providing a resist coating on the dielectric material layer as well as a development of the resist coating such that the resist coating as well substantially replicates the underlying contour with a substantially constant thickness . By now hardbaking the resist coating the "liquidised" resist coating accumulates and aligns in a self-aligned way with the underlying structure and by adj usting the thickness of the dielectric material layer, the properties of the resist coating , the time and temperature of the hardbaking and adj usted parameters of a subsequent plasma etching process , the dielectric layer can be structured in a desired way and in a self-aligned manner .

[0046] The reflective contact layer may further be provided such that an electrical contact between the semiconductor layer stack and the reflective contact layer is provided or prepared in a self-aligned manner at a time before the actual step of applying the reflective contact layer, so that the reflective contact layer can subsequently only be applied such that it is centrally adj acent to the semiconductor layer stack or a bottom contact element arranged on the bottom surface of the semiconductor layer stack .

[0047] For example , a centred sacrificial structure can already be provided on the semiconductor layer stack or on a bottom contact element arranged on the bottom surface of the semiconductor layer stack before providing and structuring the dielectric layer which can then be removed and the resulting opening can subsequently be filled by the reflective contact layer resulting in a centred electrical contact without large further efforts . Another possibility is to already provide a portion of the reflective contact layer or another conductive material on the semiconductor layer stack or on a bottom contact element arranged on the bottom surface of the semiconductor layer stack before providing and structuring the dielectric layer, which during the step of structuring the dielectric layer can then be exposed and subsequently be contacted by the reflective contact layer resulting in a centred electrical contact without large further efforts .

[0048] According to some aspects , the step of structuring the semiconductor layer stack comprises a step of surface treating pre-etched side surfaces using a wet etchant , thereby forming the etched first side surface , wherein the resulting first side surface is substantially perpendicular with respect to the bottom surface . The surface treating of the pre-etched side surfaces can in particular be a step using a wet etchant , for example KOH, thereby forming the etched first side surfaces . The KOH wet etching behaviour of for example GaN is highly anisotropic due to the different etch rates in different crystallographic directions . Therefore , by starting from a certain p- LED shape formed by for example plasma etching e . g . , a mesa shape with inclined side surfaces , the defect etching will change the shape of the p-LED resulting in substantially perpendicular first side surfaces with respect to the bottom surface . Smooth vertical sidewalls can be etched with KOH for long etching times due to the specific crystal plane etching selectivity and most of the non-radiative recombination channels generated during plasma etching of the semiconductor layer stack can be removed . According to some aspects , the method further comprises a step of providing a bottom contact layer on the second layer . The bottom contact element can in particular comprise a transparent conductive oxide , such as for example indium tin oxide ( ITO ) , IZO or IGZO . The bottom contact element can in particular be provided on the second layer before the step of structuring the semiconductor layer stack and can be structured together with the semiconductor layer stack in a desired manner . The bottom contact element can however also be provided on the bottom surface of the already structured semiconductor layer stack .

[0049] According to some aspects , the method further comprises a step of providing a first sacrificial layer on the second layer or on the bottom contact layer . The first sacrificial layer can in particular be provided on the second layer or on the bottom contact layer before the step of structuring the semiconductor layer stack and can be structured together with the semiconductor layer stack in a desired manner . The first sacrificial layer can however also be provided on the bottom surface or on the bottom contact layer of the already structured semiconductor layer stack .

[0050] According to some aspects , the method further comprises a step of providing a second sacrificial layer on the first sacrificial layer . The second sacrificial layer can in particular be provided on the first sacrificial layer before the step of structuring the semiconductor layer stack and can be structured together with the semiconductor layer stack in a desired manner . The second sacrificial layer can however also be provided on the first sacrificial layer of the already structured semiconductor layer stack .

[0051] According to some aspects , the method further comprises a step of providing a conductive layer on the second layer or on the bottom contact layer . The conductive layer can in particular be provided on the second layer or on the bottom contact layer before the step of structuring the semiconductor layer stack and can be structured together with the semiconductor layer stack in a desired manner . The conductive layer can however also be provided on the bottom surface or on the bottom contact layer of the already structured semiconductor layer stack . The conductive layer can in particular be a later portion of the reflective contact layer .

[0052] According to some aspects , the method further comprises a step of structuring the bottom contact layer; and / or a step of structuring the first sacrificial layer ; and / or a step of structuring the second sacrificial layer; and / or a step of structuring the conductive layer; and / or a step of removing the first and / or second sacrificial layer .

[0053] Aforementioned steps can in particular also comprise one or several sub steps which can in addition be combined with any other steps or sub steps mentioned . Further the named materials of the bottom contact layer, the first sacrificial layer , the second sacrificial layer and the conductive layer can together or in parts be structured in a common step or pre-structured in a common step .

[0054] The structuring steps can for example be performed by etching steps with an etchant which can in particular etch a respective one of the named materials but is selective / non etching against the other materials and / or the material of the semiconductor layer stack . In particular an etching of the first sacrificial layer and / or the bottom contact element and / or the conductive layer can be performed such that the respective material is etched only from lateral side surfaces , thinning the material uniformly at the side surfaces , resulting in a centred residue of the material when finishing the etching process . An etching of a top and bottom side of the respective material can at the same time be prevented by covering the respective material by one of the adj acent layers which is not etched by the etchant used . In case the respective material is already centred on the bottom surface of the structured semiconductor layer stack such a process is selfaligning providing a sacrificial structure / opening for the later provided reflective contact layer or through contact through the dielectric layer or already providing a conductive portion of the reflective contact through the dielectric layer .

[0055] By means of the structuring of in particular the bottom contact element , the bottom contact element can be reduced in size such that it covers only a portion of the bottom surface . By this , a current confinement can be achieved when applying a voltage to the semiconductor layer stack via the bottom contact element . This can in addition to for example a surface treatment of the first side surfaces increase the IQE of the optoelectronic device .

[0056] According to some aspects , the method further comprises a step of providing a passivation layer at least on the first side surface . In particular a passivation layer for chemical surface passivation can be applied at least to the first side surface . The passivation layer can be applied by Atomic Layer Deposition, CVD, PECVD or Sputtering , ( e . g . ALD A12O3, ALD AIN, SiO2) with for example a thickness of a single monolayer up to hundreds of nanometres . Also other passivation methods are thinkable like hydrogen passivation, 02ashing , plasma exposure or a combination thereof . The passivation layer can in particular be arranged all over the first side surfaces of the semiconductor layer stack and / or exposed portions of the bottom surface and / or the bottom contact element and / or exposed portions of the first and / or second sacrificial layer and / or exposed portions of the conductive layer .

[0057] According to some aspects , the step of structuring the dielectric layer comprises : a step of providing a mask, for example resist coating , on the dielectric layer ; and / or a step of hard baking the mask on the dielectric layer ; and / or a step of plasma etching the dielectric layer , thereby forming the etched second side surface of the dielectric layer .

[0058] According to some aspects , the method further comprises a step of providing an optical element on the top surface or a step of providing an optical element formed of the first layer . For example a lens or p- lens can be arranged on the top surface or the first layer can be structured such that it forms an optical element forming the top surface of the semiconductor layer stack .

[0059] According to some aspects , the method further comprises a step of providing a top contact element electrically coupled to the first layer, wherein optionally the top contact element is of a reflective material and surrounds the first portion of the semiconductor layer stack in a circumferential direction .

[0060] It should be understood that the method can in particular be a method for manufacturing an optoelectronic device according to some of aforementioned aspects and that the described optoelectronic device can be an optoelectronic device manufactured according to some of aforementioned aspects . It is therefore to be understood that all aspects mentioned with respect to the optoelectronic device are also applicable to the method for manufacturing the optoelectronic device and vice versa .

[0061] SHORT DESCRIPTION OF THE DRAWINGS

[0062] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0063] Fig . 1A and IB each show a cross sectional view of an embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ; and

[0064] Fig . 2A to 11B show steps of embodiments for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle .

[0065] DETAILED DESCRIPTION

[0066] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .

[0067] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0068] Figure 1A and IB show each a cross sectional view of an embodiment of an optoelectronic device 1 in accordance with some aspects of the proposed principle . The optoelectronic device 1 comprises a semiconductor layer stack 2 of a first layer 3 of a first conductivity type , a second layer 4 of a second conductivity type as well as an active region 5 between the first and second layer 3 , 4 . The semiconductor layer stack 2 is formed such that it comprises a top surface 8 , a bottom surface 7 opposite the top surface 8 and first side surfaces 6 extending from the bottom surface 7 into the direction of the top surface 8 . The first side surfaces 6 thereby comprise portions , in particular side portions of the first layer 3 , the second layer 4 and the active region 5 .

[0069] In the embodiments shown, the semiconductor layer stack 2 is etched to have first side surfaces 6 extending from the bottom surface 7 into the direction of the top surface 8 down to a continuous residual portion of the first layer 3 . The first side surfaces can however regarding the manufacturing of the optoelectronic device 1 extend from the bottom surface 7 all the way to the top surface 8 such that the continuous residual portion of the first layer 3 shown is not present .

[0070] The optoelectronic device 1 further comprises a bottom contact element

[0071] 9 of for example ITO arranged on the bottom surface 7 on the second layer 4 . The bottom contact element 9 in the embodiments shown covers only a central portion of the bottom surface 7 . By this , a current confinement can be achieved when applying a voltage to the semiconductor layer stack 2 via the bottom contact element 9 . This can in addition to for example a surface treatment of the first side surfaces 6 increase the IQE of the optoelectronic device 1 . The bottom contact element 9 can however also cover the whole bottom surface 7 .

[0072] In addition, the optoelectronic device 1 comprises a passivation layer 13 grown on and covering the first side surfaces 6 , the continuous residual portion of the first layer 3 , exposed portions of the bottom surface 7 , as well as the exposed portions of the bottom contact element 9 . The passivation layer 13 can be applied for chemical surface passivation to at least the first side surfaces 6 . The passivation layer 13 can be applied by Atomic Layer Deposition or Sputtering , ( e . g . ALD A12O3, ALD AIN, SiO2) with for example a thickness of a single monolayer up to hundreds of nanometers . Also other passivation methods are thinkable like hydrogen passivation, or a combination of A12O3for chemical passivation and Nb2O5for providing desired optical properties .

[0073] On the semiconductor layer stack 2 and in particular on the passivation layer 13 , a dielectric layer 10 is arranged covering the passivation layer 13 . The dielectric layer 10 follows the structure of the underlying semiconductor layer stack 2 and is structured such that it comprises second side surfaces 12 opposite the first side surfaces 6 , which have at least in portions a different angle ( o2) relative to the bottom surface 7 than an angle (eg ) between the first side surfaces 6 and the bottom surface 7 . In particular the dielectric layer 10 is structured such that its thickness t in a lateral direction 1 increases from the bottom surface 7 into the direction of the top surface 7 . By this a surface can be provided in a desired shape with a desired angle or curvature on which a reflective contact layer 12 is then applied to provide a bottom side reflector for the optoelectronic device 1 with desired optical properties .

[0074] Said reflective contact layer 12 is arranged on the dielectric layer 10 covering in particular the second side surfaces 12 and comprising a though contact 16 through the dielectric layer 10 electrically contacting the bottom contact element 9 . The reflective contact layer 12 can be a metallic layer following the underlying structure and forming a bottom side reflector for the optoelectronic device 1 to guide the light generated within the semiconductor layer stack into a desired direction and with a desired beam profile .

[0075] The optoelectronic device 1 further comprises an intermediate layer 17 arranged on the reflective contact layer 11 covering the reflective contact layer 11 . The intermediate layer 17 in particular forms a substantially even surface on a surface opposite the reflective contact layer 11 . On the intermediate layer 17 on the substantially even surface of the intermediate layer 17 , a carrier layer 18 is arranged . The carrier layer 18 can for example be or comprise an integrated circuit for controlling the optoelectronic device 1 and can thus for example be electrically connected ( not shown ) to the reflective contact layer 11 by means of through contact ( s ) through the intermediate layer 17 .

[0076] On the other side of the optoelectronic device 1 , the optoelectronic device 1 comprises an optical element 16 formed of the first layer 3 . The first layer 3 can therefore be structured to provide an optical element 14 like for example a lens which top surface forms the top surface 8 of the semiconductor layer stack 2 . As an alternative , a lens or p-lens can be arranged as an optical element 14 on a substantially even and not structured top surface 8 of the semiconductor layer stack 2 .

[0077] The optoelectronic device 1 further comprises a top contact element 15 electrically coupled to the first layer 3 , wherein the top contact element 15 is of a reflective material forming in addition a reflective structure and surrounds the semiconductor layer stack 2 and in particular the optical element 14 in a circumferential direction U .

[0078] The top contact element 15 exposes a portion of the top surface 8 and in particular the optical element 14 and extends from a level below the top surface 8 to a level above the top surface 8 . In the embodiments shown, the top contact element 15 is partially embedded in the dielectric layer 10 but only until a depth to not be in contact with the reflective contact layer 11 to avoid a short within the optoelectronic device 1 . The arrangement of the top contact element 15 in such a way prevents a leakage path of light through the continuous residual portion of the first layer 3 out of the optoelectronic device 1 in an undesired direction . The top contact element 15 provides a reflector surrounding the optical element 14 in the circumferential direction U, to reflect light generated within the semiconductor layer stack 2 into a desired direction . The top contact element 15 in addition can be used to electrically contact the first layer 3 , on / in which the reflective structure is arranged .

[0079] The top contact element 15 together with the reflective contact layer 11 forms a mirror, in particular parabolic-like or parabolic mirror , for light generated in the semiconductor layer stack 2 . By means of the combined mirror, light generated within the semiconductor layer stack 2 can be outcoupled of the optoelectronic device 1 in an enhanced way, as well as a focusing of the light into a smaller solid angle is possible .

[0080] The top contact element 15 can be a metallic grid surrounding the optical element 14 in the circumferential direction U . The top contact element 15 can in particular be in form of a metallic grid comprising an element surrounding the optical element 14 in the circumferential direction U and comprising bars or residues of bars connecting elements surrounding the optical element 14 in the circumferential direction U . Due to its conductivity, the metallic grid can together with the bottom contact element 9 and the reflective contact layer 11 be used to electrically connect the semiconductor layer stack 2 to a current source .

[0081] The optoelectronic device 1 of Figure 1A compared to the optoelectronic device 1 of Figure IB comprises first side surfaces 6 being substantially perpendicular with respect to the bottom surface 7 . This can in particular result from a surface treatment of pre-etched side surfaces of the semiconductor layer stack 2 using a wet etchant , for example KOH , thereby forming the etched first side surfaces 6 . By starting from a certain semiconductor layer stack 2 shape formed by for example plasma etching e . g . , a mesa shape with inclined side surfaces , the surface treatment will change the shape of the semiconductor layer stack 2 resulting in substantially perpendicular first side surfaces 6 with respect to the bottom surface 7 . Such vertical sidewalls can be etched with KOH for long etching times due to the specific crystal plane etching selectivity and most of the non- radiative recombination channels generated during plasma etching of the semiconductor layer stack 2 can be removed . Even though, the vertical first side surfaces 6 provide a comparable bad external emission characteristic for the optoelectronic device 1 , the IQE of the optoelectronic device 1 can be very much improved by means of such a surface treatment . For now improving the external emission characteristic of the optoelectronic device 1 and thus the LEE of optoelectronic device 1 the structured dielectric layer 10 comprising the second side surfaces 12 with the reflective contact layer 11 arranged on is provided, to guide and reflect light generated within the semiconductor layer stack 2 into a desired direction . The dielectric layer 10 thereby comprises a substantially index matched material with regard to the semiconductor layer stack 2 to avoid reflections at the interface between the semiconductor layer stack 2 and the dielectric layer 10 .

[0082] The optoelectronic device 1 of Figure IB on the other hand comprises first side surfaces 6 being inclined with respect to the bottom surface 7 . However still the second side surfaces 12 have at least in portions a different angle ( op ) relative to the bottom surface 7 than the angle (eg ) between the first side surfaces 6 and the bottom surface 7 . Such an embodiment can result from the fact that the shape / angle of the first side surfaces 6 is optimized to increase the IQE of the optoelectronic device 1 and the shape / angle of the second side surfaces 12 is optimized to increase the LEE of the optoelectronic device 1 . The optimization of the shape / angle of the first side surfaces 6 may thereby for example be done by means of any other method than etching by means of KOH but for example regrowth or other techniques but may be such that an optimal LEE can not be achieved with the resulting shape / angle . The decoupling of the two optimization possibilities is thus beneficial , as the optimization of the LEE of the optoelectronic device can be approached in a detached way via the shape / angle of the second side surfaces 12 .

[0083] Figures 2A to 2G show exemplary steps of a method for manufacturing an optoelectronic device according to some aspects of the proposed principle . Figures 2H to 2 J on the other hand show alternative steps to the steps shown in Figures 2E to 2G .

[0084] As shown in Figure 2A, in a first step, a semiconductor layer stack 2 of at least a first layer 3 of a first conductivity type , a second layer 4 of a second conductivity type as well as an active region 5 between the first and second layer 3 , 4 is provided . The semiconductor layer stack 2 is arranged on a growth substrate 26 and a bottom contact layer 9 of for example ITO is arranged on the semiconductor layer stack 2 . In addition, a first sacrificial layer 23 and a second sacrificial layer 24 is provided on the bottom contact layer 9 in the given order .

[0085] As shown in Figure 2B , a structured mas k 27 is then provided on the upper most layer to pixelate the semiconductor layer stack 2 with all layers on top in a subsequent step by means of plasma etching as shown in Figure 2C . The plasma etching results in etched side surfaces of a first portion 19 of the semiconductor layer stack 2 when removing an adj acent second portion 20 of the semiconductor layer stack 2 . The plasma etching is performed from an uppermost surface into the direction of the growth substrate 26 but stops well before reaching the growth substrate 26 within the first layer 3 . Thus , a continuous residual portion of the first layer 3 remains on the growth substrate 26 . The plasma etching introduces damage on the etched side surfaces and also below the side surfaces . This in particular in the active region 5 is a maj or problem, since it creates non-radiative recombination channels for charge carriers along the side surfaces leading to a low EQE of the final optoelectronic device .

[0086] The contact layer 7 and / or the first and / or second sacrificial layer 23 , 24 can however also be arranged on the first portion 19 after the step of plasma etching or at an even later point of time . Due to the etching step or due to a later provision of the layers on the first portion 19 , the layers on the bottom surface covering the whole bottom surface are due to its nature centred with respect to the first portion and thus aligned with the first portion in a self-aligning manner .

[0087] To remove the damages , the etched side surfaces are surface treated as shown in Figure 2D, using a wet chemical etching process , using for example KOH , thereby forming the etched first side surfaces 6 . By starting from a semiconductor layer stack 2 shape as shown in figure 2C formed by for example plasma etching e . g . , the surface treatment changes the shape of the semiconductor layer stack 2 resulting in substantially perpendicular first side surfaces 6 with respect to the bottom surface 7 . Such vertical sidewalls can be etched with KOH for long etching times due to the specific crystal plane etching selectivity and most of the non-radiative recombination channels generated during plasma etching of the semiconductor layer stack 2 can be removed . The structured mas k 27 is then or before the step of surface treatment removed .

[0088] Figures 2E to 2G show a first embodiment of steps of a method for structuring the bottom contact element 9 as well as the first sacrificial layer 23 . Figures 2H to 2 J on the other hand show a further embodiment of steps of a method for structuring the bottom contact element 9 as well as the first sacrificial layer 23 . The structuring steps are thereby in particular etching steps , etching a respective material to be etched but retaining other materials not to be etched . The order and arrangements of layers is thereby chosen such that a layer to be etched is sandwiched between two layers not to be etched such that a respective etchant etches the layer to be etched from its side surfaces uniformly into the direction of its centre . The explained etching steps are therefore in a self-aligned manner in terms of a residue of the layer to be etched being always centred with regard to the first portion .

[0089] As shown in Figure 2E and 2H, the first sacrificial layer 23 is etched in the explained way in a first step . The material of the first sacrificial layer 23 and the material of the other layers as well as a first etchant is thereby chosen such that by means of the first etchant only the first sacrificial layer 23 is etched but not the other layers or the first sacrificial layer 23 is etched at least a lot faster than the other layers . A possible material combination can for example be :

[0090] Growth substrate 26 of Saphire / GaN;

[0091] Semiconductor layer stack 2 of GaN;

[0092] Bottom contact layer 9 of ITO ;

[0093] First sacrificial layer 23 of SiO2;

[0094] Second sacrificial layer 24 of NiN; and HF vaporor buffered HF as first etchant .

[0095] Regarding the etching time , the depth of etching can be controlled as comparably shown in Figure 2E and 2H .

[0096] In a following step as shown in Figure 2 F and 21 , the bottom contact layer 9 is etched in the explained way . A second etchant is thereby chosen such that by means of the second etchant only the bottom contact layer 9 is etched but not the other layers or the bottom contact layer 9 is etched at least a lot faster than the other layers . A possible second etchant with regard to above mentioned exemplary material combination can for example be FeCl3. Again, regarding the etching time , the depth of etching can be controlled as desired .

[0097] The second sacrificial layer 24 is then removed as shown in Figures 2G and 2J . The resulting structure each comprises a centred bottom contact element 9 on the bottom surface 7 as well as a differently dimensioned but each centred residual portion of the first sacrificial layer 23 . The sacrificial layer 23 can now act as a spacer which is removed at a later point of time to receive a perfectly centred and self-aligned opening above the bottom contact element 9 to electrically contact the bottom contact element 9 by filling the openening with a conductive material . A smaller residue of the second sacrificial layer 23 may thereby be beneficial , as when removed and replaced by a conductive material , a current confinement can be further increased into the semiconductor layer stack 2 .

[0098] To receive the structure shown in Figure 21 and 2J respectively, it can also be conceivable to perform a third etching step similar to the first etching step, to structure the first sacrificial layer 23 another time to receive a smaller residue .

[0099] In a further embodiment , the first sacrificial layer can also be formed by a conductive layer, not acting as a spacer to be removed at a later point of time but to already use it as a portion of a later provided contact element to contact the semiconductor layer stack 2 .

[0100] A possible material combination can in such a case for for example be : Growth substrate 26 of Saphire / GaN;

[0101] Semiconductor layer stack 2 of GaN;

[0102] Bottom contact layer 9 of ITO ;

[0103] First sacrificial layer 23 in form of a conductive layer of for example a metal ;

[0104] Second sacrificial layer 24 of SiO2;

[0105] Aqua regia or any other metal etchant as first etchant ; and FeCl3or HC1 as second etchant .

[0106] Figures 3A to 3H show exemplary steps of a further embodiment of a method for manufacturing an optoelectronic device according to some aspects of the proposed principle .

[0107] In contrast to the previous embodiments , the second sacrificial layer 24 is dispensed with, but mask 27 takes over the function of sacrificial layer 24 .

[0108] As shown in Figure 3A, in a first step, a semiconductor layer stack 2 of at least a first layer 3 of a first conductivity type , a second layer 4 of a second conductivity type as well as an active region 5 between the first and second layer 3 , 4 is provided . The semiconductor layer stack 2 is arranged on a growth substrate 26 and a bottom contact layer 9 of for example ITO is arranged on the semiconductor layer stack 2 . In addition, a first sacrificial layer 23 is provided on the bottom contact layer 9 .

[0109] As shown in Figure 3B , a structured mas k 27 is then provided on the upper most layer to pixelate the semiconductor layer stack 2 with all layers on top in a subsequent step by means of plasma etching as shown in Figure 3C . The plasma etching results in etched side surfaces of a first portion 19 of the semiconductor layer stack 2 when removing an adj acent second portion 20 of the semiconductor layer stack 2 . The plasma etching is performed from an uppermost surface into the direction of the growth substrate 26 but stops well before reaching the growth substrate 26 within the first layer 3 . Thus , a continuous residual portion of the first layer 3 remains on the growth substrate 26 . The plasma etching introduces damage on the etched side surfaces and also below the side surfaces . This in particular in the active region 5 is a maj or problem, since it creates non-radiative recombination channels for charge carriers along the side surfaces leading to a low EQE of the final optoelectronic device .

[0110] The contact layer 7 and / or the first sacrificial layer 23 and / or the mask 27 can however also be arranged on the first portion 19 after the step of plasma etching or at an even later point of time . Due to the etching step or due to a later provision of the layers on the first portion 19 , the layers on the bottom surface covering the whole bottom surface are due to its nature centred with respect to the first portion and thus aligned with the first portion in a self-aligning manner .

[0111] The mas k can for example be a photolithographic material , which is then in a subsequent step , as shown in Figure 3D, structured to cover only a central portion of the uppermost area of the first portion 19 of the semiconductor layer stack 2 . This can for example be done by 02ashing , to arrow the resist .

[0112] In a following step , as shown in Figure 3E , the first sacrificial layer can be etched by means of a wet chemical etching using for example a buffered oxide etch ( BOE ) for SiO2as a material for the first sacrificial layer 23 . The same can be done with the bottom contact layer 9 using for example FeCl3, as shown in Figure 3F, before the mas k 27 is removed and a surface treatment of the plasma etched side surfaces of the semiconductor layer stack 2 can be performed using for example KOH, as shown in Figures 3G and 3H . Figures 4A and 4B show exemplary steps of further processing the structure . As shown in the figures , a passivation layer 12 for chemical surface passivation is applied to the present structure and in particular all exposed surfaces of the semiconductor layer stack 2 . The passivation layer 12 can be applied by Atomic Layer Deposition or Sputtering , ( e . g . ALD A12O3, ALD AIN, SiO2) with for example a thickness of a single monolayer up to hundreds of nanometers . Also , other passivation methods are thinkable like hydrogen passivation, or a combination of A12O3for chemical passivation and Nb2O5for providing desired optical properties . The step is hereby exemplary shown for the structures resulting from the steps shown in Figures 2G and 2J .

[0113] Figures 5A to 5D show exemplary steps of further processing the structure as well as figures 6A and 6B possible embodiments of the resulting structure after the steps shown in Figure 5A to 5D have been performed .

[0114] On the passivation layer 13 , as shown in Figure 5A, a dielectric material layer 10 is deposited by for example sputtering Nb2O5onto the present structure . Due to sputtering the material , the dielectric material layer 10 follows the underlying contour with substantially the same thickness . The deposition of the dielectric material layer 10 can however also be conducted by means of plasma coating .

[0115] On top of the dielectric material layer 10 , as shown in Figure 5B , a resist material 25 is then applied, following the underlying contour with substantially the same thickness . The resist coating 25 on the dielectric material layer 10 is then developed and hardbaked such that the resist coating "liquidises" and accumulates in a self-aligned way at the protruding portions of the underlying structure . By adj usting the thickness of the dielectric material layer 10 , the properties of the resist coating 25 , the time and temperature of the hardbaking and by adj usting the parameters of a subsequent plasma etching process ( shown in Figure 5D ) , the dielectric layer 10 can then be structured in a desired way and in a self-aligned manner resulting in the exemplarily shown structures shown in Figures 6A and 6B . It can however also be conceivable to conduct the plasma etching process shown in Figure 5D right after the step of depositing the dielectric dielectric material layer 10 , as shown in Figure 5A, to structure the dielectric layer 10 in a desired way and in a self-aligned manner . The plasma etching parameters can thereby in combination with the parameters of the deposition of the dielectric material layer 10 be tuned such that a desired structured shape can be achieved .

[0116] It is thereby important to say that the etching of the dielectric layer is thereby to be conducted until reaching / exposing the first sacrificial layer 23 , to either be able to remove the first sacrificial layer 23 to receive an opening or in case of the first sacrificial layer 23 being a conductive layer to allow a contacting of the conductive material . The removal of the first sacrificial layer 23 is for example exemplary shown in Figures 7A and 7B for the structures shown in Figures 6A and 6B .

[0117] This order of steps is particularly advantageous compared to generate the opening at a later point of time using lithographic etching process , as the order of steps takes place in a self-aligned manner and the opening is well centred above the bottom contact element 9 . In case of however generating the opening by means of a lithographic etching process into a continuous dielectric layer 10 , the position of the opening is very much dependent on a positioning of the mask or opening of the mas k to etch the opening into the dielectric layer 10 .

[0118] On the dielectric layer 10 , a reflective contact layer 11 is then deposited electrically contacting the bottom contact element 9 , as shown in Figure 8 . The reflective contact layer 11 can now be deposited all over the underlying structure while due to the provided opening already centred above the bottom contact element 9 or due to the already provided conductive layer in the opening position accuracy of proving the reflective contact layer 11 plays no or hardly any role anymore .

[0119] In a subsequent step, as shown in Figure 9A, the structure is then covered by means of an intermediate layer 17 and a carrier layer 18 is arranged on the intermediate layer 17 to be able to remove the growth substrate 16 and to expose the upper surface of the semiconductor layer stack 2 , as shown in Figure 9B .

[0120] Figures 9C to 9H show exemplary steps of further processing the structure to receive the optoelectronic device . As shown in Figures 9C to 9E an optical element 14 can for example be formed in the first layer 3 the outer surface of which forms the top surface / light emitting surface 8 of the later optoelectronic device .

[0121] Therefore , as shown in Figure 9C, a structured mas k / resist material 28 is provided on the semiconductor layer stack 2 . The material 28 is then hardbaked, as shown in Figure 9D, to specify a desired shape , which is then etched into the first layer 3 , as shown in Figure 9E . These steps and the type of optical element 14 is however to be understood exemplary and also other and more complex structures , for example nanostructures , can be formed into the first layer . Another possibility to provide an optical element can also be to provide a further layer of the semiconductor material or another material to be structured onto the semiconductor layer stack 2 or to attach an already present optical element 14 onto the top surface 8 of the semiconductor layer stack 2 .

[0122] As shown in Figures 9F to 9H top contact element 15 also acting as a reflective structure can for example be provided on / in the semiconductor layer stack 2 surrounding the optical element in a circumferential direction U .

[0123] Therefore , as shown in figure 9F, a structured mas k / resist material 29 is provided on the semiconductor layer stack 2 comprising openings 30 . By means of opening 30 , as shown in Figure 9G, opening 31 ae etched into the first layer 3 , the passivation layer 13 and into the dielectric material 10 which are then filled, as shown in Figure 9H , with a conductive and reflective material resulting in the top contact element 15 electrically contacting the first layer . The top contact element 15 can however also be provided in form of a metallic grid bonded or attached to the top surface 8 . Figures 10A to 101 show exemplary steps of a further embodiment of a method for manufacturing an optoelectronic device according to some aspects of the proposed principle .

[0124] In contrast to the previous embodiments , the first side surfaces 6 are however received by means of the first plasma etching step and are not or at least not to the same extend surface treated by means of a wet chemical etch using KOH as shown in Figures 2D and 3H but can for example be surface treated in any other way to reduce non-radiative recombination channels along the first side surfaces 6 . Most of the other steps , in particular the steps shown in Figures 10A to 10G, are comparable to that ones already described for Figures 3A to 3G . The resulting structure with inclined side surfaces 6 is then passivated by means of passivation layer 13 as shown in Figure 10H, and the dielectric material layer 10 is applied to the passivation layer 13 as shown in Figure 101 .

[0125] Figures 11A and 11B indicate that by adj usting the thickness of the dielectric material layer 10 , the properties of an overlying resist coating, the time and temperature of hardbaking of the resist coating and by adj usting the parameters of a subsequent plasma etching process ( shown in Figures 11A and 11B ) , the dielectric layer 10 can be structured in a desired way and in a self-aligned manner resulting in the exemplarily shown structures shown in Figures 11A and 11B . Hence the second side surfaces can be generated to a desired need to increase the LEE of the later optoelectronic device decoupled from optimization of the IQE within the semiconductor layer stack . This can for example in an extreme case also lead to a very shallow angle of the first side surfaces 6 but a very steep angle of the second side surfaces 12 as indicated in Figure 12B . LIST OF REFERENCES optoelectronic device semiconductor layer stack first layer second layer active region first side surface bottom surface top surface bottom contact element dielectric layer reflective contact layer second side surface passivation layer optical element top contact element through contact intermediate layer carrier layer first portion second portion first portion second portion first sacrificial layer second sacrificial layer mask growth substrate mask mask mask opening opening thickness lateral direction vertical direction

Claims

CLAIMS1. Optoelectronic device (1) comprising: a semiconductor layer stack (2) of at least a first layer (3) of a first conductivity type, a second layer (4) of a second conductivity type as well as an active region (5) between the first and second layer (3, 4) , the semiconductor layer stack (2) comprising first side surfaces (6) connecting a bottom surface (7) and a top surface (8) ; a bottom contact element (9) arranged on the bottom surface (7) ; a dielectric layer (10) arranged on the first side surfaces(6) and in particular extending partially onto the bottom surface( 7 ) ; and a reflective contact layer (11) arranged on the dielectric layer (10) electrically contacting the bottom contact element (9) ; wherein the dielectric layer (10) comprises second side surfaces (12) opposite the first side surfaces (6) with the second side surfaces (12) having at least in portions a different angle relative to the bottom surface (7) than the first side surfaces (6) .

2. Optoelectronic device according to claim 1, wherein the first side surfaces (6) are substantially perpendicular with respect to the bottom surface (7) .

3. Optoelectronic device according to claim 1 or 2 , wherein the dielectric layer (10) comprises an increasing thickness (t) in a lateral direction (1) from the bottom surface (7) to the top surface ( 8 ) .

4. Optoelectronic device according to any one of the preceding claims, wherein the second side surfaces (12) are inclined with respect to the bottom surface (7) .

5. Optoelectronic device according to any one of the preceding claims, wherein the second side surfaces (12) are curved.

6. Optoelectronic device according to any one of the preceding claims, wherein the material of the semiconductor layer stack (2) and the material of the dielectric layer (10) is index matched and in particular differs by no more than 0.1.

7. Optoelectronic device according to any one of the preceding claims, wherein a circumference of the dielectric layer (10) increases from the bottom surface (7) to the top surface (8) .

8. Optoelectronic device according to any one of the preceding claims, further comprising a passivation layer (13) at least arranged between the first side surfaces (6) and the dielectric layer (10) .

9. Optoelectronic device according to any one of the preceding claims, wherein the first layer (3) forms the top surface (8) , further comprising an optical element (14) arranged on the top surface ( 8 ) ; or further comprising an optical element (14) formed of the first layer (3) .

10. Optoelectronic device according to any one of the preceding claims, further comprising a top contact element (15) electrically coupled to the first layer (3) , wherein optionally the top contact element (15) is of a reflective material and surrounds the semiconductor layer stack (2) in a circumferential direction (U) .

11. Optoelectronic device according to any one of the preceding claims, wherein the reflective contact layer (11) comprises a through contact (16) through the dielectric layer (10) electrically contacting the bottom contact element (9) .

12. Optoelectronic device according to claim 11, wherein the through contact (16) is substantially centred with respect to the semiconductor layer stack (2) .

13. Optoelectronic device according to any one of the preceding claims,wherein the dielectric layer (10) is substantially centred with respect to the semiconductor layer stack (2) .

14. Optoelectronic device according to any one of the preceding claims, further comprising an intermediate layer (17) arranged on the reflective contact layer (11) and in particular a carrier layer (18) arranged on the intermediate layer (17) .

15. Method for manufacturing an optoelectronic device (1) comprising the steps :Providing a semiconductor layer stack (2) of at least a first layer (3) of a first conductivity type, a second layer (4) of a second conductivity type as well as an active region (5) between the first and second layer (3, 4) ;Structuring the semiconductor layer stack (2) such that at least a first portion (19) of the semiconductor layer stack (2) is retained and at least a second portion (20) of the semiconductor layer stack (2) adjacent to the first portion (19) is removed, thereby forming an etched first side surface (6) of the first portion (19) comprising the first layer (3) , the second layer (4) and the active region (5) and extending from a bottom surface (7) of the semiconductor layer stack (2) into the direction of a top surface (8) of the semiconductor layer stack (2) opposite the bottom surface ( 7 ) ;Providing a dielectric layer (10) at least on the first side surface ( 6 ) ;Structuring the dielectric layer (10) such that at least a first portion (21) of the dielectric layer (10) is retained and at least a second portion (22) of the dielectric layer (10) adjacent to the first portion (21) is removed, thereby forming an etched second side surface (12) of the dielectric layer (10) ; and Providing a reflective contact layer (11) on the dielectric layer (10) electrically contacting the semiconductor layer stack (2) ; wherein the second side surface (12) has at least in portions a different angle relative to the bottom surface (7) than the first side surface (6) .

16. Method according to claim 15, wherein the step of structuring the semiconductor layer stack (2) comprises a step of surface treating pre-etched side surfaces using a wet etchant, thereby forming the etched first side surface (6) , wherein the first side surface (6) is substantially perpendicular with respect to the bottom surface (7) .

17. Method according to claim 15 or 16, further comprising a step of providing a bottom contact layer (9) on the second layer (4) .

18. Method according to any one of claims 15 to 17, further comprising a step of providing a first sacrificial layer(23) on the second layer (4) or on the bottom contact layer (9) ; and optionally comprising a step of providing a second sacrificial layer(24) on the first sacrificial layer (23) .

19. Method according to any one of claims 15 to 18, further comprising a step of structuring the bottom contact layer ( 9 ) ; and / or further comprising a step of structuring the first sacrificial layer ( 23 ) ; and / or further comprising a step of structuring the second sacrificial layer (24) ; and / or further comprising a step of removing the first and / or second sacrificial layer (23, 24) .

20. Method according to any one of claims 15 to 19, further comprising a step of providing a passivation layer (13) at least on the first side surface (6) .

21. Method according to any one of claims 15 to 20, wherein the step of structuring the dielectric layer (10) comprises: a step of providing a mask (25) on the dielectric layer (10) ; and / or a step of hard baking the mask (25) on the dielectric layer (10) ; and / ora step of plasma etching the dielectric layer (10) , thereby forming the etched second side surface (12) of the dielectric layer (10) .

22. Method according to any one of claims 15 to 21, further comprising a step of providing an optical element (14) on the top surface (8) or a step of providing an optical element (14) formed of the first layer (3) ; and / or further comprising a step of providing a top contact element (15) electrically coupled to the first layer (3) , wherein optionally the top contact element (15) is of a reflective material and surrounds the first portion (19) of the semiconductor layer stack (2) in a circumferential direction U) .

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