Nonvolatile memory and arithmetic device

Abstract

In the present invention, high integration is achieved in nonvolatile memory in which a magnetoresistance effect element is arranged in a memory cell.　The nonvolatile memory comprises a plurality of magnetoresistance effect elements and a write circuit. In the nonvolatile memory comprising a plurality of magnetoresistance effect elements and a write circuit, the plurality of magnetoresistance effect elements are connected in series between first and second control lines. In the nonvolatile memory comprising a plurality of magnetoresistance effect elements and a write circuit, the write circuit writes data to any one of the plurality of magnetoresistance effect elements.

Description

Non-volatile memory and computing device

[0001] The present technology relates to a nonvolatile memory, and more particularly to a nonvolatile memory using a magnetoresistive element and a computing device.

[0002] In recent years, magnetoresistive random access memories (MRAMs) using magnetoresistive effect elements have been attracting attention as alternatives to volatile memories such as static random access memories (SRAMs) and dynamic random access memories (DRAMs). Among MRAMs, those that use the tunnel magnetoresistance (TMR) effect are called spin transfer torque MRAMs (STT-MRAMs). Furthermore, among MRAMs, those that use the voltage-controlled magnetic anisotropy (VCMA) effect are called voltage-controlled MRAMs (VC-MRAMs). For example, a VC-MRAM has been proposed in which one magnetoresistive effect element and one transistor are arranged for each memory cell, and the pulse width of a voltage pulse supplied to the transistor is controlled within a predetermined range (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2018-092696

[0004] In the above-mentioned conventional technology, the reliability of writing is improved by controlling the pulse width, but it is difficult to achieve a higher integration density with the above-mentioned conventional technology.

[0005] This technology was developed in light of these circumstances, and aims to achieve high integration in nonvolatile memories in which magnetoresistive effect elements are arranged within memory cells.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a nonvolatile memory including a plurality of magnetoresistive effect elements connected in series between first and second control lines, and a write circuit that writes data to any of the plurality of magnetoresistive effect elements, thereby achieving a high degree of integration of the nonvolatile memory.

[0007] In addition, in this first aspect, the plurality of magnetoresistive elements may include first and second magnetoresistive elements, each of which includes a plurality of stacked layers, and the stacking order of the first magnetoresistive element may be reversed to that of the second magnetoresistive element, thereby providing the effect of allowing data to be written individually by applying voltages of different polarities.

[0008] In addition, in this first aspect, the write circuit may apply voltages having different polarities between the first and second control lines when writing to the first magnetoresistive element and when writing to the second magnetoresistive element, thereby achieving the effect of writing data individually to the first and second magnetoresistive elements.

[0009] In this first aspect, the first magnetoresistive element may include a first free layer, a first tunnel barrier layer, and a first reference layer, and the second magnetoresistive element may include a second free layer, a second tunnel barrier layer, and a second reference layer, thereby providing the effect of individually controlling the magnetization directions of the first free layer and the second free layer.

[0010] In the first aspect, the first magnetoresistive element may include a first free layer and a first tunnel barrier layer, the second magnetoresistive element may include a second free layer and a second tunnel barrier layer, and the first and second magnetoresistive elements may share a predetermined reference layer, thereby reducing the number of reference layers.

[0011] In addition, in this first aspect, the first magnetoresistive element may include a pair of a first free layer, a first tunnel barrier layer, and a first reference layer whose magnetizations are exchange-coupled, and the second magnetoresistive element may include a pair of a second free layer, a second tunnel barrier layer, and a second reference layer whose magnetizations are exchange-coupled, thereby providing the effect of facilitating writing.

[0012] In this first aspect, the first magnetoresistive element may include a pair of a first free layer and a first tunnel barrier layer whose magnetizations are exchange-coupled, the second magnetoresistive element may include a pair of a second free layer and a second tunnel barrier layer whose magnetizations are exchange-coupled, and the first and second magnetoresistive elements may share a predetermined reference layer, thereby providing the effect of reducing the number of reference layers.

[0013] In this first aspect, each of the plurality of magnetoresistive elements may include a plurality of stacked layers, the stacking order of the plurality of magnetoresistive elements may be the same, and the VCMA coefficients of the plurality of magnetoresistive elements may be different, thereby providing the effect of allowing data to be written individually by applying voltages of the same polarity but different values.

[0014] In addition, in this first aspect, the plurality of magnetoresistive elements may include first and second magnetoresistive elements, and the write circuit may apply voltages of the same polarity but different values ​​when writing to the first magnetoresistive element and when writing to the second magnetoresistive element, thereby achieving the effect of writing data individually to the first and second magnetoresistive elements.

[0015] In the first aspect, the plurality of magnetoresistive elements may include first, second, third, and fourth magnetoresistive elements, each of which includes a plurality of stacked layers, the stacking order of the first and third magnetoresistive elements being reverse to the stacking order of the second and fourth magnetoresistive elements, and the VCMA coefficient of the first magnetoresistive element may be different from the VCMA coefficient of the third magnetoresistive element, and the VCMA coefficient of the second magnetoresistive element may be different from the VCMA coefficient of the fourth magnetoresistive element, thereby providing the effect of allowing data to be written individually by applying voltages of different polarities or values.

[0016] A second aspect of the present technology is a calculation device including: a memory cell array in which a plurality of memory cells, each including a plurality of magnetoresistive effect elements connected in series, are arranged in a two-dimensional lattice pattern; a digital calculation unit that supplies a predetermined digital signal as an input signal for each line in the memory cell array; a digital-to-analog conversion unit that converts the input signal into a voltage and supplies the voltage to the corresponding line; and an analog-to-digital conversion unit that converts, for each line, a current indicating the sum of the products of the reciprocals of the resistance values ​​of the memory cells in the line and the voltage into a digital signal and supplies the digital signal to the digital calculation unit. This results in the effect of performing a product-sum calculation.

[0017] In addition, in the second aspect, the memory cell may further include a write circuit that writes data representing the resistance value into each of the plurality of memory cells by applying a voltage, thereby providing the effect of setting the weight.

[0018] 1 is a block diagram showing a configuration example of a nonvolatile memory according to a first embodiment of the present technology. FIG. 2 is a diagram showing a configuration example of a memory cell array according to the first embodiment of the present technology. FIG. 3 is a perspective view showing a configuration example of a memory cell according to the first embodiment of the present technology. FIG. 4 is a cross-sectional view showing a configuration example of a magnetoresistive effect element according to the first embodiment of the present technology. FIG. 5 is a diagram showing an example of a state of a memory cell according to the first embodiment of the present technology. FIG. 6 is a graph showing an example of the relationship between perpendicular magnetic anisotropy of a magnetoresistive effect element and a write voltage according to the first embodiment of the present technology. FIG. 7 is a graph showing a variation in magnetization vector when writing to a memory cell in a high resistance-high resistance state according to the first embodiment of the present technology. FIG. 8 is a graph showing a variation in magnetization vector when writing to a memory cell in a high resistance-low resistance state according to the first embodiment of the present technology. FIG. 9 is a graph showing a variation in magnetization vector when writing to a memory cell in a low resistance-high resistance state according to the first embodiment of the present technology. FIG. 10 is a graph showing a variation in magnetization vector when writing to a memory cell in a low resistance-low resistance state according to the first embodiment of the present technology. 1 is a timing chart showing an example of a write operation of a nonvolatile memory according to a first embodiment of the present technology. FIG. 1 is a cross-sectional view showing an example of a configuration of a magnetoresistive effect element according to a first modified example of the first embodiment of the present technology. FIG. 2 is a cross-sectional view showing an example of a configuration of a magnetoresistive effect element according to a second modified example of the first embodiment of the present technology. FIG. 3 is a cross-sectional view showing an example of a configuration of a magnetoresistive effect element according to a third modified example of the first embodiment of the present technology. FIG. 4 is a cross-sectional view showing an example of a configuration of a magnetoresistive effect element according to a fourth modified example of the first embodiment of the present technology. FIG. 5 is a cross-sectional view showing an example of a configuration of a magnetoresistive effect element according to a fifth modified example of the first embodiment of the present technology. FIG. 6 is a cross-sectional view showing an example of a configuration of a magnetoresistive effect element according to a second embodiment of the present technology. FIG. 7 is a graph showing an example of the relationship between perpendicular magnetic anisotropy and a write voltage of a magnetoresistive effect element according to the second embodiment of the present technology. FIG. 8 is a graph showing a fluctuation in a magnetization vector when writing to a memory cell in a high resistance-high resistance state according to the second embodiment of the present technology.10 is a graph showing a variation in magnetization vector when writing to a memory cell in a high resistance-low resistance state according to a second embodiment of the present technology. FIG. 11 is a graph showing a variation in magnetization vector when writing to a memory cell in a low resistance-high resistance state according to the second embodiment of the present technology. FIG. 12 is a graph showing a variation in magnetization vector when writing to a memory cell in a low resistance-low resistance state according to the second embodiment of the present technology. FIG. 13 is a timing chart showing an example of a write operation of a nonvolatile memory according to the second embodiment of the present technology. FIG. 14 is a cross-sectional view showing an example of a configuration of a magnetoresistive effect element according to a first modified example of the second embodiment of the present technology. FIG. 15 is a cross-sectional view showing an example of a configuration of a magnetoresistive effect element according to a second modified example of the second embodiment of the present technology. FIG. 16 is a diagram showing an example of a state of a memory cell according to the second modified example of the second embodiment of the present technology. FIG. 17 is a graph showing an example of the relationship between perpendicular magnetic anisotropy and write voltage of a magnetoresistive effect element according to a second modified example of the second embodiment of the present technology. FIG. 18 is a cross-sectional view showing an example of a configuration of a magnetoresistive effect element according to a third modified example of the second embodiment of the present technology. 10 is a graph showing an example of the relationship between perpendicular magnetic anisotropy of a magnetoresistive effect element and write voltage according to a third embodiment of the present technology. FIG. 11 is a diagram showing an example of a state of a magnetoresistive effect element for each write voltage according to the third embodiment of the present technology. FIG. 12 is a timing chart showing an example of a write operation of a nonvolatile memory according to the third embodiment of the present technology. FIG. 13 is a timing chart showing an example of a write operation of a nonvolatile memory according to the third embodiment of the present technology. FIG. 14 is a block diagram showing an example of a configuration of a arithmetic device according to a fourth embodiment of the present technology. FIG. 15 is an example of a circuit diagram of a arithmetic device according to the fourth embodiment of the present technology. FIG. 16 is a timing chart showing an example of an operation of a arithmetic device according to the fourth embodiment of the present technology. FIG. 17 is a diagram showing an example of a control signal according to the fourth embodiment of the present technology. FIG. 18 is a timing chart showing an example of an operation of a MAC control circuit and a digital arithmetic unit according to the fourth embodiment of the present technology. FIG. 19 is a flowchart showing an example of an operation of a arithmetic device according to the fourth embodiment of the present technology.Fig. 14 is a block diagram showing another example of a calculation device according to a fourth embodiment of the present technology; Fig. 15 is a diagram showing an example of a schematic configuration of an imaging device; Fig. 16 is a diagram showing an example of a schematic configuration of a distance measuring device; Fig. 17 is a perspective view (exterior perspective view) showing an example of a schematic configuration of a game device; Fig. 18 is a block diagram showing an example of a schematic configuration of a game device;

[0019] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which a plurality of magnetoresistive effect elements are connected in series for each memory cell) 2. Second embodiment (an example in which a plurality of magnetoresistive effect elements are connected in series for each memory cell, and the stacking order of the elements is the same) 3. Third embodiment (an example in which four magnetoresistive effect elements are connected in series for each memory cell) 4. Fourth embodiment (an example in which a plurality of magnetoresistive effect elements are connected in series for each memory cell, and a product-sum operation is performed) 5. Configuration example of electronic device

[0020] 1 is a block diagram showing a configuration example of a nonvolatile memory 100 according to a first embodiment of the present technology. The nonvolatile memory 100 includes an input / output circuit 111, a control circuit 112, a voltage generation circuit 113, a bit / source line address decoder 114, a read circuit 115, a write circuit 116, and a bit / source line control circuit 117. The nonvolatile memory 100 further includes a word line address decoder 118, a word line control circuit 119, a memory cell array 200, and a sense amplifier 120.

[0021] The input / output circuit 111 exchanges commands, addresses, data, etc. with a host system, etc. Commands include write commands and read commands, and addresses include write addresses and read addresses.

[0022] The control circuit 112 controls writing and reading in response to commands.

[0023] The voltage generating circuit 113 generates voltages used for writing and reading, and supplies them to the reading circuit 115 and the writing circuit 116. Note that voltages required for circuit operation are supplied separately.

[0024] In the memory cell array 200, a plurality of memory cells (not shown) are arranged in a two-dimensional lattice pattern. A plurality of magnetoresistive elements are arranged in each memory cell. The structure of the memory cells will be described in detail later. In addition, in the memory cell array 200, bit lines and source lines are wired for each column, and word lines are wired for each row.

[0025] The bit / source line address decoder 114 decodes the address received by the input / output circuit 111 to select the bit line and source line to be accessed.

[0026] The bit / source line control circuit 117 outputs control signals to selected bit lines and source lines.

[0027] The word line address decoder 118 decodes the address received by the input / output circuit 111 to select the word line to be accessed.

[0028] The word line control circuit 119 outputs a control signal to a selected word line.

[0029] The read circuit 115 reads data from a memory cell at the intersection of a selected word line and a bit line in response to a command, and the write circuit 116 writes data to a memory cell at the intersection of a selected word line and a bit line in response to a command.

[0030] The sense amplifier 120 reads data by detecting the current flowing through the memory cell during reading, and outputs the read data to the control circuit 112.

[0031] Writing to a memory cell is performed when the data stored in the memory cell differs from the write data. That is, the sense amplifier 120 reads data from the memory cell, and the control circuit 112 compares the read data with the write data. If the comparison shows that the two data differ, the write circuit 116 performs writing. In this case, writing can be performed by inverting the data stored in the memory cell. That is, writing can be performed by inverting the memory state of the magnetoresistive element. The memory state of the magnetoresistive element can be inverted by applying a predetermined write voltage to the magnetoresistive element. Application of the write voltage reverses the magnetization direction of the magnetoresistive element, changing its resistance value.

[0032] 2 is a diagram showing an example of the configuration of a memory cell array 200 according to the first embodiment of the present technology. A plurality of memory cells 260 are arranged in a two-dimensional lattice pattern in the memory cell array 200. In addition, in the memory cell array 200, a source line SL and a bit line BL are wired for each column, and a word line WL is wired for each row.

[0033] Each of the memory cells 260 includes an access transistor 250 and magnetoresistive elements 210 and 220. As these magnetoresistive elements, for example, MTJ (Magnetic Tunnel Junction) elements are used.

[0034] The gate of the access transistor 250 is connected to a word line WL, the source is connected to a source line SL, and the drain is connected to the magnetoresistive element 220 .

[0035] The magnetoresistive effect elements 210 and 220 are connected in series between the source line SL and the bit line BL via the access transistor 250. The source line SL and the bit line BL are examples of the first and second control lines set forth in the claims. The magnetoresistive effect elements 210 and 220 are also examples of the first and second magnetoresistive effect elements set forth in the claims.

[0036] The control signal from the bit / source line control circuit 117 turns on the access transistor 250 connected to the word line WL to be accessed.

[0037] While the access transistor 250 is in the on state, the write circuit 116 supplies a control signal to one of the source line SL and the bit line BL via the bit / source line control circuit 117, and applies a write voltage between these lines. By controlling this voltage, the write circuit 116 can write data to either the magnetoresistive element 210 or 220. The voltage control method will be described in detail later.

[0038] As shown in the figure, magnetoresistive effect elements 210 and 220 connected in series are arranged for each memory cell 260, and write circuit 116 writes data to them individually. This allows for a higher integration of nonvolatile memory 100 compared to when one magnetoresistive effect element is arranged for each memory cell 260.

[0039] 3 is a perspective view showing a configuration example of a memory cell 260 according to the first embodiment of the present technology. A gate 251 of the access transistor 250 is connected to a word line WL (not shown), and a source 252 is connected to a source line SL (not shown) via a contact layer 261. A drain 253 of the access transistor 250 is connected to the magnetoresistive element 220 via the contact layer 261.

[0040] In the following description, the axis parallel to the rows of the memory cells 260 is referred to as the X axis, the axis parallel to the columns is referred to as the Y axis, and the axis perpendicular to the X axis and the Y axis is referred to as the Z axis.

[0041] The shape of the magnetoresistive effect elements 210 and 220 when viewed from the Z-axis direction is, for example, rectangular. Note that the shape of these elements is not limited to rectangular and may be circular, for example. The size (width, diameter, etc.) of the magnetoresistive effect elements 210 and 220 in a direction perpendicular to the Z-axis direction is, for example, 15 to 280 nanometers (nm), preferably 30 to 100 nanometers (nm). The size is more preferably 40 to 80 nanometers (nm).

[0042] Furthermore, the magnetoresistive effect elements 210 and 220 are stacked in the Z-axis direction via a connection layer 262. The magnetoresistive effect element 210 is connected to a bit line BL (not shown) via a contact layer 263. As illustrated in the figure, because the magnetoresistive effect elements 210 and 220 are stacked vertically in the Z-axis direction, the area of ​​the memory cell array 200 is the same as when one magnetoresistive effect element is arranged for each memory cell 260. Therefore, high integration can be achieved without changing the area.

[0043] 4 is a cross-sectional view showing an example configuration of magnetoresistive effect elements 210 and 220 according to the first embodiment of the present technology. Magnetoresistive effect element 210 includes reference layer 211, tunnel barrier layer 212, and free layer 213, while magnetoresistive effect element 220 includes reference layer 221, tunnel barrier layer 222, and free layer 223. Reference layer 211, tunnel barrier layer 212, and free layer 213 are examples of the first reference layer, first tunnel barrier layer, and first free layer set forth in the claims. Reference layer 221, tunnel barrier layer 222, and free layer 223 are examples of the second reference layer, second tunnel barrier layer, and second free layer set forth in the claims.

[0044] The stacking order of the magnetoresistive effect element 210 is opposite to that of the magnetoresistive effect element 220. In the magnetoresistive effect element 210, for example, a reference layer 211, a tunnel barrier layer 212, and a free layer 213 are stacked in this order from top to bottom, with the bit line BL side on the upper side. On the other hand, in the magnetoresistive effect element 220, for example, a free layer 223, a tunnel barrier layer 222, and a reference layer 221 are stacked in this order from top to bottom. It is also assumed that a magnetic field is applied in the H direction, which is perpendicular to the stacking direction (i.e., the Z-axis direction).

[0045] Reference layers 211 and 221 are layers that have magnetic anisotropy and whose magnetization direction is invariable. The magnetization direction of these reference layers is, for example, an upward direction. The magnetization direction may also be a downward direction. Although the magnetization directions of reference layers 211 and 221 are the same in the figure, the magnetization direction of reference layer 211 may be opposite to that of reference layer 221.

[0046] The reference layer may be made of cobalt-iron-boron (CoFeB), a cobalt-iron-boron alloy, a cobalt-iron-carbon (CoFeC) alloy, a nickel-iron-boron (NiFeB) alloy, or a nickel-iron-carbon (NiFeC) alloy. Alternatively, a laminated ferri-pinned structure may be used, in which a ferromagnetic layer is used, or multiple ferromagnetic layers are stacked with a non-magnetic layer interposed therebetween. Materials for the ferromagnetic layer constituting the magnetization pinned layer of the laminated ferri-pinned structure may include cobalt (Co), cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), etc. Materials for the non-magnetic layer may include ruthenium (Ru), rhenium (Re), iridium (Ir), osmium (Os), etc.

[0047] Alternatively, the reference layer can have a configuration in which the direction of magnetization is fixed by utilizing antiferromagnetic coupling between an antiferromagnetic layer and a ferromagnetic layer. Materials for the antiferromagnetic layer include iron-manganese (FeMn) alloy, platinum-manganese (PtMn) alloy, platinum-chromium-manganese (PtCrMn) alloy, nickel-manganese (NiMn) alloy, iridium-manganese (IrMn) alloy, nickel oxide (NiO), iron trioxide (FeO), and the like. ２ O ３Examples of the magnetic material include silver (Ag), copper (Cu), gold (Au), aluminum (Al), silicon (Si), bismuth (Bi), tantalum (Ta), boron (B), carbon (C), oxygen (O), nitrogen (N), lead (Pd), platinum (Pt), zirconium (Zr), hafnium (Hf), iridium (Ir), tungsten (W), molybdenum (Mo), and niobium (Nb).

[0048] The tunnel barrier layers 212 and 222 are nonmagnetic layers. These tunnel barrier layers use an oxide of at least one element selected from the group consisting of magnesium (Mg), aluminum (Al), titanium (Ti), silicon (Si), zinc (Zn), zirconium (Zr), hafnium (Hf), tantalum (Ta), bismuth (Bi), chromium (Cr), gallium (Ga), lanthanum (La), gadolinium (Gd), strontium (Sr), and barium (Ba). Alternatively, they use a nitride of at least one element selected from the group consisting of magnesium (Mg), aluminum (Al), titanium (Ti), silicon (Si), zinc (Zn), zirconium (Zr), hafnium (Hf), tantalum (Ta), bismuth (Bi), chromium (Cr), gallium (Ga), lanthanum (La), gadolinium (Gd), strontium (Sr), and barium (Ba). Furthermore, magnesium difluoride (MgF ２ ), calcium fluoride (CaF), strontium titanium dioxide (SrTiO ２ ), lanthanum aluminum trioxide (AlLaO ３ The tunnel barrier layer can also be made of various insulators, dielectrics, and semiconductors such as aluminum oxide nitride (AlNO), etc. The thickness of these layers is, for example, 0.6 nanometers (nm) or more.

[0049] The free layers 213 and 223 are layers with magnetic anisotropy and variable magnetization direction. These free layers use cobalt iron (CoFe), cobalt iron boron (CoFeB), iron (Fe), or iron boride (FeB). They may also contain transition metals, such as hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), iridium (Ir), platinum (Pt), gold (Au), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), lead (Pd), silver (Ag), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), and copper (Cu). The free layers may also contain nitrides or oxides. Iridium (Ir) and osmium (Os) may be used as materials that induce a proximity magnetic moment in the magnetic material. The free layer has a thickness of 3.0 nanometers (nm) or less. The free layer is also called a storage layer.

[0050] Furthermore, a magnetoresistive element (MTJ element) enters a high-resistance state where the resistance value is higher than a predetermined value when the magnetization directions of the reference layer and the free layer are different, and enters a low-resistance state where the resistance value is lower than a predetermined value when the magnetization directions are the same. The state where the magnetization directions are the same is called a parallel state, and the state where the magnetization directions are different is called an anti-parallel state. This magnetization direction can be changed by applying a write voltage to the magnetoresistive element. For example, logical values ​​"0" and "1" can be associated with the low-resistance state and high-resistance state of the magnetoresistive element to store one bit of data. The values ​​"0" and "1" can also be referred to as low-level voltage and high-level voltage.

[0051] As shown in the figure, each memory cell 260 is provided with a magnetoresistive element 210 and a magnetoresistive element 220, which can store one bit of data, for a total of two bits of data. This multi-level storage makes it possible to realize a nonvolatile memory 100 with twice the memory capacity while maintaining roughly the same area. In other words, the nonvolatile memory 100 can be highly integrated.

[0052] FIG. 5 is a diagram showing an example of a state of the memory cell 260 according to the first embodiment of the present technology.

[0053] For example, the resistance value of the magnetoresistive element 210 in the low resistance state is R １ The resistance value in the high resistance state is a １ ×R １ The resistance value of the magnetoresistive element 220 in the low resistance state is R ２ The resistance value in the high resistance state is a ２ ×R ２ Let us assume that: a １ and a ２ is a real number indicating the ratio of the resistance values ​​in the low resistance state to the resistance value in the high resistance state.

[0054] For ease of explanation, it is assumed that the following equation holds true: R ２ = b × R １ ...Formula 1 R １ =R...Formula 2 a １ = a ２ = a ... Equation 3 In the above equation, b is R １ and R ２ It is a real number that indicates the ratio of

[0055] When Equations 1 to 3 are satisfied, the resistance values ​​of the magnetoresistive elements 210 and 220 and their combined resistance become the values ​​exemplified in the figure. That is, when the magnetoresistive elements 210 and 220 are both in a low resistance state, their combined resistance becomes (1+b)R. When the magnetoresistive element 210 is in a high resistance state and the magnetoresistive element 220 is in a low resistance state, their combined resistance becomes (a+b)R. When the magnetoresistive element 210 is in a low resistance state and the magnetoresistive element 220 is in a high resistance state, their combined resistance becomes (1+ab)R. When the magnetoresistive elements 210 and 220 are both in a high resistance state, their combined resistance becomes a(1+b)R.

[0056] If b=1, the resistance value of the combined resistance is three, so it is preferable that b≠1, that is, the resistance values ​​in the low resistance state of each of the magnetoresistive effect elements 210 and 220 are different. Also, if a=4 and b=2, the resistance value can take four equal values. In the magnetoresistive effect elements 210 and 220, b can be controlled by the thickness of each tunnel barrier layer, and the setting of b is different from the a １ Yaa ２ This is easier than setting

[0057] FIG. 6 is a graph showing an example of the relationship between the perpendicular magnetic anisotropy and the write voltage of the magnetoresistive effect elements 210 and 220 according to the first embodiment of the present technology. The phenomenon in which the perpendicular magnetic anisotropy changes with voltage is called the VCMA effect, and an MRAM that performs writing using this VCMA effect is called a VC-MRAM. In the figure, "a" is a graph showing an example of the relationship between the perpendicular magnetic anisotropy and the write voltage of the magnetoresistive effect element 210. In the figure, "b" is a graph showing an example of the relationship between the perpendicular magnetic anisotropy and the write voltage of the magnetoresistive effect element 220. The vertical axes of "a" and "b" in the figure represent the perpendicular magnetic anisotropy K, and the horizontal axes represent the write voltage applied between the source line and the bit line. For example, a case in which the voltage of the bit line is higher than that of the source line is considered to be a negative voltage, and a case in which the voltage of the source line is higher than that of the bit line is considered to be a positive voltage.

[0058] As shown in the figure, when a positive write voltage is applied, the perpendicular magnetic anisotropy of the magnetoresistive element 210 becomes larger than 0, and the magnetization direction does not reverse. On the other hand, when a negative write voltage is applied, the perpendicular magnetic anisotropy of the magnetoresistive element 210 becomes smaller, and −V Ｗ When a voltage is applied, the perpendicular magnetic anisotropy becomes approximately 0, and the magnetization direction is reversed.

[0059] As shown in FIG. 1B, when a positive write voltage is applied, the perpendicular magnetic anisotropy of the magnetoresistive element 220 decreases, and +V Ｗ When a negative write voltage is applied, the perpendicular magnetic anisotropy of the magnetoresistive element 220 becomes greater than 0, and the magnetization direction does not reverse.

[0060] As described above, since the stacking order of the magnetoresistive elements 210 and 220 is reversed, the polarity of the voltage that reverses the magnetization direction in each element is reversed, as illustrated in a and b in the figure. Therefore, the write circuit 116 applies voltages of different polarities between the source line and the bit line when writing to the first magnetoresistive element and when writing to the second magnetoresistive element. In the characteristics illustrated in a and b in the figure, a negative voltage is applied when writing to only the magnetoresistive element 210, and a positive voltage is applied when writing to only the magnetoresistive element 220. By this control, the write circuit 116 can reverse the magnetization direction of only one of the magnetoresistive elements 210 and 220, changing the resistance value (in other words, writing data).

[0061] 7 to 10 show the fluctuation of the magnetization vector obtained by computer simulation. The vertical axis of each of the figures represents the Z-axis component m of the magnetization vector. ｚ The horizontal axis represents time. The magnetization direction is +1, which is upward, and -1, which is downward. When the magnetization direction is upward, the resistance state is low, and when it is downward, the resistance state is high. In the simulation, the voltage was turned on 10 to 12 nanoseconds (ns) from a predetermined start time, with a relaxation time of 10 nanoseconds (ns) before and after.

[0062] Furthermore, the state of the memory cell 260 in which both the magnetoresistive elements 210 and 220 are in the high resistance state is referred to as a high-high resistance state or an HH state. The state of the memory cell 260 in which the magnetoresistive element 210 is in the high resistance state and the magnetoresistive element 220 is in the low resistance state is referred to as a high-low resistance state or an HL state. The state of the memory cell 260 in which the magnetoresistive element 210 is in the low resistance state and the magnetoresistive element 220 is in the high resistance state is referred to as a low-high resistance state or an LH state. The state of the memory cell 260 in which both the magnetoresistive elements 210 and 220 are in the low resistance state is referred to as a low-low resistance state or an LL state.

[0063] 7 is a graph showing the fluctuation of the magnetization vector when writing to the memory cell 260 in the high-resistance-high-resistance state in the first embodiment of the present technology. In the figure, "a" is a graph showing the fluctuation of the magnetization vector when the high-resistance-high-resistance (HH) state is changed to the high-resistance-low-resistance (HL) state by writing. In this case, +V Ｗ is applied, and only the magnetization direction of the magnetoresistive element 220 is reversed.

[0064] In the figure, b is a graph showing the change in the magnetization vector when the high resistance-high resistance (HH) state is changed to the low resistance-high resistance (LH) state by writing. Ｗ is applied, and only the magnetization direction of the magnetoresistive element 210 is reversed.

[0065] 8 is a graph showing the fluctuation of the magnetization vector when writing to the memory cell 260 in the high-resistance-low-resistance state according to the first embodiment of the present technology. The graph "a" in the figure shows the fluctuation of the magnetization vector when writing from the high-resistance-low-resistance (HL) state to the high-resistance-high-resistance (HH) state. In this case, both the magnetoresistive elements 210 and 220 must be set to the high-resistance state, and the voltage division required for reversal becomes large. Therefore, the voltage division becomes large when the voltage is +2V. Ｗ is applied, and only the magnetization direction of the magnetoresistive element 220 is reversed.

[0066] In the figure, b is a graph showing the change in the magnetization vector when the high resistance-low resistance (HL) state is changed to the low resistance-low resistance (LL) state by writing. Ｗ is applied, and only the magnetization direction of the magnetoresistive element 210 is reversed.

[0067] 9 is a graph showing the fluctuation of the magnetization vector when writing to the memory cell 260 in the low-resistance-high resistance state according to the first embodiment of the present technology. In the figure, "a" is a graph showing the fluctuation of the magnetization vector when writing from the low-resistance-high resistance (LH) state to the low-resistance-low resistance (LL) state. In this case, +V Ｗ is applied, and only the magnetization direction of the magnetoresistive element 220 is reversed.

[0068] In the figure, b is a graph showing the change in the magnetization vector when the low resistance-high resistance (LH) state is changed to the high resistance-high resistance (HH) state by writing. In this case, both the magnetoresistive elements 210 and 220 must be put into the high resistance state, and the voltage division required for reversal becomes large. Ｗ is applied, and only the magnetization direction of the magnetoresistive element 210 is reversed.

[0069] 10 is a graph showing the fluctuation of the magnetization vector when writing to the memory cell 260 in the low-low resistance state according to the first embodiment of the present technology. In the figure, a is a graph showing the fluctuation of the magnetization vector when the low-low resistance (LL) state is changed to the low-high resistance (LH) state by writing. In this case, +V Ｗ is applied, and only the magnetization direction of the magnetoresistive element 220 is reversed.

[0070] In the figure, b is a graph showing the change in the magnetization vector when the low resistance-low resistance (LL) state is changed to the high resistance-low resistance (HL) state by writing. Ｗ is applied, and only the magnetization direction of the magnetoresistive element 210 is reversed.

[0071] 11 is a flowchart showing an example of a write operation of the nonvolatile memory 100 according to the first embodiment of the present technology. This operation is started when the nonvolatile memory 100 receives a write command. First, the read circuit 115 performs an initial read from the memory cell 260 to be accessed (step S901).

[0072] Next, the control circuit 112 determines whether the data read in step S901 matches the write data (step S902). If the data matches the write data (step S902: Yes), the nonvolatile memory 100 ends the process.

[0073] On the other hand, if the read data does not match the write data (step S902: No), the write circuit 116 sets a write voltage (step S903) and performs writing at that voltage (step S904). Next, the read circuit performs verify reading (step S905), and steps S901 and after are repeated.

[0074] 12 is a timing chart showing an example of a write operation of the nonvolatile memory 100 according to the first embodiment of the present technology. In the figure, "a" shows the timing chart when writing to the magnetoresistive effect element 210, and "b" shows the timing chart when writing to the magnetoresistive effect element 220.

[0075] As shown in FIG. 11A, the word line control circuit 119 transmits a high-level control signal to the word line WL of the row to be accessed during the period from timing T1 to T2.

[0076] Furthermore, the write circuit 116 applies +V ＷThe pulse signal is supplied as a control signal via the bit / source line control circuit 117. As a result, a negative voltage is applied to the magnetoresistive element in the memory cell 260 to be accessed. This voltage causes the magnetization vector of the free layer to precess around the H direction of the external magnetic field, and the application of the voltage is stopped when the magnetization vector reverses during this precession. As a result, data is written only to the magnetoresistive element 210.

[0077] On the other hand, when writing to only the magnetoresistive element 220, the write circuit 116 applies +V Ｗ This pulse signal (i.e., control signal) is supplied via the bit / source line control circuit 117. As a result, a positive voltage is applied to the magnetoresistive element in the memory cell 260 to be accessed, and data is written only to the magnetoresistive element 220.

[0078] As described above, according to the first embodiment of the present technology, the magnetoresistive elements 210 and 220 are connected in series between the bit line and the source line, and the write circuit 116 writes data to only one of these elements using a positive voltage or a negative voltage. This makes it possible to achieve high integration of the nonvolatile memory 100.

[0079] [First Modification] In the first embodiment described above, reference layer 211, tunnel barrier layer 212, and free layer 213 are stacked in this order from top to bottom in magnetoresistive element 210, and are stacked in the reverse order in magnetoresistive element 220. However, the stacking order is not limited to this. Nonvolatile memory 100 in this first modification of the first embodiment differs from the first embodiment in that the stacking order is reversed in magnetoresistive elements 210 and 220.

[0080] 13 is a cross-sectional view showing an example configuration of magnetoresistive effect elements 210 and 220 according to a first modification of the first embodiment of the present technology. In this first modification of the first embodiment, in magnetoresistive effect element 210, free layer 213, tunnel barrier layer 212, and reference layer 211 are stacked in this order from above. On the other hand, in magnetoresistive effect element 220, reference layer 221, tunnel barrier layer 222, and free layer 223 are stacked in this order from above.

[0081] As described above, according to the first modification of the first embodiment of the present technology, the magnetoresistive effect elements 210 and 220 having the stacking order reversed are connected in series and data is written individually, thereby realizing high integration of the nonvolatile memory 100 in the same manner as the first embodiment.

[0082] [Second Modification] In the first modification of the first embodiment described above, six layers are stacked: free layer 213, tunnel barrier layer 212, and reference layer 211; and reference layer 221, tunnel barrier layer 222, and free layer 223. However, it is preferable to reduce the number of layers. Nonvolatile memory 100 in this second modification of the first embodiment differs from the first modification of the first embodiment in that magnetoresistive element 210 and magnetoresistive element 220 share reference layer 211.

[0083] 14 is a cross-sectional view showing a configuration example of magnetoresistive effect elements 210 and 220 according to a second modified example of the first embodiment of the present technology. In this second modified example of the first embodiment, five layers are stacked, in order from top to bottom, including free layer 213, tunnel barrier layer 212, reference layer 211, tunnel barrier layer 222, and free layer 223.

[0084] Free layer 213, tunnel barrier layer 212, and reference layer 211 function as magnetoresistive element 210, and reference layer 211, tunnel barrier layer 222, and free layer 223 function as magnetoresistive element 220. That is, reference layer 211 is shared by magnetoresistive elements 210 and 220. This shared structure allows reference layer 221 to be eliminated.

[0085] As described above, according to the second modification of the first embodiment of the present technology, the magnetoresistive effect element 210 and the magnetoresistive effect element 220 share the reference layer 211, so that the reference layer 221 can be eliminated.

[0086] [Third Modification] In the first embodiment described above, the write circuit 116 applies a voltage to the memory cell 260 and stops applying the voltage when the magnetization vector of the free layer reverses during precession. However, in the first embodiment, the pulse width of the applied voltage must be precisely controlled to improve the probability of successful writing, which makes writing difficult. The nonvolatile memory 100 in this third modification of the first embodiment differs from the first embodiment in that two free layers whose magnetizations are exchange-coupled are arranged in the magnetoresistive element, making writing easier.

[0087] 15 is a cross-sectional view showing a configuration example of magnetoresistive effect elements 210 and 220 according to a third modified example of the first embodiment of the present technology. The magnetoresistive effect elements 210 and 220 according to the third modified example of the first embodiment differ from the first embodiment in that they further include isolation layers 214 and 224 and free layers 215 and 225.

[0088] In magnetoresistive element 210, reference layer 211, tunnel barrier layer 212, free layer 213, isolation layer 214, and free layer 215 are stacked in this order from top to bottom. In magnetoresistive element 220, free layer 225, isolation layer 224, free layer 223, tunnel barrier layer 222, and reference layer 221 are stacked in this order from top to bottom.

[0089] The magnetization of free layer 213 is exchange-coupled with free layer 215. In other words, free layers 213 and 215 are ferromagnetically coupled or antiferromagnetically coupled. In the case of ferromagnetic coupling, the magnetization directions of free layers 213 and 215 are the same, while in the case of antiferromagnetic coupling, the magnetization directions of free layers 213 and 215 are opposite to each other. Furthermore, free layer 213 has the VCMA effect, while free layer 215 does not. Note that free layers 213 and 215 are an example of a pair of first free layers as defined in the claims.

[0090] The separation layer 214 separates the free layer 213 and the free layer 215 while maintaining ferromagnetic or antiferromagnetic coupling.

[0091] The separation layer 214 can be composed of magnesium (Mg), aluminum (Al), titanium (Ti), silicon (Si), zinc (Zn), zirconium (Zr), hafnium (Hf), tantalum (Ta), bismuth (Bi), chromium (Cr), gallium (Ga), lanthanum (La), gadolinium (Gd), strontium (Sr), barium (Ba), tungsten (W), rhenium (Re), iridium (Ir), platinum (Pt), gold (Au), niobium (Nb), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), lead (Pd), silver (Ag), vanadium (V), manganese (Mn), nickel (Ni), copper (Cu), or the like.

[0092] The configurations of free layer 223, separation layer 224, and free layer 225 are similar to those of free layer 213, separation layer 214, and free layer 215. Note that free layers 223 and 225 are an example of a pair of second free layers set forth in the claims.

[0093] In writing, when the magnetization vector of the free layer 213 starts precessing due to the application of a voltage, the exchange-coupled free layer 215 also starts precessing accordingly. Then, the write circuit 116 stops applying the voltage when the magnetization vector is reversed.

[0094] In the first embodiment, which has only the free layer 213, if the timing at which the voltage application is stopped is shifted from the timing at which the magnetization vector reverses, the vector may reverse again. In contrast, in the configuration illustrated in the figure, the exchange-coupled free layer 215 suppresses the reversal of the free layer 213. This eliminates the need for precise control of the pulse width, making writing easier.

[0095] Since the free layers 213 and 215 are exchange-coupled, their magnetization directions cannot be reversed individually. Therefore, each of the free layers 213 and 215 records one bit. Similarly, each of the free layers 223 and 225 records one bit, so that two bits are recorded in each memory cell 260.

[0096] As described above, according to the third modified example of the first embodiment of the present technology, exchange-coupled free layers 213 and 215 and exchange-coupled free layers 223 and 225 are provided, so precise control of the pulse width is not required, and writing becomes easier.

[0097] [Fourth Modification] In the third modification of the first embodiment described above, in magnetoresistive element 210, reference layer 211, tunnel barrier layer 212, free layer 213, isolation layer 214, and free layer 215 are stacked in this order from top to bottom, and the stacking order of magnetoresistive element 220 is reversed. However, the stacking order is not limited to this. Nonvolatile memory 100 in this fourth modification of the first embodiment differs from the third modification of the first embodiment in that the stacking order of magnetoresistive elements 210 and 220 is reversed.

[0098] 16 is a cross-sectional view showing a configuration example of magnetoresistive effect elements 210 and 220 according to a fourth modification of the first embodiment of the present technology. In this fourth modification of the first embodiment, in magnetoresistive effect element 210, free layer 215, isolation layer 214, free layer 213, tunnel barrier layer 212, and reference layer 211 are stacked in this order from top to bottom. On the other hand, in magnetoresistive effect element 220, reference layer 221, tunnel barrier layer 222, free layer 223, isolation layer 224, and free layer 225 are stacked in this order from top to bottom.

[0099] As described above, according to the fourth modification of the first embodiment of the present technology, the magnetoresistive elements 210 and 220 having the stacking order reversed are connected in series and data is written individually, so that it is possible to achieve high integration of the nonvolatile memory 100 as in the first decimal mode. In addition, precise control of the pulse width is not required, making writing easier.

[0100] [Fifth Modification] In the fourth modification of the first embodiment described above, ten layers are stacked, but it is preferable to reduce the number of layers. Nonvolatile memory 100 in this fifth modification of the first embodiment differs from the fourth modification of the first embodiment in that magnetoresistive element 210 and magnetoresistive element 220 share reference layer 211.

[0101] 17 is a cross-sectional view showing a configuration example of magnetoresistive effect elements 210 and 220 according to a fifth modified example of the first embodiment of the present technology. In this fifth modified example of the first embodiment, nine layers are stacked, including, from top to bottom, free layer 215, isolation layer 214, free layer 213, tunnel barrier layer 212, reference layer 211, tunnel barrier layer 222, free layer 223, isolation layer 224, and free layer 225.

[0102] Free layer 215, separation layer 214, free layer 213, tunnel barrier layer 212, and reference layer 211 function as magnetoresistive element 210. Reference layer 211, tunnel barrier layer 222, free layer 223, separation layer 224, and free layer 225 function as magnetoresistive element 220. That is, reference layer 211 is shared by magnetoresistive elements 210 and 220. This shared structure allows reference layer 221 to be eliminated.

[0103] As described above, according to the fifth modification of the first embodiment of the present technology, the magnetoresistive effect element 210 and the magnetoresistive effect element 220 share the reference layer 211, so that the reference layer 221 can be eliminated.

[0104] 2. Second Embodiment In the first embodiment described above, the stacking order of the magnetoresistive effect elements 210 and 220 is reversed, but this configuration is not limiting. Nonvolatile memory 100 in this second embodiment differs from the first embodiment in that the VCMA coefficients of magnetoresistive effect elements 210 and 220 are different but the stacking order is the same.

[0105] 18 is a cross-sectional view showing a configuration example of magnetoresistive effect elements 210 and 220 according to the second embodiment of the present technology. The magnetoresistive effect element 220 according to the second embodiment differs from the magnetoresistive effect element 210 according to the first embodiment in that the VCMA coefficient is different from that of the magnetoresistive effect element 210, but the stacking order is the same. In the magnetoresistive effect element 210, a reference layer 211, a tunnel barrier layer 212, and a free layer 213 are stacked in this order from top to bottom, and the stacking order of the magnetoresistive effect element 220 is also the same.

[0106] 19 is a graph showing an example of the relationship between the perpendicular magnetic anisotropy and the write voltage of the magnetoresistive effect elements 210 and 220 according to the second embodiment of the present technology. In the figure, "a" indicates the characteristics of the magnetoresistive effect element 210, and "b" indicates the characteristics of the magnetoresistive effect element 220. The vertical axes of "a" and "b" in the figure indicate the perpendicular magnetic anisotropy K, and the horizontal axis indicates the write voltage.

[0107] For example, the VCMA coefficient of the magnetoresistive element 220 is set to twice that of the magnetoresistive element 210. Therefore, as illustrated in a and b in the figure, the slope of the line showing the characteristics of the magnetoresistive element 220 is twice that of the magnetoresistive element 210.

[0108] As shown in the figure, +V ｗ When +2V is applied, the perpendicular magnetic anisotropy K of the magnetoresistive element 210 becomes larger than 0, and the magnetization direction does not reverse. ｗ When this voltage is applied, the perpendicular magnetic anisotropy K of the magnetoresistive element 210 becomes approximately 0, and the magnetization direction is reversed.

[0109] As shown in FIG. 1B, +V ｗ When +2V is applied, the perpendicular magnetic anisotropy K of the magnetoresistive element 220 becomes approximately 0, and the magnetization direction is reversed. ｗ When a voltage is applied, the perpendicular magnetic anisotropy K of the magnetoresistive element 220 becomes smaller than 0, and the magnetization vector rotates within the XY plane. Therefore, the magnetization vector does not reverse for a certain period of time, and the state is maintained.

[0110] As described above, the stacking order of the magnetoresistive effect elements 210 and 220 is the same, but the VCMA coefficients are different, so that the polarity of the voltage that reverses the magnetization direction is the same in each element, but the values ​​are different, as illustrated in a and b in the figure. Therefore, the write circuit 116 applies voltages of the same polarity but different values ​​between the source line and the bit line when writing to the magnetoresistive effect element 210 and when writing to the magnetoresistive effect element 220. In the characteristics illustrated in a and b in the figure, when writing only to the magnetoresistive effect element 210, +2V ｗ is applied, and when writing to only the magnetoresistive element 220, +V ｗ In this way, by applying voltages of the same polarity but different values, the magnetization direction of only one of the magnetoresistive elements 210 and 220 can be reversed, thereby writing data.

[0111] The smaller the difference in the VCMA coefficients of the magnetoresistive elements 210 and 220, the smaller the difference in write voltage between when writing to only the magnetoresistive element 210 and when writing to only the magnetoresistive element 220. This makes voltage control easier than in the first embodiment, which requires polarity reversal.

[0112] 20 to 23 show the fluctuation of the magnetization vector obtained by computer simulation. The vertical axis of each of the figures represents the Z-axis component m of the magnetization vector. ｚ The horizontal axis represents time. The magnetization direction is +1, which is upward, and -1, which is downward. When the magnetization direction is upward, the resistance state is low, and when it is downward, the resistance state is high. In the simulation, the voltage was turned on 10 to 12 nanoseconds (ns) from a predetermined start time, with a relaxation time of 10 nanoseconds (ns) before and after.

[0113] 20 is a graph showing the fluctuation of the magnetization vector when writing to the memory cell 260 in the high-resistance-high-resistance state according to the second embodiment of the present technology. Graph a in the figure shows the fluctuation of the magnetization vector when writing from the high-resistance-high-resistance (HH) state to the high-resistance-low-resistance (HL) state. In this case, +V Ｗis applied, and only the magnetization direction of the magnetoresistive element 220 is reversed.

[0114] In the figure, b is a graph showing the change in the magnetization vector when the high resistance-high resistance (HH) state is changed to the low resistance-high resistance (LH) state by writing. Ｗ is applied, and only the magnetization direction of the magnetoresistive element 210 is reversed.

[0115] 21 is a graph showing the fluctuation of the magnetization vector when writing to the memory cell 260 in the high-resistance-low-resistance state according to the first embodiment of the present technology. In the figure, "a" is a graph showing the fluctuation of the magnetization vector when writing from the high-resistance-low-resistance (HL) state to the high-resistance-high-resistance (HH) state. In this case, +V Ｗ is applied, and only the magnetization direction of the magnetoresistive element 220 is reversed.

[0116] In the figure, b is a graph showing the change in the magnetization vector when the high resistance-low resistance (HL) state is changed to the low resistance-low resistance (LL) state by writing. Ｗ is applied, and only the magnetization direction of the magnetoresistive element 210 is reversed.

[0117] 22 is a graph showing the fluctuation of the magnetization vector when writing to the memory cell 260 in the low-resistance-high resistance state according to the first embodiment of the present technology. In the figure, "a" is a graph showing the fluctuation of the magnetization vector when writing from the low-resistance-high resistance (LH) state to the low-resistance-low resistance (LL) state. In this case, +V Ｗ is applied, and only the magnetization direction of the magnetoresistive element 220 is reversed.

[0118] In the figure, b is a graph showing the change in the magnetization vector when the low resistance-high resistance (LH) state is changed to the high resistance-high resistance (HH) state by writing. Ｗ is applied, and only the magnetization direction of the magnetoresistive element 210 is reversed.

[0119] 23 is a graph showing the fluctuation of the magnetization vector when writing to the memory cell 260 in the low-low resistance state according to the first embodiment of the present technology. In the figure, a is a graph showing the fluctuation of the magnetization vector when the low-low resistance (LL) state is changed to the low-high resistance (LH) state by writing. In this case, +V Ｗ is applied, and only the magnetization direction of the magnetoresistive element 220 is reversed.

[0120] In the figure, b is a graph showing the change in the magnetization vector when the low resistance-low resistance (LL) state is changed to the high resistance-low resistance (HL) state by writing. Ｗ is applied, and only the magnetization direction of the magnetoresistive element 210 is reversed.

[0121] 24 is a timing chart showing an example of a write operation of the nonvolatile memory 100 according to the second embodiment of the present technology. In the figure, "a" shows the timing chart when writing to the magnetoresistive effect element 210, and "b" shows the timing chart when writing to the magnetoresistive effect element 220.

[0122] As shown in FIG. 10A, the word line control circuit 119 transmits a high-level control signal to the word line WL of the row to be accessed during the period from timing T0 to T3.

[0123] Furthermore, the write circuit 116 applies +2V to the bit line of the column to be accessed during the period from timing T1 to T2. ｗ is supplied as a control signal via the bit / source line control circuit 117. As a result, a +2V ｗ This voltage causes data to be written only in the magnetoresistive element 210.

[0124] As shown in FIG. 10B, the word line control circuit 119 transmits a high-level control signal to the word line WL of the row to be accessed during the period from timing T0 to T3.

[0125] Furthermore, the write circuit 116 applies +V ｗ is supplied as a control signal via the bit / source line control circuit 117. As a result, the magnetoresistive element in the memory cell 260 to be accessed is supplied with a +V ｗ This voltage causes data to be written only in the magnetoresistive element 220.

[0126] It should be noted that the third modified example of the first embodiment can be applied to the second embodiment.

[0127] Thus, according to the second embodiment of the present technology, since the stacking order of the magnetoresistive effect elements 210 and 220 is the same but the VCMA coefficients are different, the write circuit 116 can write data individually using voltages of the same polarity but different values.

[0128] [First Modification] In the second embodiment described above, reference layer 211, tunnel barrier layer 212, and free layer 213 are stacked in this order from top to bottom in magnetoresistive element 210, and the same order is also used in magnetoresistive element 220. However, this stacking order is not limiting. Nonvolatile memory 100 in a first modification of the second embodiment differs from the first embodiment in that the stacking order is reversed in magnetoresistive elements 210 and 220.

[0129] 25 is a cross-sectional view showing a configuration example of magnetoresistive effect elements 210 and 220 according to a first modified example of the second embodiment of the present technology. In this first modified example of the second embodiment, in the magnetoresistive effect element 210, a free layer 213, a tunnel barrier layer 212, and a reference layer 211 are stacked in this order from top to bottom. In the magnetoresistive effect element 220, the layers are stacked in the same order.

[0130] The third modified example of the first embodiment can be applied to the first modified example of the second embodiment.

[0131] As described above, according to the first variant of the second embodiment of the present technology, the magnetoresistive effect elements 210 and 220 having the stacking order reversed are connected in series and data is written individually, thereby realizing high integration of the nonvolatile memory 100 in the same manner as the second embodiment.

[0132] [Second Modification] In the second embodiment described above, two magnetoresistive effect elements are arranged for each memory cell 260 to record two bits, but it is preferable to achieve even higher integration. The nonvolatile memory 100 in this second modification of the second embodiment differs from the second embodiment in that three magnetoresistive effect elements are arranged for each memory cell 260.

[0133] 26 is a cross-sectional view showing a configuration example of magnetoresistive effect elements 210, 220, and 230 in a second modified example of the second embodiment of the present technology. A memory cell 260 in the second modified example of the second embodiment differs from the second embodiment in that it further includes a magnetoresistive effect element 230.

[0134] Magnetoresistive elements 210, 220, and 230 are connected in series between a bit line and a source line. Magnetoresistive element 230 includes reference layer 231, tunnel barrier layer 232, and free layer 233, and the stacking order of these layers is the same as that of magnetoresistive elements 210 and 220. Magnetoresistive elements 210, 220, and 230 have different VCMA coefficients.

[0135] FIG. 27 is a diagram showing an example of a state of a memory cell 260 according to a second modification of the second embodiment of the present technology.

[0136] For example, the resistance value of the magnetoresistive element 210 in the low resistance state is R １ The resistance value in the high resistance state is a １ ×R １ The resistance value of the magnetoresistive element 220 in the low resistance state is R ２ The resistance value in the high resistance state is a ２ ×R ２ The resistance value of the magnetoresistive element 230 in the low resistance state is R ３ The resistance value in the high resistance state is a ３×R ３ Let us assume that: a ３ is a real number indicating the ratio of the resistance values ​​in the low resistance state to the resistance value in the high resistance state.

[0137] For ease of explanation, it is assumed that the following equation holds true: R ３ = c × R １ ...Formula 4 R ２ = b × R １ ...Formula 5 R １ =R...Formula 6 a １ = a ２ = a ３ = a ... Equation 7 In the above equation, c is R １ and R ３ It is a real number that indicates the ratio of

[0138] When Equations 4 to 7 are satisfied, the resistance values ​​of the magnetoresistive elements 210, 220, and 230 and their combined resistance are as shown in the figure. For example, if a = 4, b = 2, and c = 4, the resistance value can take on eight equal values.

[0139] FIG. 28 is a graph showing an example of the relationship between the perpendicular magnetic anisotropy and the write voltage of the magnetoresistive elements (for example, MTJ elements) 210, 220, and 230 in the second modification example of the second embodiment of the present technology.

[0140] For example, the VCMA coefficient of the magnetoresistive element 220 is set to be twice that of the magnetoresistive element 210 , and the VCMA coefficient of the magnetoresistive element 230 is set to be three times that of the magnetoresistive element 210 .

[0141] As illustrated in the figure, +V Ｗ When a write voltage of 100 V is applied, the perpendicular magnetic anisotropy K of the magnetoresistive elements 210 and 220 both becomes greater than 0, and the magnetization direction does not reverse. On the other hand, the perpendicular magnetic anisotropy K of the magnetoresistive element 230 becomes approximately 0, and the magnetization direction reverses.

[0142] Also, +2V ＷWhen a write voltage of 10 V is applied, the perpendicular magnetic anisotropy of the magnetoresistive element 210 becomes larger than 0, and the perpendicular magnetic anisotropy K of the magnetoresistive element 230 becomes smaller than 0, and no reversal of the magnetization direction occurs in these elements. On the other hand, the perpendicular magnetic anisotropy K of the magnetoresistive element 220 becomes approximately 0, and the magnetization direction is reversed.

[0143] Also, +3V Ｗ When a write voltage of 0 V is applied, the perpendicular magnetic anisotropy K of the magnetoresistive elements 210 and 220 becomes smaller than 0, and the magnetization direction does not reverse. On the other hand, the perpendicular magnetic anisotropy K of the magnetoresistive element 230 becomes approximately 0, and the magnetization direction reverses. In this way, by applying voltages of the same polarity but different values, the magnetization direction of only one of the magnetoresistive elements 210, 220, and 230 can be reversed, and data can be written.

[0144] It is also possible to arrange four or more magnetoresistive effect elements for each memory cell 260. Furthermore, the third modified example of the first embodiment can be applied to the second modified example of the second embodiment.

[0145] As described above, according to the second modification of the second embodiment of the present technology, three magnetoresistive effect elements are arranged for each memory cell 260, thereby enabling higher integration than the second embodiment.

[0146] [Third Modification] In the second modification of the second embodiment described above, the reference layer 211, the tunnel barrier layer 212, and the free layer 213 are stacked in this order from top to bottom in the magnetoresistive element 210, and the same order is also used in the magnetoresistive elements 220 and 230. However, the stacking order is not limited to this. The nonvolatile memory 100 in this third modification of the second embodiment differs from the second modification of the second embodiment in that the stacking order is reversed in each of the magnetoresistive elements 210, 220, and 230.

[0147] 29 is a cross-sectional view showing a configuration example of magnetoresistive effect elements 210, 220, and 230 according to a third modified example of the second embodiment of the present technology. In this third modified example of the second embodiment, in the magnetoresistive effect element 210, a free layer 213, a tunnel barrier layer 212, and a reference layer 211 are stacked in this order from above. The stacking order of the magnetoresistive effect elements 220 and 230 is the same as that of the magnetoresistive effect element 210.

[0148] As described above, according to the third modified example of the second embodiment of the present technology, the magnetoresistive effect elements 210, 220, and 230 having the stacking order reversed are connected in series, and data is written individually, thereby achieving high integration similar to the second modified example of the second embodiment.

[0149] 3. Third Embodiment In the second modification of the first embodiment described above, a shared structure is used and the stacking order of the magnetoresistive effect elements 210 and 220 is reversed, but this configuration is not limiting. The nonvolatile memory 100 in this third embodiment is obtained by applying the second embodiment to the second modification of the first embodiment.

[0150] 30 is a cross-sectional view showing a configuration example of magnetoresistive effect elements 210, 220, 230, and 240 according to the third embodiment of the present technology. Memory cell 260 according to the third embodiment differs from the second modification of the first embodiment in that memory cell 260 further includes free layer 233, tunnel barrier layer 232, reference layer 231, tunnel barrier layer 242, and free layer 243.

[0151] Between magnetoresistive element 220 and access transistor 250, free layer 233, tunnel barrier layer 232, reference layer 231, tunnel barrier layer 242, and free layer 243 are stacked in this order from top to bottom. Free layer 233, tunnel barrier layer 232, and reference layer 231 function as magnetoresistive element 230, and reference layer 231, tunnel barrier layer 242, and free layer 243 function as magnetoresistive element 240. In other words, reference layer 231 is shared by magnetoresistive elements 230 and 240.

[0152] Furthermore, the VCMA coefficient of the magnetoresistive effect element 210 is different from that of the magnetoresistive effect element 230, and the VCMA coefficient of the magnetoresistive effect element 220 is different from that of the magnetoresistive effect element 240. The magnetoresistive effect elements 230 and 240 are examples of the third and fourth magnetoresistive effect elements set forth in the claims.

[0153] Although magnetoresistive elements 210 and 220 share reference layer 211, they may not share it. Magnetoresistive elements 230 and 240 may also not share reference layer 221.

[0154] FIG. 31 is a diagram showing an example of a state of the memory cell 260 according to the third embodiment of the present technology.

[0155] For example, the resistance value of the magnetoresistive element 210 in the low resistance state is R １ The resistance value in the high resistance state is a １ ×R １ The resistance value of the magnetoresistive element 220 in the low resistance state is R ２ The resistance value in the high resistance state is a ２ ×R ２ The resistance value of the magnetoresistive element 230 in the low resistance state is R ３ The resistance value in the high resistance state is a ３ ×R ３ The resistance value of the magnetoresistive element 240 in the low resistance state is R ４ The resistance value in the high resistance state is a ４ ×R ４ Let us assume that: a ４ is a real number indicating the ratio of the resistance values ​​in the low resistance state to the resistance value in the high resistance state.

[0156] For ease of explanation, it is assumed that the following equation holds true: R ４ = d × R １ ...Formula 8 R ３ = c × R １ ...Formula 9 R ２ = b × R １ ...Formula 10 R １=R...Formula 11 a １ = a ２ = a ３ = a ４ = a ... Equation 12 In the above equation, d is R １ and R ４ It is a real number that indicates the ratio of

[0157] When Equations 8 to 12 are satisfied, the resistance values ​​of the magnetoresistive elements 210, 220, 230, and 240 and their combined resistance are as shown in the figure. For example, if a = 4, b = 2, c = 4, and d = 8, the resistance value can take on 16 uniform values.

[0158] FIG. 32 is a graph showing an example of the relationship between the perpendicular magnetic anisotropy and the write voltage of the magnetoresistive elements (for example, MTJ elements) 210, 220, 230, and 240 according to the third embodiment of the present technology.

[0159] FIG. 33 is a diagram showing an example of the states of the magnetoresistive elements 210, 220, 230, and 240 for each write voltage according to the third embodiment of the present technology.

[0160] For example, the VCMA coefficient of the magnetoresistive element 210 is set to twice that of the magnetoresistive element 230 , and the VCMA coefficient of the magnetoresistive element 240 is set to twice that of the magnetoresistive element 220 .

[0161] -2V ｗ When a voltage is applied, the perpendicular magnetic anisotropy K of the magnetoresistive element 220 becomes approximately 0, and the magnetization direction is reversed. On the other hand, the perpendicular magnetic anisotropy K of the magnetoresistive elements 210 and 230 becomes greater than 0, and no reversal of the magnetization direction occurs. Furthermore, the perpendicular magnetic anisotropy K of the magnetoresistive element 240 becomes smaller than 0, and the magnetization vector rotates within the XY plane.

[0162] -V ｗ When a voltage is applied, the perpendicular magnetic anisotropy K of the magnetoresistive element 240 becomes approximately 0, and the magnetization direction is reversed. On the other hand, the perpendicular magnetic anisotropy K of the magnetoresistive elements 210, 220, and 230 becomes greater than 0, and the magnetization direction is not reversed.

[0163] +Vｗ When a voltage is applied, the perpendicular magnetic anisotropy K of the magnetoresistive element 210 becomes approximately 0, and the magnetization direction is reversed. On the other hand, the perpendicular magnetic anisotropy K of the magnetoresistive elements 220, 230, and 240 becomes greater than 0, and the magnetization direction is not reversed.

[0164] +2V ｗ When a voltage is applied, the perpendicular magnetic anisotropy K of the magnetoresistive element 230 becomes approximately 0, and the magnetization direction is reversed. On the other hand, the perpendicular magnetic anisotropy K of the magnetoresistive elements 220 and 240 becomes greater than 0, and no reversal of the magnetization direction occurs. Furthermore, the perpendicular magnetic anisotropy K of the magnetoresistive element 210 becomes smaller than 0, and the magnetization vector rotates within the X-Y plane.

[0165] 34 is a timing chart showing an example of a write operation of the nonvolatile memory 100. In the figure, "a" shows the timing chart when writing to the magnetoresistive element 210, and "b" shows the timing chart when writing to the magnetoresistive element 220.

[0166] As shown in FIG. 10A, the word line control circuit 119 transmits a high-level control signal to the word line WL of the row to be accessed during the period from timing T0 to T3.

[0167] Furthermore, the write circuit 116 applies a voltage of +V ｗ is supplied as a control signal via the bit / source line control circuit 117. As a result, the magnetoresistive element in the memory cell 260 to be accessed is supplied with a +V ｗ This voltage causes data to be written only in the magnetoresistive element 210.

[0168] As shown in FIG. 10B, the word line control circuit 119 transmits a high-level control signal to the word line WL of the row to be accessed during the period from timing T0 to T3.

[0169] Furthermore, the write circuit 116 applies +2V to the bit line of the column to be accessed during the period from timing T1 to T2. ｗis supplied as a control signal via the bit / source line control circuit 117. As a result, a voltage of −2V is applied to the magnetoresistive element in the memory cell 260 to be accessed. ｗ This voltage causes data to be written only in the magnetoresistive element 220.

[0170] 35 is a timing chart showing an example of a write operation of the nonvolatile memory 100. In the figure, "a" shows the timing chart when writing to the magnetoresistive element 230, and "b" shows the timing chart when writing to the magnetoresistive element 240.

[0171] As shown in FIG. 10A, the word line control circuit 119 transmits a high-level control signal to the word line WL of the row to be accessed during the period from timing T0 to T3.

[0172] Furthermore, the write circuit 116 applies +2V to the source line of the column to be accessed during the period from timing T1 to T2. ｗ is supplied as a control signal via the bit / source line control circuit 117. As a result, a +2V ｗ This voltage causes data to be written only to the magnetoresistive element 230.

[0173] As shown in FIG. 10B, the word line control circuit 119 transmits a high-level control signal to the word line WL of the row to be accessed during the period from timing T0 to T3.

[0174] Furthermore, the write circuit 116 applies +V ｗ is supplied as a control signal via the bit / source line control circuit 117. As a result, a -V ｗ This voltage causes data to be written only to the magnetoresistive element 240.

[0175] The third modification of the first embodiment can be applied to the third embodiment.

[0176] As described above, in the third embodiment of the present technology, the second embodiment is applied to the second modified example of the first embodiment. That is, the stacking order of the magnetoresistive effect elements 210 and 230 is reversed from that of the magnetoresistive effect elements 220 and 240, and the VCMA coefficients of the magnetoresistive effect elements 210 and 220 are set to values ​​different from those of the magnetoresistive effect elements 230 and 240. This allows four bits to be recorded in each memory cell 260, enabling even higher integration.

[0177] 4. Fourth Embodiment In the first embodiment described above, the magnetoresistive effect elements 210 and 220 connected in series are provided in the nonvolatile memory 100, but these elements can also be provided in the arithmetic circuit. This fourth embodiment differs from the first embodiment in that the magnetoresistive effect elements 210 and 220 connected in series are provided in the arithmetic circuit.

[0178] 36 is a block diagram showing an example configuration of a calculation device 130 according to the fourth embodiment of the present technology. The calculation device 130 is a circuit that performs various calculations including product-sum calculations, and is used, for example, for linear transformations in a neural network. In the linear transformation, a product-sum calculation is performed between an input vector to a node and a weight.

[0179] The arithmetic unit 130 includes a word line bias application circuit 131, an input buffer 132, a digital-to-analog conversion unit 140, a memory cell array 200, a bit line bias circuit 150, and a pulse generator 133. The arithmetic unit 130 further includes a MAC (Multiply-ACcumulate) control circuit 134, an analog-to-digital conversion unit 160, a digital arithmetic unit 135, an output buffer 136, a write circuit 137, and an input / output circuit 138.

[0180] The word line bias application circuit 131 selects a word line in the memory cell array 200 and applies a bias to that line.

[0181] The input buffer 132 temporarily holds data to be written to the memory cell array 200 .

[0182] In the digital-to-analog conversion unit 140 , a DAC (Digital to Analog Converter) 141 is arranged for each column in the memory cell array 200 .

[0183] The bit line bias circuit 150 selects a bit line in the memory cell array 200 and applies a bias to the selected bit line. The pulse generator 133 generates a pulse signal for writing.

[0184] The MAC control circuit 134 controls the operation of each circuit within the arithmetic unit 130 .

[0185] In the analog-to-digital conversion unit 160 , an ADC (Analog to Digital Converter) 161 is arranged for each column in the memory cell array 200 .

[0186] The digital calculation unit 135 performs various calculations on the digital signal obtained by the ADC 161, such as signal accumulation and threshold value determination.

[0187] The output buffer 136 temporarily stores the data output from the digital calculation unit 135 .

[0188] The write circuit 137 writes data to a memory cell at the intersection of a selected word line and bit line.

[0189] The input / output circuit 138 transmits and receives data to be written to the memory cell array 200 and output data from the digital calculation unit 135 to and from the outside.

[0190] 37 is an example of a circuit diagram of the arithmetic device 130 according to the fourth embodiment of the present technology. An arithmetic value input circuit 134-1 is arranged in the MAC control circuit 134, and an arithmetic result output circuit 135-1 is arranged in the digital arithmetic unit 135. In addition, the bit line bias circuit 150 includes a selection transistor 151 and a multiplexer 152 for each column. The analog-to-digital conversion unit 160 includes an ADC 161 and a demultiplexer 162 for each column.

[0191] The configuration of the memory cell array 200 in the fourth embodiment is similar to that in the first embodiment.

[0192] The selection transistor 151 opens and closes a path between the write circuit 137 and the multiplexer 152 of the corresponding column. The multiplexer 152 selects a signal from one of the DAC 141 and the selection transistor 151 of the corresponding column and supplies the signal to the corresponding bit line. Note that the column of memory cells 260 is an example of a line as defined in the claims.

[0193] The demultiplexer 162 outputs the signal from the corresponding column to either the ADC 161 or a ground node.

[0194] First, data representing a weight is written into each memory cell 260. During writing, the MAC control circuit 134 controls the multiplexer 152 of each column to switch the input destination to the selection transistor 151 and control the selection transistor 151 to be accessed to be in the on state. The MAC control circuit 134 also controls the demultiplexer 162 of each column to connect the source line to the ground node.

[0195] The write circuit 137 supplies a pulse signal to the bit line or source line to write data to either the magnetoresistive element 210 or 220 in the memory cell 260. In the figure, the destination of the source line is omitted.

[0196] The resistance value of the memory cell 260 in the i-th row and j-th column after writing is R ｉ，ｊHere, i is an integer from 0 to N-1, and j is an integer from 0 to M-1. If I is the total number of columns, N is a value equal to or less than I, and if J is the total number of rows, M is a value equal to or less than J. As described above, if b≠1, the resistance value of memory cell 260 will be one of four values.

[0197] After writing, the MAC control circuit 134 controls the multiplexer 152 of each column to switch the input destination to the DAC 141 and controls the selection transistor 151 of each column to be in the off state. The MAC control circuit 134 also controls the demultiplexer 162 of each column to connect the source line to the ADC 161.

[0198] The calculation value input circuit 134-1 also assigns the digital signals in the input vector to each of the columns and supplies them to the corresponding DAC 141. ｉｎ （ｉ） In addition, the digital signal S ｉｎ （ｉ） is an example of an input signal as claimed.

[0199] The DAC 141 outputs a digital signal S ｉｎ （ｉ） voltage V ｉｎ （ｉ） and applied to the bit lines of the corresponding columns via multiplexer 152.

[0200] Voltage V ｉｎ （ｉ） By applying the current I ｏｕｔ （ｉ） Then, this current is expressed by the following formula:

[0201] In the above formula, I ＭＴＪ （ｊ） indicates the current flowing through the memory cell 260 in the j-th row.

[0202] From equation 13, the current I ｏｕｔ （ｉ） The value of is 1 / R ｉ，ｊ and the voltage V representing the input vector ｉｎ （ｉ）As described above, since the resistance value of the memory cell 260 is multi-valued, such as four-valued, the arithmetic unit 130 can perform a multiply-and-accumulate operation using multi-valued weights.

[0203] The ADC 161 detects the current I ｏｕｔ （ｉ） is converted into a digital signal S ｏｕｔ （ｉ） and supplies it to the operation result output circuit 135-1. As a result, the sum of products of the weight and the input vector is obtained.

[0204] The calculation result output circuit 135-1 outputs a digital signal S ｏｕｔ （ｉ） It performs various calculations such as threshold value judgment on the data and outputs the results.

[0205] The calculation result output circuit 135-1 outputs the digital signal S ｏｕｔ （ｉ） can also be output as is.

[0206] The calculation result output circuit 135-1 can also perform the calculation shown in the following equation using an activation function f() and output the result. As the activation function f(), for example, ReLU (Rectified Linear Unit) or a sigmoid function is used. T ｏｕｔ （ｉ） = f (S ｏｕｔ （ｉ） )

[0207] 38 is a timing chart showing an example of the operation of the arithmetic device 130 according to the fourth embodiment of the present technology. Before timing T0, the write circuit 137 writes data representing weights into each of the memory cells 260.

[0208] Then, during the period from timing T0 to T1, the MAC control circuit 134 outputs the digital signal S ｉｎ （ｉ） is input to the DAC 141. In the figure, signals are shown only for the i-th column and the (i+1)-th column. For example, the digital signal S ｉｎ （ｉ） and S ｉｎ （ｉ＋１） A value of "1" is input in hexadecimal.

[0209] The DACs 141 in the i-th and i+1-th columns output digital signals S ｉｎ （ｉ） and S ｉｎ （ｉ＋１） voltage V ｉｎ （ｉ） and V ｉｎ （ｉ＋１） and applied to the bit lines of the i-th and i+1-th columns. ｏｕｔ （ｉ） and I ｏｕｔ （ｉ＋１） is playing.

[0210] The ADCs 161 in the i-th and i+1-th columns detect the current I ｏｕｔ （ｉ） and I ｏｕｔ （ｉ＋１） is converted into a digital signal S ｏｕｔ （ｉ） and S ｏｕｔ （ｉ＋１） For example, the digital signal S ｏｕｔ （ｉ） and S ｏｕｔ （ｉ＋１） and the hexadecimal values ​​"7" and "3" are obtained.

[0211] 39 is a diagram illustrating an example of a control signal according to the fourth embodiment of the present technology. The MAC control circuit 134 outputs a digital signal S ｉｎ （ｉ） The input vector in which the above-mentioned inputs are arranged is supplied to the input buffer 132.

[0212] The MAC control circuit 134 also supplies an enable signal EN_DAC to the digital-to-analog conversion unit 140 and an enable signal EN_ADC to the analog-to-digital conversion unit 160. The MAC control circuit 134 also supplies an enable signal EN_LAT to a latch circuit (not shown) in the digital calculation unit 170.

[0213] The digital calculation unit 135 supplies an output vector in which the calculation results for each column are arranged to the output buffer 136 .

[0214] 40 is a timing chart showing an example of the operation of the MAC control circuit 134 and the digital calculation unit 135 according to the fourth embodiment of the present technology. The MAC control circuit 134 outputs the digital signal S ｉｎ （０） is input to the input buffer 132.

[0215] Furthermore, the MAC control circuit 134 supplies a high-level enable signal EN_DAC to the DAC 141 during the period from timing T1 to T3, thereby transmitting the digital signal S ｉｎ （０） During this period, the MAC control circuit 134 also supplies a high level EN_ADC to the ADC 161 to convert the current into a digital signal S ｏｕｔ （０） Execute the conversion to.

[0216] Within a period from timing T2 to T3, which is a certain time after timing T1, the MAC control circuit 134 supplies a high-level enable signal EN_LAT to the latch circuit, thereby storing the digital signal S ｏｕｔ （０） The time period from timing T1 to timing T2 is set to a value sufficient for the current to stabilize (for example, one cycle of the clock signal CLK).

[0217] The digital calculation unit 135 calculates the digital signal S in the output vector after the timing T2. ｏｕｔ （０） Output.

[0218] Then, the MAC control circuit 134 outputs the digital signal S ｉｎ （１） Then, by the same control, the digital signal S ｏｕｔ （１） The digital signal S ｉｎ （２） The same control is carried out thereafter.

[0219] 41 is a flowchart showing an example of the operation of the arithmetic device 130 according to the fourth embodiment of the present technology. This operation is started, for example, when a predetermined application related to a neural network is executed.

[0220] The write circuit 137 writes the data representing the weight into each of the memory cells 260 (step S951). ｉｎ （ｉ） is input to the input buffer 132 (step S952).

[0221] The DAC 141 also converts the digital signal S ｉｎ （ｉ） The voltage is converted from the voltage to a digital voltage, that is, a digital to analog conversion is performed, and the voltage is applied to the bit line (step S953).

[0222] The MAC control circuit 134 determines whether a certain time has elapsed (step S954). The time in step S954 is set to a value sufficient for the current to stabilize.

[0223] If the certain time has not elapsed (step S954: No), the MAC control circuit 134 repeats step S954. If the certain time has elapsed (step S954: Yes), the ADC 161 converts the current into a digital signal S ｏｕｔ （ｉ） In addition, the digital calculation unit 135 converts the digital signal S ｏｕｔ （ｉ） (step S955). After step S955, the calculation device 130 ends the calculation.

[0224] As shown in FIG. 42, a plurality of operation blocks 182 can be provided in the operation device 180. Circuits such as the memory cell array shown in FIG. 36 are arranged in this operation block 182. Data is transferred between operation blocks 182 via a bus 183. Input / output data to and from the outside is transmitted and received via an interface 181.

[0225] The configuration illustrated in Fig. 42 is used, for example, for calculations in a multi-stage neural network. A stage in the neural network is assigned to each calculation block 182, and the weight of the corresponding stage is recorded in each calculation block 182. The calculation device 130 then transfers the calculation result of a given stage to the calculation block 182 of the next stage, allowing the product-sum calculations of each stage to be performed consecutively.

[0226] The VC-MRAM can be embedded in a logic circuit, and the arithmetic unit 130 that expresses weights as multiple values ​​can be realized by a circuit that embeds the VC-MRAM and the logic circuit.

[0227] Note that the first to fifth modifications of the first embodiment, the second embodiment, the first, second, and third modifications of the second embodiment, and the third embodiment can all be applied to the fourth embodiment.

[0228] In this way, according to the fourth embodiment of the present technology, the ADC 161 for each column ｉ，ｊ and voltage V ｉｎ （ｉ） The arithmetic unit 130 can perform a product-sum operation to convert the current representing the sum of products of the current and the current into a digital signal.

[0229] 5. Configuration Examples of Electronic Devices Hereinafter, with reference to FIGS. 43 to 46 , an imaging device 310, a distance measuring device 410, and a game device 900 will be described as electronic devices to which the above-described embodiments (including modified examples) of the present disclosure are applied.

[0230] [5.1 Imaging Device] First, an imaging device 310 will be described as an electronic device to which the above-described embodiment (including modified examples) of the present disclosure is applied, with reference to Fig. 43. Fig. 43 is a diagram showing an example of a schematic configuration of the imaging device 310. Examples of the imaging device 310 include electronic devices such as digital still cameras, video cameras, smartphones and mobile phones with imaging functions.

[0231] 43, the imaging device 310 includes an optical system 311, a shutter device 312, an imaging element 313, a control circuit (drive circuit) 314, a signal processing circuit 315, a monitor 316, and a memory 317. The imaging device 310 is capable of capturing still images and moving images.

[0232] The optical system 311 includes one or more lenses. The optical system 311 guides light from a subject (incident light) to the image sensor 313, and forms an image on the light receiving surface of the image sensor 313.

[0233] The shutter device 312 is disposed between the optical system 311 and the image sensor 313. The shutter device 312 controls the light irradiation period and the light blocking period for the image sensor 313 under the control of the control circuit 314.

[0234] The image sensor 313 accumulates signal charges for a certain period of time in response to light that is focused on the light receiving surface via the optical system 311 and the shutter device 312. The signal charges accumulated in the image sensor 313 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 314.

[0235] The control circuit 314 outputs a drive signal that controls the transfer operation of the image sensor 313 and the shutter operation of the shutter device 312 , thereby driving the image sensor 313 and the shutter device 312 .

[0236] The signal processing circuit 315 performs various signal processing on the signal charges output from the image sensor 313. The image (image data) obtained by the signal processing performed by the signal processing circuit 315 is supplied to a monitor 316 and also to a memory 317.

[0237] The monitor 316 displays moving or still images captured by the image sensor 313 based on the image data supplied from the signal processing circuit 315. As the monitor 316, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel is used.

[0238] The memory 317 stores image data supplied from the signal processing circuit 315, that is, image data of moving images or still images captured by the image sensor 313. The memory 317 can be applied to an embodiment of the present disclosure.

[0239] [15.2 Distance Measuring Device] Next, a distance measuring device 410 will be described as an electronic device to which the above-described embodiment (including modified examples) of the present disclosure is applied, with reference to Fig. 44. Fig. 44 is a diagram showing an example of a schematic configuration of the distance measuring device 410.

[0240] 44, the distance measuring device (distance image sensor) 410 includes a light source unit 411, an optical system 412, a solid-state imaging device (image sensor) 413, a control circuit (drive circuit) 414, a signal processing circuit 415, a monitor 416, and a memory 417. The distance measuring device 410 projects light from the light source unit 411 toward an object and receives light (modulated light or pulsed light) reflected from the surface of the object, thereby obtaining a distance image according to the distance to the object.

[0241] The light source unit 411 projects light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line, is used as the light source unit 411. The laser diode array is supported by a predetermined drive unit (not shown) and is scanned in a direction perpendicular to the direction in which the laser diodes are arranged.

[0242] The optical system 412 has one or more lenses. The optical system 412 guides light from the subject (incident light) to the solid-state imaging device 413, and forms an image on the light receiving surface (sensor portion) of the solid-state imaging device 413.

[0243] The solid-state imaging device 413 accumulates signal charges in response to light that is imaged on the light-receiving surface via the optical system 412. A distance signal indicating a distance determined from a light-receiving signal (APD OUT) output from the solid-state imaging device 413 is supplied to a signal processing circuit 415. As the solid-state imaging device 413, for example, a solid-state imaging element such as an image sensor is used.

[0244] The control circuit 414 outputs a drive signal (control signal) that controls the operation of the light source unit 411, the solid-state imaging device 413, etc., and drives the light source unit 411, the solid-state imaging device 413, etc.

[0245] The signal processing circuit 415 performs various signal processing on the distance signal supplied from the solid-state imaging device 413. For example, the signal processing circuit 415 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 415 is supplied to a monitor 416 and also to a memory 417.

[0246] The monitor 416 displays the distance image captured by the solid-state imaging device 413 based on the image data supplied from the signal processing circuit 415. As the monitor 416, for example, a panel-type display device such as a liquid crystal panel or an organic EL panel is used.

[0247] The memory 417 stores image data supplied from the signal processing circuit 415, that is, image data of the distance image captured by the solid-state imaging device 413. The memory 417 can be applied to any of the embodiments of the present disclosure.

[0248] 45 and 46, a gaming device 900 will be described as an example of an electronic device to which the above-described embodiment (including modifications) of the present disclosure is applied. Fig. 45 is a perspective view (exterior perspective view) showing an example of a schematic configuration of the gaming device 900. Fig. 46 is a block diagram showing an example of a schematic configuration of the gaming device 900.

[0249] As shown in FIG. 45, the game device 900 has an external appearance in which various components are arranged inside and outside a horizontally elongated, flat outer casing 901, for example.

[0250] A display panel 902 is provided in the longitudinal center of the front surface of the outer casing 901. Operation keys 903 and 904 are provided on the left and right sides of the display panel 902, spaced apart from each other in the circumferential direction. An operation key 905 is provided at the bottom end of the front surface of the outer casing 901. The operation keys 903, 904, and 905 function as direction keys, enter keys, etc., and are used to select menu items displayed on the display panel 902, progress through the game, etc.

[0251] On the top surface of the outer casing 901, there are provided a connection terminal 906 for connecting an external device, a power supply terminal 907, a light receiving window 908 for infrared communication with an external device, and the like.

[0252] 46, the game device 900 includes an arithmetic processing unit 910 including a CPU (Central Processing Unit), a storage unit 920 that stores various information, and a control unit 930 that controls each component of the game device 900. The arithmetic processing unit 910 and the control unit 930 are supplied with power from, for example, a battery (not shown).

[0253] The arithmetic processing unit 910 generates a menu screen for allowing the user to set various information or select an application, and also executes the application selected by the user.

[0254] The storage unit 920 stores various information set by the user. The embodiments of the present disclosure can be applied to the storage unit 920.

[0255] The control unit 930 has an input reception unit 931, a communication processing unit 933, and a power control unit 935. The input reception unit 931, for example, detects the states of the operation keys 903, 904, and 905. The communication processing unit 933 performs communication processing with external devices. The power control unit 935 controls the power supplied to each unit of the game device 900.

[0256] Furthermore, the embodiments of the present disclosure can be implemented in various electronic devices that can be equipped with a memory (storage unit) as described above. For example, in addition to the imaging device 310 and the game device 900, the embodiments of the present disclosure can be applied to various electronic devices such as notebook PCs (Personal Computers), mobile devices (e.g., smartphones and tablet PCs), PDAs (Personal Digital Assistants), wearable devices, and music devices.

[0257] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0258] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0259] The present technology may also be configured as follows: (1) A nonvolatile memory comprising: a plurality of magnetoresistive effect elements connected in series between first and second control lines; and a write circuit that writes data to any of the plurality of magnetoresistive effect elements. (2) The nonvolatile memory according to (1), wherein the plurality of magnetoresistive effect elements include first and second magnetoresistive effect elements, each of the first and second magnetoresistive effect elements including a plurality of stacked layers, and wherein the stacking order of the first magnetoresistive effect elements is opposite to that of the second magnetoresistive effect elements. (3) The nonvolatile memory according to (2), wherein the write circuit applies voltages between the first and second control lines that have different polarities when writing to the first magnetoresistive effect elements and when writing to the second magnetoresistive effect elements. (4) The nonvolatile memory according to (2) or (3), wherein the first magnetoresistive element includes a first free layer, a first tunnel barrier layer, and a first reference layer, and the second magnetoresistive element includes a second free layer, a second tunnel barrier layer, and a second reference layer. (5) The nonvolatile memory according to (2) or (3), wherein the first magnetoresistive element includes a first free layer and a first tunnel barrier layer, the second magnetoresistive element includes a second free layer and a second tunnel barrier layer, and the first and second magnetoresistive elements share a predetermined reference layer. (6) The nonvolatile memory according to (2) or (3), wherein the first magnetoresistive element includes a pair of a first free layer, a first tunnel barrier layer, and a first reference layer whose magnetizations are exchange-coupled, and the second magnetoresistive element includes a pair of a second free layer, a second tunnel barrier layer, and a second reference layer whose magnetizations are exchange-coupled. (7) The nonvolatile memory according to (2) or (3), wherein the first magnetoresistive element includes a pair of a first free layer and a first tunnel barrier layer whose magnetizations are exchange-coupled, the second magnetoresistive element includes a pair of a second free layer and a second tunnel barrier layer whose magnetizations are exchange-coupled, and the first and second magnetoresistive elements share a predetermined reference layer.(8) The nonvolatile memory according to (1), wherein each of the plurality of magnetoresistive elements includes a plurality of stacked layers, the stacking order of the plurality of magnetoresistive elements is the same, and the VCMA coefficients of the plurality of magnetoresistive elements are different. (9) The nonvolatile memory according to (8), wherein the plurality of magnetoresistive elements include first and second magnetoresistive elements, and the write circuit applies voltages of the same polarity but different values ​​when writing to the first magnetoresistive element and when writing to the second magnetoresistive element. (10) The nonvolatile memory described in (1), wherein the plurality of magnetoresistive effect elements include first, second, third and fourth magnetoresistive effect elements, each of the first, second, third and fourth magnetoresistive effect elements includes a plurality of stacked layers, the stacking order of the first and third magnetoresistive effect elements is reverse to the stacking order of the second and fourth magnetoresistive effect elements, the VCMA coefficient of the first magnetoresistive effect element is different from the VCMA coefficient of the third magnetoresistive effect element, and the VCMA coefficient of the second magnetoresistive effect element is different from the VCMA coefficient of the fourth magnetoresistive effect element. (11) An arithmetic device comprising: a memory cell array in which a plurality of memory cells, each having a plurality of magnetoresistive effect elements connected in series, are arranged in a two-dimensional lattice pattern; a digital arithmetic unit that supplies a predetermined digital signal as an input signal for each line in the memory cell array; a digital-analog conversion unit that converts the input signal into a voltage and supplies it to the corresponding line; and an analog-digital conversion unit that converts, for each line, a current indicating the sum of the product of the reciprocal of the resistance value of each memory cell in the line and the voltage into a digital signal and supplies it to the digital arithmetic unit. (12) The arithmetic device according to (11), further comprising a write circuit that writes data representing the resistance value into each of the plurality of memory cells by applying a voltage.

[0260] 100 Nonvolatile memory 111, 138 Input / output circuit 112 Control circuit 113 Voltage generation circuit 114 Bit / source line address decoder 115 Read circuit 116, 137 Write circuit 117 Bit / source line control circuit 118 Word line address decoder 119 Word line control circuit 120 Sense amplifier 130, 180 Arithmetic unit 131 Word line bias application circuit 132 Input buffer 133 Pulse generator 134 MAC (Multiply-ACcumulate) arithmetic circuit 134-1 Calculation value input circuit 135 Digital arithmetic unit 135-1 Calculation result output circuit 136 Output buffer 140 Digital-to-analog conversion unit 141 DAC 150 Bit line bias circuit 151 Selection transistor 152 Multiplexer 160 Analog-to-digital conversion unit 161 ADC 162 Demultiplexer 181 Interface 182 Arithmetic block 183 Bus 200 Memory cell array 210, 220, 230, 240 Magnetoresistive effect element 211, 221, 231 Reference layer 212, 222, 232, 242 Tunnel barrier layer 213, 215, 223, 225, 233, 243 Free layer 214, 224 Isolation layer 250 Access transistor 251 Gate 252 Source 253 Drain 260 Memory cell 261, 263 Contact layer 262 Connection layer 310 Imaging device 311 Optical system 312 Shutter device 313 Imaging element 314 Control circuit 315 Signal processing circuit 316, 416 Monitor 317, 417 Memory 410 Distance measuring device 411 Light source unit 412 Optical system 413 Solid-state imaging device 414 Control circuit 415 Signal processing circuit 900 Game machine 901 Outer casing 902 Display panel 903 to 905 Operation keys 906 Connection terminal 907 Supply terminal 908 Light receiving window 910 Arithmetic processing unit 920 Storage unit 930 Control unit 931 Input reception unit 933 Communication processing unit 935 Power supply control unit

Claims

1. A non-volatile memory comprising: a plurality of magnetoresistance elements connected in series between first and second control lines; and a write circuit for writing data to any one of the plurality of magnetoresistance elements.

2. A non-volatile memory as described in claim 1, wherein the plurality of magnetoresistance effect elements include first and second magnetoresistance effect elements, each of the first and second magnetoresistance effect elements including a plurality of stacked layers, and the stacking order of the first magnetoresistance effect element is reverse to the stacking order of the second magnetoresistance effect element.

3. A non-volatile memory as described in claim 2, wherein said write circuit applies voltages of different polarities between said first and second control lines when writing to said first magnetoresistance effect element and when writing to said second magnetoresistance effect element.

4. A non-volatile memory as described in claim 2, wherein the first magnetoresistance effect element includes a first free layer, a first tunnel barrier layer and a first reference layer, and the second magnetoresistance effect element includes a second free layer, a second tunnel barrier layer and a second reference layer.

5. A non-volatile memory as described in claim 2, wherein the first magnetoresistance effect element includes a first free layer and a first tunnel barrier layer, the second magnetoresistance effect element includes a second free layer and a second tunnel barrier layer, and the first and second magnetoresistance effect elements share a predetermined reference layer.

6. A non-volatile memory as described in claim 2, wherein the first magnetoresistance effect element includes a pair of a first free layer, a first tunnel barrier layer, and a first reference layer whose magnetizations are exchange-coupled, and the second magnetoresistance effect element includes a pair of a second free layer, a second tunnel barrier layer, and a second reference layer whose magnetizations are exchange-coupled.

7. A non-volatile memory as described in claim 2, wherein the first magnetoresistance effect element includes a pair of a first free layer and a first tunnel barrier layer whose magnetizations are exchange-coupled, the second magnetoresistance effect element includes a pair of a second free layer and a second tunnel barrier layer whose magnetizations are exchange-coupled, and the first and second magnetoresistance effect elements share a predetermined reference layer.

8. A non-volatile memory as described in claim 1, wherein each of the plurality of magnetoresistance effect elements includes a plurality of stacked layers, the stacking order of each of the plurality of magnetoresistance effect elements is the same, and the VCMA coefficients of each of the plurality of magnetoresistance effect elements are different.

9. A non-volatile memory as described in claim 8, wherein the plurality of magnetoresistance effect elements include first and second magnetoresistance effect elements, and the write circuit applies voltages of the same polarity but different values ​​when writing to the first magnetoresistance effect element and when writing to the second magnetoresistance effect element.

10. A non-volatile memory as described in claim 1, wherein the plurality of magnetoresistance effect elements include first, second, third and fourth magnetoresistance effect elements, each of the first, second, third and fourth magnetoresistance effect elements includes a plurality of stacked layers, the stacking order of the first and third magnetoresistance effect elements is reverse to the stacking order of the second and fourth magnetoresistance effect elements, the VCMA coefficient of the first magnetoresistance effect element is different from the VCMA coefficient of the third magnetoresistance effect element, and the VCMA coefficient of the second magnetoresistance effect element is different from the VCMA coefficient of the fourth magnetoresistance effect element.

11. A calculation device comprising: a memory cell array in which a plurality of memory cells, each having a plurality of magnetoresistance effect elements connected in series, are arranged in a two-dimensional lattice; a digital calculation unit that supplies a predetermined digital signal as an input signal for each line in the memory cell array; a digital-to-analog conversion unit that converts the input signal into a voltage and supplies it to the corresponding line; and an analog-to-digital conversion unit that converts, for each line, a current indicating the sum of the product of the reciprocal of the resistance value of each memory cell in the line and the voltage into a digital signal and supplies it to the digital calculation unit.

12. The arithmetic device according to claim 11, further comprising a write circuit for writing data representing said resistance value into each of said plurality of memory cells by applying a voltage thereto.

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