Semiconductor storage device, storage system, and writing method

Abstract

Provided is a semiconductor storage device that is capable of stably reading and writing data at high speed. A semiconductor storage device 1000 comprises a memory cell array in which a plurality of memory cells 100 are arranged in a matrix. Each memory cell 100 includes a pair of magnetic tunnel junction elements that are neighboring in the row direction of the memory cell array, and each of the magnetic tunnel junction elements has a first node and an internal node. Each memory cell 100 further includes a first electrode that is provided so as to connect to the internal nodes of the pair of magnetic tunnel junction elements, and has a second node and a third node that are for conducting write currents. The semiconductor storage device 1000 further comprises a writing control circuit that supplies write currents to the first electrodes so as to cause the resistance conditions of the magnetic tunnel junction elements in each pair to differ from each other.

Description

Semiconductor memory device, memory system, and writing method

[0001] The present invention relates to a semiconductor memory device using a magnetic tunnel junction element, a storage system using the semiconductor memory device, and a writing method.

[0002] (Background of magnetic random access memory)

[0003] A nonvolatile memory device using a magnetoresistive effect element (MRAM: Magnetic Random Access Memory or Magnetoresistive Random Access Memory) has been attracting attention as a next-generation logic integrated circuit.

[0004] One such MRAM configuration is known as the Spin Transfer Torque (STT) MRAM. However, in STT-MRAM, a large voltage is applied across the device's tunnel oxide during write operations, resulting in a continuous trade-off between data retention, write endurance, and write speed. Thus, despite its maturity, STT-MRAM technology remains limited in its ability to meet the requirements of high-speed RAM applications, which require a combination of high speed, infinite endurance, and sufficient data retention.

[0005] As an MRAM configuration that can solve such problems, a three-terminal SOT (Spin Orbit Torque)-MRAM (Magnetic Random Access Memory) is known to be suitable for nonvolatile memories that require high-speed writing. For example, Patent Documents 1 and 2 disclose three-terminal SOT-MRAMs that are configured from a stack of a channel layer, a recording layer, a barrier layer, and a reference layer.

[0006] For example, the memory cell of the SOT-MRAM disclosed in Patent Document 1 is composed of a stack of a channel layer, a recording layer, a barrier layer, and a reference layer from the bottom, and has three terminals.

[0007] The channel layer is a conductive layer made of a heavy metal or the like, and is a region that generates a spin-orbit torque when a write current flows through this layer. The recording layer is made of a magnetic material, and is a magnetic layer whose magnetization M is variable between the +axis and -axis directions due to the spin-orbit torque generated by the write current flowing through the channel layer. The barrier layer is a non-magnetic layer made of a tunnel insulating layer.

[0008] The reference layer is made of a magnetic material, and the direction of the magnetization M is fixed.

[0009] When writing data to the SOT-MRAM, a voltage corresponding to the data to be written is applied between the second and third terminals, and a write current is passed through the channel layer. This causes a spin-orbit torque to act, and the direction of the magnetization M of the recording layer changes according to the direction of the write current. At this time, no current flows through the tunnel insulating layer.

[0010] When the magnetization M of the recording layer and the magnetization of the reference layer are oriented in the same direction (parallel state), the resistance between the reference layer and the recording layer is small. On the other hand, when the magnetization of the recording layer and the magnetization of the reference layer are oriented in opposite directions (antiparallel state), the resistance between the reference layer and the recording layer is relatively large. Data is assigned to the changing resistance value.

[0011] When reading data from the SOT-MRAM, a read voltage is applied between the first terminal and the second terminal or the third terminal, and data corresponding to the magnitude of the read current flowing through a magnetic tunnel junction (MTJ) consisting of a recording layer, a barrier layer, and a reference layer is output.

[0012] The above-described configuration of SOT-MRAM allows for the elimination of high voltage across the tunnel oxide of the device during writing.

[0013] The configuration disclosed in Patent Document 2 is such that even when the integration level is improved, the write current is suppressed and the decrease in read speed is prevented.

[0014] On the other hand, SOT-MRAM is a non-volatile memory technology that uses pure spin current due to the spin Hall effect as described above to perform high-speed writing. As one configuration for this, the use of topological insulators with a strong spin Hall effect is being considered to reduce the write current and power consumption.

[0015] Here, "topological insulators" refers to a group of materials that have an insulator-like state inside but a metallic conductive state on their surface.

[0016] The memory cell configuration of SOT-MRAM using such topological materials was formed by molecular beam epitaxial crystal growth method (Bi, Sb). ２ Te ３ A structure has also been proposed in which a topological insulator is placed as the bottom electrode, and a Ru (5 nm) intermediate layer with a crystalline structure similar to that of the topological insulator is used, on which a CoFeB (2.5 nm) / MgO (2 nm) / CoFeB (5 nm) MTJ is fabricated. In this case, a heat treatment at temperatures between 250°C and 300°C is reported to crystallize the CoFeB magnetic layer. It has been reported that a three-terminal SOT-MRAM device has been fabricated using this process (for example, see Non-Patent Document 1).

[0017] On the other hand, antiferromagnetic materials are attracting attention as a replacement for ferromagnetic materials in the hope of further improving the functionality of devices. Antiferromagnetic materials have the following advantages: (i) they do not produce stray magnetic fields, allowing for high-density devices with simple structures, (ii) their spin resonance frequency is higher at THz than that of ferromagnetic materials (GHz), enabling higher speeds, and (iii) they offer greater freedom in material selection.

[0018] However, because antiferromagnets do not have spontaneous magnetization, it is generally difficult to detect and control the spontaneous response resulting from the spin structure.

[0019] In contrast, the topological antiferromagnetic metal Mn ３ Sn is being actively researched as a candidate material for nonvolatile memory that will lead to the realization of terahertz electronic devices.

[0020] Mn ３Sn is an antiferromagnetic material in which a non-collinear spin structure, called the inverse 120-degree structure, appears at temperatures as high as 430 K. This antiferromagnetic spin structure exhibits a macroscopic broken time-reversal symmetry even in a zero-magnetization state, similar to the case of ferromagnetic order. This is due to the strongly ordered spin structure (cluster magnetic octupole) in which six spins, each consisting of three sublattices, are arranged in a two-layer kagome lattice.

[0021] Here, a "topological antiferromagnet" is a Weyl semimetal that exhibits a topological semimetal state in which the interior is semimetallic and the surface is metallic.

[0022] For example, the spin Hall effect, which converts electric current into spin current, has been studied mainly in transition metals with large spin-orbit coupling. However, the antiferromagnetic material Mn ３ The anomalous Hall effect was also observed in Sn, and furthermore, the "magnetic spin Hall effect" was observed in Mn stacked with a ferromagnetic material. ３ It has been reported that surface spin accumulation occurs on the surface of Sn, generating a spin torque on the magnetization of an adjacent ferromagnetic material (for example, Non-Patent Documents 2 and 3).

[0023] JP 2018-157108 A JP 2023-35644 A

[0024] https: / / www.titech.ac.jp / news / 2021 / 062339https: / / www.jst.go.jp / pr / announce / 20190117-2 / index.htmlhttps: / / www.jst.go.jp / pr / announce / 20151029-2 / index.html

[0025] As mentioned above, MRAM is a random access memory that is non-volatile and has excellent properties such as high speed operation and high durability. For these reasons, it is considered the leading candidate for a technology suitable for integrating non-volatile memory with integrated circuits.

[0026] Although SOT-MRAM can reduce the energy required for writing, it is necessary to form memory cells at a higher density in order to improve the storage capacity.

[0027] However, in order to realize a high-density, high-capacity memory, the change in resistance value that occurs in each memory cell due to writing data becomes relatively small.

[0028] Furthermore, in a semiconductor memory device, it is also necessary to stably reproduce stored data when the power is turned off and then turned on again.

[0029] The current situation is that sufficient research has not been carried out to date on a circuit configuration that enables stable writing and reading of data under such conditions.

[0030] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device capable of stable and high-speed data reading and writing in an SOT-MRAM, and a method for writing data thereto.

[0031] Another object of the present invention is to provide a semiconductor memory device that can stably reproduce stored data when the power is turned on again, and a method for writing data thereto.

[0032] (Item 1)

[0033] According to one aspect of the present invention, a semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell including a pair of magnetic tunnel junction elements adjacent to each other in a row direction of the memory cell array, each of the magnetic tunnel junction elements having a first node and an internal node, and further including a first electrode having a second node and a third node for conducting a write current and connected to the internal nodes of the pair of magnetic tunnel junction elements, and further including a write control circuit supplying the write current to the first electrode of the pair of magnetic tunnel junction elements so as to cause the resistance states of the pair of magnetic tunnel junction elements to differ from each other (Item 2).

[0034] Preferably, in the configuration of item 1, there are provided a plurality of first interconnections provided in the column direction of the memory cell array so as to be shared by the memory cells and for supplying a write current between the second node and the third node, a plurality of write transistors for opening and closing a current path so that a write current is conducted between the first electrode of a selected memory cell and the first interconnections in a write operation, and a write control circuit selectively controls the write transistor of a memory cell to which data is written in a write operation, and supplies the write current via the first interconnections to the first electrodes of a pair of magnetic tunnel junction elements included in the selected memory cell so as to make the resistance states of the first electrodes different from each other (item 3).

[0035] Preferably, in the configuration of item 2, the plurality of first wirings include a plurality of bit lines provided so as to be commonly connected to the second nodes of the magnetic tunnel junction elements in the plurality of memory cells in the column direction, and a plurality of source lines provided commonly to the magnetic tunnel junction elements in the plurality of memory cells in the column direction, the write transistors are provided between the third nodes and the source lines, and the write control circuit includes a write decoder that selectively controls opening and closing of the write transistors, and a driver circuit that supplies write currents, via the bit lines and source lines, to the first electrodes of the pair of magnetic tunnel junction elements in the selected memory cell in directions that cause the first electrodes to have different resistance states.

[0036] Preferably, in the configuration of either item 2 or item 3, the memory cell further includes a plurality of second wirings provided in common to the first nodes in a plurality of memory cells in the column direction for detecting the resistance between the first node and the first electrode, a plurality of read transistors for opening and closing current paths between the bit lines and the second wirings in a read operation, and a read control circuit for selectively controlling the read transistors of memory cells from which data is read in a read operation to read, as complementary signals, the resistance between the first nodes of a pair of magnetic tunnel junction elements included in the selected memory cell and a corresponding pair of second wirings (item 5).

[0037] Preferably, in the configuration of item 2, the second nodes of the pair of magnetic tunnel junction elements in the memory cell are electrically connected to each other, the plurality of first wirings include a plurality of pairs of bit lines provided in common to the pairs of magnetic tunnel junction elements in the plurality of memory cells in the column direction, the write transistors are provided between the third nodes and the bit lines, respectively, and the write control circuit includes a write decoder that selectively controls opening and closing of the write transistors, and a driver circuit that supplies write currents to the first electrodes of the pair of magnetic tunnel junction elements in the selected memory cell via the pair of bit lines in directions that cause the first electrodes to have different resistance states.

[0038] Preferably, in the configuration of item 5, the memory cell further includes a plurality of second wirings provided in common to the first nodes in a plurality of memory cells in the column direction for detecting the resistance between the first node and the first electrode, a plurality of read transistors for opening and closing the current path between the bit line and the second wiring in a read operation, and a read control circuit for selectively controlling the write transistor and read transistor of the memory cell from which data is read in a read operation and reading the resistance between the first nodes of the pair of magnetic tunnel junction elements included in the selected memory cell and the corresponding pair of second wirings as complementary signals (item 7).

[0039] Preferably, in the configuration of item 2, the plurality of first wirings include a plurality of bit lines provided in common to the second nodes of the magnetic tunnel junction elements in the plurality of memory cells in the column direction, and a plurality of source lines provided in common to each of the third nodes of a pair of magnetic tunnel junction elements in the plurality of memory cells in the column direction, the write transistors are provided between the second nodes and the bit lines, and the write control circuit includes a write decoder that selectively controls opening and closing of the write transistors, and a driver circuit that supplies write currents, via the bit lines and source lines, to the first electrodes of the pair of magnetic tunnel junction elements in the selected memory cell in directions that cause the first electrodes to have different resistance states. (Item 8)

[0040] Preferably, in the configuration of item 7, the memory cell further includes a plurality of second wirings provided in common to the first nodes in a plurality of memory cells in the column direction for detecting the resistance value between the first node and the first electrode, a plurality of read transistors for opening and closing the current path between the source line and the second wirings in a read operation, and a read control circuit for selectively controlling the read transistors of the memory cells from which data is read in a read operation and reading the resistance values ​​between the first nodes of the pair of magnetic tunnel junction elements included in the selected memory cell and the corresponding pair of second wirings as complementary signals (item 9).

[0041] Preferably, in the configuration of item 1, the memory cell further includes a cross-coupled inverter cell, the cross-coupled inverter cell having a first inverter and a second inverter whose input node and output node are cross-connected to each other, a pair of second nodes of first electrodes of the pair of magnetic tunnel junction elements are connected to the output node of the first inverter and the output node of the second inverter, respectively, the plurality of first wirings include a plurality of bit line pairs provided so as to be commonly connectable to third nodes of each of the magnetic tunnel junction elements in the plurality of memory cells, the memory cell further includes a pair of first select transistors provided between each output node of the inverter cell and the bit line pair, a pair of second select transistors provided between the pair of third nodes of the pair of magnetic tunnel junction elements and the bit line pair, and a pair of reset transistors provided between the pair of first nodes of the pair of magnetic tunnel junction elements and ground potential, which are conductive for a predetermined period after power-on to maintain the first nodes of the pair of magnetic tunnel junction elements at ground potential, and further includes a plurality of word lines for controlling opening and closing of the first select transistor and the second select transistor.

[0042] Preferably, in the configuration of item 1, the memory cell further includes a cross-coupled inverter cell, the cross-coupled inverter cell having a first inverter and a second inverter whose input node and output node are cross-connected to each other, a pair of second nodes of first electrodes of the pair of magnetic tunnel junction elements are connected to the output node of the first inverter and the output node of the second inverter, respectively, the plurality of first wirings include a plurality of bit line pairs provided so as to be commonly connectable to third nodes of each of the magnetic tunnel junction elements in the plurality of memory cells, the memory cell further includes a pair of first select transistors provided between each output node of the inverter cell and the bit line pair, and third select transistors provided between the pair of first nodes of the pair of magnetic tunnel junction elements and ground potential, the open / closed states of which are controlled by the potential of the output nodes of the pair of first inverters and the potential of the node of the output of the second inverter, and further includes a plurality of word lines for controlling the opening and closing of the first select transistors.

[0043] Preferably, a storage system incorporating a semiconductor storage device having the configuration of any one of items 1 to 10. (Item 12)

[0044] Preferably, in the semiconductor memory device having the configuration of any one of items 1 to 10, a data writing method is provided in which a write current is supplied to a pair of magnetic tunnel junction elements so as to make their resistance states different from each other.

[0045] According to the configuration of the semiconductor memory device of the present invention, stable and high-speed data reading and writing is possible in the SOT-MRAM.

[0046] The configuration of the semiconductor memory device of the present invention makes it possible to provide a semiconductor memory device that can stably reproduce stored data when the power is turned on again, and a method for writing data thereto.

[0047] 1 is a diagram showing an overview of an MTJ element constituting a memory cell.

[0023] FIG. 1 is a circuit diagram of a comparative example for explaining the circuit configuration of an MRAM.

[0024] FIG. 2 is a diagram showing the planar shape of bottom electrodes corresponding to MTJ elements adjacent in the column direction in the SOT-MRAM structure of the comparative example.

[0025] FIG. 3 is a diagram showing control of the potential of each signal line in read and write operations in the comparative example.

[0026] FIG. 4 is a conceptual diagram for explaining the configuration of a memory cell array 90 and a circuit for controlling read and write in a semiconductor memory device 9000 of the comparative example.

[0027] FIG. 5 is a circuit diagram for explaining the circuit configuration of a memory cell array 10 and memory cells 100 in a semiconductor memory device 1000 of the first embodiment.

[0028] FIG. 6 is a conceptual diagram for explaining the configuration of a memory cell array 10 and a circuit for controlling read and write in the first embodiment.

[0029] FIG. 7 is a diagram showing control of the potential of each signal line in read and write operations in the memory cell array 10 of the first embodiment.

[0029] FIG. 8 is a diagram showing current values ​​in a read operation when a memory cell has only one MTJ element.

[0029] FIG. 9 is a diagram for explaining the state of current values ​​in a read operation when complementary data are written to a pair of MTJ elements in a memory cell.

[0029] FIG. 10 is a diagram showing an example of a memory array 20 and memory cells 200 according to a second embodiment. 1 is a circuit diagram for explaining the circuit configuration of a memory cell array 20 and a memory cell 100 of a semiconductor memory device 2000 of a second embodiment. FIG. 2 is a diagram showing control of the potential of each signal line in read and write operations of the memory cell array 20 of the second embodiment. FIG. 3 is a diagram showing an example of a planar structure of an MTJ element and a lower electrode of the second embodiment. FIG. 4 is a diagram showing another example of a planar structure of an MTJ element and a lower electrode of the second embodiment. FIG. 5 is a diagram showing an example of a memory array 30 and a memory cell 300 according to a third embodiment. FIG. 6 is a circuit diagram for explaining the circuit configuration of a memory cell array 30 and a memory cell 300 of a semiconductor memory device 3000 of the third embodiment. FIG. 7 is a diagram showing control of the potential of each signal line in read and write operations of the memory cell array 30 of the third embodiment. FIG. 8 is a diagram showing an example of the structure of a cell of a cross-coupled SRAM. FIG. 9 is a diagram showing an example of the structure of a cell of a complementary SRAM. FIG. 10 is a diagram showing an example of the configuration of a memory cell 40 according to a fourth embodiment.10 is a conceptual diagram showing an example of data write and read control of a memory cell 40 according to a fourth embodiment. FIG. 11 is a diagram showing an example of a configuration of a memory cell 50 according to a fifth embodiment and an example of a data write operation. FIG. 12 is a conceptual diagram showing an example of data read control of a memory cell 50 according to a fifth embodiment. FIG. 13 is a conceptual diagram showing an example of data write control of a memory cell 50 according to a fifth embodiment. FIG. 14 is a conceptual diagram showing an example of data read control of a memory cell 50 according to a fifth embodiment.

[0048] The configuration of a semiconductor memory device according to an embodiment of the present invention will be described below. In the following embodiments, components and processing steps denoted by the same reference numerals are the same or equivalent, and unless necessary, their description will not be repeated. [Embodiment] (Comparative Example of MRAM Circuit Configuration)

[0049] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0050] FIG. 1 is a conceptual diagram showing the configuration of a magnetic tunnel junction element (hereinafter referred to as an "MTJ element") that constitutes a memory cell.

[0051] 1, the rectangle between node T2 and node T3 indicates the bottom electrode LEL, node T1 is the top electrode, node T2 is one end of the bottom electrode, and node T3 is the other end of the bottom electrode. Note that the "bottom electrode" here is an example of a "first electrode" along which a write current flows during a write operation of the SOT-MRAM. When the top-bottom structure of the MTJ element is inverted as described below, the top electrode provided on the internal node corresponds to the "first electrode."

[0052] An MTJ element is formed on the lower electrode LEL via an internal node Tint.

[0053] In FIG. 1, the MTJ element is simplified and represented as a variable resistor.

[0054] FIG. 2 is a circuit diagram of a comparative example for explaining the circuit configuration of an MRAM.

[0055] 2 shows an example of a schematic diagram of memory cells 900 in a memory array 90. This is only a portion of the memory cells, and in reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG.

[0056] 2, since the SOT-type MRAM is a three-terminal element, in principle, a transistor must be placed at each node as a select gate. In this case, three transistors are required per memory cell.

[0057] The configuration of a memory cell 900 including an MTJ element MTJ00 will be described below as an example.

[0058] In contrast, as shown in FIG. 2, for example, by controlling the potential of one of the nodes (CTN002) with a select line that is selectively set to an active potential, it is possible to provide two select transistors per memory cell. That is, select transistors TR001 and TR003 are provided corresponding to nodes CTN001 and CTN003, respectively. The gate potential of select transistor TR001 is controlled by read word line RWL0, and the gate potential of transistor TR003 is controlled by write word line WWL0. With this configuration, one MTJ element, two select transistors, and three memory cell nodes can be provided per memory cell 900.

[0059] However, the number of elements is still large in the configuration shown in Figure 2. In addition, since the read transistor TR001 needs to be provided on the semiconductor substrate, a vertical contact connection is required to connect the upper electrode of the MTJ element to the bottom silicon layer.

[0060] 3 is a diagram showing an example of the planar shape of the lower electrode LEL corresponding to the MTJ elements MTJ00 and MTJ10 in the region indicated by the symbol 2CH in the SOT-MRAM structure shown in FIG. 2, the positions of through-holes for connection from the lower surface side of the lower electrode LEL to the lower electrode LEL (portions connecting to the second node and the third node of the lower electrode via the through-holes are respectively referred to as "contact portions"), and the position of the lower surface of the MTJ element on the upper surface side of the lower electrode LEL. Therefore, FIG. 3 virtually shows the state in which the lower surfaces of the MTJ elements MTJ00 and MTJ10 are viewed from the lower surface side of the lower electrode LEL through the lower electrode LEL.

[0061] As shown in FIG. 3, through holes are located on both ends of the lower electrode LEL so that current flows directly below the MTJ elements MTJ00 and MTJ10.

[0062] In the following description, the term "MTJ element (magnetic tunnel junction element)" refers to an element having a structure in which two ferromagnetic layers sandwich a tunnel insulating film. The resistance to a current passing through this ferromagnetic layer / tunnel insulating film / ferromagnetic layer structure is small when the magnetic field directions of the two ferromagnetic layers are parallel, and large when they are antiparallel, due to the tunnel magnetoresistance effect.

[0063] In an MTJ element, the direction of one of the two magnetic layers sandwiching the tunnel insulating film is fixed. This magnetic layer is called the "pinned layer." The direction of the other magnetic layer can be changed to be parallel or anti-parallel to the magnetic field direction of the magnetic layer of the pinned layer, selectively setting the resistance of the MTJ element to either low or high. This magnetic layer is called the "free layer."

[0064] Although the stacked structure of the MTJ element shown in FIGS. 1 to 3 is not particularly limited, in each of the embodiments described later, for example, a stacked structure of CoFeB / MgO / CoFeB is formed as a conventional ferromagnetic layer / tunnel insulating film / ferromagnetic layer, and further, Mn is formed under the CoFeB on the free layer side. ３ The structure is such that Sn is provided. The Mn is provided under the CoFeB on the free layer side. ３Preferably, the alloy is a non-collinear antiferromagnetic material, such as Sn, and has a chiral spin structure.

[0065] As mentioned above, the magnetic spin Hall effect ３ Surface spin accumulation occurs on the surface of Sn, which generates a spin torque on the magnetization of the adjacent ferromagnetic material. ３ Sn has a structure that assists the spin reversal of the CoFeB in the free layer. As a result, the current density required for the spin reversal can be reduced. This allows the advantages of the memory cell and memory array structures according to each embodiment to be further utilized.

[0066] The lower electrode of the MTJ element can be made of, for example, tungsten (W). However, the metal for the electrode is not limited to this. As for the antiferromagnetic material, any (non)collinear antiferromagnetic material that produces the anomalous Hall effect, such as Mn ３ The material of the ferromagnetic layer is not limited to CoFeB, and may be, for example, CoFe. The tunnel insulating film (barrier layer) may be made of AlO in addition to MgO. ｘ , TiO ｘ etc. may also be used.

[0067] Furthermore, the structure of the MTJ element is not particularly limited to the above configuration. For example, a non-collinear antiferromagnetic material (e.g., Mn ３ The MTJ element may have a structure in which Sn) is used as the free layer and / or the fixed layer.

[0068] FIG. 4 is a diagram showing control of the potential of each signal line in read and write operations in a comparative example.

[0069] FIG. 5 is a conceptual diagram for explaining the configuration of a memory cell array 90 and a circuit for controlling reading and writing in a semiconductor memory device 9000 of the comparative example.

[0070] First, referring to FIG. 5, the semiconductor memory device 9000 includes a memory cell array 90, a write decoder 9030 for controlling the reading and writing of data from each memory cell 900 in the memory cell array 90, a read decoder 9040, a source line driver 9010, a bit line driver 9020, and sense amplifiers SA0 to SA1.

[0071] In a write operation to the memory cell 900, the write decoder 9030 selects and activates the write word line WWL of the memory cell to be written.

[0072] In a read operation to the memory cell 900, the read decoder 9040 selects and activates the read word line RWL of the memory cell that is the target of reading.

[0073] When writing data to a selected memory cell, the bit line driver 9020 and source line driver 9010 select the bit line and column source line of the corresponding column (column selection) and switch the potentials of the bit line BL0 and column source line CSL0 to either a high potential (e.g., power supply potential (Vdd) level) or a low potential (e.g., ground potential (Gnd) level) to pass a current through the lower electrode LEL in a direction corresponding to the write data. The source line driver 9010 also controls the potential of the selected source line CSL0 to a low potential during reading. The sense amplifiers SA0-SA1 amplify the current flowing from the read source lines RSL0-RSL1 of the selected memory cell and output it as read data.

[0074] 4 and 5, the control of the potentials of the word lines, column source lines, read source lines, and bit lines during writing and reading will be described.

[0075] In the following description, it is assumed that the memory cell corresponding to the MTJ element MTJ00 is selected. (Writing Data "0")

[0076] First, when writing data "0" to a selected memory cell (Write-0 in FIG. 4), the write decoder 9030 sets the write word line WWL0 to an active potential (high potential, for example, power supply potential Vdd). At this time, the read decoder 9040 sets the read word line RWL0 to an inactive potential (low potential, for example, ground potential GND).

[0077] In this state, the bit line driver 9020 sets the bit line BL0 to an active potential (high potential), and the source line driver 9010 sets the column source line CSL0 to an inactive potential (low potential). A current path is formed between the bit line BL0 and the column source line CSL0, and a current flows from the bit line BL0 to the column source line CSL0, thereby injecting spins into the MTJ element MTJ00. (Writing data "1")

[0078] When data "1" is written to the selected memory cell (Write-1 in FIG. 4), the potential of the bit line BL0 and the potential of the column source line CSL0 are controlled in the opposite manner to when data "0" is written.

[0079] During the data write operation, in unselected memory cells (memory cells to which data is not written, shown as standby state (St-by) in FIG. 4), both the bit lines and column select lines are held at an inactive potential. (Data Read)

[0080] When reading data from a selected memory cell, the read decoder 9040 sets the read word line RWL0 to an active potential.

[0081] When the bit line driver 9020 sets the potential of the bit line BL of the selected column to an active potential, a current flows through the MTJ element MTJ00, and a current corresponding to the resistance value of the MTJ element MTJ00 flows through the read source line RSL0 of the selected column. At this time, the resistance value changes depending on whether the data written to the memory cell is "1" or "0." Therefore, the sense amplifier SA0 detects the current value of the read source line RSL0, thereby reading out data. (Semiconductor Memory Device of the Embodiment)

[0082] In the semiconductor memory device 9000 of the comparative example as described above, the number of select transistors per memory cell can be set to two, as described above.

[0083] However, there is still room for improvement in read speed because it depends on the resistance of the tunnel oxide film of the MTJ element. Also, a structure is required that allows data to be stored even when the power is turned off and the data to be read again when the power is turned on again.

[0084] In the following description, the selected memory cell will be described as an example of a memory cell having a pair of MTJ elements MTJ00 and MTJ01. That is, the memory cell 100 includes a combination of two MTJ elements adjacent to each other in the row direction.

[0085] As will be described later, in one memory cell, after data is written, the pair of MTJ elements have different resistance values. That is, when data is written, data is written so that one of the pair of MTJ elements has its free layer and pinned layer parallel and the other has its free layer and pinned layer antiparallel. Therefore, "different resistance values" here means that the pair of MTJ elements in one memory cell achieves a "high resistance" state and a "low resistance" state after data writing. In other words, data "1" and "0" are stored in a complementary (differential) manner in the pair of MTJ elements in one memory cell. By writing data complementary to each other, the mutual resistance values ​​serve as a reference during read, eliminating the need for a separate reference potential. Furthermore, a high read voltage can be obtained, enabling high-speed readout.

[0086] As described above, the MTJ element has an internal node connected to the first node CTN0001 and the bottom electrode LEL00. The bottom electrode also has a second node CTN002 and a third node CTN003 that are coupled to a signal line for passing a current through the bottom electrode. [First Embodiment]

[0087] FIG. 6 is a circuit diagram for explaining the circuit configuration of the memory cell array 10 and the memory cells 100 of the semiconductor memory device 1000 of the first embodiment.

[0088] As in FIG. 2, FIG. 6 shows only a portion of the memory cells arranged in a matrix in the memory cell array. In reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG. 6.

[0089] FIG. 7 is a conceptual diagram for explaining the configuration of the memory cell array 10 according to the first embodiment and a circuit for controlling reading and writing.

[0090] Furthermore, FIG. 8 is a diagram showing the control of the potential of each signal line in the read operation and the write operation of the memory cell array 10 of the first embodiment.

[0091] 6 and 7, the semiconductor memory device 1000 includes a memory cell array in which a plurality of memory cells are arranged in a matrix. Each memory cell 100 includes a pair of magnetic tunnel junction elements (e.g., MTJ element MTJ00 and MTJ01) adjacent to each other in the row direction of the memory cell array. A write control circuit supplies a write current to the bottom electrodes of the pair of MTJ elements so as to make the resistance states of the pair of MTJ elements different from each other.

[0092] The semiconductor memory device 1000 includes a plurality of bit lines BL0, BL1 and column source lines CSL0, CSL1 that are provided in the column direction of the memory cell array 10 and are shared by a plurality of memory cells, and that supply a write current between the second node and the third node. The semiconductor memory device 1000 further includes a plurality of write transistors TR003, TR013 that open and close current paths so that a write current is conducted between the bottom electrode of a selected memory cell and the bit line and the column source line in a write operation. A write control circuit (bit line driver circuit 1020 and write decoder 1030) selectively controls the write transistors of memory cells to which data is written in a write operation, and supplies a write current to the bottom electrodes of a pair of magnetic tunnel junction elements included in the selected memory cell via the bit line and the column source line so as to make the resistance states of the elements different from each other.

[0093] More specifically, a plurality of bit lines BL0 and BL1 are provided to be commonly connected to the second nodes of the MTJ elements in a plurality of memory cells arranged in the column direction. A plurality of column source lines CSL0 and CSL1 are provided to be commonly connected to the MTJ elements in a plurality of memory cells arranged in the column direction. Write transistors TR003 and TR013 are provided between the third nodes and the column source lines, respectively. The write control circuit includes a write decoder that selectively controls opening and closing of the write transistors, and a driver circuit that supplies write currents, via the bit lines and source lines, to the bottom electrodes of a pair of magnetic tunnel junction elements in a selected memory cell in directions that cause the pair of magnetic tunnel junction elements to have different resistance states.

[0094] More specifically, as a configuration for data reading, the semiconductor memory device 1000 includes a plurality of read source lines provided in common to the first nodes of a plurality of memory cells in a column direction and for detecting the resistance between the first node and the lower electrode of the MTJ element. In FIG. 6 , the read source lines RSL0 and RSL1 are shown as examples corresponding to selected memory cells. The semiconductor memory device 1000 further includes a plurality of read transistors TR001 and TR011 for opening and closing current paths between the bit lines and the read source lines in a read operation, and a read control circuit (a source line driver circuit 1010 and a read decoder 1040) for selectively controlling the read transistors of memory cells from which data is read and reading, as complementary signals, the resistance between the first nodes of a pair of magnetic tunnel junction elements included in the selected memory cell and a corresponding pair of second wirings.

[0095] That is, in a write operation, the write decoder 1030 controls the gate potential of the write transistor of a selected memory cell by the corresponding word lines WWL0 and WWL1, thereby selectively conducting a write current between the second node CTN002 and the third node CTN003 of the lower electrode, and data is written by spin-orbit torque. The word lines are provided in the row direction of the memory cell array.

[0096] In a read operation, the resistance between the first node CTN001 and the second node CTN002 of each MTJ element of the selected memory cell can be detected by controlling the gate potentials of the read transistors TR001 and TR011 of the selected memory cell by the corresponding word line using the read decoder 1040. The sense amplifier SA0 detects the resistance of the pair of MTJ elements in the memory cell via the read source lines RSL0 and RSL1 provided corresponding to the selected memory cell, and data is read out.

[0097] 7 and 8, the control of the potentials of the write word line, read word line, column source line, read source line and bit line during writing and reading will be described.

[0098] 8, as described above, it is assumed that the memory cell 100 corresponding to the pair of MTJ elements MTJ00 and MTJ01 is selected. (Data Writing)

[0099] In the following description, for example, it is assumed that the resistance value read on the read source line RSL0 side is write data, and is read complementary to the resistance value read on the read source line RSL1 side.

[0100] That is, when writing data "0" to the MTJ element MTJ00 of the selected memory cell (Write-0 in FIG. 8), the write decoder 1030 sets the write word line WWL0 to an active potential (high potential, for example, the power supply potential Vdd). At this time, the read decoder 1040 sets the read word line RWL0 to an inactive potential (low potential, for example, the ground potential GND).

[0101] In this state, the bit line driver 1020 sets the bit line BL0 to an active potential (high potential), and the source line driver 1010 sets the column source line CSL0 to an inactive potential (low potential). A current path is formed between the bit line BL0 and the column source line CSL0, and a current flows from the bit line BL0 to the column source line CSL0 in the direction of the white arrow in Figure 6, thereby injecting spins into the MTJ element MTJ00, causing the spins in the free layer to become parallel, and data "0" is written.

[0102] Conversely, the bit line driver 1020 sets the bit line BL1 to an inactive potential (low potential), and the source line driver 1010 sets the column source line CSL1 to an active potential (high potential). A current path is formed between the bit line BL1 and the column source line CSL1, and a current flows from the bit line BL1 to the column source line CSL1 in the direction of the black arrow in the figure, thereby injecting spins into the MTJ element MTJ01, causing the spins in the free layer to become antiparallel, and data "1" is written.

[0103] By making the direction of the current opposite to that described above, data "1" is written to the MTJ element MTJ00 and data "0" is written to the MTJ element MTJ01.

[0104] For memory cells to which no data is written, both the bit lines and the column source lines are controlled to the inactive potential (data read).

[0105] When reading data from a selected memory cell, the read decoder 1040 sets the read word line RWL0 to an active potential.

[0106] When the bit line driver 1020 sets the potentials of the bit lines BL0 and BL1 of the selected column to an active potential, a current corresponding to the resistance values ​​of the MTJ elements MTJ00 and MTJ01 flows through the read source lines RSL0 and RSL1 of the selected column. At this time, the value of the current flowing through the read source lines RSL0 and RSL1 changes depending on whether the data written to the memory cell is "10" or "01." The difference between these currents can be read by amplifying it with the sense amplifier SA0. At this time, the current difference generated between the read source lines RSL0 and RSL1 is larger when there is a pair of MTJ elements than when there is only one MTJ element, allowing for high-speed reading. (Effect of Writing Data to Complementary MTJ Elements)

[0107] FIG. 9 is a diagram showing current values ​​during reading when a memory cell has only one MTJ element.

[0108] FIG. 10 is a diagram for explaining the state of the current value in a read operation when complementary data is written to a pair of MTJ elements of a memory cell.

[0109] First, as shown in FIG. 9, when a memory cell has only one MTJ element, the read current margin is small, making it difficult to increase the read speed.

[0110] Specifically, a reference current is required for reading both the high-current side (e.g., the H side where "0" is written) and the low-current side (e.g., the L side where "1" is written). However, each MTJ element has variations in characteristics, and the small read current value at high resistance (RH) and the large read current value at low resistance (RL) vary depending on the finish of the MTJ element. Furthermore, the reference current itself also varies due to variations in the circuit. This reduces the read margin, making high-speed read difficult.

[0111] On the other hand, as shown in FIG. 10, when a pair of MTJ elements of a memory cell is included, the read current margin is large and it is possible to increase the speed.

[0112] Specifically, in this embodiment, no reference current is required for reading either the H side or the L side. Therefore, a large current difference can be ensured, which enables high-speed reading. [Second embodiment]

[0113] FIG. 11 is a diagram showing an example of a memory array 20 and a memory cell 200 according to the second embodiment.

[0114] Here, as in FIG. 6, FIG. 11 shows only a portion of the memory cells arranged in a matrix in the memory cell array. In reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG. 6.

[0115] FIG. 12 is a circuit diagram for explaining the circuit configuration of the memory cell array 20 and the memory cells 100 of the semiconductor memory device 2000 of the second embodiment.

[0116] As shown in FIG. 11, the memory array 20 of the second embodiment does not require the column source lines CSL0 and CSL1 used during writing in the memory cell array 10 of the first embodiment.

[0117] That is, in the semiconductor memory device 2000 of the second embodiment, the second nodes CTN002 and CTN012 of the pair of MTJ elements in the memory cell 200 are electrically connected to each other. The semiconductor memory device 2000 also includes a plurality of pairs of bit lines provided in common to the pairs of MTJ elements in a plurality of memory cells arranged in the column direction. The write transistors WTR001 and WTR011 are provided between the third nodes CTN003 and CTN013 of the MTJ elements and the pair of bit lines BL0 and BL1, respectively. The write control circuit includes a write decoder 2030 that selectively controls the opening and closing of the write transistors WTR001 and WTR011, and a bit line driver circuit 2020 that supplies write currents to the bottom electrodes LEL00 and LEL01 of the pair of MTJ elements in the selected memory cell via the pair of bit lines BL0 and BL1 in directions that cause the electrodes to have different resistance states.

[0118] The semiconductor memory device 2000 includes a plurality of read source lines provided in common to the first nodes of a plurality of memory cells in a column direction, for detecting the resistance between the first node and the lower electrode of the MTJ element. In FIG. 12, the read source lines RSL0 and RSL1 are shown as examples corresponding to selected memory cells. The semiconductor memory device 2000 also includes a plurality of read transistors RTR001 and RTR011 for opening and closing current paths between the bit lines BL0 and BL1 and the read source lines RSL0 and RSL1, respectively, during a read operation. Furthermore, the semiconductor memory device 2000 further includes a read control circuit (a source line driver circuit 2010, a read decoder 2040, and a write decoder 2030) that selectively controls the write transistors WTR001, WTR011 and read transistors RTR001, RTR011 of the memory cell from which data is read during a read operation, and reads out the resistance values ​​between the first nodes of a pair of MTJ elements included in the selected memory cell and a corresponding pair of read source lines RSL0, RSL1 as complementary signals.

[0119] 13 is a diagram showing control of the potential of each signal line in the read operation and the write operation of the memory cell array 20 according to the second embodiment (data write).

[0120] Here, for example, the following description will be given assuming that the resistance value read on the read source line RSL0 side is write data, and that it is read complementarily to the resistance value read on the read source line RSL1 side.

[0121] That is, when writing data "0" to the MTJ element MTJ00 of the selected memory cell (Write-0 in FIG. 13), the write decoder 2030 sets the write word line WWL0 to an active potential (high potential, for example, the power supply potential Vdd). At this time, the read decoder 2040 sets the read word line RWL0 to a non-active potential (low potential, for example, the ground potential GND).

[0122] In this state, the bit line driver 2020 sets the bit line BL1 to an active potential (high potential) and the bit line BL0 to an inactive potential (low potential). A current path is formed between the bit lines BL0 and BL1, and a current flows from the bit line BL1 to the bit line BL0 in the direction of the white arrow in Figure 11, thereby injecting spins into the MTJ element MTJ00, causing the spins in the free layer to become parallel, and data "0" is written. At the same time, a current flows in the direction of the white arrow, causing spins in the MTJ element MTJ01, causing the spins in the free layer to become antiparallel, and data "1" is written.

[0123] By making the direction of the current opposite to that described above, data "1" is written to the MTJ element MTJ00 and data "0" is written to the MTJ element MTJ01.

[0124] For memory cells to which no data is written, the bit lines are controlled to an inactive potential (data read).

[0125] When reading data from a selected memory cell, the read decoder 2040 sets the read word line RWL0 to an active potential, and the write decoder 2030 sets the write word line WWL0 to an active potential.

[0126] The bit line driver 2020 sets the potentials of the bit lines BL0 and BL1 of the selected column to an inactive potential. A current corresponding to the resistance values ​​of the MTJ elements MTJ00 and MTJ01 flows through the read source lines RSL0 and RSL1 of the selected column. At this time, the value of the current flowing through the read source lines RSL0 and RSL1 changes depending on whether the data written to the memory cell is "10" or "01." The difference between these currents can be read by amplifying it with the sense amplifier SA0. At this time, the current difference generated between the read source lines RSL0 and RSL1 is larger when there is a pair of MTJ elements than when there is only one MTJ element, so high-speed reading is possible, as in the first embodiment. (Configuration of the Bottom Electrode)

[0127] FIG. 14 is a diagram showing an example of a planar structure of the MTJ element and the lower electrode according to the second embodiment.

[0128] FIG. 14 illustrates an example of the pattern of the bottom electrodes of a pair of MTJ elements adjacent to each other in the row direction in a memory cell in the memory cell array 10 of the second embodiment.

[0129] Similar to FIG. 3, FIG. 14 is a conceptual diagram showing the internal node side of the MTJ element when the MTJ element is viewed from the side of the lower electrode LEL opposite to the MTJ element, through the lower electrode LEL itself (assuming that the lower electrode LEL is transparent).

[0130] 14, one surface of each of the bottom electrodes LEL00 and LEL01 is connected to an internal node of the memory cell MTJ00 adjacent thereto in the row direction and an internal node of the memory cell MTJ01. The bottom electrodes of the MTJ elements adjacent thereto in the row direction in other memory cells also have a similar pattern.

[0131] A contact hole CTH001 for connection to the source node (node ​​CTN003) of the write transistor WTR001 is provided on the other surface of the lower electrode LEL00 that faces the one surface described above. Similarly, a contact hole CTH011 for connection to the source node (node ​​CTN013) of the write transistor WTR011 is provided on the other surface of the lower electrode LEL01 that faces the one surface described above.

[0132] On the other hand, the lower electrodes LEL00 and LEL01 are connected to each other by a connection wiring via contact holes CTH002 and CTH012.

[0133] FIG. 15 is a diagram showing another example of the planar structure of the MTJ element and the bottom electrode according to the second embodiment.

[0134] One surface of the bottom electrode LEL is commonly connected to each of the internal nodes of a pair of MTJ elements adjacent to each other in the row direction, and contact holes CTH001 and CTH011 are provided on the other surface of the bottom electrode for connection to the write transistors WTR001 and WTR011, respectively, as in FIG.

[0135] Specifically, when the shape of the lower electrode in FIG. 15 is adopted, the lower electrode LEL00 and the lower electrode LEL10 are formed as an integrated pattern.

[0136] With the above configuration, the bottom electrodes of the two complementary MTJ elements have a short-circuit structure, which eliminates the need for contacts for connecting the connection wiring layer to the bottom electrodes and the connection wiring layer itself, thereby reducing the memory cell area.

[0137] Furthermore, in the second embodiment, since control using the potentials of the column source lines CSL0 and CSL1 is not performed, control of the write operation becomes easier and the circuit configuration can be simplified. As a result, when mounted on an LSI, for example, when multiple memory circuits with different combinations of the number of rows and columns are mounted as IP cores (Intellectual Property cores), the configuration becomes easy to handle (compilable) as IP cores with variable memory capacities. Therefore, for example, it becomes easy to mount the semiconductor memory device 2000 together with a logic LSI (Large Scale Integration) circuit. [Third Embodiment]

[0138] FIG. 16 is a diagram showing an example of a memory array 30 and a memory cell 300 according to the third embodiment.

[0139] Here, as in FIG. 6, FIG. 16 shows only a portion of the memory cells arranged in a matrix in the memory cell array. In reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG. 16.

[0140] FIG. 17 is a circuit diagram for explaining the circuit configuration of the memory cell array 30 and the memory cells 300 of the semiconductor memory device 3000 of the third embodiment.

[0141] 16, in the semiconductor memory device 3000 of the third embodiment, the second nodes CTN002 and CTN012 of a pair of MTJ elements in a memory cell 300 are electrically connected to each other. In addition, in the memory array 30 of the third embodiment, the bit line BL0 and the column source line CSL0 used during writing are shared by the pair of MTJ elements in the memory cell.

[0142] That is, the memory cell array 30 of the third embodiment includes a plurality of bit lines provided in common to the second nodes (e.g., nodes CTN002 and CTN012) of each MTJ element (e.g., each of MTJ00 and MTJ01) in a plurality of memory cells arranged in the column direction, a plurality of source lines (e.g., column source line CSL0) provided in common to each of the third nodes (e.g., nodes CTN003 and CTN013) of a pair of MTJ elements in a plurality of memory cells arranged in the column direction, and write transistors (e.g., WTR00) provided between the second nodes of the MTJ elements and the bit lines, respectively. The semiconductor memory device 3000 includes a write decoder 3030 that selectively controls opening and closing of the write transistors, and write control circuits (a bit line driver circuit 3020 and a source line driver 3010) that supply write currents in directions that cause the pair of MTJ elements in a selected memory cell to have different resistance states via the bit lines and source lines.

[0143] More specifically, the semiconductor memory device 3000 further includes a plurality of read source lines (e.g., read source lines RSL0, RSL1) that are provided in common to first nodes (e.g., CTN001) of MTJ elements in a plurality of memory cells in the column direction and that detect the resistance value between the first node and the lower electrode, a plurality of read transistors (e.g., RTR001, RTR011) that open and close current paths between the read source lines and column source lines (e.g., column source line CSL0) in a read operation, and a read control circuit (source line driver 3010, sense amplifier SA0) that selectively controls the read transistors of memory cells from which data is read and reads out the resistance values ​​between the first nodes of a pair of MTJ elements included in the selected memory cell and a corresponding pair of read source lines as complementary signals in a read operation.

[0144] More specifically, the write transistor WTR00 is provided between the second nodes CTN002 and CTN012 of the pair of MTJ elements, which are connected to each other, and the bit line BL0. The read transistor RTR001 is provided between the first node CTN001 of the MTJ element MTJ00 and the read source line RSL0, and the read transistor RTR011 is provided between the first node CTN011 of the MTJ element MTJ01 and the read source line RSL1.

[0145] The write control circuit includes a write decoder 3030 that selectively controls the opening and closing of the write transistor WTR00, and a bit line driver circuit 3020 and a source line driver 3010 that supply write currents in directions that cause the lower electrodes LEL00, LEL01 of a pair of MTJ elements in a selected memory cell to have different resistance states via the bit line BL0 and the column source line CSL0.

[0146] The semiconductor memory device 3000 further includes a read control circuit (a source line driver circuit 3010, a bit line driver circuit 3020, and a read decoder 3040) that selectively controls the read transistors RTR001 and RTR011 of the memory cell from which data is read during a read operation, and reads out the resistance values ​​between the first nodes of a pair of MTJ elements included in the selected memory cell and a corresponding pair of read source lines RSL0 and RSL1 as complementary signals.

[0147] Therefore, in the semiconductor memory device 1000 of the first embodiment, a pair of bit lines and a pair of column source lines are provided for memory cells arranged in the column direction as one column, whereas in the semiconductor memory device 3000 of the third embodiment, one bit line and one column source line are provided for memory cells arranged in the column direction as one column in the memory cell array 30, making it possible to reduce the circuit area.

[0148] Furthermore, the semiconductor memory device 3000 of the third embodiment has a configuration in which the number of write transistors per memory cell is reduced compared to the semiconductor memory device 3000 of the second embodiment, which also makes it possible to reduce the circuit area.

[0149] 18 is a diagram showing control of the potential of each signal line in the read operation and write operation of the memory cell array 30 according to the third embodiment (data write).

[0150] Here, for example, the following description will be given assuming that the resistance value read on the read source line RSL0 side is write data, and that it is read complementarily to the resistance value read on the read source line RSL1 side.

[0151] That is, when writing data "0" to the MTJ element MTJ00 of the selected memory cell (Write-0 in FIG. 18), the write decoder 3030 sets the write word line WWL0 to an active potential (high potential, for example, the power supply potential Vdd). At this time, the read decoder 2040 sets the read word line RWL0 to a non-active potential (low potential, for example, the ground potential GND).

[0152] In this state, the bit line driver 2020 sets the bit line BL0 to an active potential (high potential), and the source line driver circuit 3010 sets the column source line CSL0 to an inactive potential (low potential). A current path is formed between the bit line BL0 and the column source line CSL0, and a current flows from the bit line BL0 to the column source line CSL0 in the direction of the white arrow in Figure 16, thereby injecting spins into the MTJ element MTJ00, causing the spins in the free layer to become parallel, and data "0" is written. At the same time, a current flows in the direction of the white arrow, causing spins in the MTJ element MTJ01, causing the spins in the free layer to become antiparallel, and data "1" is written.

[0153] By making the direction of the current opposite to that described above, data "1" is written to the MTJ element MTJ00 and data "0" is written to the MTJ element MTJ01.

[0154] For memory cells to which no data is written, the bit lines are controlled to an inactive potential (data read).

[0155] When reading data from a selected memory cell, the read decoder 3040 sets the read word line RWL0 to an active potential, and the write decoder 3030 sets the write word line WWL0 to an active potential.

[0156] The bit line driver 3020 sets the potential of the bit line BL0 of the selected column to an inactive potential. A current corresponding to the resistance values ​​of the MTJ elements MTJ00 and MTJ01 flows through the read source lines RSL0 and RSL1 of the selected column. At this time, the value of the current flowing through the read source lines RSL0 and RSL1 changes depending on whether the data written to the memory cell is "10" or "01." The difference between these currents can be read by amplifying it with the sense amplifier SA0. At this time, the current difference generated between the read source lines RSL0 and RSL1 is larger when there is a pair of MTJ elements than when there is only one MTJ element, so high-speed reading is possible, as in the first embodiment. [Fourth Embodiment]

[0157] Next, as a premise for explaining the fourth embodiment, examples of the structure of a conventional cross-coupled static random access memory (SRAM) cell and a complementary MRAM cell will be explained.

[0158] FIG. 19 is a diagram showing an example of the structure of a cell of a cross-coupled SRAM.

[0159] FIG. 20 is a diagram showing an example of the structure of a cell of a complementary SRAM.

[0160] In this case, when the memory circuit is operated, the memory cells are arranged in a matrix to form a memory cell array. Therefore, in reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG.

[0161] First, the control of the cross-coupled SRAM cell shown in FIG. 19 will be described.

[0162] A cross-coupled SRAM cell is constructed by interconnecting the inputs and outputs of a first inverter and a second inverter, both of which are CMOS (Complementary Metal Oxide Semiconductor) circuits, forming a "flip-flop circuit" that does not require refreshing to retain data.

[0163] When writing data, the word line WL is set to an active potential, the access transistors ACTR01 and ACTR02 are set to a conductive state, and write data is input from a pair of complementary bit lines BL and / BL. When setting the nodes of the cross-coupled CMOS inverters to H level and L level data as shown in Figure 19, L data is written from the bit line BL and H data is written from the bit line / BL.

[0164] When reading data, the word line WL is set to an active potential, and the cross-coupled inverter node is connected to the bit line BL and bit line / BL. At this time, the L-level inverter node is connected to the bit line BL, so the potential of the bit line BL drops. Conversely, the H-level inverter node is connected to the bit line / BL, but the potential of the bit line / BL is also H, so the potential does not drop. The potential difference between the bit lines BL and / BL is amplified, and data is read out.

[0165] On the other hand, in a cross-coupled SRAM cell, when power is turned on, the power supply potential (Vdd) level within the circuit gradually rises from the ground potential (GND). At this time, due to manufacturing variations, the cross-coupled inverter nodes each change to either an H level or an L level. Which node becomes an H level and which node becomes an L level depends on manufacturing variations and the power-on sequence, making it unstable. Therefore, when power is turned on again, it is difficult to guarantee that the data will be restored to the state it was in before power was turned off.

[0166] 20, the complementary MRAM cell has a higher probability of restoring data to the state it was in before power was turned off than a cross-coupled SRAM cell because data storage is nonvolatile. However, due to variations in the reference current and the characteristics of the MTJ element, as well as the power-on sequence, it is not necessarily guaranteed that data can be read out in the same way as before power was turned off.

[0167] Fig. 21 is a diagram showing an example of the configuration of a memory cell 40 according to the fourth embodiment. Fig. 22 is a conceptual diagram showing an example of data write and read control of the memory cell 40 according to the fourth embodiment.

[0168] Again, when operated as a memory circuit, the memory cells 40 form a memory cell array arranged in a matrix. Therefore, in reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG.

[0169] 21 , the memory cell 40 of the fourth embodiment has a cross-coupled CMOS inverter in which one end of the bottom electrode of an MTJ element MTJ001 and one end of the bottom electrode of an MTJ element MTJ011 are connected to the output nodes of the first and second inverters, respectively, and a node (first node) on the top electrode side of the MTJ element is connected to the ground potential via transistors MRTR11 and MRTR12 whose opening and closing is controlled by a POR (Power on Reset) signal. Here, the “POR signal” is a signal transmitted from a reset circuit (not shown) to start the memory circuit in a stable state when power is turned on, and is a signal that keeps the circuit in a reset state for a predetermined period until the power supply voltage stabilizes and then releases the reset state.

[0170] More specifically, the memory cell 40 includes a pair of MTJ elements MTJ00 and MTJ01 and a cross-coupled inverter cell SRCEL.

[0171] The cross-coupled inverter cell SRCEL has a first inverter and a second inverter whose input and output nodes are cross-connected to each other. A pair of second nodes (one end) of the lower electrodes of the pair of MTJ elements are connected to the output node of the first inverter and the output node of the second inverter, respectively. The memory circuit of the fourth embodiment includes a plurality of bit line pairs BL, / BL provided so as to be commonly connectable to the third nodes of each MTJ element in a plurality of memory cells. The memory cell 40 further includes a pair of first select transistors SRTR01, SRTR02 provided between each output node of the cross-coupled inverter cell SRCEL and the bit line pair. A pair of second select transistors MRTR01, MRTR02 is provided between the pair of third nodes (the other end) of the pair of MTJ elements and the bit line pair BL, / BL, respectively. The memory cell 40 also includes a pair of reset transistors MRTR11 and MRTR12 that are respectively provided between the pair of first nodes of the pair of MTJ elements and ground potential, and that are turned on by a POR signal for a predetermined period after power-on to maintain the first nodes of the pair of MTJ elements at ground potential. The memory circuit of the fourth embodiment further includes a plurality of word lines for controlling opening and closing of the first select transistor and the second select transistor in accordance with signals from a write control circuit (not shown) and a read control circuit (not shown).

[0172] The write operation will be described with reference to FIG.

[0173] Under the control of the write control circuit, the word line WL is activated and write data is input from the bit lines BL and / BL. When the output nodes of the cross-coupled inverter cell SRCEL are set to H level and L level data as shown in Figure 22, L data is written from the bit line BL and H data is written from the bit line / BL.

[0174] At the same time, the bit lines BL and / BL are connected to the MTJ element side by the second select transistors MRTR01 and MRTR02. At this time, a current flows from the H-level node of the inverter toward the L-level node of the bit line BL. Also, a current flows from the H-level node of the bit line / BL toward the L-level node of the inverter. This causes complementary data to be written to the pair of MTJ elements. Here, the MTJ element MTJ001 connected to the H-level node of the inverter is in a high-resistance antiparallel state (RH state), and the MTJ element MTJ011 connected to the L-level node of the inverter is in a low-resistance parallel state (RL state).

[0175] Next, the read operation will be described with reference to Figure 22. Under the control of the read control circuit, the word line WL is activated, and the bit lines BL, / BL are connected to the output nodes of the cross-coupled inverter cell SRCEL. The cross-coupled inverter cell SRCEL is controlled in the same manner as the read operation of the cross-coupled inverter cell SRCEL described in Figure 19. On the MTJ element side, if the state retention capability of the cross-coupled inverter cell SRCEL is sufficient, no current path that changes this state is generated, and therefore, it does not contribute to the read operation.

[0176] When power is turned on, the power supply potential (Vdd) level gradually rises from the ground potential (GND). At this time, the output node of the cross-coupled inverter cell SRCEL rises in an unstable state. However, because the resistance value recorded in the MTJ element is nonvolatile, it becomes the respective resistance values ​​in the RH and RL states. The POR signal is activated only for a predetermined period after power is turned on, activating a current path to the ground potential (GND) level via the resistance of the MTJ element. As a result, the node that was the H-level node of the inverter has a high resistance value in the RH state in the current path to the ground potential (GND). On the other hand, the node that was the L-level node of the inverter has a low resistance value in the RL state in the current path to the ground potential (GND). As a result, the node that was the L-level node of the inverter is strongly attracted to the ground potential (GND), and rises to the L level. This operation restores the recorded information of this memory cell before power was turned off. [Fifth Embodiment]

[0177] Fig. 23 is a diagram showing an example of the configuration of a memory cell 50 according to the fifth embodiment. Figs. 24 to 27 are conceptual diagrams showing an example of data write and read control of the memory cell 50 according to the fifth embodiment.

[0178] Again, when operated as a memory circuit, the memory cells 50 form a memory cell array arranged in rows and columns. Therefore, in reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG.

[0179] As shown in FIG. 23, in the memory cell 50, one end of the lower electrodes of the MTJ element MTJ001 and the MTJ element MTJ011 are connected to the output nodes of the first and second inverters in a cross-coupled CMOS inverter, and the nodes on the upper electrode side of the MTJ elements are connected to the ground potential (GND) via transistors MRTR11 and MRTR12 whose opening and closing is controlled by the potential of the output nodes of the first and second inverters.

[0180] More specifically, the memory cell 40 includes a pair of MTJ elements MTJ00 and MTJ01 and a cross-coupled inverter cell SRCEL.

[0181] The cross-coupled inverter cell SRCEL has a first inverter and a second inverter whose input node and output node are cross-connected to each other. A pair of second nodes (one end) of the bottom electrodes of the pair of MTJ elements MTJ001 and MTJ011 are connected to the output node of the first inverter and the output node of the second inverter, respectively. The memory circuit of the fifth embodiment includes a plurality of bit line pairs BL, / BL provided so as to be commonly connectable to the third nodes (other end) of the bottom electrodes of each MTJ element in a plurality of memory cells. The memory cell 50 further includes a pair of first select transistors WLTR01, WLTR02 provided between each output node of the cross-coupled inverter cell SRCEL and the bit line pair BL, / BL, and third select transistors MRTR11, MRTR12 provided between the pair of first nodes of the pair of MTJ elements MTJ00, MTJ01 and ground potential, and whose open / closed states are controlled by the potentials of the output nodes of the pair of first inverters and the potential of the node of the output of the second inverter.

[0182] The first select transistors WLTR01 and WLTR02 are controlled in open / closed state by a plurality of word lines whose potentials are controlled by a write control circuit (not shown) and a read control circuit (not shown).

[0183] Other parts that are the same as those in Figure 21 are given the same reference numerals and description thereof will not be repeated.

[0184] The write operation will be described with reference to FIG.

[0185] A write control circuit sets the word line WL to an active potential, and write data is input from the bit lines BL and / BL. When setting the output node of the cross-coupled inverter cell SRCEL to H-level and L-level data as shown in FIG. 23, L data is written from the bit line BL and H data is written from the bit line / BL. At this time, the lower electrode of the MTJ element is inserted in the path of the data write current, and a current flows. This injects spins into the MTJ element, and the resistance value of the MTJ element can be set to the RH state or the RL state. At this time, the resistance of the MTJ element connected to the L-level node of the inverter is set to the RL state, and the resistance of the MTJ element connected to the H-level node of the inverter is set to the RH state.

[0186] The read operation will be described with reference to FIG.

[0187] The read control circuit activates the word line WL, connecting the bit lines BL and / BL to each node of the memory cell. The cross-coupled inverter cell SRCEL side is controlled in the same way as SRAM read. On the MTJ element side, current flows from the high-level bit line BL to the low-level inverter node. On the other hand, no current flows from the high-level inverter node to the high-level bit line / BL. When current flows from the high-level bit line BL to the low-level inverter node, the resistance of the MTJ element is low in the RL state, and the transistor MRTR11 is also conductive, so more current flows and the potential of the bit line BL is further reduced. This enables faster read operations.

[0188] Next, the operation when the power is turned on will be described with reference to FIG.

[0189] When power is turned on, the power supply potential (Vdd) level gradually rises from the ground potential (GND). At this time, the potential of the output node of the cross-coupled inverter cell SRCEL rises in an unstable state. However, because the resistance value recorded in the MTJ element is nonvolatile, it becomes the respective resistance values ​​of the RH and RL states. Due to the current path to the ground potential (GND) level via the resistance of the MTJ element, the node that was the H-level node of the inverter has a high resistance value in the RH state in the path to the ground potential (GND), and the node that was the L-level node of the inverter has a low resistance value in the RL state in the path to the ground potential (GND). As a result, the node side that was the L-level node of the cross-coupled inverter cell SRCEL is strongly attracted to GND, and the node side that was the L-level node of the inverter rises to the L level. This operation restores the information recorded in this memory cell before power was turned off.

[0190] Next, with reference to FIG. 25, a case where data opposite to the state shown in FIG. 24 is written will be described.

[0191] The write control circuit sets the word line WL to an active potential and inputs write data from the bit lines BL and / BL. When the output node of the cross-coupled inverter cell SRCEL is to have data opposite to that shown in Figure 24, H data is written from the bit line BL and L data is written from the bit line / BL. Therefore, basically, the L level of the original inverter changes to H level, and the H level changes to L level. At this time, the resistance of the MTJ element connected to the node of the inverter that changes to L level is set to the RL state, and the resistance of the MTJ element connected to the node of the inverter that changes to H level is set to the RH state.

[0192] Next, with reference to FIG. 26, a read operation for the state in FIG. 25 where the data has been rewritten to the opposite data will be described.

[0193] The read control circuit sets the word line WL to an active potential, and the bit line BL, the bit line / BL and each node of the memory cell are connected.

[0194] The cross-coupled inverter cell SRCEL side is controlled in the same way as SRAM read. On the MTJ element side, no current flows from the high-level bit line BL to the low-level inverter node. Also, no current flows from the high-level inverter node to the high-level bit line BL. Since the transistor MRTR12 is conductive, when current flows from the high-level bit line / BL to the low-level inverter node, the resistance of the MTJ element MTJ011 is low in the RL state, so more current flows, further lowering the potential of BL. This enables faster readout.

[0195] Next, with reference to FIG. 27, a case where the same data as in the state shown in FIG. 26 is written will be described.

[0196] The write control circuit sets the word line WL to an active potential and inputs write data from the bit lines BL and / BL. If the output node of the cross-coupled inverter cell SRCEL is set to the same data as in FIG. 26, H data is written from the bit line BL and L data is written from the bit line / BL. Since the data is the same, no current flows from the bit lines BL and / BL. Therefore, the data is retained.

[0197] The memory cell 50 of the fifth embodiment can be applied, for example, as a memory cell of a PUF (Physically Unclonable Function). Topological materials have the property of not emitting a magnetic field to the outside, and when applied to a PUF memory cell, the stored information is difficult to read, ensuring security. (Example of a system including an MRAM described in each embodiment)

[0198] The semiconductor memory device formed in accordance with each of the above embodiments can be used as a memory device for a circuit that performs arithmetic processing of data.

[0199] For example, a central processing unit (CPU) has multiple levels of cache memory. For example, a hierarchical cache memory is typically provided, such as a level 1 (L1) primary cache memory, a level 2 (L2) secondary cache memory, a level 3 (L3) tertiary cache memory, and so on. In this case, cache memory has traditionally been implemented using static random access memory (SRAM). However, SRAM has drawbacks, such as low memory density (each memory cell is composed of six transistors) and relatively high standby power consumption (significant leakage current). Replacing SRAM with MRAM can reduce the silicon area per memory capacity and significantly reduce standby power consumption.

[0200] Therefore, for example, the semiconductor memory device of the MRAM according to each of the above-described embodiments can be employed as a last level cache such as an L3 cache or an L4 cache.

[0201] Furthermore, with the spread of new technologies such as AI, IoT, and 5G, there is a demand for high-speed, highly reliable memory solutions. Therefore, the applications of MRAM are not limited to the above, and it is expected that it will be used as a storage system in fields where high-speed, highly reliable memory is required, such as data storage in industrial automation systems, data storage in medical devices, and data centers.

[0202] According to the configuration of the semiconductor memory device of each embodiment as described above, stable data recording and high-speed data writing and reading are possible in the SOT-MRAM.

[0203] Finally, while various embodiments of the present disclosure have been described, they are presented as examples and are not intended to limit the scope of the invention. The novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. Such embodiments and modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the inventions and their equivalents as defined in the claims.

[0204] Therefore, the embodiments disclosed herein are merely examples of configurations for specifically implementing the present invention, and do not limit the technical scope of the present invention. The technical scope of the present invention is defined by the claims, not by the description of the embodiments, and is intended to include modifications within the literal scope of the claims and within the scope of equivalent meanings.

[0205] 10, 20, 30 memory cell array, 100, 200, 300 memory cell, MTJ00, MTJ01, MTJ10, MTJ11 magnetic tunnel junction element, T1 first node of MTJ element, T2 second node of MTJ element, T3 third node of MTJ element, BL0, BL1 bit line, CSL0, CSL1 column source line, RSL0, RSL1 read source line, RSL0 shared source line, RWL0, RWL1 read word line, WWL0, WWL1 write word line, 1000, 2000, 3000 semiconductor memory device, 1010 source line driver, 1020 bit line driver, 1030 write decoder, 1040 read decoder.

Claims

1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix; each of the memory cells comprises a pair of magnetic tunnel junction elements adjacent to each other in a row direction of the memory cell array, each of the magnetic tunnel junction elements having a first node and an internal node, and further comprising a first electrode provided to be connected to the internal node of the pair of magnetic tunnel junction elements and having a second node and a third node for conducting a write current; and further comprising a write control circuit that supplies the write current to the first electrode of the pair of magnetic tunnel junction elements so as to make the resistance states of the pair of magnetic tunnel junction elements different from each other.

2. A semiconductor memory device as claimed in claim 1, comprising: a plurality of first wirings provided in the column direction of the memory cell array so as to be shared by the memory cells, for supplying a write current between the second node and the third node; and a plurality of write transistors for opening and closing a current path so that a write current is conducted between the first electrode of the selected memory cell and the first wirings during a write operation, wherein the write control circuit selectively controls the write transistor of the memory cell to which data is written during a write operation, and supplies the write current via the first wirings to the first electrodes of the pair of magnetic tunnel junction elements included in the selected memory cell so as to make the resistance states of the first electrodes different from each other.

3. The semiconductor memory device according to claim 2, wherein the plurality of first wirings include a plurality of bit lines provided so as to be commonly connected to the second nodes of the magnetic tunnel junction elements in the plurality of memory cells in the column direction, and a plurality of source lines provided commonly to the magnetic tunnel junction elements in the plurality of memory cells in the column direction, the write transistors are provided between the third nodes and the source lines, respectively, and the write control circuit includes: a write decoder that selectively controls opening and closing of the write transistors, and a driver circuit that supplies write currents in directions such that the first electrodes of the pair of magnetic tunnel junction elements in the selected memory cell are in different resistance states via the bit lines and the source lines.

4. A semiconductor memory device as claimed in claim 3, further comprising: a plurality of second wirings provided in common to the first nodes in a plurality of the memory cells in the column direction for detecting a resistance value between the first node and the first electrode; a plurality of read transistors for opening and closing a current path between the bit line and the second wiring in a read operation; and a read control circuit for selectively controlling the read transistors of the memory cells from which data is read in a read operation, and reading out the resistance values ​​between the first nodes of the pair of magnetic tunnel junction elements included in the selected memory cell and a corresponding pair of the second wirings as complementary signals.

5. The semiconductor memory device according to claim 2, wherein the second nodes of the pair of magnetic tunnel junction elements in the memory cell are electrically connected to each other, the multiple first wirings include multiple pairs of bit lines provided in common to the pair of magnetic tunnel junction elements in the multiple memory cells in the column direction, the write transistors are provided between the third nodes and the bit lines, respectively, and the write control circuit includes: a write decoder that selectively controls opening and closing of the write transistors, and a driver circuit that supplies write currents in directions such that the first electrodes of the pair of magnetic tunnel junction elements in the selected memory cell are in different resistance states via the pair of bit lines.

6. A semiconductor memory device as claimed in claim 5, further comprising: a plurality of second wirings provided in common to the first nodes in a plurality of the memory cells in the column direction for detecting a resistance value between the first node and the first electrode; a plurality of read transistors for opening and closing a current path between the bit line and the second wiring in a read operation; and a read control circuit for selectively controlling the write transistor and the read transistor of the memory cell from which data is read in a read operation, and reading out the resistance values ​​between the first nodes of the pair of the magnetic tunnel junction elements included in the selected memory cell and a corresponding pair of the second wirings as complementary signals.

7. The semiconductor memory device according to claim 2, wherein the plurality of first wirings include a plurality of bit lines provided in common to the second nodes of the magnetic tunnel junction elements in the plurality of memory cells in the column direction, and a plurality of source lines provided in common to each of the third nodes of the pair of magnetic tunnel junction elements in the plurality of memory cells in the column direction, the write transistors are provided between the second nodes and the bit lines, respectively, and the write control circuit includes: a write decoder that selectively controls opening and closing of the write transistors, and a driver circuit that supplies write currents in directions such that the first electrodes of the pair of magnetic tunnel junction elements in the selected memory cell are in different resistance states via the bit lines and the source lines.

8. A semiconductor memory device as claimed in claim 7, further comprising: a plurality of second wirings provided in common to the first nodes in a plurality of the memory cells in the column direction for detecting a resistance value between the first node and the first electrode; a plurality of read transistors for opening and closing a current path between the source line and the second wiring in a read operation; and a read control circuit for selectively controlling the read transistors of the memory cells from which data is read in a read operation, and reading out the resistance values ​​between the first nodes of the pair of the magnetic tunnel junction elements included in the selected memory cell and a corresponding pair of the second wirings as complementary signals.

9. The memory cell further includes a cross-coupled inverter cell, the cross-coupled inverter cell having a first inverter and a second inverter whose input node and output node are cross-connected to each other, the pair of second nodes of the first electrodes of the pair of magnetic tunnel junction elements are connected to the output node of the first inverter and the output node of the second inverter, respectively, and the plurality of first wirings include a plurality of bit line pairs provided so as to be commonly connectable to the third node of each of the magnetic tunnel junction elements in the plurality of memory cells, the memory cell further includes a pair of first selection transistors provided between each output node of the inverter cell and the bit line pair, a pair of second selection transistors provided between the pair of third nodes of the pair of magnetic tunnel junction elements and the bit line pair, respectively, and a pair of reset transistors provided between the pair of first nodes of the pair of magnetic tunnel junction elements and a ground potential, and being in a conductive state for a predetermined period after power-on to maintain the first nodes of the pair of magnetic tunnel junction elements at the ground potential, 2. The semiconductor memory device according to claim 1, further comprising a plurality of word lines for controlling opening and closing of said first selection transistor and said second selection transistor.

10. The semiconductor memory device according to claim 1, wherein the memory cell further includes a cross-coupled inverter cell having a first inverter and a second inverter whose input node and output node are cross-connected to each other, the pair of second nodes of the first electrodes of the pair of magnetic tunnel junction elements are connected to the output node of the first inverter and the output node of the second inverter, respectively, and the plurality of first wirings include a plurality of bit line pairs provided so as to be commonly connectable to the third node of each of the magnetic tunnel junction elements in the plurality of memory cells, and the memory cell further includes a pair of first selection transistors provided between each output node of the inverter cell and the bit line pair, respectively, and third selection transistors provided between the pair of first nodes of the pair of magnetic tunnel junction elements and ground potential, the open / closed state of which is controlled by the potential of the output nodes of the pair of first inverters and the potential of the node of the output of the second inverter, and further comprising a plurality of word lines for controlling opening and closing of the first selection transistors.

11. A storage system incorporating the semiconductor storage device according to any one of claims 1 to 10.

12. A data write method for a semiconductor memory device according to any one of claims 1 to 10, further comprising the step of supplying the write current to the pair of magnetic tunnel junction elements so as to make their resistance states different from each other.

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