System and method for storing bit planes in a display

Abstract

Displaying an image as a sequence of bit planes can include storing the sequence of bit planes in a buffer. Reducing the storage space of the buffer can decrease its physical size and power consumption, which is desirable for some mobile applications. The amount of storage space required depends on the compressibility and the brightness of the image, so is difficult to predict. The disclosed display can adjust how the bit planes are stored based on the compressibility and brightness of the image so that the storage space is utilized efficiently. Further, the disclosed display can disable some bit planes to fit into the storage space without dramatically reducing the quality of the displayed image.

Description

SYSTEM AND METHOD FOR STORING BIT PLANES IN A DISPLAYCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 587,809, filed on October 4, 2023, which is hereby incorporated by reference in its entirety.FIELD OF THE DISCLOSURE

[0002] The present disclosure relates to a display and more specifically to a display configured to display images based on bit planes.BACKGROUND

[0003] Color or grayscale images can be represented as a weighted series (i.e., sequence) of bit planes. To generate a sequence of bit planes, binary numbers are determined from each pixel’s grayscale level. Each binary' number has a number of bits corresponding to the bit depth of the display. A bit plane can be generated for each bit of the binary number. A sequence of bit planes can be arranged from a most significant bit plane, which includes a most significant bit (MSB) of the binaty number for each pixel, to a least significant bit plane, which includes a least significant bit (LSB) of the binary7number for each pixel. Rendering images on a display using bit planes can help reduce the power and size of the display, making these displays useful for mobile and / or body-wom applications.SUMMARY

[0004] A display can adjust which bit planes are used to render an image based on the brightness of the image. The adjustability allows for the efficient use of a buffer associated with the display, which can result in it being made smaller to reduce the power consumed by the display.

[0005] In some aspects, the techniques described herein relate to a method including: receiving an image; generating a set of bit planes based on the image; writing pairs of bit planes from the set of bit planes to respective segments of a buffer, each of the pairs including a more significant bit plane and a less significant bit plane; detecting that a pair of bit planes overlap in a particular segment; and disabling the less significant bit plane frombeing stored in the particular segment so that the more significant bit plane can be stored in the particular segment without overlap.

[0006] In a possible implementation of the method, generating the set of bit planes includes detecting zero pixels in each bit plane of the set of bit planes and removing groups of zero pixels form each bit plane before writing the bit planes to the buffer so that each bit plane has a different compressed length.

[0007] In some aspects, the techniques described herein relate to a display including: a bit plane generator configured to generate a set of bit planes based on an image received at the display; a zero detector configured to remove groups of zero pixels in each bit plane so that each bit plane in the set of bit planes has a different compressed length; and a buffer including segments configured to store pairs of bit planes, each pair including a more significant bit plane and a less significant bit plane from the set of bit planes, the buffer including a controller configured to: detect that a pair of bit lanes overlap in a particular segment; and disable the less significant bit plane of the pair from being stored so that the more significant bit plane can be stored in the particular segment without overlap.

[0008] In some aspects, the techniques described herein relate to a method for displaying an image, the method including: receiving a sequence of bit planes, each bit plane having a different data length; classifying each bit plane as more significant or less significant based on its position in the sequence of bit planes; writing more significant bit planes and less significant bit planes to segments of a buffer so that one more significant bit plane and one less significant bit plane is written to each segment; detecting a data overlap in a particular segment; disabling a particular bit plane from being stored in the particular segment in response to the data overlap; disabling each bit plane that is less significant than the particular bit plane from being stored in its respective segment; and storing all bit planes that have not been disabled in in the buffer.

[0009] The foregoing illustrative summary, as well as other exemplary objectives and / or advantages of the disclosure, and the manner in which the same are accomplished, are further explained within the following detailed description and its accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a system block diagram of a display according to a possible implementation of the present disclosure.

[0011] FIG. 2 illustrates a bit-plane sequence based on an image according to a possible implementation of the present disclosure.

[0012] FIG. 3A illustrates the contribution of each bit representing a grayscale level according to a possible implementation of the present disclosure.

[0013] FIG. 3B illustrates the effect of brightness on the content of bit planes according to a possible implementation of the present disclosure.

[0014] FIG. 4 is a system block diagram of a controller for a display according to a possible implementation of the present disclosure.

[0015] FIG. 5 is a flowchart of a method for displaying an image according to a possible implementation of the present disclosure.

[0016] FIG. 6 is a flowchart of a storage protocol according to a possible implementation of the present disclosure.

[0017] FIG. 7 illustrates growth rates of a pair of bit planes in a segment for a low brightness image and a high brightness image according to a possible implementation of the present disclosure.

[0018] FIG. 8 illustrates writing bit planes to segments of a buffer according to a possible implementation of the present disclosure.

[0019] FIG 9 illustrates a method for detecting a data overlap in a segment of a buffer according to a possible implementation of the present disclosure.

[0020] FIG. 10A illustrates a flagged bit-plane sequence according to a possible implementation of the present disclosure.

[0021] FIG. 10B illustrates rendering the flagged bit plane sequence according to a first possible implementation.

[0022] FIG. 10C illustrates rendering the flagged bit-plane sequence according to a second possible implementation.

[0023] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.DETAILED DESCRIPTION

[0024] A sequence of bit planes may be generated based on an image. The pixels of the bit planes are spatially arranged to have a one-to-one correspondence with the pixels of the image. Each pixel of a bit plane can have a binary value representing a bit of the gray scale level of its corresponding pixel in the image. Bit planes corresponding to more significant bits of the gray scale level (i.e., more significant bit planes) carry more visual information than less significant bit planes. A memory (e.g., buffer) can store bit planes so that they can be recalled (e.g., bitplane-by-bitplane) to render the image on a pixel array. During therendering, the pixels in the pixel array may be cycled ON / OFF according to a weighted sequence of bit planes so that a user perceives a gray scale level for each pixel.

[0025] For some applications (e.g., mobile devices), power consumption and physical size are strictly limited. For these applications, it may be desirable to reduce the size of the buffer used for the display. Reducing the size of the buffer can limit the number of bit planes that can be stored. Storing only the bit planes that contribute most to the gray scale levels of the image may help to reduce the size of the buffer without significantly affecting the quality of the image. A technical problem with this approach is that the selection of the bit planes necessary' for an acceptable image can depend on the brightness of the image.

[0026] The brightness of an image may be expressed as the average gray scale level of the pixels in the image. Dimmer images may have pixels with lower gray scale levels than brighter images. These lower gray scale levels can be represented without some of the more significant bit planes. For example, an eight-bit binary number can represent 32 gray scale levels (e.g., 00000000 to 00011111) without ever using the three most significant bits. Accordingly, if memory is limited, then only storing the less significant bit planes for low gray scale (i. e.. dim) images may be sufficient for rendering the image.

[0027] Brighter images may have pixels with higher gray scale levels than dimmer images. These higher gray scale levels can be approximated without some of the less significant bit planes. For example, a gray scale level of 255 (i.e., 11111111) can be reasonably approximated as 248 (i.e., 11111000) without the three least significant bits. Accordingly, if memory is limited, then only storing the most significant bit planes for high gray scale (i.e., bright) images may be sufficient for rendering the image.

[0028] The present disclosure describes methods for determining which bit planes should be stored based on the brightness of the image, which can be determined by computing how much memory is required for more significant bit planes versus less significant bit planes. The disclosure further describes how bit planes, which were disabled for storage, can be approximated when it comes time to render the image on the pixel array. Finally, the disclosure further describes how lossless compression techniques can be used to further reduce the size of each of the bit planes enabled for storage. What results is a display capable of displaying reasonably high-quality images with a very small buffer.

[0029] A technical effect of the proposed solution is a small buffer display that consumes less power and has a smaller mechanical size than other displays. These features facilitate the use of the disclosed display in body-worn devices (e.g.. augmented reality glasses, augmented reality goggles, smart watches, smart glasses, etc.).

[0030] FIG. 1 is a schematic block diagram of a display according to a possible implementation of the present disclosure. The display 100 includes a plurality of pixels arranged in a 2D grid (i.e., pixel array 120). Each pixel 121 includes a micro-LED configured to generate light while conducting a drive current from a drive current module 140. Each pixel 121 further includes a memory cell (e.g., SRAM) for setting and maintaining the illumination state of a micro-LED as ON or OFF. The state of an SRAM cell of a pixel can be controlled (i.e., set / reset) by a signal (e.g., bit-line signal) transmitted over a column conductor (i.e., bit-line) coupled to the SRAM cell. The SRAM cell of the pixel is coupled to the bit-line based on a signal (e.g., word-line signal) transmitted over a row conductor (i.e., word-line) to the pixel. Accordingly, the display 100 further includes a word-line driver 112 configured to transmit a word-line signal to a word-line (i.e., row) of the pixel array 120. The word-line signal can activate a row so that each pixel in an active row is coupled to its respective bit-line.

[0031] As shown in FIG. 1, the display 100 further includes a bit-line driver 113 configured to transmit bit-line signals to the bit-lines of the pixels in an active row. The bit- line signals may change or maintain the state of the SRAMs in the active row according to a bit plane for display. In a possible implementation, a bit-line signal is a differential signal. In this case, each bit-line may include a positive bit-line (BL+) configured to cany7a positive bit-line signal and a negative bit-line configured to carry a negative bit-line signal (BL-). In this differential configuration, the positive bit-line and the negative bit-line may be referred to collectively as the bit-line.

[0032] The display 100 further includes a controller 400 configured to control the operation of the word-line driver 112 and the bit-line driver 113 to render a bit plane on the pixel array 120. For example, the controller 400 may transmit a word-line signal (i.e., ROW) to activate a row and then transmit the bit plane data (i.e., DATA(COLUMN)) to the columns of the activated row.

[0033] The controller 400 may be configured to address and write to the SRAMs of the pixel array 120 so that each micro-LEDs is illuminated (i.e. ON) or not illuminated (i.e. OFF) according to a bit plane. Each bit plane may be rendered on the pixel array 120 on a row-by- row basis until every row necessary for rendering the bit plane has been activated.

[0034] In a possible implementation, a rendering process includes transmitting a wordline signal to activate a row7. After being activated, a bit-line signal for each pixel in the row controls the pixel ON / OFF according to the bit plane data for each pixel in the active row. After the bit-line signals configure (i.e., write to) the pixels of the active row, the row may bedeactivated, and another row may be activated until all rows of a bit plane have been activated. The SRAM cells for pixels in deactivated rows can hold the pixels of the deactivated rows ON or OFF while the other rows of the bit plane are activated. After writing a bit plane to the SRAM cells of the pixel array 120, the SRAM cells can hold their values (e.g., 0, 1) until they are changed. As a result, updating the values in an SRAM display may only require a portion of the SRAM cells to change their state (i.e., flip) from bit plane to bit plane. This feature of the display contributes to the low power consumption of the display.

[0035] The ON / OFF control of the pixels described above can be used to render a binary' bit plane in which each pixel is either ON (e.g., SRAM at binary 1) or OFF (e.g., SRAM at binary 0). A sequence of bit planes may be displayed at a high rate to create a grayscale image perceived by an observer.

[0036] FIG. 2 illustrates a sequence of bit planes for an image according to a possible implementation of the present disclosure. In this example, an image 201 has four pixels. Each pixel defines a location and a grayscale level. The grayscale level for each pixel of the image 201 may be represented as a binary number. The binary numbers have a number of bits corresponding to the bit depth of the display. In the example shown, the display is a four-bit display in which the gray scale level of each pixel is represented by a binary' number with four bits arranged left-to-right from the most significant bit to the least significant bit.

[0037] A bit plane sequence 220 can be generated to have a bit plane for each bit of the binary number. As shown, the bit plane sequence 220 includes four bit planes. A first bit plane in the sequence is a binary' image that represents the most significant bit (MSB) of each pixel (i.e., the most significant bit plane 221). A second bit plane 222 is less significant than the most significant bit plane 221. A third bit plane 223 is less significant than the second bit plane 222 but is more significant than the least significant bit plane 224, which represents the least significant bit (LSB) of each pixel. The bit plane sequence 220 may be divided in half to form a first group including the more significant bit planes 231 of the sequence and a second group including the less significant bit planes 232. When there are an odd number of bit planes, a median significant bit plane may have a significance in the sequence that is between the first group and the second group.

[0038] The significance of the bit planes with respect to the gray scale value decreases from the most significant bit plane 221 to the least significant bit plane 224. Accordingly, a first bit plane may be referred to as being below a second bit plane when the first bit plane is of lower significance (in the bit plane sequence 220) than the second bit plane. Likewise, thesecond bit plane may be referred to as being above the first bit plane when the second bit plane is of higher significance (in the bit plane sequence 220) than the first bit plane.

[0039] In the discussion so far, bit planes are described as being the bits of a binary representation of the grayscale levels of the pixels. As a result, a pair of adjacent bit planes have maximum pixel values separated by a factor of two (i.e., have a separation of 2x). In general, however, bit planes can be generated for different representations corresponding to the grayscale levels. For example, a pair of adjacent bit planes have maximum pixel values separated by a factor of four. What is more, this separation between pairs of bit planes may vary based on the pair’s significance in the sequence. For example, less significant bit planes may have a greater separation (e.g., 4x) than a lesser separation (e.g., 2x) of more significant bit planes. Any of these types of bit plane representations can be used with the techniques described herein.

[0040] Rendering the gray scale image may include writing each bit plane to the pixel array (i.e., SRAM) in succession during a rendering period. When each bit plane is displayed at the same intensity, each bit plane may be weighted by the duration that it is displayed relative to the other bit planes. As shown, the weights (W) of the bit planes may double for each bit plane from the least significant bit plane 224 to the most significant bit plane 221. In other words, the portions of the rendering period may double for each successive bit plane from the least significant bit plane 224 to the most significant bit plane 221.

[0041] The quality of an image may be determined by how well the sequence of bit planes represents the gray scale level of each pixel. The significance of the bit plane may correspond to how much its bit contributes to the binary value. More significant bit planes may contribute more image information than less significant bit planes.

[0042] FIG. 3A illustrates the contribution of each bit representing a grayscale level according to a possible implementation of the present disclosure. As shown, the binary number, 11111111, represents the grayscale level value of 255. The binary number includes eight bits (i.e., bl, b2, b3, b4, b5, b6, b7, b8) ranging from the most significant bit (bl) to the least significant bit (b8). The bits can be classified as more significant bits 301 (i.e.. bl. b2. b3, b4) or less significant bits 302 (i.e., b5, b6, b7, b8).

[0043] The graph illustrates how each bit contributes to this grayscale level value. As shown, half of the gray scale level of 255 is determined by the most significant bit. In fact, the more significant bits 301 (bl, b2, b3, b4) contribute 94% of the grayscale level of 255, while the less significant bits 302 (i.e., b5, b6, b7, b8) contribute 6% of the grayscale level of255. Accordingly, gray scale levels in a bright range (e g., 240 to 255) can be approximated using the more significant bits 301 because these bits are most significant in the bright range. This is not the case for gray scale levels in a dim range (e.g., 0 to 15) because the more significant bits 301 are unused (i.e., zero) in the dim range.

[0044] Selecting bit planes to best represent an image is based on the grayscale levels of the pixels in the image (i.e., the image brightness). Brighter images have pixels with higher grayscale levels than dimmer images. In other words, brighter images will have more significant bit planes that are used (i.e., include nonzero pixels), while dimmer images will have more significant bit planes that are unused (i.e., include all zero pixels). Accordingly, determining which bit planes to store in a limited buffer size may be based on the zero and nonzero content of the bit planes, which depends on the brightness of the image.

[0045] FIG. 3B illustrates the effect of brightness on the content of bit planes according to a possible implementation of the present disclosure. The bit planes generated for a display are shown for the same image at three brightness levels. In this example, eight bit planes are generated, all bit planes are the same size, and the capacity of the buffer is five bit planes. Bit planes required (i.e.. used) to represent the grayscale levels of the image are nonzero while bit planes not required (i.e., unused) to represent the grayscale levels of the image are zero.

[0046] At a dim brightness 311, the less significant bit planes (i.e., 6, 7, 8) are used (i.e., nonzero), while more significant bit planes (i.e.. 1, 2, 3, 4, 5) are unused (i.e., zero). Accordingly, if the buffer can only store five bit planes, then a first group 321 of the bit planes (i.e., 4, 5, 6, 7, 8) may be selected for storage in the buffer (i.e., enabled), while the remaining bit planes (i.e., 1, 2, 3) may not be stored in the buffer (i.e., disabled).

[0047] At a moderate brightness 312 more of the bit planes (i.e., 3, 4, 5, 6, 7, 8) are used (i.e., nonzero), but some (i.e., 1, 2) are still unused to represent the grayscale levels of the pixels (i.e., zero). Accordingly, if the buffer can only store five bit planes, then a second group 322 of the bit planes (i.e., 3, 4, 5, 6, 7) may be stored in the buffer (i.e., enabled), while the remaining bit planes (i.e., 1, 2, 8) may not be stored in the buffer (i.e., disabled). The least significant bit plane (i.e., 8) can be disabled because it affects the grayscale level the least. The most significant bit planes (i.e.. 1, 2) can be disabled because they are unused (i.e., zero).

[0048] At a high brightness 313, all of the bit planes (i.e., 1, 2, 3, 4, 5, 6, 7, 8) are used (i.e., nonzero). Accordingly, if the buffer can only store five bit planes, then a third group 323 of the bit planes (i.e., 1, 2. 3, 4, 5) may be stored in the buffer (i.e.. enabled), while the remaining bit planes (i.e., 6, 7, 8) may not be stored in the buffer (i.e., disabled). The leastsignificant bit planes (i.e., 6, 7, 8) can be disabled because they affect the grayscale level the least (see. FIG. 3A).

[0049] The bit planes may be compressed before being stored in the buffer. After compression, each bit plane may have a reduced size (i.e., data length, length), and the compressed data length (i.e., compressed length) of each bit plane may be different. The compression of a bit lane may include removing groups (e.g., pairs, lines, areas, etc.) of zero pixels from the bit plane before storage. A map specifying the locations of the removed zero pixels (i.e. zero-pixel map) may be created so that when the stored bit plane is recalled, these zero pixels can be added back to reconstruct the original bit plane without loss of information. The compression of the bit planes complicates the selection of bit planes and makes the bit plane capacity of the buffer less certain.

[0050] FIG. 4 is a system block diagram of a controller for a display according to a possible implementation of the present disclosure. The controller may be implemented as a unitary device or may be part of a distributed computing system. The controller 400 includes digital processing, logic, and memory to perform the operations associated with controlling the pixels in a pixel array to render (i.e.. display) an image. These operations may be performed by modules, which can include circuitry and / or software to perform one or more of the operations.

[0051] As shown in FIG. 4, the controller 400 includes a display preprocessor module (i.e., display preprocessor 410). The display preprocessor 410 may be configured to receive an image for display. The image may be a grayscale image or a color image. A color image for display can include three color channels, each represented by a gray scale image. Accordingly, the example of a grayscale image for display will be discussed in detail.

[0052] As shown in FIG. 4, the controller 400 can include a display preprocessor 410. The display preprocessor 410 may be configured to prepare the image for display. The preparation may include formatting, thresholding, and the like. After preprocessing a bit plane generator 415 can generate a set of bit planes based on the image. The bit plane generator 415 may generate a number of bit planes that is larger than what is ultimately stored based on the idea that some bit planes will be removed because they are unused or insignificant.

[0053] As shown in FIG. 4, the controller 400 can include a zero pixel detection / removal module (i.e. a zero detector 425). The zero detector 425 is configured to receive the set of bit planes and generate a compressed bit plane based on each bit plane in the set. In a possible implementation, the compression can include detecting compressible portions in each bitplane, which can be groups (e.g., segments, groups, rows, areas, lines, etc.) of pixels that have a grayscale level (i.e. , intensity) that is zero (i. e.. zero pixels). In other words, the zero detector 425 can remove groups of zero pixels in each bit plane so that each bit plane has a different compressed length. Bit planes that are all zero pixels (i.e., unused bit planes) may be removed altogether so that the zero detector 425 outputs only nonzero bit planes.

[0054] The compressed bit planes (i.e., nonzero bit planes) may have a reduced size (i.e., data length) compared to the received bit plane. Highly compressible bit planes may have a very short data length (i.e. length), while less compressible bit planes may have a data length that is almost as long as the received bit planes. The data length is expressed in the context of the storage size of a buffer 450, which is configured to store the nonzero bit planes after zeropixel removal. For example, the data length of a compressed bit plane may be the number (i.e., a count) of nonzero bits in the compressed (i.e., nonzero) bit plane.

[0055] The buffer 450 may be partitioned into segments that are configured to store the bit planes. Each segment can be defined by the memory' locations associated with the segment. For example, a segment may begin at a first location (i.e., first memory’ address) in the buffer and end at a second location (e.g., second memory address) in the buffer. Writing a bit plane to a segment may include (i) starting to write at the first location and writing in a first direction towards the second location or (ii) starting to write at the second location and writing in a second direction towards the first location. Pairs of bit planes may be written to each segment of the buffer 450. For example, the first bit plane of the pair may be written in the first direction from the first location and the second bit plane of the pair may be written in the second direction from the second location. In other words, a pair of bit planes may be written to a segment of the buffer 450 so that as they are written, they grow towards each other in the segment.

[0056] The controller 400 may further include a zero-pixel map generator configured to generate zero-pixel maps 420 for each of the nonzero bit planes. Each zero-pixel map can locate the groups of zero pixels removed from a corresponding bit plane. For example, the zero-pixel map can include row and column addresses corresponding to the zero pixels in the bit plane, which were removed by the zero detector 425.

[0057] As shown in FIG. 4, the controller 400 may further include a nonzero bitplane reader 455 configured to recall nonzero bit planes from the buffer 450. In a possible implementation, some of the nonzero bit planes are disabled from being stored due to an overwrite condition detected in a segment. The nonzero bitplane reader 455 can reconstruct bit planes to include both nonzero and zero pixels based on the zero-pixel maps 420. Thereconstruction replaces the removed zero pixels with zero pixels so there is no loss of information (i.e.. lossless compression). The controller 400 further includes a display post processor 460 that can create the weighted sequence of bit planes and the word-line and bit- line signals necessary for rendering the bit planes on the pixel array.

[0058] FIG. 5 is a flowchart of a method for display ing an image according to a possible implementation of the present disclosure. Steps of method may be implemented by controller 400 described previously. The method 500 includes receiving an image and converting 510 the image to a set of bit planes. Each bit plane has an equal data length with may be expressed as the number of pixels in the image. The method 500 further includes reducing these data lengths by detecting and removing 520 groups of zero pixels from each bit plane to form nonzero bit planes. At the same time, zero-pixels maps are generated 570 so that the removal process can be reversed. The method 500 further includes writing 530 the (nonzero) bit planes to a buffer 450 according to a storage protocol. The storage protocol can include writing the bit planes in pairs to respective segments of the buffer so that each segment includes a more significant bit plane and a less significant bit plane. Based on the data lengths of the (nonzero) bit planes, one or more of the bit planes may be disabled so that they are not stored in the buffer 450. In other words, the buffer 450 may contain a subset of the (nonzero) bit planes. The bit planes that are stored may be recalled 540 and reconstituted into full length bit planes by replacing 550 the removed zero pixels. The prescription for where to replace the zero pixels in a bit plane may be provided by the zero-pixels map for the bit plane. The method 500 further includes rendering 560 the image on the pixel array based on the bit planes.

[0059] While the recalled bit planes have had their zero-pixels restored at this point, some bit planes may be missing from the set of bit planes because they were not written to the buffer 450 per the storage protocol. Accordingly, the rendering 560 may include replacing the disabled bit plane (or bit planes) with an approximate bit plane. The approximate bit plane may take the place of the disabled bit plane (or bit planes) in the sequence of bit planes presented on the pixel array 120. In one possible implementation, the approximate bit plane is a bit plane including all zeros. In another possible implementation, the approximate bit plane is a bit plane including all ones. In another possible implementation, the approximate bit plane is a bit plane that has pixels equal to the corresponding pixels in a bit plane recalled from the buffer. For example, a disabled bit plane may be replaced with an approximate bit plane that matches the next higher significance bit plane in the sequence of bit planes.

[0060] FIG. 6 is a flowchart of a storage protocol according to a possible implementation of the present disclosure. The storage protocol 600 includes receiving 610 a sequence of bit planes for storage in a buffer. Each bit plane, which is received, can have a different length as a result of a (lossless) compression (e.g., zero-pixel removal) to reduce its size (i.e., data length). The storage protocol 600 further includes classifying 620 (i.e., grouping, designating, etc.) each bit plane in the sequence as more significant or less significant. The grouping of the bit planes may be based on each bit plane's position in the sequence. The storage protocol 600 further includes writing 630 the bit planes, in pairs, to the segments of the buffer. Each pair includes a bit plane from the more significant group of bit planes and a bit plane from the less significant group of bit planes. The number of segments in the buffer can correspond to the number of pairs so that each segment includes a unique segment pair. In each segment 615, the less significant bit plane 631 of the segment pair is written starting at a first position and in a first direction. The first position may be a first edge 621 (e.g., top edge) of the segment and the first direction can be into the segment away from the first edge 621 and towards a second edge 622 (e.g., bottom edge) of the segment 615. At the same time, the more significant bit plane 632 may be wnting starting at a second position (e.g., the second edge 622) and in a second direction. The first direction and the second direction are opposite to each other. In other words, the pair of bit planes are written towards each other from opposite edges of the segment 615. As the pair of bit planes are written, they fill the segment 615 independently based on their content. The rates that each bit plane fills the segment may be referred to as its growth rate.

[0061] FIG. 7 illustrates growth rates of a pair of bit planes in a segment for a low brightness image and a high brightness image according to a possible implementation of the present disclosure. As shown, for an image with a relatively low brightness 710. the less significant bit planes 711 have a higher growth rate in the buffer than the more significant bit planes 712. The higher growth rate of the less significant bit planes 711 may be due to the fact that there can be many more low grayscale level pixels than high grayscale level pixels when the image has a low brightness. For an image with a relatively high brightness 720, the less significant bit planes 721 and the more significant bit planes 722 have approximately the same growth rate. The comparable growth rates may be due to the fact that most pixels have high grayscale levels which require all bits to enumerate.

[0062] Returning to FIG. 6, the storage protocol 600 further includes detecting 640 a data overlap in the data in the segment. The data overlap may include the less significant bit plane 631 and the more significant bit plane 632 attempting to write to the same memory location.Accordingly, this may also be referred to as a data collision. Computationally this detection can include counting a first data length of the less significant bit plane 631 (e.g., as it is written) and counting a second data length of the more significant bit plane 632 (e.g., as it is written) and comparing the sum of these data lengths to a data length of the segment 615, which can be the number of storage bits (i.e., locations) between the first edge 621 and the second edge 622 of the segment 615.

[0063] As shown in FIG. 6, after a data overlap is detected, the storage protocol 600 further includes disabling 650 a particular bit plane (of the pair of bit planes) from being stored in the segment 615. Disabling one of the bit planes of the pair allows the other bit plane of the pair to w rite over the disabled bit plane’s former memory locations and fill more of the segment. Disabling the less significant bit plane may lead to a more accurate approximation of the gray scale level (see FIG. 3A). Disabling the particular bit plane means that a subset of the bit planes received will be stored in the buffer. As a result, the disabled bit plane (or bit planes) may be flagged as not existing for rendering. The image rendered on the display will use a subset of bit planes generated, which means the grayscale levels of the rendered image will be approximate. This approximation may be an acceptable trade for the reduced size and power consumption of a smaller buffer.

[0064] As shown in FIG. 6, the storage protocol 600 may also disable 660 each bit plane that is less significant than the particular bit plane, which resulted in the data overlap. For example, in a bit plane sequence where each bit plane is numbered as BPi, BP2, BP3. BP4, BP5, BPe, BP7, and BPs from MSB to LSB, if BPe is disabled, then BP7 and BPs are also be disabled. Disabling the bit planes can flag them as disabled which can instruct the buffer not to write these bit planes and can indicate that they w ere not stored in the buffer w hen the bit planes are recalled. The storage protocol 600 further includes storing 670 all bit planes that have not been disabled to the respective segments of the buffer.

[0065] FIG. 8 illustrates writing bit planes to segments of a buffer according to a possible implementation of the present disclosure. As shown, a buffer 450 includes a buffer that can be addressed according to segments, where each segment is a range of memory locations (i.e. addresses) in the buffer 450. Each segment has a segment length corresponding to the amount of data (i.e., data length) that can be stored between a first location (i.e., first address) and a second location (i.e., second address). The segment length corresponds to the maximum data length that a bit plane can have and be stored properly in the buffer 450.

[0066] As shown in FIG. 8, a bit plane sequence, where each bit plane numbered as BPi. BP2, BP?, BPy BPs, BPe, BP7, and BPs from MSB to LSB, is w ritten, pairwise, to equal-sizedsegments (i.e., SEGi, SEG2, SEG3, SEG4) of a buffer 450. The buffer 450 includes as many segments as pairs. The pairs are selected from more significant bit planes 801 (i.e., BP1. BP2, BP3, BP4) and less significant bit planes 802 (i.e., BP5, BP6, BP7, BP8) groups. In this example, BPi is paired with BPs in SEGi; BP2 is paired with BPe in SEG2; BPs is paired with BP7 in SEG3; and BP4 is paired with BPs in SEG4. In other possible implementations, the bit planes may be paired differently (e.g., BPi is paired with BPs, etc.). In other possible implementations the segments may be sized differently. For example, a segment configured to store more significant bit planes (e g., SEGi) may be allocated more data length than a segment configured to store less significant bit planes (e.g., SEG4).

[0067] The size of bit planes may be monitored to detect a data overlap. FIG 9 illustrates a method for detecting a data overlap in a segment of a buffer according to a possible implementation of the present disclosure. The method 900 includes determining 910 a more significant bit plane (e.g., BP2 in FIG. 8) of a segment (e.g., SEG2 in FIG. 8)and a less significant bit plane (e.g., BP6 in FIG. 8) of the segment. The method 900 includes counting 920 the nonzero data length of the more significant bit plane (i.e.. MSBP) to obtain a first count 921, and the method 900 includes counting 925 the nonzero data length of the less significant bit plane (i.e., LSBP) to obtain a second count 926. The counts correspond to a first data length and a second data length respectively. The data lengths can be combined and compared to the segment length (e.g., SEG. LENGTH in FIG. 8) to determine an overlap in the segment. In other words, an overlap may occur when a first data length of the more significant bit plane combined with a second data length of the less significant bit plane equals, or exceeds, the segment length. Accordingly, the method 900 includes adding 930 the first count 921 and the second count 926 and comparing 940 the sum to the segment length. If the sum is less than the segment length, then the method 900 includes writing 945 both bit planes to the segment. If the sum is greater than or equal to the segment length, then a data overlap is detected 950. In response to the data overlap, the less significant bit plane can be flagged 955. Flagging the bit plane may change the way that a controller writes the bit planes to the buffer. For example, based on the flag, the less significant bit plan can be disabled so that it is not written to the segment and so that any portion of the segment including a portion of the disabled bit plane can be overwritten. After disabling the less significant bit plane from being stored in the segment, only the more significant bitplane is written 950 to the segment. In other words, after a data overlap is detected, the entire segment may be made available for storing the more significant bit plane. A (second) flag for the more significantbit plane may be generated, if this bit plane is too large for the entire segment. In this case, the second flag may disable the more significant bit plane from being written to the segment.

[0068] Flagging a bit plane can change the way a controller (e.g., a buffer controller) writes the bit planes to the buffer. In a first possible implementation, flagging a bit plane may disable (only) the flagged bit plane from being stored in the buffer. In a second possible implementation, flagging a bit plane may disable the bit plane and any bit plane less significant than the flagged bit plane from being stored in the buffer.

[0069] Flagging a bit plane can change the way a controller (e g., the nonzero bitplane reader 455) recalls the bit planes from the buffer and reconstructs a bit plane sequence for rendering on the pixel array. For example, a flag can indicate that the bit plane is not in the buffer. A flag can trigger the controller to remove or replace the bit plane from a reconstructed sequence. For example, the flag may trigger the controller to generate an approximate bit plane to replace the absent bit plane in the reconstructed sequence.Rendering the image on a display can be based on a subset of bit planes and approximations for the disabled bit planes (i.e., approximate bit planes).

[0070] FIG. 10A illustrates a flagged bit-plane sequence according to a possible implementation of the present disclosure. As shown, two bit planes (i.e., BP5 and BP7) are flagged as being disabled (i.e. not stored) in the buffer. In other words, a subset (BP1, BP2, BP3, BP4, BP6, and BP8) are available for display. The subset includes two empty spaces (i.e., periods) in the time sequence of the bit planes. The empty spaces correspond to missing bits in the gray scale level. The missing bit planes can be replaced so that the gray scale level generated by the sequence approximates the gray scale level of the image within an acceptable (e.g., predetermined) margin of error.

[0071] FIG. 10B illustrates rendering the flagged bit plane sequence according to a first possible implementation. The empty spaces resulting from the flagged bit planes (i.e., BP5, BP7) may be filled using other bit planes of the sequence. For example, a period that a preceding bit plane is displayed can be adjusted (i.e. lengthened) to cover a period of the missing bit plane in the sequence. For example, a preceding bit plane (i.e., BP4) may be displayed for an adjusted period 1010 covering its period in the sequence and the period of the disabled bit plane (i.e., BP5) in the sequence. Likewise, the missing bit plane, BP7, may be replaced with its preceding bit plane (i.e., BP6) in the sequence.

[0072] FIG. 10B illustrates rendering the flagged bit plane sequence according to a first possible implementation. As shown, the disabled bit planes (BP5 and BP7) are not displayed. In other words, a subset (BP1, BP2, BP3, BP4, BP6, and BP8) are available for display. Thedisabled bit planes can be approximated in the time sequence of bit planes by extending the time a previous bit plane is displayed in the time sequence. For example, BP4 can be displayed in place of BP5.

[0073] FIG. 10C illustrates rendering the flagged bit-plane sequence according to a second possible implementation. The empty7spaces resulting from the flagged bit planes (i.e., BPS, BP7) may be filled using approximate bit planes. In a first possible implementation, an approximate bit plane is a bit plane including pixels that are all one. In a second possible implementation, an approximate bit plane is a bit plane including pixels that are all zero. The approximations may be extended to any disabled bit plane. For example, when all bit planes less significant than a flagged bit plane are disabled, then these disabled bit planes may be replaced by the approximate bit plane.

[0074] In the specification and / or figures, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term “and / or” includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and so are not necessarily drawn to scale. Unless otherwise noted, specific terms have been used in a generic and descriptive sense and not for purposes of limitation.

[0075] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification, and in the appended claims, the singular forms “a,” “an,” “the” include plural referents unless the context clearly dictates otherwise. The term “comprising” and variations thereof as used herein is used synonymously with the term “including” and variations thereof and are open, non-limiting terms. The terms “optional” or “optionally” used herein mean that the subsequently described feature, event or circumstance may or may not occur, and that the description includes instances where said feature, event or circumstance occurs and instances where it does not. Ranges may be expressed herein as from "about" one particular value, and / or to "about" another particular value. When such a range is expressed, an aspect includes from the one particular value and / or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.

[0076] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or sub-combinations of the functions, components and / or features of the different implementations described.

[0077] It will be understood that, in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on. directly connected to or directly coupled to another element, there are no intervening elements present. Although the terms directly on. directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application, if any, may be amended to recite exemplary relationships described in the specification or shown in the figures.

[0078] As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

Claims

WHAT IS CLAIMED IS:

1. A method comprising: receiving an image; generating a set of bit planes based on the image; writing pairs of bit planes from the set of bit planes to respective segments of a buffer, each of the pairs including a more significant bit plane and a less significant bit plane; detecting that a pair of bit planes overlap in a particular segment; and disabling the less significant bit plane from being stored in the particular segment so that the more significant bit plane can be stored in the particular segment without overlap.

2. The method according to claim 1, wherein generating the set of bit planes includes: detecting zero pixels in each bit plane of the set of bit planes; and removing groups of zero pixels from each bit plane before writing the bit planes to the buffer.

3. The method according to claim 2, further comprising: generating zero-pixel maps for respective bit planes based on the groups of zero pixels removed from each bit plane so that each bit plane may be reconstructed without loss of information.

4. The method according to any one of the preceding claims, wherein writing the pairs of bit planes from the set of bit planes to the respective segments of the buffer includes: writing the more significant bit plane in a first direction from a first location of the particular segment; and writing the less significant bit plane in a second direction from a second location of the particular segment, the second direction opposite to the first direction.

5. The method according to claim 4, wherein a segment length between the first location and the second location corresponds to a maximum data length of a bit plane.

6. The method according to any one of the preceding claims, wherein detecting that the pair of bit planes overlap includes: determining that a first data length of the more significant bit plane combined with a second data length of the less significant bit plane exceeds a segment length of the particular segment.

7. The method according to any one of the preceding claims, further comprising: further disabling additional bit planes of the set of bit planes that are lower in significance than the less significant bit plane, which was disabled from being stored in the particular segment.

8. The method according to any one of the preceding claims, further comprising: recalling a subset of bit planes from the buffer, the subset of bit planes not including the less significant bit plane, which was disabled from being stored; and rendering the image on a display based on the subset of bit planes.

9. The method according to claim 8, wherein rendering the image on the display based on the subset of bit planes includes: replacing the less significant bit plane, which was disabled from being stored, with an approximate bit plane; and displaying the subset of bit planes and the approximate bit plane in a sequence.

10. The method according to claim 9, wherein the approximate bit plane has all pixels equal to zero.

11. The method according to claim 9, wherein the approximate bit plane has all pixels equal to one.

12. The method according to claim 9, wherein the approximate bit plane has pixels equal to corresponding pixels in another bit plane in the subset of bit planes.

13. A display comprising: a bit plane generator configured to generate a set of bit planes based on an image received at the display; anda buffer including segments configured to store pairs of bit planes, each pair including a more significant bit plane and a less significant bit plane from the set of bit planes, the buffer including a controller configured to: detect that a pair of bit lanes overlap in a particular segment; and disable the less significant bit plane of the pair from being stored so that the more significant bit plane can be stored in the particular segment without overlap.

14. The display according to claim 13, further comprising: a zero detector configured to remove groups of zero pixels in each bit plane so that each bit plane in the set of bit planes has a different compressed length; a zero-pixel map generator configured to: generate zero-pixel maps for respective bit planes based on the groups of zero pixels removed from each bit plane; and a nonzero bitplane reader configured to: recall a subset of bit planes from the buffer, the subset of bit planes not including the less significant bit plane, which was disabled from being stored; and replacing the groups of zero pixels removed based on the zero-pixel maps.

15. The display according to claim 14. further comprising a display post processor configured to: replace the less significant bit plane, which was disabled from being stored, with an approximate bit plane; and address a pixel array to display the subset of bit planes and the approximate bit plane in a sequence.

16. The display according to claim 15, wherein the approximate bit plane has all pixels equal to zero or all pixels equal to one.

17. The display according to claim 15. wherein the approximate bit plane has pixels equal to corresponding pixels in another bit plane in the subset of bit planes.

18. A method for displaying an image, the method comprising: receiving a sequence of bit planes, each bit plane having a different data length;classifying each bit plane as more significant or less significant based on its position in the sequence of bit planes; writing more significant bit planes and less significant bit planes to segments of a buffer so that one more significant bit plane and one less significant bit plane is written to each segment; detecting a data overlap in a particular segment; disabling a particular bit plane from being stored in the particular segment in response to the data overlap; disabling each bit plane that is less significant than the particular bit plane from being stored in its respective segment; and storing all bit planes that have not been disabled in in the buffer.

19. The method according to claim 18, wherein writing to each segment of the buffer includes: starting to write a more significant bit plane at a first location and writing the more significant bit plane in a first direction; starting to write a less significant bit plane at a second location and writing the less significant bit plane in a second direction, opposite to the first direction; counting a first data length of the more significant bit plane and a second data length of the less significant bit plane as they are being written; and comparing a sum of the first data length and the second data length to a segment length of the particular segment.

20. The method according to claim 19, further comprising: recalling the bit planes that have not been disabled from the buffer; generating a bit plane sequence including the bit planes recalled from the buffer and approximate bit planes replacing each disabled bit plane; and rendering the bit plane sequence on a pixel array to display the image.

Images