Phase detector

Abstract

Described herein is a method for determining a time-varying phase difference between two time- varying signals, the method comprising: receiving or generating two independent time-varying in-phase components and two independent time-varying quadrature components from two or more demodulated time-varying signals; determining the time-varying phase difference from the two time-varying in-phase components and two time-varying quadrature components by: combining the four signals at each time point; and determining a time-varying phase difference from the combined signals, and optionally determining a time-varying phase from the time-varying phase difference.

Description

PHASE DETECTOR Technical Field

[0001] The present disclosure relates to systems and methods for phase determination, including determining (which includes measuring and / or recovering) time-varying phase of time-varying signals.

[0002] The invention has been developed primarily for use in methods and systems for detecting time-varying phase of time-varying signals using an open-loop phasemeter topology for differential optical interferometric measurements and will be described hereinafter with reference to this application. However, it will be appreciated that the invention is not limited to this particular field of use. Background

[0003] Any discussion of the background art throughout the specification should in no way be considered as an admission that such background art is prior art, nor that such background art is widely known or forms part of the common general knowledge in the field in Australia or worldwide as at the priority date of the present application.

[0004] All references, including any patents or patent applications, cited in this specification are hereby incorporated by reference, which means that it should be read and considered by the reader as part of this text. That the document, reference, patent application or patent cited in this text is not repeated in this text is merely for reasons of conciseness.

[0005] No admission is made that any reference or documentation cited in the present specification constitutes prior art. The discussion of the references states what their authors assert, and the applicants reserve the right to challenge the accuracy and pertinence of the cited documents. It will be clearly understood that, although a number of prior art publications may be referred to herein, such reference does not constitute an admission that any of these documents forms part of the common general knowledge in the art, in Australia or in any other country, at the priority date of the application

[0006] Detecting time-varying phase of time-varying signals is important in many signal processing systems. Various types of phase detection techniques have been used to deliver precision radio frequency (RF) phase measurements.

[0007] Precision optical interferometer metrology employs a range of techniques to measure the optical phase at the interferometer output. Frequently used techniques include heterodyne [1–3] and homodyne [4–7] schemes that both effectively generate the in-phase (I) and quadrature (Q) components of the interferometer optical field. An arctangent operation can then return the desired optical phase, with phase-unwrapping yielding the total integrated phase ^^ = unwrap{arctan( ^^ / ^^)} in an open loop configuration.

[0008] In either case, there are a number of interferometer configurations that can benefit from using phase difference measurements to remove common noise sources and thus improve measurand sensitivity. Examples, include, laser interferometer length measurements [1,8], fiber strain sensing [9], interferometer stability characterization [10,11], cyclic error reduction [12,13] and, dispersion spectroscopy

[0014] . In these scenarios, common mode noise suppression through phase subtraction is integral to achieving the desired sensitivity.

[0009] Typical phase subtraction techniques use two phasemeters that independently track their required phases with the subtraction computed following phase recovery. This requires each phasemeter to phase track with the required sensitivity of the final subtraction and the dynamic range of the individual signals to fully remove common noise sources. However, in the presence of large and fast common dynamics, the aforementioned arctangent and unwrap operations can degrade. This makes achieving the required phase fidelity on each individual phasemeter difficult. Therefore, a trade-off exists between the differential measurement sensitivity and the individual measurement dynamic range.

[0010] In order to address this trade off, Heinzel et al

[0015] proposed a novel solution when using wavefront sensing to extract beam pointing errors in addition to longitudinal length sensing, for the Laser Interferometer Space Antenna mission (LISA)

[0016] . Heinzel et al. demonstrate; four parallel PLLs, a combination matrix, individually tailored servo controllers for each variable of interest and, a decombination matrix. This solution removes common mode dynamics from each phase-difference variable. This, in turn, allows the optimization of each controller dependent only on the dynamics of the particular variable. However, in order to operate correctly, all four PLLs must phase track without error. If the high speed, longitudinal variable PLL cycle slips, then all variables are compromised.

[0011] One type of phase detection technique uses an arctan operation. This technique is used in conjunction with quadrature demodulation (also referred to as “IQ demodulation”) to return the in-phase (“I”) and quadrature (“Q”) components of a time-varying signal, e.g., representing an RF field. The “I” and “Q” components are referred to as an “IQ pair”.

[0012] Arctan typically uses the “arctan2” algorithm operating on an IQ pair to produce phase (ϕ) using the following operation: arctan(Q / I) modulo 2π. The arctan2 function has discontinuities at ±π where the Q value transits zero and the I value is negative. An unwrapping algorithm, the second component of this phase recovery method, is then required to recover the desired phase (ϕ) using the following operation: unwrap{arctan(Q / I)} to remove the discontinuities. A significant limitation of the arctan operation arises when the unwrap algorithm must make a decision to either unwrap, or not, at or near a discontinuity based on the immediate history of phase evolution. As the phase discontinuity point corresponds to a zero in Q, even a small amount of noise at this location can generate an incorrect unwrap decision. Accurate decision-making therefore requires high bandwidth and high-fidelity phase measurements that encompass all signal phase dynamics, even if the required signal bandwidth is modest. When this onerous requirement is not met, cycle slips will occur, corrupting the recovered phase signal.

[0013] Thus, due to the high noise susceptibility of the arctan-unwrap technique at the phase discontinuity points, precision phase metrology seldom uses this technique for large dynamic range phase tracking.

[0014] Another type of phase detection technique uses a phase-locked loop (PLL). The PLL avoids phase unwrapping and the related cycle slip issues of the arctan-unwrap technique. The PLL typically mixes down a single quadrature component (Q) and, after low pass filtering, uses this Q component to drive a numerically controlled oscillator (NCO), or a voltage-controlled oscillator (VCO) in an analog PLL. The NCO / VCO drives the original mixer used to extract the Q component, thus providing negative feedback that tracks the phase of the time-varying input signal. Phase recovery is obtained by integrating the control signal provided to the NCO / VCO. The PLL may be understood to use negative feedback to linearize the Q component and thus recover the signal phase.

[0015] However, the PLL architecture requires that all significant signal phase dynamics are tracked and that the total phase dynamics at frequencies above the PLL unity gain frequency are sufficiently small to stay well within the linear range of the Q component mixer response. Additionally, the in-loop sensor noise is limited by shot noise, dark noise and ADC noise; thus, if the total sensor noise, when integrated across the PLL bandwidth, becomes sufficiently large to drive the Q component mixer response outside its linear response range, then cycle slipping may occur and phase tracking will become compromised.

[0016] It is desired to address or ameliorate one or more disadvantages or limitations associated with existing systems and methods, or to at least provide a useful alternative. Summary

[0017] It is an object of the present invention to overcome or ameliorate at least one or more of the disadvantages of the prior art, or to provide a useful alternative.

[0018] Throughout this specification, unless the context requires otherwise, the words “comprise”, “comprises” and “comprising” will be understood to imply the inclusion of a stated step or element or group of steps or elements but not the exclusion of any other step or element or group of steps or elements.

[0019] Any one of the terms “including” or “which includes” or “that includes” as used herein is also an open term that also means including at least the elements / features that follow the term, but not excluding others. Thus, “including” is synonymous with and means “comprising”.

[0020] In the claims, as well as in the summary above and the description below, all transitional phrases such as “comprising”, “including”, “carrying”, “having”, “containing”, “involving”, “holding”, “composed of”, and the like are to be understood to be open-ended, i.e., to mean “including but not limited to”. Only the transitional phrases “consisting of” and “consisting essentially of” alone shall be closed or semi-closed transitional phrases, respectively.

[0021] Even though particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of possible implementations. In fact, many of these features may be combined in waysnot specifically recited in the claims and / or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of possible implementations includes each dependent claim in combination with every other claim in the claim set.

[0022] Disclosed herein is an improved phase detection method, Direct Differential Phase Recovery (DDPR)¾an open-loop phasemeter topology for differential optical interferometric measurements. Embodiments of the methods described remove common mode signal dynamics prior to phase tracking, which reduces the dynamic range requirements of the phasemeter tracking optical phase difference.

[0023] The DDPR phasemeter implementation described herein eliminates common phase signals prior to phase tracking. In doing so, it dramatically reduces the dynamic range and signal bandwidth required to measure phasemeter differences. Operating directly in ^^ ^^ space, DDPR generates the ^^ ^^ Vector of the phase subtraction. The phase difference alone can then be recovered by implementing the arctangent of the DDPR generated ^^ ^^ pair, removing the need to track the full dynamic range of the individual signals. In addition, by utilizing an arctangent phase readout we eliminate the need for feedback resulting in complete elimination of common mode dynamics such that high fidelity phase difference signals are routinely available when common mode phase dynamics make phase tracking impossible for individual channels.

[0024] According to a first aspect of the present invention, there is provided a method for determining a time-varying phase difference between two time- varying signals, the method comprising: receiving or generating two independent time-varying in-phase components and two independent time-varying quadrature components from two or more demodulated time-varying signals; and determining the time-varying phase difference from the two time-varying in-phase components and two time-varying quadrature components by combining the four signals at each time point.

[0025] The method may further comprise the step of determining a time-varying phase difference from the combined signals, and optionally determining a time-varying phase from the time-varying phase difference.

[0026] The step of determining the time- varying phase difference from the combined signals may comprise determining an arctan of the combined signals.

[0027] The method may further comprise the steps of anti-alias filtering and / or decimating the determined time-varying phase difference.

[0028] The step of determining the two independent time- varying in-phase components and the two independent time-varying quadrature component may comprise: automatically generating one of the two time-varying in-phase components by delaying the other of the two time-varying in-phase components by a selected time delay such that the two signals are independent; and automatically generating one of the two time-varying quadrature components by delaying the other of two time-varying quadrature components by the selected time delay such that the two signals are independent.

[0029] The step of determining the time- varying phase difference from the combined signals may comprise determining an arctan of the combined signals; or, when the selected time delay is below a predetermined threshold, determining that the time-varying phase difference is linearly related to the combined signals.

[0030] The step of determining the time-varying phase may comprise integrating the time-varying phase difference with respect to time.

[0031] The method may further comprise the step of performing the delaying and / or the integrating in one or more DSP hardware components, for example in FPGAs.

[0032] The method may further comprise the steps of anti-alias filtering and / or decimating the determined time-varying phase.

[0033] The step of determining the arctan of the combined signals may comprise the step of using a coordinate rotation method or component, for example on a coordinate rotation digital computer (CORDIC).

[0034] The step of combining the four determined signals into the combined signals may comprise: determining products of the [I1(t), I2(t)] and the [Q1(t), Q2(t)], including according to the relationships: IA.IB, QA.QB, QA.IB, and IA.QB.; anddetermining a sum and a difference of the products, including according to the relationships: (IA.IB + QA.QB), and (QA.IB ? IA.QB).

[0035] The step of determining the time-varying phase from the combined signals may comprise determining a ratio of the difference and the sum of the products, including according to the relationship: (QA.IB ? IA.QB) / (IA.IB + QA.QB).

[0036] The method may further comprise the step of determining the products, the sum, the difference and / or the ratio in one or more DSP hardware components, for example in one or more FPGAs.

[0037] The method may further comprise the step of low-pass filtering the four determined signals and prior to determining the time-varying phase difference, optionally using a code filter.

[0038] The time-varying phase difference or the time-varying phase may comprise radio frequencies.

[0039] According to a second aspect of the present invention, there is provided a system configured / built to perform the method according to the first aspect, for example in an FPGA.

[0040] According to a third aspect of the present invention, there is provided a system for determining a time-varying phase difference between two time- varying signals, the system comprising: means for receiving or generating two independent time-varying in-phase components and two independent time-varying quadrature components from two or more demodulated time-varying signals; and means for determining the time-varying phase difference from the two time-varying in-phase components and two time-varying quadrature components by combining the four signals at each time point.

[0041] The system may further comprise means for determining a time-varying phase difference from the combined signals, and optionally determining a time-varying phase from the time-varying phase difference.

[0042] In a further aspect, there is provided a method for determining a time-varying phase difference between two time-varying signals or a time-varying phase of one time-varying signal, the method comprising: receiving or generating two time-varying in-phase components and two time-varying quadrature components from one or more demodulated time-varying signals; and determining the time-varying phase difference from the two time- varying in-phase components and two time-varying quadrature components by: combining the four signals at each time point, and determining a time-varying phase difference from the combined signals; and optionally determining a time-varying phase from the time- varying phase difference.

[0043] In some embodiments, the two time-varying signals are independent signals.

[0044] In some embodiments, the step of determining the time-varying phase difference from the combined signals include determining an arctan of the combined signals.

[0045] In some embodiments, the method further comprises the steps of anti-alias filtering and / or decimating the determined time-varying phase difference.

[0046] In some embodiments, the step of determining the two time-varying in-phase components and the two time-varying quadrature component includes: automatically generating one of the two time-varying in-phase components by delaying the other of the two time-varying in-phase components by a selected time delay; and automatically generating one of the two time-varying quadrature components by delaying the other of two time-varying quadrature components by the selected time delay.

[0047] In some embodiments, the step of determining the time-varying phase difference from the combined signals includes: determining an arctan of the combined signals; or when the selected time delay is below a predetermined threshold, determining that the time- varying phase difference is linearly related to the combined signals.

[0048] In some embodiments, the step of determining the time-varying phase includes integrating the time-varying phase difference with respect to time.

[0049] In some embodiments, the method further comprises the step of performing the delaying and / or the integrating in one or more DSP hardware components, for example in FPGAs.

[0050] In some embodiments, the method further comprises the steps of anti-alias filtering and / or decimating the determined time-varying phase.

[0051] In some embodiments, the step of determining the arctan of the combined signals comprises the step of using a coordinate rotation method or component, optionally on a coordinate rotation digital computer (CORDIC).

[0052] In some embodiments, the step of combining the four determined signals intothe combined signals comprises: determining products of the [I1(t), I2(t)] and the [Q1(t),Q2(t)], including according to the relationships: IA.IB, QA.QB, QA.IB, and IA.QB.; and determining a sum and a difference of the products, including according to the relationships: IA.IB + QA.QB, and QA.IB − IA.QB.

[0053] In some embodiments, the step of determining the time-varying phase from the combined signals comprises: determining a ratio of the difference and the sumof theproducts, including according to the relationship: (QA.IB− IA.QB) / (IA.IB+ QA.QB).

[0054] In some embodiments, the method further comprises the step of determining the products, the sum, the difference and / or the ratio in one or more DSP hardware components, for example in one or more FPGAs.

[0055] In some embodiments, the method further comprises the step of low-pass filtering the four determined signals and prior to determining the time-varying phase difference, optionally using a code filter.

[0056] In some embodiments, the time-varying phase difference or the time-varying phase may include radio frequencies (RF).

[0057] In another aspect, there is provided a system configured / built to perform the method according to the previous aspect, for example in an FPGA.

[0058] Those skilled in the art will appreciate that the invention described herein is susceptible to variations and modifications other than those specifically described. The invention includes all such variation and modifications. The invention also includes all of the steps, features, formulations, and compounds referred to or indicated in the specification, individually or collectively and any and all combinations of any two or more of the steps or features. Brief Description of the Drawings

[0059] Notwithstanding any other forms which may fall within the scope of the present invention, a preferred embodiment / preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

[0060] Figures 1A and 1B are flow diagrams of an exemplary method embodiment. Figure 2A is a schematic diagram of an exemplary direct differential phase recovery system embodiment.

[0061] Figures 2B to 2C are flow diagrams of exemplary embodiments of a direct differential phase recovery method.

[0062] Figure 3A is a schematic diagram of an exemplary time differential phase recovery system embodiment.

[0063] Figure 3B to 3D are flow diagrams of exemplary embodiments of a time differential phase recovery method.

[0064] Figure 4 is a graph of a transfer function according to an exemplary embodiment of a time differential phase recovery system.

[0065] Figure 5 is a block diagram of an exemplary embodiment of a time differential phase recovery system implemented on an FPGA.

[0066] Figure 6 shows a flow diagram demonstrating the signal processing to extract regular post phase tracking subtraction differential phase.

[0067] Figure 7 shows digital signal processing to extract DDPR phase.

[0068] Figure 8 shows a schematic diagram showing the bidirectional Mach-Zehnder interferometer optical configuration used for the example DDPR implementation.

[0069] Figures 9A and 9B show the bit growth to extract the ^^diff, reg(Figure 9A) and ^^diff, ddpr (Figure 9B).

[0070] Figures 10A to 10D show the time domain phase recovery of 2 ^^ phase ramp at a frequency of 2 Hz.

[0071] Figures 11A and 11B show time domain phase recovery of 2 ^^ phase ramp at a frequency of 656 Hz

[0072] Figure 12 shows the phase spectral density plot of time domain plot shown in Figure 11B

[0073] Figure 13 shows the time domain phase recovery of a 2 ^^ phase ramp at a frequency of 1.3 KHz.

[0074] Figures 14A and 14B show a detail version of the time domain phase recovery of 2 ^^ phase ramp at a frequency of 1.3 kHz of Figure 13.

[0075] Figure 14B shows a plot demonstrating the CW and CCW signals contributing to the DDPR and regular differential phase signals of Figure 14A.

[0076] Figure 15 shows the time domain DDPR phase recovery of a 400 kHz linear frequency tuning ramp at 1.3 kHz into the AOM and thermal tuning of laser over a frequency of 20 GHz over 80 seconds. The insert shows the start of the thermal turning.

[0077] Figure 16 shows a plot of the same DDPR trace as shown in Figure 15 with the post processed subtraction phase.

[0078] Figure 17 shows a time domain DDPR and post-processed subtraction phase recovery with a CORDIC phase recovery and diode laser tracking.

[0079] Figure 18 shows a time domain recovery of 2π phase ramp at 2.6kHz and 17 Hz sinusoidal signal using IQ demodulation and TDPR.

[0080] Figure 19 shows a plot of the RMS phase error in TDPR subtraction with respect to DDPR phase as a function of^.

[0081] Figures 20A and 20B show plots of diode laser tracking with DDPR and regular subtraction in both time and frequency domain with a differential 2π phase ramp at 5 Hz and differential sinusoidal signal at 217 Hz. Definitions

[0082] The following definitions are provided as general definitions and should in no way limit the scope of the present invention to those terms alone, but are put forth for a better understanding of the following description.

[0083] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For the purposes of the present invention, additional terms are defined below. Furthermore, all definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms unless there is doubt as to the meaning of a particular term, in which case the common dictionary definition and / or common usage of the term will prevail.

[0084] For the purposes of the present invention, the following terms are defined below.

[0085] The articles “a” and “an” are used herein to refer to one or to more than one (i.e. to at least one) of the grammatical object of the article. By way of example, “an element” refers to one element or more than one element.

[0086] The term “about” is used herein to refer to quantities that vary by as much as 30%, preferably by as much as 20%, and more preferably by as much as 10% to a reference quantity. The use of the word 'about' to qualify a number is merely an express indication that the number is not to be construed as a precise value.

[0087] The term, “real time”, for example “displaying real time data”, refers to the display of the data without intentional delay, given the processing limitations of the system and the time required to accurately measure the data. Similarly, a process occurring “in real time” refers to operation of the process without intentional delay or in which some kind of operation occurs simultaneously (or nearly simultaneously) with when it is happening.

[0088] Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, preferred methods and materials are described. It will be appreciated that the methods, apparatus and systems described herein may be implemented in a variety of ways and for a variety of purposes. The description here is by way of example only.

[0089] As used herein, the term “exemplary” is used in the sense of providing examples, as opposed to indicating quality. That is, an “exemplary embodiment” is an embodiment provided as an example, as opposed to necessarily being an embodiment of exceptional quality for example serving as a desirable model or representing the best of its kind.

[0090] The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and / or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.

[0091] In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other non-transitory medium or tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the invention discussed above. The computer readable medium or media can be transportable, such that the program or programs stored thereon can beloaded onto one or more different computers or other processors to implement various aspects of the present invention as discussed above.

[0092] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of” or “exactly one of”, or, when used in the claims, “consisting of” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either”, “one of”, “only one of”, or “exactly one of”. “Consisting essentially of”, when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0093] As used herein in the specification and in the claims, the phrase “at least one”, in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B”, or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0094] For the purpose of this specification, where method steps are described in sequence, the sequence does not necessarily mean that the steps are to be carried outin chronological order in that sequence, unless there is no other logical manner of interpreting the sequence. Detailed Description

[0095] Modifications and variations such as would be apparent to the skilled addressee are considered to fall within the scope of the present invention. The present invention is not to be limited in scope by any of the specific embodiments described herein. These embodiments are intended for the purpose of exemplification only. Functionally equivalent products, formulations and methods are clearly within the scope of the invention as described herein. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

[0096] Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those who are skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.

[0097] Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

[0098] The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed.

[0099] Reference to positional descriptions and spatially relative terms), such as “inner”, “outer”, “beneath”, “below”, “lower”, “above”, “upper” and the like, are to be taken in context of the embodiments depicted in the figures, and are not to be taken as limiting the invention to the literal interpretation of the term but rather as would be understood by the skilled addressee.

[0100] Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as “first”, “second”, and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

[0101] It will be understood that when an element is referred to as being “on”, “engaged”, “connected” or “coupled” to another element / layer, it may be directly on, engaged, connected or coupled to the other element / layer or intervening elements / layers may be present. Other words used to describe the relationship between elements / layers should be interpreted in a like fashion (e.g., “between”, “adjacent”). As used herein the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0102] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. The use of the singular includes the plural unless specifically stated otherwise. As used herein, the singular forms “a”, “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprise”, “comprises”, “comprising”, “including”, and “having”, or variations thereof are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0103] The following modes, features or aspects, given by way of example only, are described in order to provide a more precise understanding of the subject matter of a preferred embodiment or embodiments.

[0104] Disclosed herein is an improved phase detection method, Direct Differential Phase Recovery (DDPR) - an open-loop phasemeter topology for differential optical interferometric measurements. Embodiments of the methods described remove common mode signal dynamics prior to phase tracking, which reduces the dynamicrange requirements of the phasemeter tracking optical phase difference. A phase difference measurement is experimentally demonstrated with this technique, achieving a phase sensitivity of 1×10−6rad / √Hz with a common-mode noise rejection of 141 dB. The technique is also demonstrated where individual channels are subject to numerous cycle-slips and unable to track phase. 1. Overview

[0105] An overview will be provided with reference to Figures 1A and 1B.

[0106] Figures 1A and 1B show an exemplary method 1 for determining a time-varying phase difference [ΔΦ(t)] between two time-varying signals or a time-varying phase [Φ(t)] of one time-varying signal.

[0107] The method includes at step 10, receiving or generating two time-varying in-phasecomponents [I1(t), I2(t)] and two time-varying quadrature components [Q1(t),Q2(t)] fromone or more demodulated time-varying signals. This may be done by demodulation using a local oscillator, for example. The method includes at step 20 determining the time- varying phase difference [ΔΦ(t)] from the determined twotime-varying in-phasecomponents [I1(t), I2(t)] and two time-varying quadrature components [Q1(t), Q2(t)]. Step 20 includes the step of combining the four signals [I1(t),I2(t)] and [Q1(t), Q2(t)] at eachtime point, at step 22. Step 20 also includes the step of determining a time-varying phase difference [ΔΦ(t)] from the combined signals, at step 24. Optionally, step 20 also includes the step of determining a time-varying phase [Φ(t)] from the time-varying phase difference [ΔΦ(t)] at step 26.

[0108] As will be apparent from the remainder of the description, embodiments depicted in Figures 1A and 1B, as well as embodiments that fall within the scope of the exemplary method of Figures 1A and 1B provide a method or system of efficiently determining a time-varying phase difference [ΔΦ(t)] between two time-varying signals or a time-varying phase [Φ(t)] of one time-varying signal. 2. General Embodiments

[0109] Two general embodiments that fall within the scope of the method of Figures 1A and 1B will now be described with reference to Figures 2A-2C and Figures 3A-3D:• Figures 2A-2C refer to a direct differential phase recovery system 100 / method 101 that can be used to implement the method according to Figures 1A to 1B. As will be discussed further, system 100 / method 101 can be used to determine a time-varying phase difference [ΔΦ(t)] between two time-varying signals. • Figure 3A-3D refer to a time differential phase recovery system 200 / method 201 that can be used to implement the method according to Figures 1A to 1B. As will be discussed further, system 200 / method 201 can be used to determine a time-varying phase [Φ(t)] of one time-varying signal (based on a determined time-varying phase difference [ΔΦ(t)]).

[0110] Disclosed herein is described in detail the general direct differential phase recovery system 100 / method 101 embodiment. Following this is described in detail the general time differential phase recovery system 200 / method 201 embodiment.

[0111] The general embodiment of the direct differential phase recovery system 100 / method 101 is described with respect to Figures 2A-2C.

[0112] Figure 2A shows a direct differential phase recovery system 100, which may be wholly or partly implemented on one or more hardware controllers 150, the hardware controller preferably being a DSP controller such as an FPGA, for example. Figures 2B-2C show possible method steps of a method 101 that the system 100 may be configured to perform. Unless context dictates otherwise, one or more of the method steps as described with respect to Figures 2B to 2C may be optional.

[0113] For the avoidance of doubt, the following mathematical relationships apply with respect to embodiments of system100and method101: I1(t)=I1=IA, I2(t)=I2=IB, Q1(t)=Q1=QA, Q2(t)=Q2=QB.

[0114] At step 110, the system 100 is configured to receive or generate two time-varying in-phase components [IA, IB] and receive or generate two time-varying quadrature components [QA, QB] from two demodulated time-varying signals [A(t), B(t)] that are independent of each other. In some embodiments, the four signals are decoded outputs 152. In some embodiments, the system 100 is configured to low pass filter the received or generated two time-varying in-phase components [IA, IB] and twotime-varying quadrature components [QA, QB], at step 112, using a low pass filter 154 for example.

[0115] The system 100 is configured to determine the time-varying phase difference [ΔΦ(t)] from the two time-varying in phase components [IA, IB] and two time-varying quadrature components [QA, QB] as follows.

[0116] At step 122, the system 100 is configured to combine the four signals [IA, IB, QA,QB] at each time point into two combined signals [IΔ, QΔ] 156 as shown in Figure 2A. In some embodiments, the step of combining the four determined signals [IA, IB, QA, QB] into the combined signals [IΔ, QΔ] 156 includes: • determining products of the [IA, IB] and the [QA, QB], including according to the relationships: IA.IB, QA.QB, QA.IB, and IA.QB., at step 122a; and •determininga sum and a difference of the products, including according to therelationships: IA.IB+ QA.QB, and QA.IB− IA.QB, at step 122b.

[0117] At step 124, the system 100 is configured to determine the time-varying phase difference [ΔΦ(t)] from the two combined signals [IΔ, QΔ]156. The determination of the time-varying phase difference [ΔΦ(t)] may be done by determining an arctan of the ratio of two combined signals [IΔ, QΔ]156. The ratio may be determined according to a ratio of the difference and the sum of the products, including according to the relationship: (QA.IB− IA.QB) / (IA.IB+ QA.QB), at step224a. The arctan of the ratio of the twocombinedsignals may be computed for example by using a coordinate rotation method or component, such as a CORDIC rectangular polar operation 158 for example. The “determining” of the time-varying phase difference [ΔΦ(t)] from the two combined signals [IΔ, QΔ]156can beconsideredto include “generating” the time-varying phase difference [ΔΦ(t)] from the two combined signals [IΔ, QΔ]156. The “determining” of an arctan of the two combined signals [IΔ, QΔ]156can be considered to include “generating” an arctan of the two combined signals [IΔ, QΔ]156.

[0118] In some embodiments, the system 100 is configured to anti-alias the determined time-varying phase difference [ΔΦ(t)], at step 128, using an anti-aliasing filter 160. In some embodiments, the system 100 is configured to decimate the determined time-varying phase difference [ΔΦ(t)], at step 129, for example using adown sampler 162. In some embodiments, the system 100 is configured to read out the time-varying phase difference [ΔΦ(t)], at step 130, for example using a phase readout display 164.

[0119] In some embodiments, the time-varying phase difference [ΔΦ(t)] determined by the system 100 / method 101 can include radio frequencies (RF), e.g., from electrical and / or optical signals. The RF frequencies include one or more frequencies between 3 Hz and 300 GHz. In some embodiments, the included RF frequencies may include frequencies up to: 30 MHz, 200 MHz, or 600 MHz.

[0120] The general embodiment of the time differential phase recovery system 200 / method 201 will now be described with respect to Figures 3A-3C.

[0121] Figure 3A shows a time differential phase recovery system 200, which may be wholly or partly implemented on one or more hardware controllers 250, the hardware controller preferably being a DSP controller such as an FPGA for example. Figures 3B-3D show possible method steps of a method 201 that the system 200 may be configured to perform. Unless context dictates otherwise, one or more of the method steps as described with respect to Figures 3B-3D may be optional.

[0122] For the avoidance of doubt, the following mathematical relationships apply with respect to embodiments of system200and method 201: I1(t)=I1=IP I2(t)=I2=IDQ1(t)=Q1=QPQ2(t)=Q2=QD

[0123] At step 210, the system 200 is configured to receive or generate two time-varying in-phase components [IP, ID] and receive or generate two time-varying quadrature components [QP, QD] from one demodulated time-varying signal. In some embodiments, the step of generating / receiving two time-varying in-phase components [IP, ID] and generating / receiving two time-varying quadrature components [QP, QD] includes one or more steps of: • receiving or generating the time-varying in-phase component [IP] and time-varying quadrature component [QP] from one demodulated time-varying signal, at step210a, as decoded outputs 252, for example;• low pass filtering the received or generated time-varying in-phase component [IP] and time-varying quadrature component [QP], at step 210b,for exampleusing a low pass filter254;• automatically generating one of the two time-varying in-phase components [ID],for exampleby delaying the other of the two time-varying in-phase components [IP] by a selectedtime delay [ ^], atstep 210c, using a Z-ktime delay shift 255 where k is an integer; or • automatically generating one of the two time-varying quadrature components [QD], for exampleby delaying the other of two time-varying quadrature components [QP] by theselected time delay [ ^], at step210d, using a Z-ktime delay shift 255 where k is an integer, for example.

[0124] In some embodiments, the system 200 is configured to low pass filter the received two time-varying in-phase components [IP, ID] and two time-varying quadrature components [QP, QD], at step 212, using a low pass filter for example (not shown). Such low pass filtering may be carried out after receiving / generating the two time-varying in- phase components [IP, ID] and two time-varying quadrature components [QP, QD], for example if the step at 210b is omitted (in which there is low pass filtering of IPand QPprior to generation of IDand QD).

[0125] The system 200 is configured to determine the time-varying phase difference [ΔΦ(t)] from the two time-varying in phase components [IP, ID] and two time-varying quadrature components [QP, QD] as follows.

[0126] At step 222, the system 200 is configured to combine the four signals [IP, ID, QP, QD] into two combined signals [IΔ, QΔ] 256. In some embodiments, the step of combining the four determined signals [IP, ID, QP, QD] into the combined signals [IΔ, QΔ] 256 includes: • determining products of the [IP, ID] and the [QP, QD], including according to the relationships: IP.ID, QP.QD, QP.ID, and IP.QD., at step222a; and • determining a sum and a difference of the products, including according to therelationships: IP.ID+ QP.QD, and QP.ID– IP.QD, at step222b.

[0127] At step 224, the system 200 is configured to determine the time-varying phase difference [ΔΦ(t)] from the two combined signals [IΔ, QΔ]256. In some embodiments,thedetermination of the time-varying phase difference [ΔΦ(t)] is done by determining an arctan of the ratio of two combined signals [IΔ, QΔ]256. The ratio may be determined according to a ratio of the difference and the sum of the products, including according to the relationship: (QP.ID– IP.QD) / (IP.ID+ QP.QD), at step222c. The arctan of the ratio of the two combined signals may be computed for example by using a coordinate rotation method or component, such as a CORDIC rectangular polar operation 258, for example. In some embodiments, the determination of the time-varying phase difference [ΔΦ(t)], when the selected time delay [ ^] is below a predetermined threshold, is done by determining that the time-varying phase difference [ΔΦ(t)] is linearly related to the twocombined signals[IΔ, QΔ]256, for example through a ratio of QΔ / IΔ. The ratio of QΔ / IΔmay be determinedby using a coordinate rotation method or component, such as a CORDIC rectangular polar operation 258 for example. The predetermined threshold is set by a desire that the phase difference be within the linear range of arctan. So, the value of ^ that this corresponds to depends on the signal phase dynamics as well as the actual selected value of ^. This will be discussed in more detail later with respect to the transfer function of Figure 4. The “determining” of the time-varying phase difference[ΔΦ(t)] from the two combined signals[IΔ, QΔ]256can be considered to include“generating” the time time-varying phase difference [ΔΦ(t)] from the two combined signals [IΔ, QΔ]256. The “determining” of an arctan of the two combined signals [IΔ, QΔ]256can be considered to include “generating” an arctan of the two combined signals [IΔ, QΔ]256.

[0128] At step 226, the system 200 is configured to determine the time-varying phase [Φ(t)] from the time-varying phase difference [ΔΦ(t)]. In some embodiments, the determination of the time-varying phase [Φ(t)] is done through integration 259 of the time- varying phase difference [ΔΦ(t)] with respect to time [t]. The “determining” of the time- varying phase [Φ(t)] from the time-varying phase difference [ΔΦ(t)] can be considered to include “generating” the time-varying phase [Φ(t)] from the time-varying phase difference [ΔΦ(t)], for example by integration 259 of the time-varying phase difference [ΔΦ(t)] with respect to time [t].

[0129] In some embodiments, the system 200 is configured to anti-alias the determined time-varying phase [Φ(t)], at step 228, using an anti-aliasing filter 260. In some embodiments, the system 200 is configured to decimate the determined time-varying phase [Φ(t)], at step 229, for example using a down sampler 262. In some embodiments, the system 200 is configured to read out the time-varying phase [ΔΦ(t)], at step 230, for example using a phase readout display 264.

[0130] In some embodiments, the time-varying phase difference [ΔΦ(t)] determined by the system 200 / method 201 and / or the time-varying phase [Φ(t)] determined by the system 200 / method 201 can include radio frequencies (RF), e.g., the RF frequencies mentioned hereinbefore.

[0131] The method and system embodiments of Figures 1A-3D are advantageous because they are computationally efficient. In particular, mathematical operations involved in combining the four signals at each time point (step 22, 122, 122a-c, 222, 222a-c) use only simple multiplications, additions, subtractions and delays which allows for easy and efficient implementation on a hardware controller(s), particularly DSP hardware such as FPGAs.

[0132] Thus, there is provided a method 1, 101, 201 for determining a time-varying phase difference [ΔΦ(t)] between two time-varying signals or a time-varying phase [Φ(t)] of one time-varying signal. The method comprises receiving or generating twotime-varying in-phase components [I1(t), I2(t), IA, IB, IP, ID] and two time-varying quadrature components [Q1(t), Q2(t), QA, QB, QP, QD] from one or moredemodulatedtime-varying signals (steps10, 110, 210). The method comprises determining thetime-varying phase difference[ΔΦ(t)] from the two time-varying in-phase components [I1(t), I2(t), IA,IB, IP, ID] and two time-varying quadrature components [Q1(t), Q2(t), QA,QB, QP, QD] (step 20). Determining the time-varying phase difference [ΔΦ(t)] comprises combining the four signals [I1(t), I2(t), IA,IB, IP, ID] and [Q1(t), Q2(t), QA, QB, QP,QD] at each time point (steps22,122,222).Determining the time-varying phasedifference [ΔΦ(t)] also comprises determining a time-varying phase difference [ΔΦ(t)]from the combined signals [IΔ, QΔ] 156, 256 (steps24,124, 224). Optionally, themethod comprises determining a time-varying phase [Φ(t)] from the time-varying phase difference [ΔΦ(t)] (steps 26, 226). In embodiments of method101, I1(t)= IA, I2(t)=IB,Q1(t)=QA(t), Q2(t)=QB. In embodiments of method 201, I1(t)= IP, I2(t)=ID, Q1(t)=QP, Q2(t)=QD.

[0133] In some embodiments, the two time-varying signals are independent signals [A(t), B(t)] (step 110). In some embodiments, the step of determining the time-varyingphasedifference [ΔΦ(t)] from the combined signals [IΔ, QΔ] 156 (step 124) includes determining an arctan of the combined signals [IΔ, QΔ]156. In some embodiments,method 101 furthercomprises the steps of anti-alias filtering (step 128) and / or decimating the determined time-varying phase difference [ΔΦ(t)] (step 129).

[0134] In some embodiments, the step of determining the two time-varying in-phase components [IP, ID] and the two time-varying quadrature component [QP, QD] (step 210) includes: automatically generating one of the two time-varying in-phase components [ID] by delaying the other of the two time-varying in-phase components [IP] by a selected time delay [ ^] 255 (step 210c); and automatically generating one of the two time-varying quadrature components [QD] by delaying the other of two time-varying quadrature components [QP] by the selected time delay [ ^] 255 (step 210d).

[0135] In some embodiments, the step of determining the time-varying phase difference [ΔΦ(t)] from the combined signals [IΔ, QΔ] 256 (step 224) includes: determining an arctan of the combined signals [IΔ, QΔ] 256; or when the selected time delay [ ^] is below a predetermined threshold, determining that the time-varying phase difference [ΔΦ(t)] is linearly related to the combined signals [IΔ, QΔ] 256.

[0136] In some embodiments, the step of determining the time-varying phase [Φ(t)] (step 226) includes integrating 259 the time- varying phase difference [ΔΦ(t)] with respect to time [t]. In some embodiments, the method 201 further comprises the step of performing the delaying and / or the integrating in one or more DSP hardware components, for example in FPGAs 250. In some embodiments, the method 201 further comprises the steps of anti-alias filtering 260 (step 228) and / or decimating the determined time-varying phase [Φ(t)] 262 (step 229).

[0137] In some embodiments, the step of determining the arctan of the combinedsignals[IΔ, QΔ]156,256 comprisesthe step of using a coordinate rotation method orcomponent,e.g., a coordinate rotation digital computer (CORDIC) 158, 258.

[0138] In some embodiments, the step of combining the four determined signals [I1(t), I2(t), IA, IB, IP, ID, Q1(t), Q2(t), QA,QB, QP, QD] into the combined signals [IΔ, QΔ] 156, 256 (steps 22, 122, 222) comprises determining products of [I1(t), I2(t), IA, IB, IP, ID] and [Q1(t), Q2(t), QA,QB, QP, QD] according to the relationships: I1.I2, Q1.Q2, Q1.I2, and I1.Q2(steps 122a, 222a). In some embodiments, the step of combining the four determined signals [I1(t), I2(t), IA, IB, IP, ID, Q1(t), Q2(t), QA,QB, QP, QD] into the combined signals [IΔ, QΔ]156, 256 (steps 22, 122, 222) comprises determining a sum and a difference of the products according to the relationships: ( I1.I2 + Q1.Q2), and ( Q1.I2 − 1A.Q2) (steps 122b, 222b). In some embodiments, the step of determining the time-varying phase [ΔΦ(t)] from the combined signals [IΔ, QΔ] 156, 256 (steps 24, 124, 124a, 224, 224a) comprises determining a ratio of the difference and the sum of the products according to the relationship: Q1.I2 – I1.Q2) / (I1.I2 + Q1.Q2) (steps 124a, 224a). For the avoidance of doubt, the following mathematical relationships apply with respect to steps 122, 122a, 122b, 124, and 124a: I1(t)=I1=IA, I2(t)=I2=IB, Q1(t)=Q1=QA, Q2(t)=Q2=QB. For the avoidance of doubt, the following mathematical relationships apply with respect to steps 222, 222a, 222b, 224, and 224a, the following mathematical relationships apply: I1(t)=I1=IP, I2(t)=I2=ID, Q1(t)=Q1=QP, Q2(t)=Q2=QD.

[0139] In some embodiments, the method 1, 101, 201 further comprises the step of determining the products, the sum, the difference and / or the ratio in one or more DSP hardware components, e.g., FPGAs 150,250. In some embodiments, the methods 1, 101, 201 further comprise the step of low-pass filtering 154, 254 the four determinedsignals[I1(t), I2(t), IA, IB, IP, ID] and [Q1(t), Q2(t), QA,QB, QP, QD] prior to determining thetime-varying phase difference [ΔΦ(t)] (steps 112, 210b, 212). In some embodiments, the time- varying phase difference [ΔΦ(t)] or the time-varying phase [ΔΦ(t)] may include radio frequencies.

[0140] In addition, there is also provided a system 100, 200 configured / built to perform any described embodiment or aspect of methods 1, 101, 201, for example in an FPGA150, 250. In embodiments of system100, I1(t)= IA, I2(t)=IB, Q1(t)=QA(t), Q2(t)=QB. In embodiments of system200, I1(t)= IP, I2(t)=ID, Q1(t)=QP, Q2(t)=QD.3. Explanations

[0141] Detailed explanations will now be provided in relation to the mathematical representations of direct differential phase recovery (referred to as “DDPR” herein). 3.1. IQ Demodulation

[0142] IQ demodulation is a simple and robust method for continuous, sub-wavelength phase tracking. IQ demodulation uses phase locked sine and cosine radio frequency local oscillators to mix down an input signal (step 10, 110). For simplicity of notation we start with a signal described by Equation (1), which consists of a DC component and a signal ϕ(t) at frequency ω: (1)

[0143] The first stage of IQ demodulation is the mixing of the signal s(t) with the RF local oscillators. We can use Equation (1) to write down this process as follows:

[0144] Where s(t) is defined in Equation (1) and ωmis the (mixing) RF local oscillator frequency. The process of mixing with the RF local oscillators upshifts the DC component and downshifts the RF component at the mixing frequency. When the mixing frequency is matched to the IF frequency, in this case ω, the signal frequency is then shifted to DC. By normalising to the input signal power, the mixing terms can be expanded out as follows:

[0145] This is followed by a low pass filter (LPF) to remove high frequency upshifted components (step 112). Disregarding the factor of 1 / 2 and sign of the demodulation phase, the resultant outputs from the LPFs are the in-phase (I) and quadrature (Q) components of the signal relative to the demodulation frequency:3.2. Direct Differential Phase Recovery

[0146] Using standard IQ demodulation, we extract the in-phase (I) and quadrature (Q) components of a phase signal. Let A = IA + iQA and B = IB + iQB be two complex numbers composed of I and Q components of the two signals A and B. The phase difference of signals ^^ and ^^ is given by Equation (2). ^^diff = ∠ ^^ − ∠ ^^ (2)

[0147] Standard signal processing then uses: ∠ ^^ = ^^^^, reg= unwrap{arctan( ^^ ^^ / ^^ ^^)}, ∠ ^^ = ^^^^, reg= unwrap{arctan( ^^ ^^ / ^^ ^^)}, (3) to independently give the phases of signals A and B respectively. In Equation (3), the ‘reg’ subscript refers to regular, arctangent-unwrap phase determination. Subtracting these two phases then gives:which can also be represented as the difference in angle of the two complex numbers A and B. Implementing Equations (3) and (4) means that both the A and B signal phases are tacked independently in order to measure the phase difference ^^diff, reg = ^^ ^^ , reg – ^^ ^^ , reg.

[0148] For large scale phase dynamics, both the I and Q components of each signal contribute significantly to the recovered phase information and thereby the need to track all the significant phase dynamics. Also, given these phase dynamics, it is necessary to unwrap each of these phase signals independently to attribute the arctangent discontinuities. This makes the post-phase-tracking subtraction implementation a problematic task and highly susceptible to cycle slips.

[0149] To perform the subtraction with the desired accuracy whilst avoiding cycle slips, each signal tracks all significant dynamics with the desired precision of the desired phase difference measurement. In addition, each phase measurement is independentlyphase unwrapped without error. In the presence of large common noise, this is an onerous requirement that can be avoided.

[0150] Alternatively, two combined signals IΔand QΔcan be produced as follows (step 22, 122). The phase difference of signals A and B can be represented as:

[0151] We then expand A.B∗and collect real and imaginary terms to give:

[0152] The angle of A.B∗is determined using:(7)

[0153] In situations where there are significant common-mode signal dynamics the difference than be computed directly in IQ space as per Equation (7). This consists offormingthe four products IA.IB,QA.QB,QA.IB, and IA.QB(step 122a) immediately afterformation ofIQ components for both signals. The addition and subtraction operations are then performed on these four products (step 122b) to create the real and imaginary components of Equation (6) to give: (8)

[0154] This DDPR signal processing operates on signals in the IQ stage, generating IΔ and QΔ. From the output of the DDPR stage, the IQ components that correspond to phase subtraction of signals A and B can then be used directly to compute Δϕ without the presence of any large common-mode signal dynamics (step 24, 124, 124a). (9)

[0155] This method allows common-mode dynamics to be removed prior to phase tracking of Δϕ without loss of accuracy in the final measurement.4. Time Differential Phase Recovery

[0156] The purpose of TDPR is to linearise the phase measurement of a signal by measuring the phase derivative over a fixed, short, time duration, given by a delay time ^ . To start the analysis, standard IQ demodulation is described below.

[0157] The DDPR signal processing system outlined above, can be modified to operate on a single IQ signal pair that is low-pass filtered (step 210, 210a-c). Initially, both I and Q are delayed by a fixed time delay ^ . The following assignments can then be made:where subscripts P and D designate Prompt and Delayed respectively. IΔand QΔare then formed (step 22, 222, 222a-b) as:

[0158] As these expressions use only simple multiplications, additions, subtractions and delays, the nature of this algorithm allows for easy and efficient implementation on DSP hardware such as FPGAs.

[0159] The phase difference (step 24, 224, 224a) between the prompt and delayed signals is given by:

[0160] As ^ is reduced, IΔ approaches IP2+ QP2while QΔ becomes progressively smaller. For sufficiently small ^ ,the approximation Δϕ = arctan (QΔ / IΔ) ≈ (QΔ / IΔ) applies which eliminates the need for both arctan and phase unwrapping operations. It is desirable to use Δϕ to recover ϕ (step 26, 226). To do this, a time domain integration of Δϕ is performed to give:(13)

[0161] Time Differential Phase Recovery may therefore circumvent the need for arctan and phase unwrapping operations, whilst providing an open loop, unconditionally stable phase readout technique. In addition, both Δϕ and ϕ are linear variables in which each frequency component is independent of all others. It is thus possible to filter these variables as desired at liberty, without damage.

[0162] Figure 3A presents a simplified signal processing flow diagram of an implementation of TDPR.

[0163] A possible implementation may include: • Filter: 84 kHz low pass filter; • Time delay of ^: for example, this could be a delay Z-k, where k is an integer; • CORDIC: co-ordinate rotation algorithm used to divide QΔby IΔ; • Anti-Aliasing Filter: 2nd order CIC LPF with 2.6 kHz bandwidth; • Down sampling: down sample to 5.2 kHz sample rate for uploading to host computer; and • Σ: phase integrator in host to form ϕ.

[0164] Starting with digitised IQ components (step 210a), the I and Q components are initially filtered in the Filter stage (step 210b), implemented with independent, first order, cascaded integrator-comb (CIC) filters. Variable delays of^are implemented for both I and Q using FPGA memory-based delay lines (steps210c-d). DDPR processing of IP, QPand ID, QDare then realised using four multipliers and sum and difference operations (steps222a-c) before a co-ordinate rotation transformation (CORDIC) usesQΔand IΔtogenerate Δϕ (step 224). ϕ is recovered by integrating Δϕ (step 226). After an anti-aliasing filter stage (step 228) consisting of a second order CIC low pass filter, ϕ is then down sampled (step 229) before streaming to the host computer (step 230).

[0165] The transfer function of the input phase ϕ(t) to Δϕ(t) can be determined by taking the Laplace Transform of Equation (12) to give:(14)

[0166] Dividing through by Φ(s) then yields:with the frequency response obtained by substituting s = i2πf:

[0167] Figure 4 plots the absolute amplitude of Equation (16) for ^ = 12 μsec. As can be seen, the Δϕ transfer function exhibits low frequency signal suppression that approximates an f+1differentiator response at frequencies below ≈ 40 kHz. In addition, this transfer function reaches a maximum value of 2 at 42 kHz.

[0168] Whilst the TDPR processing to create Δϕ is seen in Figure 4 to suppress low frequency components of the signal spectrum, it also suppresses all input noise sources such as shot noise and photo-detector dark noise by exactly the same ratio. With careful DSP implementation (lossless), the initial signal-to-noise ratio (SNR) can be preserved when recovering ϕ.

[0169] In order to recover ϕ, Δϕ is integrated on the FPGA prior to low pass filtering and decimation before transferring to the host. 4.1. Optimum Value of ^

[0170] The optimum selection of ^ requires the selection of the largest value of ^ that ensures Δϕ phase dynamics are suppressed into the linear range of arctan. It is noted that increasing the value of^results in improved DC accuracy, whereas decreasing the length of ^ results in improved high-frequency noise tracking. Thus, the optimal value of ^ can be found to minimally track high-frequency noise ensuring the maximum possible DC accuracy for given system dynamics. 5. TDPR Implementation

[0171] In this section, we discuss in detail the digital signal processing implementation of time differential phase recovery (referred to as “TDPR” herein). This discussion isprovided with respect to Figure 5, which outlines some DSP steps of a method 271 a TDPR system 200 implemented on an FPGA 270 can be configured to perform. 5.1. Demodulated IQ Components¾Step 272

[0172] Precision optical interferometer metrology employs a range of techniques to measure the optical phase at the interferometer output and thereby infer the measurand.

[0173] The most transparent technique is perhaps, heterodyne interferometry where two optical fields, radio frequency (RF) offset from each other, beat together before photo-detection. The photo-detector output then includes an RF interference term with the phase carried over from the interferometer optical field. Demodulation at the chosen RF frequency with both cosine and sine signals then yields the in-phase (I) and quadrature (Q) components of the interferometer optical field. Here, we assume that IQ components are available by any means and focus on how TDPR operates on these IQ variables. 5.2. RT Filter¾Step 274

[0174] Low pass filtering operations, possibly with decimation, operate in parallel on both I and Q variables in order to remove non-baseband spectral components that may arise from IQ variable generation. The RT low pass filter may be a code filter in systems utilising pseudo-random modulation, such as in digital interferometry (DI) systems for example. As an example, in heterodyne systems, this filter removes both the fundamental and second harmonic of the heterodyne frequency and other inter-modulation products. 5.3. Combining IQ Components¾Step 276

[0175] TDPR processing involves firstly delaying both IPand QPby a time delay^to form IDand QD. We then implement:5.4. Phase (CORDIC)¾Step 278

[0176] For sufficiently small ^ we can approximate Δϕ = arctan (QΔ / IΔ) ≈ (QΔ / IΔ) and eliminate the need for both arctan and phase unwrapping operations.

[0177] In fact, we implement the (QΔ / IΔ) division using the phase readout of the CORDIC function which implements arctan((QΔ / IΔ)) with no need for the above approximation even though it is well justified. The arctan((QΔ / IΔ)) operation can be performed in this implementation without the difficulties associated with the unwrapping decision that comes with performing an arctan operation over multiple phase cycles. This is because the differential phase Δϕ is small between successive samples of the readout. In this such circumstance, there will be no large dynamics to necessitate an unwrapping decision. The lack of requirement for phase unwrapping, avoids the computational intensity associated with phase unwrapping. 5.5. Integration and Bitshift¾Steps 280, 282

[0178] Integration of Δϕ on the FPGA is performed immediately after the CORDIC (step 280). This integration recovers ϕ prior to data bit depth truncation, reducing the impact ofquantizationnoise within the integration step. A dramatic (-32 bit) bitshift is then able to be implemented after integration without compromising low frequency phase sensitivity (step 282). 5.6. 2nd Order Decimating CIC Filter¾Step 284

[0179] IQ variables are, in general, non-linear and require non-linear processing (arctan and unwrap) to produce a linear output phase variable. However, by selectingthe delay ^to be small compared to all significant signal dynamics, the approximation arctan(QΔ / IΔ) ≈ (QΔ / IΔ) can be made with no need for an arctan operation orsubsequent phase unwrapping. Thisensures that Δϕ is a linear variable. Sinceintegration is a linear operation, ϕ is also a linear variable that can be arbitrarily filtered as required. Hence, a low pass anti-aliasing filter on ϕ can be implemented prior to decimation without damage. Decimated ϕ can then be transferred to a host computer for recording and further processing, if desired.6. Summary of DDPR and TDPR implementation

[0180] The implementation of DDPR and TDPR may be summarised as follows:

[0181] DDPR operates on two IQ pairs (two independent signals), where the real time processing of IQ variables is used to implement the equivalent of phase subtraction between the two signals at the IQ stage by implementing Equation (8) prior to phase tracking (Equation (9)). This enables the removal of common mode phase dynamics before phase tracking. This in turn, dramatically reduces the dynamic range required for many phase tracking applications. The output of the DDPR real time processing is the differential phase between two independent signals, with common-mode noise removed in a robust, and cycle-slip reduced way. TDPR builds on DDPR, using the same IQ algorithm to process IQ pairs and generate the IQ pair corresponding to phase subtraction. Whereas DDPR simply operates on two IQ pairs (two independent signals), TDPR generates two IQ pairs from a single IQ pair by delaying the original IQ pair and then using the prompt and delayed IQ pairs for the DDPR algorithm of Equation (7). TDPR processing thus generates the IQ pair corresponding to the time differential ( ^) of phase of the original signal. 7. DDPR Implementation Example 7.1. Differential Phase Signal Processing 7.1.1. Regular Differential Phase Readout

[0182] Figure 6 shows the digital signal processing involved in the regular phase tracking. Each analog to digital converter (ADC) input 601 is multiplied by the IQ extraction code, generating IQ pairs for diff, DDPR signals A and B respectively. These two IQ pairs are then low pass filtered and decimated using identical second-order cascaded integrator–comb (CIC) filters. All the processing 610, up to this point, is performed on a high-speed field programmable gate array (FPGA). Finally, Equations (2) and (3) are implemented in post processing 620 using the in-built functions “atan2” and “unwrap” in MATLAB, to give ^^diff, reg= ^^^^ , reg– ^^^^ , reg. The ADC inputs of each signal is demodulated to extract the IQ pairs for CW and CCW direction. These IQ pairs then are low pass filtered and decimated in real time FPGA. The final step of computing the ^^ ^^ , reg and ^^ ^^, reg is done in post processing using MATLAB, where subtraction of these two phases yields ^^diff, reg.

[0183] Figure 7 shows digital signal processing to extract DDPR phase. Part of this process is done in real time FPGA. The ADC input for each signal is demodulated to extract the IQ pair, followed by the DDPR operation that yields ^^Δand ^^Δthen is low pass filtered and decimated. Finally, in post-processing, the ^^Δ. The extracted ^^Δ and ^^diff, ddpr is computed using atan2 in MATLAB. 7.1.2. DDPR Phase Readout

[0184] As an alternative change this means of deriving a differential phase signal, the phase difference of signals ^^ and ^^ can be represented as: ^^diff= ∠ ^^ − ∠ ^^ = ∠( ^^ / ^^) = ∠ ^^. ^^*(18)

[0185] Expanding ^^. ^^∗and collecting real and imaginary terms gives:

[0186] By forming the four products ^^ ^^. ^^ ^^, ^^ ^^. ^^ ^^, ^^ ^^. ^^ ^^, and ^^ ^^. ^^ ^^ immediately after extraction of ^^ ^^ components for both signals, the differential phasor of Equation (19) can be defined in terms of its ^^ ^^ projections: ^^Δ = ^^ ^^. ^^ ^^ + ^^ ^^. ^^ ^^ , ^^Δ= ^^^^. ^^^^− ^^^^. ^^^^. (20)

[0187] We the differential ^^ and ^^ components from Equation (20) can be used to directly compute the differential phase. ^^diff, ddpr= ∠ ^^. ^^*unwrap{arctan (QΔ / IΔ)} (21)

[0188] The digital signal processing involved in DDPR is shown in Figure 7. Analogous to the regular phase tracking, the ADC inputs are multiplied by ^^ ^^ extraction codes to give the ^^ ^^ pairs for the two signals. These two ^^ ^^ pairs are then multiplied according to Equation (20) to generate ^^Δand ^^Δ. The last step-in high-speed FPGA is the low pass filtering and decimation of ^^Δand ^^Δ. Finally, Equation (21) is implemented on MATLAB using the same “unwrap” and “atan2” in-built functions used for regular phase tracking.

[0189] As this process operates on signals at the ^^ ^^ stage as per Equation (20) to generate ^^Δand ^^Δ, common mode phase dynamics of signals ^^ and ^^ are removed prior to phase recovery. This removal of common mode noise prior to the phase recovery results in a few significant advantages. Firstly, this ensures that ^^diff, ddpris able to recover only the differential phase without loss of accuracy. Secondly, DDPR makes the need of unwrap necessary only when the difference signal amplitude approaches the arctan discontinuities, irrespective of the common mode dynamic range. 7.2. Experimental Test Bed

[0190] In the present example implementation, the operation and advantages of DDPR on a bidirectional Mach-Zehnder interferometer (BiMZI) 800 are shown in Figure 8. The open arrows 801 and the closed arrows 803 show the clockwise and counterclockwise direction, respectively. Notated features of Figure 8 include AOM: Acousto-Optic Modulator 805, P: Polarization Controller 807, DAC: Digital to Analog Converter 809, ADC: Analog to Digital Converter 811, I: isolator 813, and C: 3dB Coupler 815.

[0191] In this interferometer 800, the reference path is the through-beam of the 3 dB couplers at the input 815a and output 815b of the 500m coil 817, while the signal path travels the same path with the addition of one transit through the 500 m coil. As can be seen from Figure 8, this configuration enables the simultaneous readout of both clockwise (CW) and counter-clockwise (CCW) directions around the fiber loop 817. Digitally enhanced homodyne interferometry (DEHoI) is used to generate orthogonally coded quadrature phase shift key (QPSK) modulation enabling extraction of the ^^ ^^ pairs for each direction [7]. Implicit in this realization of DEHoI is the integration across a full pseudo-random, maximal length, binary code. Here, a code of 12 ^^sec duration is used, implementing an 84 kHz first order low pass filter on all ^^ ^^ components and set a differential signal bandwidth requirement of 1 kHz. It will be readily appreciated by the skilled addressee that alternative modulation techniques may be used, provided they can obtain ^^ ^^ pairs for each of the two signal measurements.

[0192] By using a BiMZI, near identical laser frequency noise is induced in each direction. This provides reliable common-mode phase dynamics proportional to the coil length

[0017] . In addition, both common-mode and differential phase signals can beinjected into the two acousto-optic modulators (AOM), allowing the phase tracking to be tested with a broad range of phase signal dynamics.

[0193] For this experimental demonstration, a Koheras X15 fiber laser operating at 1550 nm is used, whilst the interferometer is composed of SMF-28 optical fiber throughout. The polarization controllers 807 evident in Figure 8 maximize fringe visibility for both clockwise (CW) and counter-clockwise (CCW) interferometers. The entire interferometer 800 sits inside an aluminium box to shield the BiMZI from mechanical noise and reduce temperature variation. The interfered signals from each direction are detected by Insight BPD-1 balanced photo-receivers and digitized on a National Instruments (NI) 5782 transceiver before being processed using an NI 7966R Virtex 5 field programmable gate array (FPGA). This FPGA demodulates the digitized signals to extract ^^ ^^ pairs for both CW and CCW directions and implements Equation (20) to generate the DDPR ^^ ^^ pair in real-time. All three ^^ ^^ pair components are then low pass filtered using identical second order cascaded integrator–comb (CIC) filters, each with a zero at 1.3 kHz. All ^^ ^^ components are then decimated down to a 2.6 kHz sample rate prior to transfer to a host computer. Finally, the host implements Eqn.6to give ^^diff, ddpr = arctan ( ^^Δ / ^^Δ) and, by way of comparison, Equations (2) and (3) to give ^^diff, reg = ^^ ^^, reg – ^^ ^^, reg. This arrangement gives access to all ^^ ^^ pairs as well as the resulting phases and allows a detailed comparison between both techniques throughout their signal processing paths.

[0194] Figure 9A shows the bit growth in signal processing to extract ^^diff, ddprand ^^diff,reg. In both cases, the extracted ^^ ^^ pairs 901a and 901b for each signal are 23 bits in size with a bandwidth of 84 KHz. The resulted ^^diff, regand ^^diff, ddprare 43 bits and 61 bits in depth, respectively. The difference arises from the extra DDPR operation that involves numerous multiplications thereby, increasing the size of ^^Δand ^^Δ, and ultimately larger bit growth in ^^diff, ddpr.

[0195] The regular phase extraction (Figure 9A) then undergoes a second order CIC filter 903a that decimates the ^^ ^^ pairs to a sample speed of 2.6 KHz, adding 30 extra bits and bringing the bit depth up to 43 bits. In MATLAB, all ^^ ^^ components are converted into double-precision floating point variables and the phase calculated for each interferometer direction. Finally, ^^diff, reg is calculated by subtracting the two, double-precision floating point, phase variables.

[0196] Figure 9B shows the bit growth in signal processing for DDPR. Using the same extracted ^^ ^^ pairs as before, 23 bits in size with a bandwidth of 84 kHz, the four products ^^ ^^. ^^ ^^, ^^ ^^. ^^ ^^, ^^ ^^. ^^ ^^, and ^^ ^^. ^^ ^^ are formed by multiplication doubling the bit depth to 46 bits. Addition and subtraction, as per Equation (20), are then performed to generate ^^Δ and ^^Δ with a bit depth of up to 47 bits. As the CIC filter 903 (analogous to regular phase extraction) adds 30 additional bits and would therefore saturate the maximum 64-bit depth of our FPGA compiler, it becomes essential to bit-shift down. We choose a bit-shift of -16 bits 905 as this creates a new quantization limit well below the quantization limit imposed by the ADC. Consequently, the -16-bit shift 905 adds negligible addition quantization noise to the ^^Δ and ^^Δ components. The final decimated ^^ and ^^Δ components at 2.6 kHz, have a bit depth of 61 bits. These 61-bit components are then processed in MATLAB as double-precision floating point variables to generate the DDPR phase. 7.3. Experimental Results

[0197] To demonstrate the fundamental operation of DDPR, a large common mode frequency ramp is applied by modulating both AOMs depicted in Figure 8. This ramp has a depth of 400 kHz, equal to one free spectral range (FSR) of our BiMZI, resulting in a 2 ^^ optical common-mode phase modulation at the ramp frequency of 2 Hz. Figure 10A plots the CW (blue) and CCW (dashed orange) phase recovery: ^^^^ ^^(dark trace 1001) and ^^^^ ^^(light trace 1003) as well as the 2 Hz optical phase (trace 1005) derived from ^^ ^^ ^^ and ^^^^ ^^for the CW interferometer. The zoomed-in windows show a full sinusoidal cycle for both ^^ ^^ ^^ and ^^ ^^ ^^ and a 2 ^^ peak-to-peak linear phase ramp derived from them. At this slow speed of 2 Hz CW variables are identical to CCW as can be seen from Figure 10B which plots the CW phase (solid trace 1007) and the CCW phase (dashed trace 1009), both of which are superimposed in Figure 10B. Both traces show the same 2 Hz linear ramp superimposed on the phase drift, common to both interferometers, over 60 seconds.

[0198] Figure 10C plots the DDPR quadrature components ^^Δand ^^Δand the resulting differential phase ^^diff, ddprover the same time scale. Clearly, DDPR processing removes all common mode dynamics and therefore ^^Δand ^^Δno longer exhibit simple sinusoidal traces. The insert 1010 of Figure 10C zooms in on the identical 2 ^^ phase ramp in CW and CCW phases.

[0199] Instead, both variables are smaller, particularly ^^Δ, leading to ^^diff, ddprbeing far smaller than a full 2 ^^ cycle. Finally, Figure 10D) plots both ^^diff, ddpr(green dashed trace) and ^^diff, reg(purple trace) demonstrating excellent agreement for these slow dynamics. Here, both traces demonstrate 70 dB of cancellation of the 2 ^^ phase excursion and the interferometer phase drift. Figure 10D shows the post-phase-tracking subtraction of CW and CCW (solid trace 1013) phase, and DDPR phase (dashed trace 1015) Both the traces are identical, and the insert shows the rejection of the 2 ^^ phase ramp.

[0200] To test phase tracking performance with higher speed phase dynamics, the ramp frequency is increased to 656 Hz. Figure 11A shows the recovered optical phase signals where, CW is shown by trace 1101, CCW is shown by dashed trace 1103, and the two traces are again in close agreement. The higher ramp frequency used here results in only 4 samples per ramp period from the decimated FPGA output. Figure 11B shows the corresponding DDPR (trace 1105) and post-phase-tracking subtraction of CW and CCW phases (trace 1107). In Figure 11B, DDPR common mode suppression is seen to outperform the post-phase-tracking subtraction of CW and CCW interferometer phases, yielding a suppression ratio of 76 dB compared with the 58 dB suppression obtained by post-phase-tracking subtraction. Note that DDPR yields apparently larger suppression at 656 Hz compared to the 2 Hz result of Figure 10B. This is due to higher harmonics of the 656 Hz ramp being partially removed by the low pass filter prior to down sampling.

[0201] Figure 12 presents the phase spectral density plots of the time domain data shown in Figure 11B. Analogous to the time domain data, DDPR (solid trace 1201) is seen to outperform post-phase- tracking subtraction (dashed trace 1203), exhibiting a noise floor of 1×10−6rad / √Hz above1 Hz while small phase tracking errors in the individual channels limit the post-phase-tracking subtraction to 3×10−6rad / √Hz over the same frequency range.

[0202] As the ramp frequency is increased above 800 Hz, the fast ramp causes the individual phasemeters to undergo numerous cycle slips in the post-phase-tracking subtraction phase, effectively rendering post-phase-tracking subtraction inoperable in this regime. As an example, Figure 13 demonstrates time domain post-phase-tracking subtraction phase (trace 1205) and DDPR (trace 1207) when attempting to track a common 2 ^^, 1.3 kHz phase ramp over 60 seconds. Here, DDPR correctly removescommon mode phase dynamics while post-phase-tracking subtraction yields numerous cycle slips, producing an unusable output.

[0203] Figure 14 plots both the individual CW and CCW phases for the zoomed in section of Figure 13 showing a single cycle slip event at 10.82 seconds where the phase jumps by 2 ^^ radians and CCW phase continues to track. Note that as all the data for Figures 13 and 14A / 14B is recorded with a sample rate of 2.6 kSamples / s with a 2 ^^ phase ramp close to the Nyquist frequency at 1.3 kHz, all traces have only two samples per ramp cycle. Figure 14A plots the phase for the CW interferometer (trace 1401) as well as the resulting CCW interferometer phase (trace 1403) using MATLAB atan2 and unwrap functions. With this 1.3 kHz phase ramp, the recovered phase amplitude is approximately half the amplitude expected and variable in size due to the small number of samples per ramp cycle. However, in the duration plotted in Figure 14A, the CCW interferometer phase is seen to avoid full cycle slips where, as the CW interferometer phase shows a single cycle slip at 10.82 seconds. The DDPR phase recovery (trace 1405) and regular differential phase recovery (trace 1407) showing the clear cycle slip in the latter. The common ramp is also evidently suppressed in both the traces.

[0204] In Figure 14B, the resulting differential phases is shown with the trace 1405 plotting ^^diff, ddpr and trace 1407 plotting ^^diff, reg that is computed by subtracting the CW phase from the CW phase in MATLAB: ^^diff, reg= ^^ccw− ^^cw.

[0205] Clearly, ^^diff, reg contains a cycle slip event at 10.82 seconds while ^^diff, ddpr tracks faithfully throughout. In addition, ^^diff, ddpr reliably tracks the differential cyclic error of the interferometer whilst ^^diff, reg shows numerous small tracking errors that obscure this repetitive feature.

[0206] To demonstrate the robust performance of DDPR in dynamic and mechanically noisy environments, a mallet was used to apply mechanical impulses to mounting hardware surrounding the interferometer whilst simultaneously tuning AOM centre frequencies by 400 kHz at 1.3 kHz repetition frequency and, thermally tuning the Koheras X-15 laser over approximately 20 GHz of optical frequency over 80 seconds. Here, the 1.3 kHz frequency ramp simulates a laser source with far greater linewidththan the 100 Hz linewidth fiber laser while thermal tuning over 20 GHz introduces a huge dynamic range phase signal of ≈ 3×105radians. Figure 10 plots the DDPR response as mechanical impulses are applied to the optical table surface hosting the entire experiment. Impulses are applied to the top of the interferometer housing (IF box), the optical breadboard and the optical table. For each location, the impulse is repeated three times. The size of the impulse responses reflects the mechanical responsivity of the different parts of the experiment where DDPR measures the differential optical phase induced.

[0207] In Figure 15, the time domain DDPR phase recovery of a 400 kHz linear frequency tuning ramp at 1.3 kHz into the AOM and thermal tuning of laser over a frequency of 20 GHz over 80 seconds is demonstrated. Laser thermal tuning is seen to start at around 9 seconds (see insert) and monotonically increases for approximately 80 seconds, producing a DDPR phase excursion of 2.7×10−2radians. Mechanical impulses applied with the mallet to the interferometer housing (IF box top), the breadboard hosting the interferometer housing (Breadboard Edge) and, the optical table Surface and Edge each of which appears in the phase response as discontinuities. This phase response is repeatable over time scales up to tens of minutes and is caused by fiber birefringence within the interferometer in conjunction with small differences in the CW and CCW polarization states.

[0208] Superimposed on the thermal tuning response plotted in Figure 15, the mechanical impulse responses can be seen starting at 39 seconds. While all four locations produce measurable responses, the breadboard table edge and the interferometer housing yield the largest DDPR phase excursions of 1.4×10−2radians peak-to-peak. For the optical table edge impulses, signals of 1×10 radians peak-to-peak can clearly be detected.

[0209] The common mode phase suppression is quantified by taking the ratio of the peak-to-peak phase excursion of DDPR shown in Figure 15 (2.7×10−2radians) and the total laser thermal tuning signal injected (3×105radians). This yields a common mode phase suppression of 141 dB. For a direct comparison of DDPR and post-phase-tracking subtraction, Figure 16 plots both results for the mechanical impulse tests of Figure 15 with laser thermal tuning and linewidth broadening (injection of a 400 kHz linear frequency tuning ramp at 1.3 kHz into each AOM and thermally tuning the laser over frequency of 20 GHz over 80 seconds). On this scale, the DDPR (trace1601) is a flat line at approximately zero phase while post-phase-tracking subtraction demonstrates over 400 radians of cycle slip errors. The thermal tuning of the laser over approximately 80 seconds causes multiple cycle-slip events in the post-phase-subtraction readout while DDPR maintains slip-free tracking of the CW-CCW difference for the entire duration. In this implementation, the arctan computation of both the phases is done at the down sampled rate in MATLAB. 7.3.1. Discussion

[0210] The relationship between the desired interferometer variable, ^^ and the extracted variables ^^ and ^^, given by ^^ = arctan( ^^ / ^^), is highly nonlinear exhibiting discontinuities at ^^ = ± ^^. A phase unwrap algorithm is then required to correctly attribute these discontinuities and create the well behaved variable ^^ = unwrap{arctan( ^^ / ^^)}, effectively using the non-linear phase unwrap function to remove the discontinuities produced by arctan( ^^ / ^^). The correct functioning of both non-linear functions arctan( ^^ / ^^) and unwrap places stringent requirements on the processing of ^^ ^^ components to generate a high-fidelity phase readout. In particular, it is necessary to capture and process, all significant ^^ ^^ dynamics in order to produce an accurate phase output. Hence, the bandwidth of the ^^ ^^ signal pipeline must be substantially greater than all ^^ ^^ dynamics to avoid ^^ ^^ damage, irrespective of the desired phase signal bandwidth.

[0211] These ^^ ^^ requirements translate into dramatically different bandwidth requirements for the DDPR phasemeter when compared to the regular, post phase tracking subtraction implementation. While both techniques start with the same 23-bit depth, 84 kHz low pass filtered ^^ ^^ components, DDPR removes all common mode dynamics by implementing Equation (20) and generating ^^Δand ^^Δquadrature components. All subsequent processing can then be bandwidth limited to the differential signal requirement; in this experiment, set to 1 kHz. Thus, enabling ^^Δ and ^^Δ, to be low pass filtered and down sampled to 2.6 kSamples / s without degradation.

[0212] In contrast, regular post phase tracking subtraction requires both individual channel phasemeters to track all dynamics, common and differential. Consequently, as common mode phase dynamics approach the Nyquist frequency of 1.3 kHz, low pass filtering and down sampling to 2.6 kSamples / s of individual channel ^^ ^^ components causes irreversible damage resulting in both phasemeters frequently cycle slipping.7.3.2. Conclusion (DDPR Implementation Example)

[0213] In this example demonstration it has been shown how Direct Differential Phase Recovery (DDPR) operates directly on ^^ ^^ pairs to implement the ^^ ^^ equivalent of phase subtraction, prior to phase tracking, thus enabling highly robust differential phase measurements. Using DDPR, a differential phase sensitivity of 1×10−6rad / √Hz and a common mode rejection of 141 dB has been experimentally demonstrated in the presence of large, laser frequency dynamics. When perturbed by high frequency mechanical noise, DDPR has demonstrated robust performance whilst maintaining high sensitivity, when both individual channels are unable to phase track due to large and fast common mode phase dynamics. 8. Further Example DDPR and TDPR Implementations

[0214] Figure 17 shows a time domain DDPR and post-processed subtraction phase recovery: Here the phase difference of a 5km arm-length armlength mismatched bi-directional Mach-Zehnder interferometer is tracked where the laser used is the DX1 laser diode by Eblana Photonics. A 217Hz differential sinusoidal signal was also injected to calibrate the measurement. As seen in the left insert 1701, the post-processed phase subtraction undergoes multiple cycle slip whereas the right insert 1702 shows the DDPR phase continues to track the 217Hz differential signal without any cycle slip. In this implementation, in both DDPR and post-processed subtraction, the arctan operation occurs at the full clock rate of the FPGA.

[0215] Figure 18 shows a time domain recovery of 2π phase ramp at 2.6kHz and 17 Hz sinusoidal signal using IQ demodulation and TDPR. The IQ demodulation undergoes multiple cycle slips whereas the TDPR phase tracks the 17Hz sinusoidal signal without any cycle slips. It is noted that the 17 Hz signal is not visible on this scale so it’s not clear that TDPR is tracking it.

[0216] Figure 19 shows a plot of the RMS phase error in TDPR subtraction with respect to DDPR phase as a function of ^. Here ^ is varied from 744 ns to 31 µs for 1000 seconds of phase tracking data recordings. Overall, as ^ is increased, integrated quantization noise is reduced relative to signal size thus minimizing the phase error.

[0217] Figures 20A and 20B show a plot of the time domain and frequency domain readout from a diode laser interrogating the Bi-MZI system. The system is further modulated with a 2π phase ramp at 5 Hz and a sinusoidal differential signal at 217 Hz. Both differential signals are tracked and recovered using DDPR while regular subtraction is unable to track the signals. 9. Application Areas for DDPR

[0218] There are one or more applications of DDPR in optical phase metrology where DDPR provide an advantage: • DDPR can be applied to traditional, non-DI, heterodyne IQ phase tracking. Indeed, in this application, the lack of a DI code filter enables far higher bandwidth operation. In this application, both the bandwidth and cycle slipping probability should outperform dual phase locked loop implementations. • DDPR can be compatible with digital interferometric (DI) systems that utilise pseudo-random modulation for signal identification. • DDPR should enable high levels of common-mode noise rejection and signal isolation, which is necessary when synthesizing compound / multiple interferometer responses or other highly multiplexed optical sensing applications measuring small differential signal dynamics on a large common noise background. This may be removing common laser frequency noise between two or more independent measurements. • DDPR should enable tracking of the low frequency components of broadband lasers without cycle slipping whilst avoiding the need to track all the high frequency noise present. This could be an ideal solution when phase locking two or more high power lasers together to form optical phased arrays. 10. Application Areas for TDPR

[0219] There are one or more applications of TDPR in optical phase metrology where TDPR provide an advantage:• TDPR can be applied to traditional, non-DI, heterodyne IQ phase tracking. Indeed, in this application, the lack of a DI code filter enables far higher bandwidth operation. In this application, both the bandwidth and cycle slipping probability should outperform phase locked loop implementations. • TDPR can be compatible with digital interferometric (DI) systems that utilise pseudo-random modulation for signal identification. • TDPR should enable tracking of time-differential phase of broadband lasers without cycle slipping whilst avoiding the need to track all the high frequency noise present. This could be an ideal solution when measuring phase differences between coherent pulses to resolve time-of-flight / distance as in LiDAR and Distributed Acoustic Sensing (DAS) systems. • Weak light phase meter applications should benefit from the use of TDPR to reduce, or eliminate, cycle slipping when performing very low power phase measurements. Simple SNR degradation due to shot noise should dominate and obviate the need for the PLL signal bandwidth-cycle slip trade-off. Interpretation

[0220] In this specification, the term “i” is used to represent imaginary number, and is therefore interchangeable with the term “j”.

[0221] In this specification, the terms “I1(t)”, “I2(t)”, “Q1(t)”, and “Q2(t)” refer to digital signals, and are interchangeable with “I1[t]”, “I2[t]”, “Q1[t]”, and “Q2[t]” respectively.

[0222] Thepresenceofin a Figure or the text herein is understood to mean “and / or” unless otherwise indicated, for example, “X / Y” is understood to mean “X, or Y, or both X and Y”. The recitation of a particular numerical value or value range herein is understood to include or be a recitation of an approximate numerical value or value range, for instance, within about + / - 20%, + / - 15%, + / - 10%, + / - 5%, + / -2.5%, + / - 2%, + / - 1%, + / - 0.5%, or + / - 0.25%. The term “essentially all” or “substantially” can indicate apercentage greater than or equal to 90%, for instance, about 92.5%, 95%, 97.5%, 99%, or 100%.

[0223] From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated. Moreover, one or more components of a described apparatus or system, or one or more steps of a described method, may have been omitted from the description for clarity or for another reason. In addition, one or more components of a described apparatus or system that have been included in the description may be omitted from the apparatus or system, and one or more steps of a described method that have been included in the description may be omitted from the method.

[0224] It is understood that functions and operations described as being performed by software are performed by hardware, such as a controller (e.g., a microcontroller, or microprocessor), executing the software. Furthermore, it is understood that functions and operations described as being performed by software can be performed, instead, by hardware, firmware, one or more field-programmable gate arrays (FPGAs), one or more controllers, or a combination or sub-combination of one or more of hardware, firmware, FPGAs, and controllers.

[0225] The reference in this specification to any prior publication (or information derived from it), or to any matter which is known, is not, and should not be taken as, an acknowledgement or admission or any form of suggestion that that prior publication (or information derived from it) or known matter forms part of the common general knowledge in the field of endeavour to which this specification relates. Embodiments

[0226] Reference throughout this specification to “one embodiment”, “an embodiment”, “one arrangement” or “an arrangement” means that a particular feature, structure or characteristic described in connection with the embodiment / arrangement is included in at least one embodiment / arrangement of the present invention. Thus, appearances of the phrases “in one embodiment / arrangement” or “in an embodiment / arrangement” in various places throughout this specification are not necessarily all referring to the sameembodiment / arrangement, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments / arrangements.

[0227] Similarly it should be appreciated that in the above description of example embodiments / arrangements of the invention, various features of the invention are sometimes grouped together in a single embodiment / arrangement, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment / arrangement. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment / arrangement of this invention.

[0228] Furthermore, while some embodiments / arrangements described herein include some but not other features included in other embodiments / arrangements, combinations of features of different embodiments / arrangements are meant to be within the scope of the invention, and form different embodiments / arrangements, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments / arrangements can be used in any combination. Specific Details

[0229] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. Terminology

[0230] In describing the preferred embodiment of the invention illustrated in the drawings, specific terminology will be resorted to for the sake of clarity. However, the invention is not intended to be limited to the specific terms so selected, and it is to beunderstood that each specific term includes all technical equivalents which operate in a similar manner to accomplish a similar technical purpose. Terms such as “forward”, “rearward”, “radially”, “peripherally”, “upwardly”, “downwardly”, and the like are used as words of convenience to provide reference points and are not to be construed as limiting terms. Different Instances of Objects

[0231] As used herein, unless otherwise specified the use of the ordinal adjectives “first”, “second”, “third”, etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in any ranking, or in any other manner. Scope of Invention

[0232] Thus, while there has been described what are believed to be the preferred arrangements of the invention, those skilled in the art will recognize that other and further modifications may be made thereto without departing from the spirit of the invention, and it is intended to claim all such changes and modifications as fall within the scope of the invention. Functionality may be added or deleted from the block diagrams and operations may be interchanged among functional blocks. Steps may be added or deleted to methods described within the scope of the present invention.

[0233] Although the invention has been described with reference to specific examples, it will be appreciated by those skilled in the art that the invention may be embodied in many other forms.

[0234] It will be appreciated that the methods / apparatus / devices / systems described / illustrated above at least substantially provide improved methods and systems for detecting time-varying phase of time-varying signals.

[0235] The methods and systems described herein, and / or shown in the drawings, are presented by way of example only and are not limiting as to the scope of the invention. Unless otherwise specifically stated, individual aspects and components of the methods and systems may be modified, or may have been substituted therefore known equivalents, or as yet unknown substitutes such as may be developed in the future orsuch as may be found to be acceptable substitutes in the future. The methods and systems may also be modified for a variety of applications while remaining within the scope and spirit of the claimed invention, since the range of potential applications is great, and since it is intended that the present methods and systems be adaptable to many such variations. References 1. M. T. L. Hsu, I. C. M. Littler, D. A. Shaddock, et al., “Subpicometer length measurement using heterodyne laser interferometry and all-digital rf phase meters,” Opt. Lett.35, 4202–4204 (2010). 2. 2.D. A. Shaddock, “Digitally enhanced heterodyne interferometry,” Opt. Lett.32, 3355–3357 (2007). 3. D. Shaddock, B. Ware, P. Halverson, et al., “Overview of the lisa phasemeter,” in AIP conference proceedings, vol.873 (American Institute of Physics, 2006), pp.654–660. 4. 4.Kylia, “90-hybrids,” https: / / kylia.com / 90-hybrids. 5. Y. Nasu, T. Mizuno, R. Kasahara, and T. Saida, “Temperature insensitive and ultra wideband silica-based dual polarization optical hybrid for coherent receiver with highly symmetrical interferometer design,” Opt. Express 19, B112–B118 (2011). 6. 6.K. Creath, “V phase-measurement interferometry techniques,” (Elsevier, 1988), pp.349–393. 7. A. J. Sutton, O. Gerberding, G. Heinzel, and D. A. Shaddock, “Digitally enhanced homodyne interferometry,” Opt.Express 20, 22195–22207 (2012). 8. D. M. R. Wuchenich, T. T.-Y. Lam, J. H. Chow, et al., “Laser frequency noise immunity in multiplexed displacement sensing,” Opt. Lett.36, 672–674 (2011). 9. K. Chen, M. Guo, Y. Yang, et al., “A fiber-optic displacement sensor based on high-precision differential phase measurement,” J. Light. Technol. 36, 4046– 4050 (2018).Y. Zhang, C. P. Bandutunga, T. G. McRae, et al., “Double Rayleigh scattering in a digitally enhanced, all-fiber optical frequency reference,” Opt. Express 29, 26319–26331 (2021). C. P. Bandutunga, T. G. McRae, Y. Zhang, et al., “Infrasonic performance of a passively stabilized, all-fiber, optical frequency reference,” Opt. Express 28, 9280–9287 (2020). T. G. McRae, M. T. L. Hsu, C. H. Freund, et al., “Linearization and minimization of cyclic error with heterodyne laser interferometry,” Opt. Lett. 37, 2448–2450 (2012). T. Kissinger, T. O. Charrett, and R. P. Tatam, “Range-resolved interferometric signal processing using sinusoidal optical frequency modulation,” Opt. Express 23, 9415–9431 (2015). J. Wong, C. P. Bandutunga, P. Singh, et al., “Molecular dispersion spectroscopy using a code-division-multiplexed optical carrier,” Phys. Rev. Appl.19, 044027 (2023). G. Heinzel, M. D. Álvarez, A. Pizzella, et al., “Tracking length and differential-wavefront-sensing signals from quadrant photodiodes in heterodyne interferometers with digital phase-locked-loop readout,” Phys. Rev. Appl. 14, 054013 (2020). K. Danzmann and A. Rüdiger, “Lisa technology—concept, status, prospects,” Class. Quantum Gravity 20, S1 (2003). A. P. Hilton, P. S. Light, L. Talbot, and A. N. Luiten, “Optimal design for spectral narrowing and fast frequency sweep of an interferometer-stabilized laser,” Opt. Lett.45, 45–48 (2020).

Claims

CLAIMS:

1. A method for determining a time-varying phase difference between two time- varying signals, the method comprising: receiving or generating two independent time-varying in-phase components and two independent time-varying quadrature components from two or more demodulated time-varying signals; and determining the time-varying phase difference from the two time-varying in-phase components and two time-varying quadrature components by combining the four signals at each time point.

2. A method according to Claim 1, further comprising the step of determining a time-varying phase from the time-varying phase difference.

3. A method according to either Claim 1 or Claim 2, wherein the step of determining the time- varying phase difference from the combined signals comprises determining an arctan of the combined signals.

4. A method according to any one of the preceding claims, wherein the method further comprises the steps of anti-alias filtering and / or decimating the determined time-varying phase difference.

5. A method according to any one of the preceding claims, wherein the step of determining the two independent time- varying in-phase components and the two independent time-varying quadrature component comprises: automatically generating one of the two time-varying in-phase components by delaying the other of the two time-varying in-phase components by a selected time delay such that the two signals are independent; and automatically generating one of the two time-varying quadrature components by delaying the other of two time-varying quadrature components by the selected time delay such that the two signals are independent.

6. A method according to either Claim 1 or Claim 5, wherein the step of determining the time- varying phase difference from the combined signals comprises: determining an arctan of the combined signals; or when the selected time delay is below a predetermined threshold, determining that the time-varying phase difference is linearly related to the combined signals.

7. A method according to any one of Claims 1, 5, or 6, wherein the step of determining the time-varying phase comprises integrating the time-varying phase difference with respect to time.

8. A method according to any one of Claims 1 or 5 to 7, wherein the method further comprises the step of performing the delaying and / or the integrating in one or more DSP hardware components, for example in FPGAs.

9. A method according to any one of Claims 1 or 5 to 8, wherein the method further comprises the steps of anti-alias filtering and / or decimating the determined time-varying phase.

10. A method according to any one of the preceding claims, wherein the step of determining the arctan of the combined signals comprises the step of using a coordinate rotation method or component, for example on a coordinate rotation digital computer (CORDIC).

11. A method according to any one of the preceding claims, wherein the step of combining the four determined signals into the combined signals comprises: determiningproducts of the [I1(t), I2(t)] and the [Q1(t), Q2(t)], including according to the relationships: IA.IB, QA.QB, QA.IB, and IA.QB.; and determining a sum and a difference of the products, including according to the relationships: (IA.IB+ QA.QB), and (QA.IB− IA.QB).

12. A method according to Claim 11, wherein the step of determining the time-varying phase from the combined signals comprises determining a ratio of thedifference and the sum of the products, includingaccordingtothe relationship (QA.IB−IA.QB) / (IA.IB+ QA.QB).

13. A method according to any one of the preceding claims, wherein the method further comprises the step of determining the products, the sum, the difference and / or the ratio in one or more DSP hardware components, for example in one or more FPGAs.

14. A method according to any one of the preceding claims, wherein the method further comprises the step of low-pass filtering the four determined signals and prior to determining the time-varying phase difference, optionally using a code filter.

15. A method according to any one of the preceding claims, wherein the time-varying phase difference or the time-varying phase comprises radio frequencies.

16. A system configured / built to perform the method according to any one of the preceding claims, for example in an FPGA.

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