Server system, configuration method, CPU, control module and nonvolatile readable storage medium

Abstract

Provided are a server system, a configuration method, a CPU, a control module and a storage medium. The server system comprises: a plurality of CPUs, each CPU being provided with at least one bus interface; at least one data transmission bus, all of the CPUs being connected to the at least one data transmission bus by means of respective bus interfaces; a plurality of extended memories CXLs; and a memory resource allocation module CXL Switch, the CXL Switch being connected to each CPU by means of interfaces of a first type and being connected to each CXL by means of interfaces of a second type, and the CXL Switch being used for turning on a data path between a target CXL and a target CPU under the indication of a communication signal so as to allocate the target CXL to the target CPU. Because bus connection modes ensure advantages in transmission speed, even if allocating extended memories CXLs to CPUs increases data in the CPUs, the data can also be transmitted promptly.

Description

Server system, configuration method, CPU, control module and non-volatile readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on October 9, 2023, with application number 202311300080.8 and application name “Server system, configuration method, CPU, control module and storage medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the server field, and specifically, to a server system, a configuration method, a CPU, a control module, and a non-volatile readable storage medium. Background Art

[0004] Servers include tower, rack, blade, and cabinet types. Regardless of the machine type, the relationship between its CPU (Central Processing Unit) and memory is tightly coupled. Multi-way interconnection technology is generally used to connect multiple CPUs in a server. This connection method is difficult to avoid indirect connections between CPUs when there are many CPUs (for example, the first CPU needs to go through the second CPU before connecting to the third CPU). However, this indirect connection method limits the speed of data transmission between CPUs, and the storage resources of the CPUs in the server are relatively fixed, affecting the server's performance.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a server system, configuration method, CPU, control module and non-volatile readable storage medium to at least solve the problem in the related art that the CPUs in the server are indirectly connected and the storage resources of the CPU in the server are relatively fixed, which affects the performance of the server.

[0007] According to some embodiments of the present application, a server system is provided, comprising: multiple CPUs, each having at least one bus interface; at least one data transmission bus, all the CPUs connected to the at least one data transmission bus via the bus interface, and any two CPUs transmitting data via the at least one data transmission bus; multiple extended memories based on Compute Express Link (CXL); and a memory resource allocation module, a CXL Switch, having a first-type interface and a second-type interface, the CXL Switch connected to each of the CPUs via the first-type interface and connected to each of the extended memories via the second-type interface. The CXL Switch is configured to connect a data path between a target extended memory and a target CPU under the instruction of a connection signal, thereby allocating the target extended memory to the target CPU. The target extended memory is one or more of the multiple extended memories, and the target CPU is one of the multiple CPUs.

[0008] According to some embodiments of the present application, the CXL switch includes: a plurality of cascaded sub-CXL switches, each of the sub-CXL switches having a first type interface and a second type interface, one of the plurality of sub-CXL switches being connected to each of the CPUs via its first type interface, one of the plurality of sub-CXL switches being connected to each of the expansion memories via its second type interface, and the second type interface of a first-stage sub-CXL switch in two stages of the cascaded sub-CXL switches being connected to the first type interface of a second-stage sub-CXL switch.

[0009] According to some embodiments of the present application, the server system further includes: a control module, which is respectively connected to each of the extended memories, the CXL Switch, and each of the CPUs, and is configured to allocate the corresponding extended memory to each of the CPUs, and is further configured to combine at least one of the CPUs and at least one of the extended memories into a server unit to obtain multiple server units, so as to implement one or more functions using the multiple server units.

[0010] According to some embodiments of the present application, the server system also includes: a front panel; a back panel; and a CPU board sandwiched between the front panel and the back panel, wherein the CPU board integrates multiple CPUs and at least one data transmission bus, and the CPU board is connected to the back panel via a first board interface located on the back panel.

[0011] According to some embodiments of the present application, the server system further includes: one or more memory boards, integrating a plurality of the extended memories and the CXL Switch, sandwiched between the front panel and the backplane, and the memory board is connected to the backplane via a second board interface located on the backplane.

[0012] According to some embodiments of the present application, the system further includes: a control board, which integrates a control module and is sandwiched between the front panel and the back panel, and the control board is connected to the back panel via a third board interface located on the back panel, wherein the control module is respectively connected to each of the extended memories, the CXL Switch, and each of the CPUs.

[0013] According to some embodiments of the present application, it also includes: a power board, which is clamped between the front panel and the back panel, and the power board is connected to the back panel through a fourth board interface located on the back panel, and the power board supplies power to the server system.

[0014] According to some embodiments of the present application, a display unit and a control switch are also integrated on the front panel.

[0015] According to other embodiments of the present application, a configuration method in a CPU applied to a server system is provided, including: determining whether data needs to be transmitted between a first CPU and a second CPU, wherein the first CPU and the second CPU are any two of a plurality of CPUs; in the case where data needs to be transmitted between the first CPU and the second CPU, determining whether there is an idle data transmission bus; in the case where there is an idle data transmission bus, transmitting data between the first CPU and the second CPU via the idle data transmission bus.

[0016] According to some embodiments of the present application, in the presence of an idle data transmission bus, data is transmitted between the first CPU and the second CPU via the idle data transmission bus, including: in the presence of multiple idle data transmission buses, selecting an idle data transmission bus; and using the selected idle data transmission bus to transmit data between the first CPU and the second CPU.

[0017] According to some embodiments of the present application, determining whether there is an idle data transmission bus includes: obtaining a level signal of a preset position of each data transmission bus; and determining whether the corresponding data transmission bus is the idle data transmission bus based on the level signal.

[0018] According to some embodiments of the present application, a configuration method in a control module applied to a server system is provided. The server system further includes a control module, the control module being connected to each extended memory, the CXL Switch, and each CPU, respectively. The method includes: initializing the CXL Switch; detecting and saving the port number of the CPU connected to the first type interface; detecting and saving the port number of the extended memory connected to the second type interface; creating a memory resource pool and adding all the extended memories to the memory resource pool; obtaining corresponding extended memories from the memory resource pool according to performance requirements, and allocating the obtained extended memories to corresponding CPUs based on the port numbers of the CPUs and the extended memories.

[0019] According to some embodiments of the present application, the method also includes: determining whether the usage rate of the extended memory configured under the target CPU exceeds a preset usage rate, the target CPU is one of multiple CPUs, and the usage rate represents the proportion of the extended memory in use to the total extended memory, and / or the proportion of the used space of the extended memory in use to its total space; when the usage rate of the extended memory configured under the target CPU exceeds the preset usage rate, applying for new extended memory from the memory resource pool for the target CPU.

[0020] According to some embodiments of the present application, after applying for new extended memory from the memory resource pool for the target CPU, the method further includes: determining whether there is free extended memory in the memory resource pool, and if so, obtaining the free extended memory from the memory resource pool and obtaining the port number of the free extended memory; obtaining the port number of the target CPU, and matching the port number of the free extended memory with the port number of the target CPU to allocate the free extended memory to the target CPU.

[0021] According to some embodiments of the present application, the method also includes: determining whether the idle rate of the extended memory configured under the target CPU exceeds a preset idle rate, the idle rate representing the proportion of the unused space of the extended memory to its total space; when the idle rate of the extended memory configured under the target CPU exceeds the preset idle rate, the configuration relationship between the extended memory that exceeds the preset idle rate and the target CPU is terminated.

[0022] According to some embodiments of the present application, the configuration relationship between the extended memory that exceeds the preset idle rate and the target CPU is released, including: powering off the extended memory that exceeds the preset idle rate; and recycling the extended memory after power off into the memory resource pool to release the configuration relationship between the extended memory and the target CPU.

[0023] According to some embodiments of the present application, the configuration relationship between the extended memory that exceeds the preset idle rate and the target CPU is released, including: determining the extended memory with the highest idle rate; and releasing the configuration relationship between the extended memory with the highest idle rate and the target CPU.

[0024] According to some embodiments of the present application, the method further includes: combining at least one of the CPUs and at least one of the extended memories into a server unit to obtain a plurality of the server units; and controlling the plurality of the server units to run in parallel to implement one or more functions.

[0025] According to other embodiments of the present application, a CPU in the server system is provided, comprising: a first determination unit, configured to determine whether data needs to be transmitted between a first CPU and a second CPU, wherein the first CPU and the second CPU are any two of a plurality of CPUs; a second determination unit, configured to determine whether there is an idle data transmission bus when data needs to be transmitted between the first CPU and the second CPU; and a transmission unit, configured to transmit data between the first CPU and the second CPU via the idle data transmission bus when there is an idle data transmission bus.

[0026] According to other embodiments of the present application, a control module in a server system is provided. The server system further includes a control module, which is respectively connected to each of the extended memories, the CXL Switch, and each of the CPUs, and includes: an initialization unit configured to initialize the CXL Switch; a first detection and storage unit configured to detect and store the port number of the CPU connected to the first type interface; a second detection and storage unit configured to detect and store the port number of the extended memory connected to the second type interface; a creation unit configured to create a memory resource pool and add all of the extended memories to the memory resource pool; and an allocation unit configured to obtain corresponding extended memories from the memory resource pool according to performance requirements, and allocate the obtained extended memories to corresponding CPUs based on the port numbers of the CPUs and the extended memories.

[0027] According to some further embodiments of the present application, a non-volatile readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when running.

[0028] This application's solution, utilizing a bus connection, enables direct connection between any two CPUs, resolving the issue of excessively long transmission steps when indirectly connecting CPUs and improving data transmission speeds between them. Consequently, this connection method is much less restrictive on the number of CPUs than solutions in related technologies. This means that while increasing the number of CPUs, data transmission speeds are also maintained. Furthermore, the inclusion of extended memory and the memory resource allocation module (CXL Switch) allows for flexible configuration of CPU storage resources, ensuring superior server performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic diagram of a first server system according to an embodiment of the present application;

[0030] FIG2 is a schematic diagram of a second server system according to an embodiment of the present application;

[0031] FIG3 is a schematic diagram of a connection method between CPUs in the related art;

[0032] FIG4 is a schematic diagram of another connection method between CPUs in the related art;

[0033] FIG5 is a schematic diagram of a third server system according to an embodiment of the present application;

[0034] FIG6 is a schematic diagram of a cascade connection mode of a memory resource allocation module according to an embodiment of the present application;

[0035] FIG7 is a schematic diagram of a fourth server system according to an embodiment of the present application;

[0036] FIG8 is a schematic diagram of a fifth server system according to an embodiment of the present application;

[0037] FIG9 is a schematic diagram of a sixth server system according to an embodiment of the present application;

[0038] FIG10 is a flow chart of a configuration method applied in a CPU according to an embodiment of the present application;

[0039] FIG11 is a flow chart of an optional configuration method applied in a CPU according to an embodiment of the present application;

[0040] FIG12 is a flow chart of a configuration method applied in a control module according to an embodiment of the present application;

[0041] FIG13 is a flow chart of an optional configuration method applied in a control module according to an embodiment of the present application;

[0042] FIG14 is a flow chart of a method for determining a usage rate according to an embodiment of the present application;

[0043] FIG15 is a flow chart of an idle rate method according to an embodiment of the present application;

[0044] FIG16 is a schematic diagram of a CPU according to an embodiment of the present application;

[0045] FIG17 is a schematic diagram of a control module according to an embodiment of the present application.

[0046] The above drawings include the following reference numerals:

[0047] 10. Front panel; 20. Back panel; 30. CPU board; 40. Memory board; 50. Control board; 60. Power board; 31. First board interface; 41. Second board interface; 51. Third board interface; 61. Fourth board interface. DETAILED DESCRIPTION

[0048] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0050] It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present application described herein. In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, product, or apparatus.

[0051] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element or intervening elements may be present. Moreover, in the specification and claims, when it is described that an element is "connected to" another element, the element may be "directly connected to" the other element or "connected to" the other element through a third element.

[0052] For ease of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0053] In a first aspect of an embodiment of the present application, a server system is provided, as shown in FIG1 , including:

[0054] A plurality of CPUs, each CPU having at least one bus interface;

[0055] The number of CPUs is limited by the server system's structure and performance, and the number of bus interfaces on each CPU is also limited by the CPU's structure and performance. In other words, the number of CPUs and the number of bus interfaces on each CPU cannot be increased indefinitely.

[0056] At least one data transmission bus, all CPUs are connected to the at least one data transmission bus through a bus interface, and any two CPUs transmit data through the at least one data transmission bus.

[0057] In some embodiments, the total number of bus interfaces of each CPU is equal to the total number of data transmission buses, or the total number of bus interfaces of each CPU is greater than the total number of data transmission buses;

[0058] The total number of bus interfaces of each CPU is equal to the total number of data transmission buses, which means that the total number of data transmission buses is set based on the total number of bus interfaces of each CPU. For example, if a CPU has three bus interfaces, then three buses are set accordingly.

[0059] The total number of bus interfaces of each CPU is greater than the total number of data transmission buses. If a CPU has three bus interfaces, two buses are set accordingly, and one bus interface is idle.

[0060] In some embodiments, the bus in the present application may be a UPI-like bus, and the bus interface of the CPU may be a UPI-like interface structure;

[0061] In some embodiments, each of the N CPUs in the server system shown in FIG2 has two bus interfaces, and correspondingly, two buses are provided, namely, bus 0 and bus 1;

[0062] Figures 3 and 4 show the connection method of CPUs in related art. Taking Intel's UPI (Ultra Path Interconnect) as an example, if each CPU has two UPIs, the connection method between the four CPUs is shown in the left figure of Figure 3:

[0063] Two adjacent CPUs (such as CPU0 and CPU1) are directly connected with a step size of 1, while diagonal CPUs (such as CPU0 and CPU3) are indirectly connected with a step size of 2.

[0064] If the connection between any two CPUs among the four CPUs is required to be a direct connection (ie, the step size is 1), then the CPU must have three UPIs, as shown in the right figure in Figure 3.

[0065] Direct connections between CPUs are obviously more efficient than indirect connections. However, CPU UPI resources are limited and cannot be increased indefinitely. As the number of CPUs in a server increases, indirect connections between CPUs are inevitable. If a CPU has three UPIs and the maximum connection step is 2, the maximum number of CPUs supported is 8. Figure 4 shows the CPU connection method.

[0066] As can be seen from the above, the point-to-point connection method between CPUs, the maximum number of CPU UPI paths, and the maximum step size of CPU indirect connections determine the maximum number of CPUs in a server. However, if the CPU connection step size is too large, the data transmission speed between CPUs will become unacceptable, so the number of CPUs in a server will be limited.

[0067] Regarding the UPI connection method, this application's solution modifies the CPU connection method. The original CPU's UPI is directly connected to the UPI of another CPU. The modified CPU also has a UPI-like structure, but this UPI-like structure is directly connected to the bus. CPUs can have multiple UPI-like interfaces, which means that CPUs can be connected via multiple buses. Of course, the same implementation principle applies to connection methods other than UPI.

[0068] In addition, Intel also uses QPI (Quick Path Interconnect) and AMD uses HyperTransport, both of which are point-to-point connections.

[0069] The bus-based approach utilizes the principle of time-sharing multiplexing.

[0070] Multiple extended memories;

[0071] Compute Express Link (CXL), also known as Compute Express Link (CXL), is a high-speed interconnect technology that provides high-bandwidth, low-latency connections between a host computer's processors and devices such as accelerators, memory buffers, and intelligent input / output devices. CXL can be used for high-speed, low-latency connections between a host computer's CPU and GPUs, hard drives (such as mechanical hard drives, solid-state drives, hybrid hard drives), and network adapters (such as standard network adapters and smart network adapters). It can also be used for high-speed, low-latency connections between host computers or between host computers and external devices such as memory resource pools (such as external hard drives) and GPU resource pools. For example, high-speed channels can be used to connect multiple processors, accelerators, storage, and other devices, providing higher bandwidth and lower latency, thereby improving computing efficiency. Essentially, CXL maintains memory coherency between the CPU's memory space and the memory on connected devices. This enables resource sharing (or pooling) for higher performance, reduces software stack complexity, and lowers overall system cost. CXL enables data transfer between PCIe channels and memory, providing better memory access and management. It also allows computing and storage resources to be shared, reducing complexity and cost in the data center.

[0072] The memory resource allocation module CXL Switch (or computer extended interconnect network switch) can be used, but is not limited to, to interconnect processors and external devices in computer devices using CXL. The CXL Switch supports connecting the computer host's processor to more devices, allowing corresponding resources (such as computing resources, storage resources, and network transmission resources, etc.) to be allocated from connected external devices (such as GPUs, hard drives, and network cards, etc.) based on the processor workload requirements of the connected computer host, thereby improving resource utilization and reducing overall system costs. The CXL Switch in this application has a first type of interface and a second type of interface. The CXL Switch connects to each CPU via the first type of interface, and the memory resource allocation module connects to each CXL via the second type of interface. The CXL Switch is configured to connect the data path between the target extended memory and the target CPU under the instruction of a connection signal to allocate the target extended memory to the target CPU, wherein the target extended memory is one or more of a plurality of extended memories, and the target CPU is one of a plurality of CPUs.

[0073] The connection signal is sent by the control module in the CPU. Under the instruction of the connection signal, the memory resource allocation module CXL Switch connects the data path between the target extended memory and the target CPU to allocate resources to the target CPU.

[0074] In some embodiments, the configuration of one or more sub-servers (i.e., server units) is completed through the control module on the control board, that is, the CPU, extended memory, and other peripherals are physically connected into a whole that can operate independently. The connection method between the CPU and the extended memory: the PCIeRootComplex on the CPU is connected to the upstream port of the CXLSwitch, the extended memory is connected to the downstream port of the CXLSwitch, and the CXLSwitch is configured to connect the CPU to the extended memory, and both ports are enabled at the same time. After the power board is powered, the control board can power on the CPU through the control signal line connected to the CPU. After the CPU is powered on, it first completes its own initialization, and then initializes the bus controller, including the PCIeRootComplex that carries the CXL protocol. After the RC initialization is completed, it will detect the extended memory hanging under it, and will load the corresponding driver to initialize it, thereby completing the loading of the CPU and the extended memory hanging under it. During system operation, the extended memory can be hot-swapped. Before inserting the extended memory, its slot is in a non-powered state, and the CXLSwitch downstream port corresponding to the slot connected to the extended memory is also in a disabled state. After inserting the extended memory, the control module enables the downstream port connected to the extended memory and powers the slot, then notifies the CPU. The PCIeRootComplex on the CPU then detects the extended memory, triggering the operating system to load the extended memory driver to complete initialization. The extended memory is then added to the memory resource pool and can be used. To remove the extended memory, the control module first sends a request to the CPU to remove the extended memory. The operating system first transfers the program running on the extended memory to another memory location and deletes the memory device from the memory resource pool. This triggers the driver to perform deinitialization, and finally shuts down the downstream port of the slot. The slot is disconnected from power, and the extended memory is removed.

[0075] In some embodiments, as shown in Figure 5, the first type of interface is shown as interface UP, and the second type of interface is shown as interface DOWN. In addition, the emergence of extended memory leads to the possibility of decoupling the close relationship between CPU and memory.

[0076] With the above settings, the memory resource allocation module allocates extended memory to the CPUs in response to the connectivity signal. For example, CXL Memory0 and CXL Memory1 are allocated to CPU0, CXL Memory2 is allocated to CPU1, CXL Memory4 and CXL Memory5 are allocated to CPU3, and so on. This dynamically allocates memory resources to the CPUs based on actual needs. Allocating sufficient memory resources to the CPUs reduces data transmission between the CPUs, which in turn reduces bus busyness and improves data transmission speed between the CPUs.

[0077] Among them, the extended memory CXL Memory in this application can refer to, but is not limited to, memory expansion boards and persistent memory devices without local cache. Extended memory CXL Memory can use the CXL.io protocol and the CXL.memory protocol to provide the CPU of the computer host with access to memory through load and store commands. Extended memory CXL Memory can support volatile and persistent memory architectures. Extended memory CXL Memory can be a dedicated storage device that communicates directly with the CPU of the computer host and can use the CXL protocol to achieve low-latency, high-throughput data transmission. Extended memory CXL Memory can be used as a memory buffer and can also be used to expand memory bandwidth and memory capacity.

[0078] The CXL.io protocol is an enumeration and configuration protocol. It serves as a foundational communication protocol for device discovery and enumeration, error reporting, and more. In this mode, a host computer can extend its memory to external devices, enabling faster data transfer. For example, a CPU supporting this protocol and an external device can be connected via the PCIe bus, allowing the CPU to share memory with the external device and directly access the device's I / O (input and output) resources, resulting in lower latency, higher bandwidth, and improved scalability. The CXL.memory protocol is a memory protocol that uses load and store commands to provide the host computer processor with access to the memory of an external device. The host CPU acts as the master and the external device as a slave, supporting both volatile and persistent memory architectures. In this mode, the host computer can use an external device as main memory, achieving greater memory capacity. CXL.memory mode allows the host computer CPU to treat the external device as extended memory, enabling greater data storage. This improves system reliability, allowing the host CPU to continue operating through the external device even in the event of a memory failure.

[0079] In other words, the solution of this application, by utilizing a bus connection, enables direct connection between any two CPUs, resolving the issue of excessively long transmission steps when connecting CPUs indirectly and improving data transmission speed between CPUs. Accordingly, this connection method of this application places far fewer restrictions on the number of CPUs than solutions in the related art. This means that while increasing the number of CPUs, data transmission speed is also taken into account. Furthermore, the provision of extended memory and the memory resource allocation module (CXL Switch) allows for flexible configuration of CPU storage resources. This means that, because the bus connection method ensures superior transmission speed, even if extended memory is allocated to the CPUs, increasing the amount of data in the CPUs, timely data transmission can be achieved, ensuring the server's performance advantage.

[0080] Furthermore, the memory resource allocation module includes:

[0081] Multiple cascaded sub-CXL switches, each sub-CXL switch having a first type interface and a second type interface, one of the multiple sub-CXL switches connected to each CPU via its first type interface, one of the multiple sub-CXL switches connected to each expansion memory via its second type interface, and the second type interface of the first-stage sub-CXL switch in two stages of cascaded sub-CXL switches connected to the first type interface of the second-stage sub-CXL switch.

[0082] As shown in Figure 6, among the three sub-CXL switches, the first sub-CXL switch is cascaded with the second and third sub-CXL switches. Specifically, the UP port on the top layer is connected to the CPU, and the DOWN port on the bottom layer is connected to the expansion memory device.

[0083] For example, the connection method shown in Figure 5 can only allocate three CXL memories to a CPU within a time period. However, the connection method shown in Figure 6 can allocate six CXL memories to this CPU within the same time period. This means that more CXL memories can be allocated to this CPU without affecting the functions of other CPUs, ensuring normal functions and reducing the waiting time for free CXL memories.

[0084] The cascaded configuration above allocates more extended memory to the CPU. This means that compared to a non-cascaded configuration, more memory resources can be allocated to the CPU, enabling richer server functionality. This connection provides the foundation for pooling CPUs and extended memory.

[0085] Furthermore, as shown in FIG7 , the server system further includes:

[0086] The control module is respectively connected to each extended memory, the memory resource allocation module CXL Switch and each CPU, and is configured to allocate corresponding extended memory to each CPU. It is also configured to combine at least one CPU and at least one extended memory into a server unit to obtain multiple server units, and use multiple server units to implement one or functions.

[0087] For example, for a banking system, if it wants to realize the functions of deposit, withdrawal, and financial management, the solution of the relevant technology needs to set up at least one separate server system for the deposit function, at least one separate server system for the withdrawal function, and at least one separate server system for the financial management function; that is, multiple server systems are required to realize the three functions of deposit, withdrawal, and financial management. However, by adopting the solution of the present application, multiple server units are obtained by combining the CPU and the extended memory, and the multiple server units are in the same server system, that is, the same device realizes the three functions at the same time, saving space and cost.

[0088] In some embodiments, the control module may be a baseboard management controller BMC, a single chip microcomputer, etc.

[0089] Because the above-mentioned method combines at least one CPU and at least one extended memory into a server unit according to performance requirements to obtain multiple server units, a server system has the functions of multiple conventional servers, that is, it simplifies the server combination architecture, realizes the corresponding functions while saving space, and because the CPU and extended memory are highly integrated, the number of servers in the data center and the complexity of wiring between servers are further reduced. In other words, the entire machine can be configured as either a single server unit or multiple server units. Since this server model can integrate a large number of CPUs and memories in a single machine, it can greatly optimize the server layout of the data center, increase the data transmission speed between servers, and reduce the external connections between servers.

[0090] As mentioned above, this new CXL-based server implements hardware resource pooling for CPUs and extended memory. The control module flexibly manages and configures the combination of CPUs and extended memory devices. A single machine can be combined into one or more servers as needed. Because the server has a high level of CPU and extended memory integration, it reduces the number of servers in a data center and the complexity of cabling between servers.

[0091] In some implementations, when the functions to be implemented are relatively complex, the priorities of the functions to be implemented can be sorted, and the execution time of the functions to be implemented can be sorted. The order in which the server units are assigned to the functions can then be determined based on the priority and execution time results. For example, the server units can be assigned to the functions in order of execution time. If the execution times are the same, the server units for the higher-priority functions can be assigned first, followed by the server units for the lower-priority functions.

[0092] In some implementations, when the functions to be implemented are more complex, the spare extended memory in the server units configured for higher priority functions is greater than the spare extended memory in the server units configured for lower priority functions, thereby ensuring the reliability of the implementation of higher priority functions.

[0093] As shown in FIG8 and FIG9, the server system further includes:

[0094] front panel 10;

[0095] Back plate 20;

[0096] And a CPU board 30 sandwiched between the front panel 10 and the back panel 20, wherein the CPU board integrates multiple CPUs and at least one data transmission bus, and the CPU board is connected to the back panel via a first board interface 31 located on the back panel.

[0097] Among them, there can be one or more CPU boards;

[0098] In some embodiments, the CPU board is composed of multiple CPUs, each CPU can have its own independent memory, and the extended memory can be fully released. When more storage resources are needed, the extended memory is involved, and when it is idle, the extended memory is released;

[0099] Multiple CPUs can be placed on a single board, but each CPU can be controlled independently. A machine can have multiple CPU boards connected to other devices within the machine via a backplane. The control board controls the power-up of all CPUs. CPU boards are also hot-swappable.

[0100] The server device of the present application includes the aforementioned server system and possesses the functions of the aforementioned server system. Furthermore, by integrating the front panel, back panel, and CPU board into a single unit, the server device's integration is improved. This means that even complex functions can be implemented using the server device of the present application, eliminating the need for complex server architecture.

[0101] As shown in Figures 8 and 9, it also includes:

[0102] One or more memory boards 40, which integrate multiple extended memories and memory resource allocation modules, are sandwiched between the front panel 10 and the back panel 20, and the memory board is connected to the back panel via a second board interface 41 located on the back panel, wherein the memory resource allocation module is connected to each CPU via a first type interface, and the memory resource allocation module is connected to each extended memory via a second type interface.

[0103] In some embodiments, an expansion memory board comprises a CXL switch and an expansion memory device. The CPU is connected to the expansion memory device via the CXL switch and supports hot-swappable functionality. After the control board connects the CPU to the expansion memory device and powers it on, the CPU detects the expansion memory device and loads it. Alternatively, the expansion memory device can be powered on after the system is loaded on the CPU. When the CPU no longer needs the expansion memory, it must be uninstalled and removed, and the control board is notified. The control board then places it in a resource pool awaiting its next use. The expansion memory board is hot-swappable.

[0104] In some embodiments, the memory board is an extended memory board. Since a plurality of extended memories and memory resource allocation modules are integrated in the memory board, the memory board in the present application has the functions of extended memory and memory resource allocation module.

[0105] As shown in FIG8 and FIG9, it also includes:

[0106] The control board 50, which integrates a control module, is sandwiched between the front panel 10 and the back panel 20, and the control board is connected to the back panel through a third board interface 51 located on the back panel, wherein the control module is respectively connected to each extended memory, memory resource allocation module and each CPU.

[0107] In some embodiments, the control module and each extended memory, the memory resource allocation module and each CPU may be connected using a data bus, such as an I2C bus and a BUS bus;

[0108] The control board is similar to the BMC of existing servers and is responsible for the control, configuration and management of the CPU, extended memory expansion devices, and other device boards. It configures the connection between the CPU and the extended memory expansion devices. It can form a computer system by combining all CPUs and extended memory expansion devices, or it can use some CPUs and extended memory expansion devices to configure multiple computer systems as needed.

[0109] As described above, since the control module is integrated in the control board, the control board has the function of the control module. The control module is connected with the CPU, extended memory and memory resource allocation module through connections to configure memory resources for each CPU.

[0110] As shown in FIG8 and FIG9, it also includes:

[0111] The power board 60 is sandwiched between the front panel 10 and the back panel 20 , and is connected to the back panel via a fourth board interface 61 on the back panel. The power board supplies power to the server device.

[0112] As described above, a power board is provided to supply power to the control board, memory board, front panel, and back panel in the server device, thereby ensuring the normal operation of each part of the server device.

[0113] Furthermore, the front panel also integrates a display unit and a control switch. The display unit can be an indicator light, and different display states of the indicator light indicate different results of the function. The control switch can realize linkage control with the control board, memory board, etc. For example, when the control switch is turned on, the control board and memory board are enabled, and when the control switch is turned off, the control board and memory board are disabled.

[0114] In some embodiments, the first board interface, the second board interface, the third board interface, and the fourth board interface are all PCIe interfaces, which facilitates interconnection between boards.

[0115] A third aspect of the embodiments of the present application provides a first configuration method, which is applied to a CPU in a server system, as shown in FIG10 , including:

[0116] Step S101: determining whether data needs to be transmitted between a first CPU and a second CPU, wherein the first CPU and the second CPU are any two of a plurality of CPUs;

[0117] Step S102: When data needs to be transmitted between the first CPU and the second CPU, determining whether there is an idle data transmission bus;

[0118] Step S103 : when there is an idle data transmission bus, data is transmitted between the first CPU and the second CPU via the idle data transmission bus.

[0119] With the above setup, the CPUs independently determine whether there is an idle data transmission bus. If so, they occupy the idle data transmission bus to transfer data between the two CPUs. Furthermore, the two CPUs are directly connected, ensuring fast data transfer between them.

[0120] In some embodiments, when an idle data transmission bus exists, transmitting data between the first CPU and the second CPU via the idle data transmission bus includes:

[0121] When there are multiple idle data transmission buses, an idle data transmission bus is selected;

[0122] The selected idle data transmission bus is used to transmit data between the first CPU and the second CPU.

[0123] That is, when there are multiple data transmission buses to choose from, just select one of them to transmit data to prevent wrong transmission.

[0124] An optional implementation is shown in Figures 2 and 11. When data needs to be transferred between two CPUs, first determine whether Bus 0 is idle. If Bus 0 is idle, Bus 0 is set to a busy state and data is transferred using Bus 0. If Bus 0 is not idle, determine whether Bus 1 is idle in the same manner as Bus 0. If both Bus 0 and Bus 1 are busy, enter a waiting state until an idle bus is available, and then transfer data. It can be concluded that the bus-based inter-CPU data transmission bandwidth is shared by multiple CPUs within the server. Since inter-CPU data transmission is primarily memory-to-memory data transmission, the emergence of extended memory has greatly expanded the local memory of the CPU. This greatly reduces cross-CPU data access, significantly reducing the data transmission pressure on the inter-CPU bus. Accordingly, the number of CPUs within a server can be greatly increased, reducing the coupling between CPUs and paving the way for CPU resource pooling.

[0125] In some embodiments, determining whether there is an idle data transmission bus includes:

[0126] Obtaining a level signal of a preset position of each data transmission bus;

[0127] It is determined according to the level signal whether the corresponding data transmission bus is an idle data transmission bus.

[0128] For example, if the bus header is at a high level, it is determined to be busy; if the bus header is at a low level, it is determined to be idle. This level method can be used to easily determine the busy or idle state of the transmission bus.

[0129] A fourth aspect of the present application provides a second configuration method, which is applied to a control module in a server system. The server system further includes a control module, which is connected to each extended memory, CXL Switch, and each CPU, as shown in FIG12 , including:

[0130] Step S201: Initialize the memory resource allocation module;

[0131] Step S202: Detect and save the port number of the CPU connected to the first type interface;

[0132] For example, there are five CPUs: CPU0, CPU1, CPU2, CPU3, and CPU4, and their corresponding port numbers are: 001, 002, 003, 004, and 005;

[0133] Step S203: Detecting and saving the port number of the extended memory connected to the second type interface;

[0134] For example, there are five extended memories, namely: M0, M1, M2, M3 and M4, and the corresponding port numbers are: 0001, 0002, 0003, 0004, 0005;

[0135] Step S204: Create a memory resource pool and add all extended memories to the memory resource pool;

[0136] In some embodiments, M0, M1, M2, M3, and M4 with port numbers 0001, 0002, 0003, 0004, and 0005 are all added to the memory resource pool;

[0137] Step S205: Acquire corresponding extended memory from the memory resource pool according to performance requirements, and allocate the acquired extended memory to the corresponding CPU based on the port number of the CPU and the port number of the extended memory.

[0138] For example, if two extended memories need to be configured for CPU0 based on performance requirements and M0 and M1 are available, then M0 and M1 can be allocated to CPU0. This establishes a correspondence between 0001, 0002, and 0001.

[0139] The configuration method of the control module in the server system of the present application, through the steps of initialization, detecting and saving the port number of the extended memory, detecting and saving the port number of the extended memory, and creating a resource pool, finally realizes the allocation of corresponding extended memory to the CPU.

[0140] In an optional implementation, as shown in Figure 13, the memory resource allocation module uses a CXL switch, the first type interface is represented as an UP port, the second type interface is represented as an UP port, the DOWN port, the extended memory uses an extended memory, and the memory resource pool uses an extended memory resource pool, including:

[0141] Initialize the CXL Switch; detect the CPU on the UP port; save the CPU's corresponding port number; detect the extended memory on the DOWN port; save the extended memory's corresponding port number; create and initialize an extended memory resource pool; and add all extended memory devices to the resource pool. After the CXL Switch is initialized, the software can dynamically configure the connection between the CPU and the extended memory device. The extended memory is powered off before being connected to the CPU. After the CXL Switch completes the configuration of the extended memory, the CPU and the extended memory device are connected. The extended memory needs to be powered on, ultimately triggering the CPU to load the device. After completing these steps, the CPU can use the extended memory. Accordingly, when the CPU no longer needs a particular extended memory device, or when the device is hot-removed and powered off, the CXL Switch can allocate it to another CPU. In this way, the extended memory acts as a resource pool. The server organizes and manages all extended memory devices as a unified resource pool. When a CPU needs memory resources, it can allocate idle extended memory from the extended memory resource pool. When the CPU's memory resources become idle, the CPU must release the extended memory and return it to the extended memory resource pool. And all extended memory resources are idle during initialization.

[0142] The resource pool of the extended memory and its management functions, the initialization of the CXL Switch, and the connection between the CPU and the extended memory are completed by a management system outside the CPU, such as the BMC.

[0143] Furthermore, the method further comprises:

[0144] Determining whether a usage rate of extended memory configured under a target CPU exceeds a preset usage rate, where the target CPU is one of multiple CPUs, and the usage rate represents a ratio of the extended memory in use to the total extended memory, and / or a ratio of the used space of the extended memory in use to the total space;

[0145] When the usage of the extended memory configured for the target CPU exceeds the preset usage, new extended memory is requested from the memory resource pool for the target CPU.

[0146] The number of new extended memories can be one or more;

[0147] That is, if the usage of the extended memory configured under the target CPU exceeds a preset threshold, in order to ensure normal implementation of the function, new extended memory can be applied for the target CPU.

[0148] Furthermore, after applying for new extended memory from the memory resource pool for the target CPU, the method further includes:

[0149] Determine whether there is free extended memory in the memory resource pool. If so, obtain the free extended memory from the memory resource pool and obtain the port number of the free extended memory.

[0150] The port number of the target CPU is obtained, and the port number of the idle extended memory is matched with the port number of the target CPU to allocate the idle extended memory to the target CPU.

[0151] That is, first initiate an instruction to apply for new extended memory, then determine whether there is free extended memory in the memory resource pool. If so, allocate the free extended memory to the target CPU by pairing the port numbers.

[0152] An optional implementation method, as shown in Figure 14, determines whether the extended memory usage exceeds the threshold value. If so, the CPU applies for new extended memory from the resource pool, and queries the extended memory resource pool. If there is free extended memory in the pool, the DOWN port number of the extended memory and the UP port number of the CPU are obtained, the CPU and the extended memory are connected, and the extended memory is powered on and loaded (powering on here refers to powering on the extended memory alone), and the entire system remains powered on; after powering on and loading the extended memory, the new threshold value is adjusted.

[0153] Furthermore, the method further comprises:

[0154] Determine whether an idle rate of extended memory configured on a target CPU exceeds a preset idle rate, where the target CPU is one of multiple CPUs, and the idle rate represents a ratio of unused space of the extended memory to its total space;

[0155] When the idle rate of the extended memory configured under the target CPU exceeds the preset idle rate, the configuration relationship between the extended memory exceeding the preset idle rate and the target CPU is released.

[0156] That is to say, when the idle rate of the extended memory exceeds the idle rate threshold, the extended memory needs to be released so that it can be used by other CPUs.

[0157] Furthermore, the configuration relationship between the extended memory exceeding the preset idle rate and the target CPU is released, including:

[0158] Power off the extended memory that exceeds the preset idle rate;

[0159] After the power is turned off, the extended memory is reclaimed into the memory resource pool to release the configuration relationship between the extended memory and the target CPU.

[0160] That is, by powering off the extended memory separately and then recycling it, the configuration relationship between the extended memory and the target CPU is released. In other words, the release is achieved by utilizing the hot-swappable function of the extended memory.

[0161] In some embodiments, releasing the configuration relationship between the extended memory exceeding a preset idle rate and the target CPU includes:

[0162] Determine the extended memory with the highest idle rate;

[0163] Remove the configuration relationship between the extended memory with the highest idle rate and the target CPU.

[0164] Among them, the highest idle rate can be either absolutely idle or with a small amount of data. If it is absolutely idle, there is no need to migrate data and it can be released directly. If there is a small amount of data, even if data migration is performed, it will take less time, which is convenient and fast.

[0165] Some optional implementation methods are shown in Figure 15. It is judged that the idle rate of the extended memory exceeds the threshold value. If not, there is no need to release it. If so, find the most idle extended memory, allocate new pages on other memory devices, copy the used page content, and remap it. The CPU hot removes the idle extended memory, and the CPU applies to the resource pool to delete the extended memory and put the extended memory into the resource pool.

[0166] Furthermore, the method further comprises:

[0167] Combining at least one CPU and at least one extended memory into a server unit according to performance requirements to obtain a plurality of server units;

[0168] Control multiple server units to run in parallel to achieve multiple functions to meet performance requirements.

[0169] That is to say, the control module can realize the combination of CPU and extended memory according to performance requirements. All CPUs and extended memories can be considered to form a computer system, or all or part of the CPUs and extended memories can be considered to form multiple computer systems as needed.

[0170] In a fifth aspect of an embodiment of the present application, a CPU in a server system is provided, as shown in FIG16 , including:

[0171] A first determining unit 161 is configured to determine whether data needs to be transmitted between a first CPU and a second CPU, wherein the first CPU and the second CPU are any two of a plurality of CPUs;

[0172] The second determining unit 162 is configured to determine whether there is an idle data transmission bus when data needs to be transmitted between the first CPU and the second CPU;

[0173] The transmission unit 163 is configured to transmit data between the first CPU and the second CPU via the idle data transmission bus when there is an idle data transmission bus.

[0174] The CPUs in the server system of the present application independently determine whether there are idle data transmission buses. If so, they occupy the idle data transmission buses to transfer data between the two CPUs. Furthermore, the two CPUs are directly connected, ensuring fast data transmission between the two CPUs.

[0175] Furthermore, the transmission unit includes a selection module and a transmission module. The selection module is configured to select an idle data transmission bus when there are multiple idle data transmission buses; the transmission module is configured to use the selected idle data transmission bus to transmit data between the first CPU and the second CPU.

[0176] Furthermore, the second determination unit includes an acquisition module and a first determination module, the acquisition module is configured to acquire the level signal of the preset position of each data transmission bus; the first determination module is configured to determine whether the corresponding data transmission bus is an idle data transmission bus according to the level signal.

[0177] In a sixth aspect of an embodiment of the present application, a control module in a server system is provided. The server system further includes multiple extended memories and a memory resource allocation module. The memory resource allocation module is connected to each CPU via a first type interface, and the memory resource allocation module is connected to each extended memory via a second type interface, as shown in FIG17 . The control module includes:

[0178] The initialization unit 171 is configured to initialize the memory resource allocation module;

[0179] A first detection and storage unit 172 is configured to detect and store a port number of the CPU connected to the first type interface;

[0180] The second detection and storage unit 173 is configured to detect and store the port number of the extended memory connected to the second type interface;

[0181] The creation unit 174 is configured to create a memory resource pool and add all extended memories to the memory resource pool;

[0182] The allocating unit 175 is configured to obtain corresponding extended memory from the memory resource pool according to performance requirements, and allocate the obtained extended memory to the corresponding CPU based on the port number of the CPU and the port number of the extended memory.

[0183] The control module in the server system of the present application, after the steps of initialization, detecting and saving the port number of the extended memory, detecting and saving the port number of the extended memory, and creating a resource pool, finally realizes the allocation of corresponding extended memory to the CPU.

[0184] Furthermore, the control module also includes a third determination unit and an application unit. The third determination unit is configured to determine whether the usage rate of the extended memory configured under the target CPU exceeds the preset usage rate. The target CPU is one of multiple CPUs. The usage rate represents the proportion of the extended memory in use to the total extended memory, and / or the proportion of the used space of the extended memory in use to its total space; the application unit is configured to apply for new extended memory for the target CPU from the memory resource pool when the usage rate of the extended memory configured under the target CPU exceeds the preset usage rate.

[0185] Furthermore, the control module also includes a fourth determination unit and an acquisition unit. The fourth determination unit is configured to determine whether there is free extended memory in the memory resource pool after applying for new extended memory from the memory resource pool for the target CPU. If so, the free extended memory is obtained from the memory resource pool and the port number of the free extended memory is obtained; the acquisition unit is configured to obtain the port number of the target CPU and match the port number of the free extended memory with the port number of the target CPU to allocate the free extended memory to the target CPU.

[0186] Furthermore, the control module also includes a fifth determination unit and a release unit. The fifth determination unit is configured to determine whether the idle rate of the extended memory configured under the target CPU exceeds a preset idle rate. The target CPU is one of multiple CPUs, and the idle rate represents the proportion of unused space of the extended memory to its total space; the release unit is configured to release the configuration relationship between the extended memory that exceeds the preset idle rate and the target CPU when the idle rate of the extended memory configured under the target CPU exceeds the preset idle rate.

[0187] Furthermore, the release unit includes a power-off module and a recycling module. The power-off module is configured to power off the extended memory that exceeds a preset idle rate; the recycling module is configured to recycle the extended memory after power off into the memory resource pool to release the configuration relationship between the extended memory and the target CPU.

[0188] Furthermore, the release unit includes a second determining module and a release module. The second determining module is configured to determine the extended memory with the highest idle rate; the release module is configured to release the configuration relationship between the extended memory with the highest idle rate and the target CPU.

[0189] Furthermore, the control module also includes a combination unit and a control unit. The combination unit is configured to combine at least one CPU and at least one extended memory into a server unit according to performance requirements to obtain multiple server units; the control unit is configured to control multiple server units to run in parallel to realize multiple functions to meet performance requirements.

[0190] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0191] An embodiment of the present application further provides a non-volatile readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when running.

[0192] In an exemplary embodiment, the non-volatile readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0193] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0194] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0195] The examples in this embodiment can refer to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0196] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0197] The above are merely optional embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may be subject to various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A server system, characterized in that: include: A plurality of central processing units (CPUs), each of the CPUs having at least one bus interface; At least one data transmission bus, all the CPUs are connected to at least one data transmission bus through corresponding bus interfaces, and any two CPUs transmit data through at least one data transmission bus; Multiple extended memories based on Computer Extension Interconnect (CXL); A memory resource allocation module CXL Switch has a first type interface and a second type interface. The CXL Switch is connected to each of the CPUs via the first type interface and is connected to each of the extended memories via the second type interface. The CXL Switch is configured to connect a data path between a target extended memory and a target CPU under the instruction of a connection signal so as to allocate the target extended memory to the target CPU, wherein the target extended memory is one or more of the multiple extended memories, and the target CPU is one of the multiple CPUs.

2. The server system according to claim 1, characterized in that: The CXL Switch comprises: A plurality of cascaded sub-CXL Switches, each of the sub-CXL Switches having a first type interface and a second type interface, one of the plurality of sub-CXL Switches being connected to each of the CPUs via its first type interface, one of the plurality of sub-CXL Switches being connected to each of the extended memories via its second type interface, and the second type interface of a first-stage sub-CXL Switch in two stages of the cascaded sub-CXL Switches being connected to the first type interface of a second-stage sub-CXL Switch.

3. The server system according to claim 1, characterized in that: The server system also includes: The control module is respectively connected to each of the extended memories, the CXL Switch and each of the CPUs, and is configured to allocate the corresponding extended memory to each of the CPUs, and is also configured to combine at least one of the CPUs and at least one of the extended memories into a server unit to obtain a plurality of the server units, so as to implement one or more functions using the plurality of the server units.

4. The server system according to claim 1, characterized in that: The server system also includes: Front panel; Back panel; and a CPU board sandwiched between the front panel and the back panel, wherein the CPU board integrates a plurality of the CPUs and at least one data transmission bus, and the CPU board is connected to the back panel via a first board interface located on the back panel.

5. The server system according to claim 4, characterized in that: The server system also includes: One or more memory boards, integrating a plurality of the extended memories and the CXL Switch, are sandwiched between the front panel and the back panel, and the memory boards are connected to the back panel via a second board interface located on the back panel.

6. The server system according to claim 4, characterized in that: The server system also includes: A control board, integrated with a control module, is sandwiched between the front panel and the back panel, and the control board is connected to the back panel via a third board interface located on the back panel, wherein the control module is respectively connected to each of the extended memories, the CXL Switch and each of the CPUs.

7. The server system according to claim 4, characterized in that: The server system also includes: A power board is sandwiched between the front panel and the back panel, and the power board is connected to the back panel via a fourth board interface located on the back panel, and the power board supplies power to the server system.

8. The server system according to any one of claims 4 to 7, characterized in that: The front panel is also integrated with a display unit and a control switch.

9. A configuration method in a CPU in a server system according to any one of claims 1 to 8, characterized in that: include: Determine whether data needs to be transmitted between a first CPU and a second CPU, wherein the first CPU and the second CPU are any two of a plurality of CPUs; In the case where data needs to be transmitted between the first CPU and the second CPU, determining whether there is an idle data transmission bus; In the case where there is an idle data transfer bus, the first CPU and the second CPU are connected via the idle data transfer bus. Transfer data between CPUs.

10. The configuration method according to claim 9, characterized in that: In the case where there is an idle data transmission bus, transmitting data between the first CPU and the second CPU via the idle data transmission bus, comprising: When there are multiple idle data transmission buses, selecting an idle data transmission bus; The selected idle data transmission bus is used to transmit data between the first CPU and the second CPU.

11. The configuration method according to claim 9, characterized in that: Determine whether there is an idle data transfer bus, including: Acquiring a level signal of a preset position of each of the data transmission buses; Determine whether the corresponding data transmission bus is the idle data transmission bus according to the level signal.

12. A configuration method in a control module in a server system according to any one of claims 1 to 8, characterized in that: The server system further includes a control module, which is respectively connected to each of the extended memories, the CXL Switch and each of the CPUs, and includes: Initializing the CXL Switch; Detecting and saving the port number of the CPU connected to the first type of interface; Detecting and saving the port number of the extended memory connected to the second type interface; Creating a memory resource pool, and adding all the extended memories to the memory resource pool; The corresponding extended memory is obtained from the memory resource pool according to performance requirements, and the obtained extended memory is allocated to the corresponding CPU based on the port number of the CPU and the port number of the extended memory.

13. The configuration method according to claim 12, characterized in that: The method further comprises: Determine whether the usage rate of the extended memory configured under the target CPU exceeds a preset usage rate, wherein the usage rate represents the ratio of the extended memory in use to the total extended memory, and / or the ratio of the used space of the extended memory in use to the total space; When the usage rate of the extended memory configured under the target CPU exceeds the preset usage rate, a new extended memory is applied for from the memory resource pool for the target CPU.

14. The configuration method according to claim 13, characterized in that: After applying for new extended memory from the memory resource pool for the target CPU, the method further includes: Determine whether there is idle extended memory in the memory resource pool, and if yes, obtain the idle extended memory from the memory resource pool and obtain the port number of the idle extended memory; The port number of the target CPU is obtained, and the port number of the idle extended memory is matched with the port number of the target CPU to allocate the idle extended memory to the target CPU.

15. The configuration method according to claim 12, characterized in that: The method further comprises: Determine whether the idle rate of the extended memory configured under the target CPU exceeds a preset idle rate, where the idle rate represents the ratio of the unused space of the extended memory to its total space; When the idle rate of the extended memory configured under the target CPU exceeds the preset idle rate, the configuration relationship between the extended memory exceeding the preset idle rate and the target CPU is released.

16. The configuration method according to claim 15, characterized in that: Removing the configuration relationship between the extended memory exceeding the preset idle rate and the target CPU includes: Powering off the extended memory exceeding the preset idle rate; The extended memory after power failure is recycled into the memory resource pool to release the configuration relationship between the extended memory and the target CPU.

17. The configuration method according to claim 15, characterized in that: Removing the configuration relationship between the extended memory exceeding the preset idle rate and the target CPU includes: Determine the extended memory with the highest idle rate; The configuration relationship between the extended memory with the highest idle rate and the target CPU is released.

18. The configuration method according to claim 12, characterized in that: The method further comprises: Combining at least one of the CPUs and at least one of the extended memories into a server unit to obtain a plurality of the server units; Control multiple server units to run in parallel to achieve one or more functions.

19. A CPU in a server system according to any one of claims 1 to 8, characterized in that: include: A first determining unit is configured to determine whether data needs to be transmitted between a first CPU and a second CPU, wherein the first CPU and the second CPU are any two of a plurality of CPUs; a second determining unit, configured to determine whether there is an idle data transmission bus when data needs to be transmitted between the first CPU and the second CPU; The transmission unit is configured to transmit data between the first CPU and the second CPU via the idle data transmission bus when the idle data transmission bus exists.

20. A control module in a server system according to any one of claims 1 to 8, characterized in that: The server system further includes a control module, which is respectively connected to each of the extended memories, the CXL Switch and each of the CPUs, and includes: an initialization unit, configured to initialize the CXL Switch; a first detection and storage unit, configured to detect and store a port number of the CPU connected to the first type of interface; A second detection and storage unit is configured to detect and store a port number of the extended memory connected to the second type interface; A creating unit, configured to create a memory resource pool and add all of the extended memories to the memory resource pool; The allocation unit is configured to obtain the corresponding extended memory from the memory resource pool according to performance requirements, and allocate the obtained extended memory to the corresponding CPU based on the port number of the CPU and the port number of the extended memory.

21. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 9 to 11, or implements the steps of the method described in any one of claims 12 to 18.

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