Piezoelectric MEMS resonator and electronic element

Abstract

The present application relates to the field of semiconductor devices, and provides a piezoelectric MEMS resonator and an electronic element. The resonator comprises a cap wafer and a device wafer. The cap wafer comprises a cap layer. The device wafer comprises: a substrate layer; a resonant cavity, which is arranged in the substrate layer; a device silicon layer, which is located on the resonant cavity; a piezoelectric layer, which is located on the device silicon layer; a top electrode, which is located on the piezoelectric layer; and a first dielectric layer, which is located on the top electrode and covers the top electrode, wherein the first dielectric layer is in bonding connection with the cap layer, and the projection of at least one part of the first dielectric layer bonded to the cap layer in a vertical direction overlaps with the projection of the top electrode in the vertical direction, and the upper surface of the part, at least bonded to the cap layer, of the first dielectric layer is in the same plane. By means of the present application, the bonding characteristics of a cap wafer and a device wafer are improved by planarizing the surface of a dielectric layer covering a top electrode, thereby ensuring a good bonding effect.

Description

Piezoelectric MEMS resonators and electronic components Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a piezoelectric MEMS resonator and an electronic component. Background Art

[0002] The resonator is the core component of the oscillator. Since the electrostatically driven silicon-based MEMS resonator has a smaller size, lower manufacturing cost and higher reliability, the MEMS oscillator with the electrostatically driven silicon-based MEMS resonator as the core component is expected to become a substitute for the traditional quartz oscillator as the technology becomes more mature.

[0003] With the development of piezoelectric thin film materials, compared with electrostatically driven silicon-based MEMS resonators, piezoelectrically driven silicon-based MEMS resonators (referred to as "piezoelectrically driven silicon-based MEMS resonators") exhibit excellent performance such as lower motional impedance and higher electromechanical coupling coefficient, which is more conducive to reducing the power consumption and phase noise of the oscillator.

[0004] Since piezoelectrically driven silicon-based MEMS resonators do not require the application of electrostatic bias voltage, the error term caused by power supply jitter on the output signal is reduced; in addition, piezoelectrically driven silicon-based MEMS resonators do not require the formation of sub-micron-level silicon layer slits during processing, which reduces the process difficulty, helps improve the device yield, and is conducive to further miniaturization of the device.

[0005] Piezoelectrically driven silicon-based MEMS resonators often adopt a wafer-level packaging structure. In order to ensure that the piezoelectrically driven silicon-based MEMS resonator has a small size, the device wafer signal is usually led out through a conductive through-hole structure in the cap wafer. That is, a conductive through-hole structure for leading out the signal is formed in the silicon cap, thereby leading the electrode in the device layer to the outside of the package.

[0006] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art.

[0007] Summary of the Invention

[0008] The inventors have found that in the above-mentioned packaging structure, the process of machining the silicon cap with the conductive through-hole is relatively complicated and involves many steps, resulting in high manufacturing costs and low yield, thereby increasing the cost of a single chip.

[0009] In addition, the method of leading out the device wafer signal through the conductive through-hole structure in the cap wafer will affect the device performance before and after bonding, thereby having a great impact on the device frequency, impedance characteristics and other performance. It is not conducive to controlling these performances and maintaining consistency of device performance in production, which increases the intra-chip fluctuation of device performance.

[0010] In addition, due to the presence of a patterned electrode layer in the device wafer, the surface of the dielectric layer deposited on the electrode layer is usually uneven, which affects the bonding characteristics between the cap wafer and the device wafer.

[0011] In order to solve at least one of the above problems or other similar problems, embodiments of the present application provide a piezoelectric MEMS resonator and an electronic component.

[0012] According to one aspect of an embodiment of the present application, a piezoelectric MEMS resonator is provided, wherein the resonator includes a cap wafer and a device wafer, wherein the cap wafer includes a cap layer.

[0013] The device wafer comprises:

[0014] substrate layer;

[0015] A resonant cavity provided on the substrate layer;

[0016] a device silicon layer located on the upper side of the resonant cavity;

[0017] a piezoelectric layer located on the upper side of the device silicon layer;

[0018] a top electrode located on an upper side of the piezoelectric layer; and

[0019] a first dielectric layer located on the upper side of the top electrode and covering the top electrode,

[0020] The first dielectric layer is bonded to the cap layer, a projection of at least a portion of the first dielectric layer bonded to the cap layer in the vertical direction overlaps with a projection of the top electrode in the vertical direction, and an upper surface of at least the portion of the first dielectric layer bonded to the cap layer is in the same plane.

[0021] According to another aspect of the embodiments of the present application, an electronic component is provided, comprising the resonator described in the above embodiment.

[0022] One of the beneficial effects of the embodiments of the present application is that the bonding characteristics of the cap wafer and the device wafer are improved by planarizing the surface of the dielectric layer covering the top electrode, thereby ensuring a good bonding effect.

[0023] With reference to the following description and accompanying drawings, specific embodiments of the present application are disclosed in detail, indicating the manner in which the principles of the present application can be employed. It should be understood that the embodiments of the present application are not limited in scope. Within the spirit and scope of the appended claims, the embodiments of the present application include many variations, modifications and equivalents.

[0024] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0025] It should be emphasized that the terms “include / comprising / having” when used herein refer to the presence of features, integers, steps or components, but do not preclude the presence or addition of one or more other features, integers, steps or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The elements and features described in one figure or one embodiment of the present application can be combined with the elements and features shown in one or more other figures or embodiments. In addition, in the accompanying drawings, similar reference numerals represent corresponding parts in several figures and can be used to indicate corresponding parts used in more than one embodiment.

[0027] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0028] FIG1 is a schematic top view of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0029] FIG2 is a cross-sectional view of the piezoelectric MEMS resonator shown in FIG1 along the AA' direction;

[0030] FIG3 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0031] FIG4 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0032] FIG5 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0033] FIG6 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0034] FIG7 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0035] FIG8 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0036] FIG9 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0037] FIG10 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0038] FIG11 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0039] FIG12 is a schematic diagram of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0040] FIG13 is a cross-sectional view of the piezoelectric MEMS resonator shown in FIG12 along the AA' direction;

[0041] FIG14 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0042] FIG15 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0043] FIG16 is a schematic top view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0044] FIG17 is a cross-sectional view of the piezoelectric MEMS resonator shown in FIG16 along the BB′ direction. DETAILED DESCRIPTION

[0045] The above and other features of the present application will become apparent through the following description with reference to the accompanying drawings. In the description and the accompanying drawings, specific embodiments of the present application are disclosed in detail, which illustrate some embodiments in which the principles of the present application can be adopted. It should be understood that the present application is not limited to the described embodiments. On the contrary, the present application includes all modifications, variations and equivalents that fall within the scope of the appended claims.

[0046] In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish different elements from the name, but do not indicate the spatial arrangement or temporal order of these elements, and these elements should not be limited by these terms. The term "and / or" includes any one and all combinations of one or more of the associated listed terms. The terms "comprising", "including", "having", etc. refer to the presence of the stated features, elements, components or components, but do not exclude the presence or addition of one or more other features, elements, components or components.

[0047] In the embodiments of this application, the singular forms "a," "the," etc. include plural forms and should be broadly understood to mean "a" or "a type" rather than being limited to "one." Furthermore, the term "said" should be understood to include both singular and plural forms, unless the context clearly indicates otherwise. Furthermore, the term "according to" should be understood to mean "at least in part based on...", and the term "based on" should be understood to mean "at least in part based on...", unless the context clearly indicates otherwise.

[0048] The following describes various implementations of the present application in conjunction with the accompanying drawings. These implementations are merely illustrative and are not intended to limit the present application.

[0049] An embodiment of the present application provides a piezoelectric MEMS resonator, which may be a silicon-based MEMS resonator based on piezoelectric drive, but the embodiment of the present application is not limited to this. The piezoelectric MEMS resonator of the present application is described below using a silicon-based MEMS resonator based on piezoelectric drive as an example.

[0050] FIG1 is a schematic top view of a piezoelectric MEMS resonator according to an embodiment of the present application. FIG2 is a cross-sectional view of the piezoelectric MEMS resonator shown in FIG1 along the line AA′.

[0051] As shown in FIG2 , a piezoelectric MEMS resonator (hereinafter referred to as the “resonator”) 1 includes a cap wafer 30 and a device wafer 20. The cap wafer 30 includes a cap layer 301. The device wafer 20 includes a substrate layer 101, a resonant cavity 102 provided on the substrate layer, a piezoelectric layer 202 located above the resonant cavity 102, a top electrode 203 located above the piezoelectric layer 202, and a first dielectric layer 204 located above and covering the top electrode 203. In addition, for the sake of convenience, other layers of the device wafer 20 except the substrate layer 101 are sometimes collectively referred to as “device layers” when no ambiguity is caused.

[0052] In some embodiments, as shown in FIG2 , the first dielectric layer 204 is bonded to the cap layer 301, and the projection of at least a portion of the first dielectric layer 204 bonded to the cap layer 301 in the vertical direction overlaps with the projection of the top electrode 203 in the vertical direction. The upper surface of at least the portion of the first dielectric layer 301 bonded to the cap layer 301 is in the same plane. In other words, at least the area of ​​the upper surface of the first dielectric layer 301 bonded to the cap layer 301 is flat.

[0053] Therefore, by planarizing the surface of the dielectric layer covering the top electrode, the bonding characteristics between the cap wafer and the device wafer are improved, thereby ensuring a good bonding effect.

[0054] As shown in Figure 1, the cap wafer 30 and the device wafer 20 are bonded in the first direction z. In the embodiment of the present application, the first direction z, the second direction x, and the third direction y are perpendicular to each other. In addition, when there is no ambiguity, the first direction z is sometimes referred to as the "vertical direction", and the second direction x and the third direction y are sometimes referred to as the "horizontal direction". In addition, for the convenience of description below, unless otherwise specified, the dimension in the first direction z is referred to as "thickness", the dimension in the second direction x is referred to as "width", and the dimension in the third direction y is referred to as "length". For the first direction z, the direction from the device wafer 20 to the cap wafer 30 is referred to as "up", the direction from the cap wafer 30 to the device wafer 20 is referred to as "down", the surface located on the "upper" side is referred to as the "upper surface", and the surface located on the "lower" side is referred to as the "lower surface".

[0055] In some embodiments, the cap layer 301 of the cap wafer 30 may be formed of materials such as silicon or glass to protect the active device area of ​​the device wafer 20. In addition, for ease of description, the "cap layer" is sometimes referred to as a "silicon cap".

[0056] In some embodiments, the "device effective area" refers to, for example, the area where the resonant cavity 102 and the effective acoustic area of ​​the piezoelectric layer 202 overlap in the first direction z. For example, as shown in FIG2 , the effective acoustic area of ​​the piezoelectric layer 202 is, for example, the area of ​​the piezoelectric layer 202 covered by the top electrode 203, and the "device effective area" is, for example, the portion where the resonant cavity 102 overlaps with the top electrode 203 in the first direction z.

[0057] In some embodiments, the substrate layer 101 may be formed of a semiconductor material, or may be formed of a composite of multiple layers of materials, which is not limited in this embodiment of the present application. For example, the substrate layer 101 may be formed of single crystal silicon, for example, a high-resistance silicon material, the resistivity of the silicon material being, for example, greater than 1000 Ω·cm, for example, a resistivity >5000 Ω·cm, which is not limited in this embodiment of the present application. For example, the substrate layer 101 may also be formed of materials such as lithium niobate, lithium tantalate, silicon carbide (SiC), sapphire, and quartz. In addition, the substrate layer 101 may also be formed of semiconductor materials such as silicon dioxide, silicon nitride, polycrystalline silicon, and amorphous silicon, which is not limited in this embodiment of the present application.

[0058] In some embodiments, the resonant cavity 102 is a recess formed in the substrate layer 101, and the embodiments of the present application do not limit its formation process. In addition, although the word "cavity" is used for description, it can also be a Bragg reflector layer or other acoustic reflector layer with acoustic impedance characteristics close to or similar to the "cavity". The embodiments of the present application do not limit the choice of acoustic reflector structure, and can be designed according to actual needs. For example, when the Q value of the resonator is required to be high, a cavity can be selected as the acoustic reflector layer; when the heat dissipation performance or power of the resonator is required to be high, a Bragg reflector layer can be selected as the acoustic reflector layer. The following description takes the cavity as an example, and those skilled in the art should know that the embodiments of the present application are also applicable to acoustic reflector layers of other structures.

[0059] In some embodiments, the piezoelectric layer 202 can be formed of a piezoelectric film, for example, a piezoelectric film can be formed of a single crystal piezoelectric material. The embodiments of the present application do not limit the specific material and can be selected according to actual needs or performance requirements. For example, a material with a large piezoelectric coupling coefficient corresponding to transverse electric field excitation is selected, for example, a single crystal piezoelectric material such as lithium niobate or lithium tantalate is selected. In the embodiments of the present application, by selecting a suitable cut shape and the angle between the in-plane interdigitated electrodes and the crystal axis, the lithium niobate or lithium tantalate can have a large d11 (or e11), d15 (or e15), and d16 (or e16) piezoelectric coupling coefficient, thereby respectively causing the resonator to excite the zero-order symmetric Lamb Wave mode (abbreviated as S0 mode), the first-order antisymmetric Lamb Wave mode (abbreviated as A1 mode), the zero-order shear horizontal mode (abbreviated as SH0 mode), and higher-order or lower-order modes of the above modes.

[0060] In addition, the wafer-level packaging structure of the embodiment of the present application is suitable for piezoelectrically driven silicon-based MEMS resonators with different vibration modes. The planar structure of the piezoelectrically driven silicon-based MEMS resonator can be of various types, and the corresponding electrode arrangement structures are also different. Its vibration modes can also be of various types, such as: in-plane flexural vibration mode (in-plane flexural mode), out-of-plane flexural vibration mode (out-of-plane flexural mode), width extensional mode (WE mode for short), length extensional mode (LE mode for short), Lamé mode, etc., but not limited to the above vibration modes. In addition, the resonant frequency that can be achieved by the resonator of the embodiment of the present application can, for example, cover a range from tens of kHz to hundreds of MHz.

[0061] In some embodiments, the material forming the top electrode 203 can be a metal, for example, a single metal such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), chromium (Cr), or an alloy thereof, or a composite stack thereof; the material of the top electrode 203 can also be doped polysilicon, and the doping element can be boron (B), phosphorus (P), arsenic (As), etc., and the doping concentration can be, for example, 10 19 cm -3 As mentioned above, the higher the doping concentration, the lower the sheet resistance of the polysilicon electrode will be, and the lower the electrical loss will be. The material selected to form the top electrode 203 can be determined according to actual needs, and this embodiment of the application does not limit this.

[0062] In some embodiments, the material forming the first dielectric layer 204 can be silicon dioxide, fluorine-doped silicon dioxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, titanium oxide, tantalum pentoxide, etc., and can be a single layer or a combination of multiple layers of different dielectric materials. The first dielectric layer 204 can serve as a passivation layer of the resonator 1 and as an isolation layer between the signal line and the cap.

[0063] When the first dielectric layer 204 covers the surface of the resonant cavity, the first dielectric layer 204 also participates in the vibration of the resonant cavity. Therefore, the first dielectric layer 204 affects the frequency, temperature drift characteristics, and quality factor of the resonator. For example, the first dielectric layer 204 is formed of silicon dioxide material, which can also play a temperature compensation role in the resonator performance.

[0064] In some embodiments, a first dielectric layer 204 can be formed on the upper surface of the piezoelectric layer 202 including the top electrode 203 through a deposition process. The surface of the first dielectric layer 204 is higher at locations where metal leads are present than at other locations. If the thickness of the top electrode 203 is less than 1000 Å, this height difference will substantially not affect the bonding characteristics. However, if the thickness of the top electrode 203 is greater than 1000 Å, this height difference will affect the bonding characteristics. Therefore, after depositing the first dielectric layer 204, a chemical mechanical polishing (CMP) process can be performed on the first dielectric layer 204 to eliminate the surface height difference and ensure a good subsequent bonding effect. For example, the entire upper surface of the first dielectric layer 204 is flat.

[0065] In some embodiments, as shown in Figure 1, at least a portion of the projection of the top electrode 203 in the vertical direction z does not overlap with the projection of the cap layer 301 in the vertical direction z. As shown in Figure 2, the device wafer 20 also includes at least one first lead-out electrode P1 electrically connected to the top electrode 203, and the at least one first lead-out electrode P1 passes through the first dielectric layer 204 from the portion of the top electrode 203 that does not overlap with the cap layer 301 and covers the area on the upper surface of the first dielectric layer 204 that is not covered by the cap layer.

[0066] Thus, the processing of complex conductive through-hole structures in the silicon cap is avoided, the manufacturing cost is reduced, and the chip manufacturing yield is improved, so that a low-cost resonator chip can be obtained.

[0067] On the other hand, because the electrodes are led out laterally, the test pins and leads are not changed before and after the cap wafer is bonded to the device wafer. Therefore, the device performance is almost unaffected by the bonding process, which can improve the on-chip stability of the device performance. In traditional structures, the device layer signals are led out through the conductive via structure in the cap wafer. The device performance before and after bonding is affected by the process of forming the conductive via. The process of forming the conductive via has a significant impact on the device frequency and impedance characteristics, which is not conducive to maintaining good consistency in controlling device performance, thereby increasing the on-chip fluctuation of device performance.

[0068] In some embodiments, the first extraction electrode P1 is formed of, for example, gold, aluminum, copper, or aluminum-copper alloy, or aluminum-silicon-copper alloy, which is not limited in the present embodiment.

[0069] In some embodiments, as shown in FIG2 , the device wafer 20 further includes a device silicon layer 201 located between the piezoelectric layer 202 and the substrate layer. The device silicon layer 201 is a doped silicon layer. Thus, the device frequency-temperature characteristics can be improved. The device silicon layer 201 can be, for example, single crystal silicon or polycrystalline silicon. Furthermore, to further improve the device frequency-temperature characteristics, the device silicon layer 201 can be heavily doped silicon. The doping elements can be boron (B), phosphorus (P), arsenic (As), etc., with a doping concentration of, for example, 10 19 cm -3 Above, optionally, the doping concentration is 10 20 cm -3 above, thereby making the resistivity lower than 1 mΩ·cm.

[0070] In some embodiments, at least a portion of the projection of the device silicon layer 201 in the vertical direction z does not overlap with the projection of the cap layer 301 in the vertical direction z. As shown in FIG2 , the device wafer 20 further includes a second extraction electrode P2 electrically connected to the upper surface of the device silicon layer 201. The second extraction electrode P1 extends from the portion of the device silicon layer 201 that does not overlap with the cap layer 301, through the piezoelectric layer 202 and the first dielectric layer 204, and covers the area of ​​the upper surface of the first dielectric layer 204 that is not covered by the cap layer 301. Thus, the function of the bottom electrode of the piezoelectric layer 202 is realized by the device silicon layer 201. In addition, the material forming the second extraction electrode P2 can be the same as or different from the material forming the first extraction electrode P1, and this is not limited in this embodiment of the present application.

[0071] FIG3 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to an embodiment of the present application.

[0072] In some embodiments, as shown in FIG2 , the device wafer 20 further includes a silicon oxide layer 207 located between the device silicon layer 201 and the substrate layer 101. The portion of the silicon oxide layer 207 corresponding to the resonant cavity 102 is located on the lower surface of the device silicon layer 201. Alternatively, as shown in FIG3 , the portion of the silicon oxide layer 103 corresponding to the resonant cavity 102 is formed on the upper surface of the substrate layer 101.

[0073] For example, when forming an SOI wafer with a preset cavity (Cavity SOI, abbreviated as CSOI), the silicon oxide layer 207 used for bonding is formed below the device silicon layer 201. At this time, the silicon oxide layer 207 exists below the suspended area of ​​the device finally formed; optionally, when forming CSOI, the silicon oxide layer 103 used for bonding is formed on the surface of the substrate 101. At this time, the silicon oxide layer 103 does not exist below the suspended area of ​​the device finally formed.

[0074] In addition, the silicon oxide layer 207 or the silicon oxide layer 103 can be formed by a thermal oxidation method, or by other methods such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). The specific formation method can refer to the relevant technology, and the embodiments of the present application are not limited to this.

[0075] FIG. 4 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application.

[0076] In some embodiments, as shown in Figure 4, the device wafer 20 also includes a bottom electrode 208 located on the lower side of the piezoelectric layer 202 and at least one second lead-out electrode P2 electrically connected to the bottom electrode 208, at least a portion of the projection of the bottom electrode 202 in the vertical direction z does not overlap with the projection of the cap layer 301 in the vertical direction z, and at least one second lead-out electrode P2 passes through the piezoelectric layer 202 and the first dielectric layer 204 from the portion of the bottom electrode 208 that does not overlap with the cap layer 301 and covers the upper surface of the first dielectric layer 204.

[0077] For example, the bottom electrode 208 is located between the piezoelectric layer 202 and the device silicon layer 201 , thereby further reducing the motion impedance of the device and improving the reliability of the connection between the second extraction electrode P2 and the device silicon layer 201 .

[0078] In addition, the bottom electrode 208 is, for example, a metal layer, and can be made of a single metal such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), chromium (Cr), or an alloy thereof, or a composite stack thereof, and the embodiments of the present application are not limited to this.

[0079] In addition, the structure of the cap wafer 30 shown in Figure 3 is different. The edge of the cap wafer 30 shown in Figure 4 is formed with an eaves structure protruding outward in the horizontal direction. This is formed by different processing techniques and is not limited in the embodiments of the present application.

[0080] In some embodiments, as shown in FIG2 , the device wafer further includes a sealing ring 205 , through which the first dielectric layer 204 is bonded to the cap layer 301 . The sealing ring 205 is formed from at least one layer of metal material and / or dielectric material. For example, the metal material can be gold, aluminum, germanium, tin, copper, or the like, used to form a metal-silicon bond or a metal-metal bond, and can also include at least one layer of adhesion layer or barrier layer material, such as titanium (Ti), titanium tungsten (TiW), or chromium (Cr). The dielectric material can be silicon dioxide, glass frit, or the like, which can be used to bond to the silicon wafer or the glass wafer, respectively. Furthermore, the sealing ring 205 can be formed from the same material as the first electrode P1 or the second electrode P2 . For example, the sealing ring 205 and the first electrode P1 or the second electrode P2 can be formed simultaneously through the same process. Alternatively, the sealing ring 205 can be formed from a different material than the first electrode P1 or the second electrode P2 , which is not limited in this embodiment of the present application.

[0081] FIG. 5 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application.

[0082] In some embodiments, as shown in FIG. 5 , a portion of the first dielectric layer 204 bonded to the capping layer 301 is thicker than a portion of the first dielectric layer 204 not bonded to the capping layer 301 .

[0083] For example, the first dielectric layer 204 is bonded to the cap layer 301 through the sealing ring 205, and the cap wafer 30 and the device wafer 20 can be bonded together by gold-silicon bonding. After the device layer is manufactured and before bonding with the cap wafer), sometimes in order to adjust the frequency of the resonator, it is necessary to adjust the thickness of the first dielectric layer 204. For example, the first dielectric layer 204 is silicon dioxide or aluminum nitride, or a stacked combination of the two materials. The first dielectric layer 204 can be subjected to ion beam frequency correction treatment, that is, the first dielectric layer 204 is thinned by ion beam bombardment. At this time, the first dielectric layer 204 below the sealing ring 205 is protected by the sealing ring 205, and its thickness remains unchanged, and the thickness of the first dielectric layer 204 not covered by the sealing ring 205 is thinned.

[0084] In some embodiments, as shown in Figures 1 to 5, the cap layer 301 and the first dielectric layer 204 form an upper cavity 302. The upper cavity 302 can be a single cavity or include multiple sub-cavities. The size (or "depth") of the upper cavity 302 in the first direction z can be set according to the vibration amplitude of the resonator, which is not limited in this embodiment of the present application.

[0085] In addition, as shown in Figures 1 to 5, the resonator 1 has a groove H that passes through the upper cavity 302 and the resonant cavity 102, thereby realizing the sealed package of the resonator 1. In addition, by adjusting the bonding parameters, the sealing vacuum degree can be adjusted to achieve packages of different pressures, for example, to achieve normal pressure packaging, that is, consistent with or slightly less than the external atmospheric pressure; or to achieve high vacuum packaging, for example, less than 10Pa, or less than 1Pa, less than 0.1Pa, etc.; or to achieve general vacuum packaging, for example, less than 100Pa, or less than 1kPa, etc. The corresponding vacuum degree can be selected according to actual needs, and the embodiments of the present application are not limited to this.

[0086] FIG6 is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator according to an embodiment of the present application.

[0087] Different from the structure of the resonator shown in FIG4 , the piezoelectric layer 202 or the first dielectric layer 204 of the resonator 1 shown in FIG6 and the end surface of the device silicon layer 201 on the groove H side are located in different planes, that is, the piezoelectric layer 202 or the first dielectric layer 204 and the end surface of the device silicon layer 201 on the groove H side are not flush.

[0088] In some embodiments, as shown in FIG6 , the end surfaces of the first dielectric layer 204 and the piezoelectric layer 202 on the side of the groove H may be flush, for example, the end surfaces of the first dielectric layer 204 and the piezoelectric layer 202 on the side of the groove H may be parallel to the vertical direction or inclined relative to the vertical direction; the end surfaces of the device silicon layer 201 and the silicon oxide layer 207 on the side of the groove H may also be flush, for example, parallel to the vertical direction; the end surface of the bottom electrode 208 on the side of the groove H is not flush with the end surfaces of the piezoelectric layer 202 and the device silicon layer 201 on its upper and lower sides.

[0089] For example, when forming the groove H using an etching process, a distributed shell etching method can be used. For example, the piezoelectric layer 202 and the first dielectric layer 204 are formed using the same photolithography etching, and the bottom electrode 208 is formed using wet etching, which is 0 to 5 μm smaller inward than the piezoelectric layer 202. Optionally, it is 1 to 2.5 μm smaller inward than the piezoelectric layer 202. Finally, the device silicon layer 201 and the silicon oxide layer 207 are etched using a Bosch deep silicon etching process, so that the device silicon layer 201 and the silicon oxide layer 207 have a high verticality feature close to 90° on the end face of the groove H.

[0090] In addition, the embodiments of the present application are not limited thereto. For example, the first dielectric layer 204 and the piezoelectric layer 202 may not be flush at the end surfaces of the trench H, and the device silicon layer 201 and the silicon oxide layer 207 may not be flush at the end surfaces of the trench H. In addition, for example, as shown in FIG. 2 to FIG. 5 , all layer structures may be flush at the end surfaces of the trench H. For example, the trench H may be formed by a continuous etching method. The embodiments of the present application are not limited thereto.

[0091] 7 and 8 are cross-sectional views of another embodiment of the piezoelectric MEMS resonator according to the present application.

[0092] In some embodiments, the first dielectric layer 204 located in the active region of the device can be removed by etching, thereby preventing the first dielectric layer 204 from affecting device performance and serving only as an isolation layer between the signal line and the cap. For example, FIG7 differs from FIG2 in that, as shown in FIG7 , the first dielectric layer 204 corresponding to the active region of the device, for example, at least the suspended portion of the device layer, is removed by etching.

[0093] In some embodiments, as shown in FIG8 , the resonator 1 further comprises a second dielectric layer 209 located between the first dielectric layer 204 and the top electrode 203. The second dielectric layer 209 and the first dielectric layer 204 may be formed of different materials. Thus, the second dielectric layer 209 can serve as a passivation layer for the top electrode 203 and a barrier layer for etching the first dielectric layer 204. It can also serve as a temperature compensation layer for the resonator. For example, the first dielectric layer 204 is formed of silicon dioxide and the second dielectric layer 209 is formed of aluminum nitride. In this case, the second dielectric layer 209 can serve as a passivation layer for protecting the metal top electrode 203. At the same time, the second dielectric layer 209 can serve as a barrier layer when etching the first dielectric layer 204. For another example, the first dielectric layer 204 is formed of silicon nitride and the second dielectric layer 209 is formed of silicon dioxide. In this case, in addition to achieving the above functions, the second dielectric layer 209 can also serve as a temperature compensation layer for the resonator. This embodiment of the present application is not limited to this.

[0094] FIG. 9 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application.

[0095] In some embodiments, the first dielectric layer 204 located in the active region of the device can be patterned by etching, thereby achieving simultaneous adjustment of the temperature coefficient and the frequency characteristic.

[0096] For example, the difference between FIG. 9 and FIG. 8 is that, as shown in FIG. 9 , the first dielectric layer 204 is etched into a predetermined pattern within the active device region, e.g., at least the overhanging portion of the device layer. This predetermined pattern can be configured based on desired temperature coefficients and frequency characteristics. For example, the material density, stiffness, and temperature coefficient of the first dielectric layer 204 differ from those of the second dielectric layer 209, and the removal rates of the two differ during ion beam bombardment. This facilitates simultaneous adjustment of the temperature coefficient and frequency characteristics through ion beam bombardment.

[0097] FIG. 10 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application.

[0098] In some embodiments, as shown in FIG10 , the cap wafer 30 further includes a metal layer 304 , through which the cap layer 301 is bonded to the sealing ring 205 . The metal layer 304 is formed of at least one layer of metal material, thereby achieving a metal-to-metal bonding method, such as gold-gold bonding, aluminum-germanium bonding, or gold-tin-copper bonding.

[0099] In some embodiments, as shown in FIG10 , the cap wafer 30 further includes a first insulating layer 303 covering the outer surface of the cap layer 301, and a metal layer 304 is formed on the lower surface of the first insulating layer 303. For example, the cap wafer 30 is formed of single crystal silicon, and the first insulating layer 303 can be a silicon dioxide layer formed by thermal oxidation, thereby further reducing the parasitic capacitance generated by the cap wafer, or improving bonding reliability and extending device life.

[0100] FIG. 11 is a cross-sectional view of another embodiment of a piezoelectric MEMS resonator according to an embodiment of the present application.

[0101] In some embodiments, the device wafer 20 further includes a second insulating layer 215 located below the bottom electrode 208. For example, as shown in FIG11 , compared to the resonator shown in FIG4 , a second insulating layer 215 is added below the bottom electrode 208. The second insulating layer 215 can be formed of materials such as silicon dioxide, doped silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, or tantalum pentoxide. The second insulating layer 215 can be a single layer or a combination of multiple layers of different dielectric materials. Because the bottom electrode 208 is insulated from the device silicon layer 201 by the second insulating layer 215, the bottom electrode 208 can be patterned into multiple electrode shapes to connect electrical signals of different polarities.

[0102] Figure 12 is a schematic diagram of another embodiment of the piezoelectric MEMS resonator of the embodiment of the present application, Figure 13 is a cross-sectional view of the piezoelectric MEMS resonator shown in Figure 12 along the AA' direction, and Figures 14 and 15 are cross-sectional views of another embodiment of the piezoelectric MEMS resonator of the embodiment of the present application.

[0103] In some embodiments, as shown in FIG13 , the device silicon layer 201 further includes a trench-shaped isolation layer 210 penetrating the device silicon layer 201 . The isolation layer 210 extends from the portion of the device silicon layer 201 located in the device active area to the portion corresponding to the second extraction electrode P2 .

[0104] As shown in FIG13 , the isolation layer 210 includes a third insulating layer 211 filled in the trench. For example, a groove structure is etched in the device silicon layer 201, and the groove structure is filled with an insulating material such as silicon dioxide or a combination of silicon dioxide and polysilicon. Finally, the excess insulating layer is removed by etching or CMP. For example, by CMP, only the third insulating layer 211 in the trench shown in FIG13 is retained, while no insulating layer is retained on the surface of the device silicon layer 201.

[0105] As shown in FIG. 14 and FIG. 15 , the isolation layer 210 may also include a fourth insulating layer 212 located on the upper surface of the device silicon layer 201 . The fourth insulating layer 212 is located on the portion of the upper surface of the device silicon layer 201 that is not covered by the second lead electrode P2 and the piezoelectric layer 202 .

[0106] For example, after the insulating material is filled in the groove, the insulating layer on the surface of the device silicon layer 201 where the piezoelectric layer 202 needs to be grown and the location where the piezoelectric layer 202 needs to be connected to the second lead-out electrode P2 is etched away by etching, while the insulating layer in other areas of the surface of the device silicon layer 201 is retained, thereby forming the fourth insulating layer 212 shown in Figure 14.

[0107] For another example, after the insulating material is filled in the groove, the insulating layer at the position where the piezoelectric layer 202 needs to be grown on the surface of the device silicon layer 201 is first etched away by etching, while the insulating layer in other areas of the surface of the device silicon layer 201 is retained. When the second lead electrode P2 is formed to connect to the bottom electrode, the first dielectric layer 204 and the piezoelectric layer 202 are etched, and then the insulating layer at the exposed position is etched away to expose the device silicon layer 201 or the bottom electrode.

[0108] FIG16 is a schematic top view of another embodiment of the piezoelectric MEMS resonator according to an embodiment of the present application. FIG17 is a cross-sectional view of the piezoelectric MEMS resonator shown in FIG16 along the BB′ direction.

[0109] In some embodiments, the sealing ring 205 may also be electrically connected to the bottom electrode of the piezoelectric layer 202 , thereby reducing the parasitic capacitance effect of the metal sealing ring 205 and the cap wafer 30 on the resonator, thereby improving the performance of the resonator.

[0110] For example, when the device silicon layer 201 serves as the bottom electrode of the piezoelectric layer 202, the sealing ring 205 can be electrically connected to the device silicon layer 201 through at least one conductive via. For example, as shown in FIG17 , the conductive via P3 passes through at least the first dielectric layer 204 and the piezoelectric layer 202 and is electrically connected to the top surface of the device silicon layer 201. FIG16 and FIG17 illustrate only one conductive via, but the embodiments of the present application are not limited thereto; multiple conductive vias may be provided as needed.

[0111] In addition, optionally, in the case where the device wafer 20 includes a bottom electrode 208, the sealing ring 205 can be electrically connected to the bottom electrode 208 through at least one conductive hole, and the at least one conductive hole at least passes through the first dielectric layer 204 and the piezoelectric layer 202 and is electrically connected to the upper surface of the bottom electrode 208. Alternatively, the at least one conductive hole can also pass through the first dielectric layer 204, the piezoelectric layer 202 and the bottom electrode 208 and be electrically connected to the device silicon layer 201.

[0112] In addition, the projection of the above-mentioned conductive hole in the vertical direction can overlap with the sealing ring 205, or be located inside the annular area of ​​the sealing ring 205, or be located outside the annular area of ​​the sealing ring 205. The embodiment of the present application does not limit the setting position of the conductive hole.

[0113] It can be seen from the above embodiments that by planarizing the surface of the dielectric layer covering the top electrode, the bonding characteristics between the cap wafer and the device wafer are improved, thereby ensuring a good bonding effect.

[0114] The present application has been described above in conjunction with specific embodiments. However, those skilled in the art should understand that these descriptions are merely illustrative and are not intended to limit the scope of protection of the present application. Those skilled in the art may make various modifications and variations to the present application based on the spirit and principles of the present application, and such modifications and variations are also within the scope of the present application.

Claims

1. A piezoelectric MEMS resonator, comprising a cap wafer and a device wafer, characterized in that: The cap wafer comprises a cap layer, The device wafer comprises: substrate layer; A resonant cavity disposed on the substrate layer; A device silicon layer located on the upper side of the resonant cavity; a piezoelectric layer located on the upper side of the device silicon layer; a top electrode located on an upper side of the piezoelectric layer; and a first dielectric layer located on the upper side of the top electrode and covering the top electrode, The first dielectric layer is bonded to the cap layer, a projection of at least a portion of the first dielectric layer bonded to the cap layer in the vertical direction overlaps with a projection of the top electrode in the vertical direction, and an upper surface of at least a portion of the first dielectric layer bonded to the cap layer is in the same plane.

2. The resonator according to claim 1, characterized in that The upper surface of the first dielectric layer is flat.

3. The resonator according to claim 1, characterized in that The device wafer further includes at least one first extraction electrode electrically connected to the top electrode, At least a portion of a projection of the top electrode in the vertical direction does not overlap with a projection of the cap layer in the vertical direction, The at least one first extraction electrode passes through the first dielectric layer from a portion of the top electrode that does not overlap with the cap layer and covers a region of the upper surface of the first dielectric layer that is not covered by the cap layer.

4. The resonator according to claim 1, characterized in that The device wafer further includes a bottom electrode made of a metal material located at the lower side of the piezoelectric layer and at least one second extraction electrode electrically connected to the bottom electrode. At least a portion of the projection of the bottom electrode in the vertical direction does not overlap with the projection of the cap layer in the vertical direction, The at least one second extraction electrode passes through the piezoelectric layer and the first dielectric layer from a portion of the bottom electrode that does not overlap with the cap layer and covers an upper surface of the first dielectric layer.

5. The resonator according to claim 1, characterized in that The device silicon layer is a doped silicon layer, and the doping concentration of the device silicon layer is 10 19 cm -3 above.

6. The resonator according to claim 1, characterized in that The cap layer and the first dielectric layer form an upper cavity, The resonator has a groove penetrating the upper cavity and the resonant cavity.

7. The resonator according to claim 6, characterized in that The piezoelectric layer or the first dielectric layer and the end surface of the device silicon layer on the groove side are located in different planes.

8. The resonator according to claim 1, characterized in that The device wafer further includes a silicon oxide layer located between the device silicon layer and the substrate layer. The portion of the silicon oxide layer corresponding to the resonant cavity is located on the lower surface of the device silicon layer, or, A portion of the silicon oxide layer corresponding to the resonant cavity is formed on an upper surface of the substrate layer.

9. The resonator according to claim 1, characterized in that The resonator also has a second dielectric layer located between the first dielectric layer and the top electrode.

10. The resonator according to claim 1 or 9, characterized in that: The first dielectric layer located in the active region of the device is removed.

11. The resonator according to claim 1 or 9, characterized in that: The first dielectric layer located in the active area of ​​the device is patterned.

12. The resonator according to claim 1, characterized in that The device wafer further includes a sealing ring, the first dielectric layer is bonded to the cap layer via the sealing ring, and the sealing ring is formed by at least one layer of metal material and / or dielectric material.

13. The resonator according to claim 12, characterized in that A portion of the first dielectric layer bonded to the cap layer is thicker than a portion of the first dielectric layer not bonded to the cap layer.

14. The resonator according to claim 12, characterized in that The cap wafer further includes a metal layer, the cap layer is bonded to the sealing ring through the metal layer, and the metal layer is formed by at least one layer of metal material.

15. The resonator according to claim 14, characterized in that The cap wafer further includes a first insulating layer covering the outer surface of the cap layer. The metal layer is formed on The lower surface of the first insulating layer.

16. The resonator according to claim 4, characterized in that The device wafer further includes a second insulating layer located on the lower surface of the bottom electrode.

17. The resonator according to claim 1 or 5, characterized in that The device wafer further includes a second extraction electrode electrically connected to the upper surface of the device silicon layer. At least a portion of a projection of the device silicon layer in the vertical direction does not overlap with a projection of the cap layer in the vertical direction, The second extraction electrode passes through the piezoelectric layer and the first dielectric layer from a portion of the device silicon layer that does not overlap with the cap layer and covers a region of the upper surface of the first dielectric layer that is not covered by the cap layer.

18. The resonator according to claim 17, characterized in that The device silicon layer further includes a trench-shaped isolation layer penetrating the device silicon layer, wherein the isolation layer extends from a portion of the device silicon layer located in the device active region to a portion corresponding to the second extraction electrode.

19. The resonator according to claim 18, characterized in that The isolation layer includes a third insulating layer filled in the trench.

20. The resonator according to claim 19, characterized in that The isolation layer further includes a fourth insulating layer located on the upper surface of the device silicon layer, The fourth insulating layer is located on a portion of the upper surface of the device silicon layer other than that covered by the second extraction electrode and the piezoelectric layer.

21. The resonator according to claim 12, characterized in that The sealing ring is electrically connected to the device silicon layer through at least one conductive hole.

22. The resonator according to claim 4, characterized in that The device wafer further includes a sealing ring, the first dielectric layer is bonded to the cap layer via the sealing ring, and the sealing ring is formed by at least one layer of metal material and / or dielectric material. The sealing ring is electrically connected to the bottom electrode through at least one conductive hole.

23. An electronic component, characterized in that: The electronic component comprises the resonator according to any one of claims 1 to 22.

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