Semiconductor device and manufacturing method therefor, transistor and electronic device
By alternately stacking insulating layers and metal layers in 3D memory to form a multi-layer transistor structure, etching and oxidation technology are used to solve the problems of increased storage density and cost, and efficient storage density and low-cost 3D memory production are achieved.
Patent Information
- Application Number
- PCT/CN2024/122804
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-10-09
- Filing Date
- 2024-09-30
- Publication Date
- 2025-09-04
AI Technical Summary
The storage density and production cost of existing 3D memories are difficult to further increase.
By alternately stacking insulating layers and metal layers on the substrate, forming a stacked structure, and forming transistors arranged in a multi-layer array in the structure, including a first isolation layer, a second isolation layer, a semiconductor layer, a gate dielectric layer and a gate electrode, an etching technology is used to form a through hole and an oxide metal layer to form an isolation layer, deposit semiconductor and gate dielectric materials, and finally a gate and a bit line are formed.
The storage density of 3D memory is increased, the production cost per unit GB is reduced, and the driving current of the device is increased.
Smart Images
Figure CN2024122804_04092025_PF_FP_ABST
Abstract
Description
Semiconductor device and manufacturing method thereof, transistor, and electronic device
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on October 9, 2023, with application number 202311303627.X and invention name “Device structure, preparation method and electronic device of semiconductor device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field
[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a transistor, and an electronic device. Background Art
[0004] 3D (3D) memory is an emerging form of memory. It is a semiconductor memory that accumulates layers based on stacking technology. Compared with planar memory, 3D memory has increased storage density, thereby reducing the production cost per GB (Gigabyte).
[0005] Summary of the Invention
[0006] According to various embodiments of the present disclosure, a semiconductor device and a method for manufacturing the same, a transistor, and an electronic device are provided.
[0007] According to some embodiments, the present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following steps:
[0008] Alternating multiple insulating layers and metal layers on a substrate to form a stacked structure;
[0009] A plurality of transistors arranged in a multilayer array are formed in the stacked structure; the transistors include a first isolation layer, a second isolation layer, a semiconductor layer, a gate dielectric layer and a gate; wherein the first isolation layer and the second isolation layer are arranged opposite to each other and spaced apart in a first direction parallel to the substrate; the semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer respectively covering two side walls of the first isolation layer opposite to each other in the first direction, and a third sub-semiconductor layer and a fourth sub-semiconductor layer respectively covering two side walls of the second isolation layer opposite to each other in the first direction; the gate dielectric layer covers the semiconductor layer; and the gate covers the gate dielectric layer.
[0010] According to some embodiments, forming a plurality of transistors arranged in a multilayer array in a stacked structure includes the following steps:
[0011] Etching the stacked structure in a direction perpendicular to the substrate to form a plurality of through holes arranged in an array;
[0012] Based on each through hole, oxidizing the metal layer exposed in the through hole to form a plurality of first isolation layers and a plurality of second isolation layers alternately arranged in a first direction;
[0013] forming a first sub-semiconductor layer and a second sub-semiconductor layer on two side walls of the first isolation layer that are opposite to each other in the first direction, and forming a third sub-semiconductor layer and a fourth sub-semiconductor layer on two side walls of the second isolation layer that are opposite to each other in the first direction;
[0014] depositing a gate dielectric material on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer, and the fourth sub-semiconductor layer to form a gate dielectric layer;
[0015] A gate is formed on the gate dielectric layer.
[0016] According to some embodiments, the plurality of through holes are arranged in a row along a first direction. Before oxidizing the metal layer exposed in each through hole to form the plurality of first isolation layers and the plurality of second isolation layers, the preparation method further includes: etching the metal layer based on the through holes to thin the metal layer between adjacent through holes in any row of through holes.
[0017] Accordingly, the metal layer exposed in the through hole by oxidation includes the metal layer after oxidation and thinning.
[0018] According to some embodiments, the metal layer is etched using a wet etching process.
[0019] According to some embodiments, the oxidation of the metal layer exposed in the through-hole based on each through-hole to correspondingly form a plurality of first isolation layers and a plurality of second isolation layers includes: oxidizing the metal layer exposed in the through-hole to form a metal oxide layer; etching the metal oxide layer along a second direction parallel to the substrate based on the through-hole to expose metal layers opposite in the second direction in the through-hole; wherein the metal oxide layers retained in the through-hole and opposite in the first direction constitute the first isolation layer and the second isolation layer respectively; and the second direction intersects with the first direction.
[0020] According to some embodiments, the preparation method further includes: forming a bit line and a first electrode of a capacitor connected to the semiconductor layer based on the metal layers opposite to each other in the second direction exposed in the through hole; or forming a source / drain electrode of a transistor based on the metal layers opposite to each other in the second direction exposed in the through hole.
[0021] According to some embodiments, the steps of forming a first sub-semiconductor layer and a second sub-semiconductor layer on two side walls of the first isolation layer that are opposite to each other in the first direction, forming a third sub-semiconductor layer and a fourth sub-semiconductor layer on two side walls of the second isolation layer that are opposite to each other in the first direction, and depositing a gate dielectric material on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer, and the fourth sub-semiconductor layer to form a gate dielectric layer include the following steps:
[0022] Depositing semiconductor material and gate dielectric material in sequence in each through hole;
[0023] The gate dielectric material and the semiconductor material covering the insulating layer in the through hole are etched away to expose the insulating layer, and the semiconductor material remaining on the first isolation layer constitutes the first sub-semiconductor layer and the second sub-semiconductor layer, respectively, the semiconductor material remaining on the second isolation layer constitutes the third sub-semiconductor layer and the fourth sub-semiconductor layer, respectively, and the gate dielectric material remaining on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer and the fourth sub-semiconductor layer constitutes the gate dielectric layer.
[0024] According to some embodiments, after the etching removes the gate dielectric material and semiconductor material covering the insulating layer in the through hole to expose the insulating layer, redundant semiconductor material and redundant gate dielectric material remain on the inner sidewalls of the through hole opposite to each other in the second direction parallel to the substrate. A row of the plurality of through holes includes alternating first and second through holes. Forming a gate on the gate dielectric layer includes: forming a gate material layer covering the gate dielectric layer, redundant gate dielectric material, and insulating layer in each through hole; etching the stacked structure along a second direction parallel to the substrate and perpendicular to the substrate based on the second through hole, while simultaneously removing the gate material layer, redundant gate dielectric material, and redundant semiconductor material on the opposite sidewalls of the second through hole in the second direction, forming a trench extending in the second direction, and allowing the gate material layer remaining in the first through hole and on the opposite sidewalls of the second through hole in the first direction to constitute the gate of the corresponding transistor and a word line connected to the gate.
[0025] According to some embodiments, the preparation method further includes: filling the first through hole and the trench with an isolation material.
[0026] According to some embodiments, the semiconductor material includes a metal oxide semiconductor material.
[0027] According to some embodiments, before etching the stacked structure in a direction perpendicular to the substrate to form a plurality of through holes arranged in an array, the preparation method further includes: depositing a protective layer on the surface of the stacked structure; removing the protective layer on the surface of a specified area, wherein the specified area is related to the position of the transistor; wherein the through hole is formed in the specified area.
[0028] According to some embodiments, the preparation method further includes: preparing capacitors on one side of each transistor in the stacked structure to form a semiconductor device; wherein the first electrodes of the capacitors are correspondingly connected to the semiconductor layers of the transistors.
[0029] According to some embodiments, another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a substrate and a stacked structure; the stacked structure is located on the substrate; the stacked structure includes: a plurality of memory cell arrays stacked in a direction perpendicular to the substrate and a plurality of bit lines extending in a first direction parallel to the substrate, each layer of the memory cell array includes a plurality of memory cells arranged in an array, and each bit line is connected to at least one column of memory cells arranged in the first direction; wherein each memory cell includes a transistor. The transistor includes: a first isolation layer, a second isolation layer, a semiconductor layer, a gate dielectric layer, and a gate; wherein the first isolation layer and the second isolation layer are arranged opposite to each other and spaced apart in the first direction parallel to the substrate; the semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer respectively covering two side walls of the first isolation layer opposite to each other in the first direction, and a third sub-semiconductor layer and a fourth sub-semiconductor layer respectively covering two side walls of the second isolation layer opposite to each other in the first direction; the gate dielectric layer covers the semiconductor layer; and the gate covers the gate dielectric layer.
[0030] According to some embodiments, the memory cell further includes a capacitor including a first electrode connected to an end of the semiconductor layer in the memory cell that is away from the bit line.
[0031] According to some embodiments, the stacked structure further comprises: a plurality of word lines. The word lines extend in a direction perpendicular to the substrate. In a row of memory cells arranged perpendicular to the substrate, the gates of the transistors are connected to the same word line.
[0032] In some embodiments, two columns of memory cells arranged along a first direction and adjacent to each other along a second direction parallel to the substrate share a common bit line, wherein the first direction intersects the second direction.
[0033] According to some embodiments, the present disclosure provides a transistor in another aspect. The transistor includes: a first isolation layer, a second isolation layer, a semiconductor layer, a gate dielectric layer, and a gate; wherein the first isolation layer and the second isolation layer are arranged opposite to each other and spaced apart in a first direction parallel to the substrate; the semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer respectively covering two side walls of the first isolation layer that are opposite to each other in the first direction, and a third sub-semiconductor layer and a fourth sub-semiconductor layer respectively covering two side walls of the second isolation layer that are opposite to each other in the first direction; the gate dielectric layer covers the semiconductor layer; and the gate covers the gate dielectric layer.
[0034] According to some embodiments, the semiconductor layer is made of a metal oxide semiconductor material.
[0035] According to some embodiments, another aspect of the present disclosure provides an electronic device, which includes a memory, and the memory includes: a semiconductor device prepared according to the method for preparing a semiconductor device as described in any of the above embodiments; or, a semiconductor device as described in any of the above embodiments; or, a transistor as described in any of the above embodiments.
[0036] In some embodiments, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal.
[0037] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.
[0039] FIG1 is a schematic diagram of a semiconductor device and a transistor provided by an exemplary embodiment of the present disclosure;
[0040] FIG2 is a flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;
[0041] 3 is a schematic diagram of a structure obtained after forming a stacked structure in a method for preparing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0042] FIG4 is a flow chart of step S202 in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0043] FIG5 is a flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;
[0044] FIG6 is a schematic diagram of a structure obtained after forming a protective layer in a method for preparing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0045] 7 is a schematic diagram of a structure obtained after patterning a designated area in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0046] FIG8 is a schematic diagram of a structure obtained after forming a through hole in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0047] FIG9 is a schematic diagram of a structure obtained after thinning a metal layer in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0048] FIG10 is a schematic diagram of a structure obtained after forming a metal oxide layer in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0049] FIG11 is a schematic diagram of a structure obtained after forming a metal oxide semiconductor material in a method for preparing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0050] FIG12 is a schematic diagram of a structure obtained after forming a gate dielectric material in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0051] 13 is a schematic diagram of a structure obtained after etching a protruding portion in a through hole until the insulating layer is exposed in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;
[0052] FIG14 is a schematic diagram of a structure obtained after forming a gate material layer in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0053] 15 is a schematic diagram of a structure obtained after trenches are formed in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;
[0054] FIG16 is a schematic diagram of a structure obtained after filling with an isolation material in a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0055] FIG. 17 is a schematic diagram of a structure obtained after removing a residual protective layer in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION
[0056] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0057] An embodiment of the present disclosure provides a semiconductor device. Referring to FIG1 , FIG1 (A) shows the structure of the semiconductor device. The semiconductor device includes a substrate 100 and a stacked structure 101. The stacked structure 101 is located on the substrate 100. The stacked structure 101 includes: a multi-layer memory cell array stacked in a direction perpendicular to the substrate and a plurality of bit lines 102 extending in a first direction parallel to the substrate. The first direction is parallel to the upper surface of the substrate 100. Each layer of the memory cell array includes a plurality of memory cells 103 arranged in an array. Each bit line 102 is connected to at least one column of the memory cells 103 arranged in the first direction. Each memory cell 103 includes a transistor 104. Taking the enlarged top view of the memory cell 103 in part (A) of FIG1 as an example, referring to FIG1 (B), the transistor 104 in the memory cell 103 includes: a first isolation layer 106, a second isolation layer 107, a semiconductor layer 108, a gate dielectric layer 109, and a gate 110.
[0058] For example, the first isolation layer 106 and the second isolation layer 107 are arranged opposite to each other and spaced apart in a first direction parallel to the substrate 100. For example, there is a through hole 105 between the first isolation layer 106 and the second isolation layer 107, and the first isolation layer 106 and the second isolation layer 107 are respectively located on two opposite sidewalls of the through hole 105 in the first direction.
[0059] For example, the semiconductor layer 108 includes a first sub-semiconductor layer 111 and a second sub-semiconductor layer 112, each covering two side walls of the first isolation layer 106 that are opposite to each other in the first direction, and a third sub-semiconductor layer 113 and a fourth sub-semiconductor layer 114, each covering two side walls of the second isolation layer 107 that are opposite to each other in the first direction. The first sub-semiconductor layer 111, the second sub-semiconductor layer 112, the third sub-semiconductor layer 113, and the fourth sub-semiconductor layer 114 can be used to form a first channel, a second channel, a third channel, and a fourth channel of a transistor, respectively.
[0060] Illustratively, the gate dielectric layer 109 covers the semiconductor layer 108 ; and the gate 110 covers the gate dielectric layer 109 .
[0061] It should be noted that, in the process of constructing the transistor 104, since the side walls of the through hole 105 other than the side walls where the first isolation layer 106 and the second isolation layer 107 are located (i.e., the side walls opposite to each other in the second direction parallel to the substrate 100) are embedded in the stacked structure 101, this part cannot be observed in the enlarged top view (B) of Figure 1, and only the side walls where the first isolation layer 106 and the second isolation layer 107 are located in the through hole 105 can be observed.
[0062] In some embodiments, the memory cell further includes a capacitor 115. Capacitor 115 is connected to an end of transistor 104 in memory cell 103 that is remote from bit line 102. For example, capacitor 115 includes a first electrode (not shown in FIG. 1 ) connected to an end of semiconductor layer 108 in the memory cell that is remote from bit line 102, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer and disposed opposite the first electrode.
[0063] In some embodiments, the stacked structure 101 further includes a plurality of word lines (referring to the location of the gate 110). The word lines extend perpendicular to the substrate 100. In a row of memory cells 103 arranged perpendicular to the substrate 100, the gates 104 of each transistor 104 are connected to the same word line.
[0064] For example, each gate 104 in a row of memory cells 103 arranged perpendicular to the substrate 100 is integrally structured with the word line connected thereto.
[0065] For example, the gate 110 serves as a control switch of the transistor 104 and can be turned on in response to a control signal of a word line connected thereto. The bit line 102 serves as a data signal line of the transistor 104 and can write and / or read data to the transistor 104 .
[0066] For example, two columns of memory cells 103 arranged along a first direction and adjacent to each other along a second direction parallel to the substrate 100 share a bit line 102. The first direction intersects with the second direction, for example, is orthogonal.
[0067] In some examples, the material of the semiconductor layer 108 in the transistor 104 is a metal oxide semiconductor material. The material of the metal oxide semiconductor includes but is not limited to indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor 104 is small (for example, the leakage current can be less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic storage. It should be noted that the material of the metal oxide semiconductor can also be ITO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Gay Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a 、Sn x In y Zn z O a、 Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a 、Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO, IAZO, IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide), IZO x As long as the leakage current of the transistor 104 can meet the requirements, the specific adjustment can be made according to the actual situation.
[0068] The embodiments of the present disclosure also provide a method for preparing a semiconductor device, which is used to prepare the semiconductor devices in some of the above embodiments.
[0069] Optionally, the method for preparing the semiconductor device is mainly used in the preparation process of a 3D memory.
[0070] In combination with the above introduction to the semiconductor device, FIG2 is a flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure. As shown in FIG2 , the method includes the following steps.
[0071] Step 201 : alternately stacking a plurality of insulating layers and metal layers on a substrate to form a stacked structure.
[0072] For example, the bottommost insulating layer is in contact with the substrate. By stacking transistors on the substrate, the device area can be reduced and the device density can be increased, making 3D memory possible.
[0073] Please refer to Figure 3 for understanding. Figure (A1) in Figure 3 takes a stacked structure with three insulating layers and three metal layers as an example, showing a first insulating layer 301, a first metal layer 302, a second insulating layer 303, a second metal layer 304, a third insulating layer 305, and a third metal layer 306 stacked in sequence on a substrate 100. Optionally, the direction parallel to the substrate 100 is the horizontal direction, and the first direction is the bit line extension direction. Figure (A2) in Figure 3 shows a two-dimensional cross-sectional view of the stacked structure observed along the first direction.
[0074] It should be noted that FIG3 is only a schematic diagram of a multi-layer stacked structure. In some embodiments, the specific number of stacked thin film layers is determined based on the device design.
[0075] Step 202: Form multiple transistors arranged in a multilayer array within the stacked structure. The transistors include a first isolation layer, a second isolation layer, a semiconductor layer, a gate dielectric layer, and a gate electrode. The first isolation layer and the second isolation layer are disposed opposite each other and spaced apart in a first direction parallel to the substrate. The semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer, respectively covering two opposite side walls of the first isolation layer in the first direction, and a third sub-semiconductor layer and a fourth sub-semiconductor layer, respectively covering two opposite side walls of the second isolation layer in the first direction. The gate dielectric layer covers the semiconductor layer, and the gate electrode covers the gate dielectric layer.
[0076] Please understand in conjunction with FIG. 1 , FIG. 1 (B) shows a top-view structure of the transistor 104 observed along a direction perpendicular to the substrate.
[0077] In some embodiments, a through hole 105 is provided between the first isolation layer 106 and the second isolation layer 107 . The first isolation layer 106 and the second isolation layer 107 are respectively located on two opposite sidewalls of the through hole 105 in the first direction.
[0078] For example, the first isolation layer 106 and the second isolation layer 107 can be consistent in structure and material. Based on the through hole 105, each isolation layer has two inner and outer sidewalls; that is, semiconductor layers (e.g., the first sub-semiconductor layer 111, the second sub-semiconductor layer 112, the third sub-semiconductor layer 113, and the fourth sub-semiconductor layer 114) can be formed on the inner and outer sidewalls of the isolation layer, so that corresponding channels can be formed through each sub-semiconductor layer. Furthermore, the subsequent gate dielectric layer 109 and the gate 110 will also be sequentially covered and formed on the sidewalls of the semiconductor layer (e.g., the first sub-semiconductor layer 111, the second sub-semiconductor layer 112, the third sub-semiconductor layer 113, and the fourth sub-semiconductor layer 114).
[0079] In addition, the second sub-semiconductor layer 112 and the third sub-semiconductor layer 113 in the above-mentioned transistor 104 can be connected and closed in the through hole 105, so that they are ringed between the inner wall of the corresponding through hole 105 and the outer wall of the gate dielectric layer 109, and their corresponding gate dielectric layer 109 is ringed on the outer wall of the corresponding gate 110.
[0080] The fabrication method provided by the disclosed embodiments can produce a semiconductor device with multiple channels in a stacked configuration, which can be a 3D memory device, effectively increasing the memory's drive current. Furthermore, the three-dimensional stacking of semiconductor devices increases the storage density of the 3D memory device and reduces the production cost per GB.
[0081] In some embodiments of the present disclosure, referring to FIG. 4 , forming a plurality of transistors arranged in a multi-layer array in a stacked structure in step S202 may include the following steps S410 to S450 .
[0082] In step S410 , the stacked structure is etched in a direction perpendicular to the substrate to form a plurality of through holes arranged in an array.
[0083] In step S420 , based on each through hole, the metal layer exposed in the through hole is oxidized to form a plurality of first isolation layers and a plurality of second isolation layers alternately arranged in a first direction.
[0084] In step S430 , a first sub-semiconductor layer and a second sub-semiconductor layer are respectively formed on two opposite sidewalls of the first isolation layer in the first direction, and a third sub-semiconductor layer and a fourth sub-semiconductor layer are respectively formed on two opposite sidewalls of the second isolation layer in the first direction.
[0085] Step S440 : depositing a gate dielectric material on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer, and the fourth sub-semiconductor layer to form a gate dielectric layer.
[0086] Step S450: forming a gate on the gate dielectric layer.
[0087] In some embodiments, referring to FIG5 , a plurality of through holes are arranged in a first direction. Before step S420 oxidizing the metal layer exposed in each through hole to form a plurality of first isolation layers and a plurality of second isolation layers, the preparation method further includes step S415 .
[0088] Step S415 , etching the metal layer based on the through holes to thin the metal layer between adjacent through holes in any column of through holes.
[0089] Accordingly, the oxidation of the metal layer exposed in the through hole in step S420 includes oxidizing the thinned metal layer.
[0090] Optionally, the metal layer is etched using a wet etching process.
[0091] In some embodiments of the present disclosure, please continue to refer to FIG. 5 , step S420 oxidizes the metal layer exposed in each through hole based on each through hole to correspondingly form multiple first isolation layers and multiple second isolation layers, which may include step S421 and step S422 .
[0092] Step S421 , oxidizing the metal layer exposed in the through hole to form a metal oxide layer.
[0093] Step S422: Based on the through hole, the metal oxide layer is etched along a second direction parallel to the substrate to expose the metal layer opposite in the second direction in the through hole; wherein the metal oxide layers retained in the through hole and opposite in the first direction constitute a first isolation layer and a second isolation layer respectively; the second direction intersects with the first direction.
[0094] It should be added that, in some embodiments, the preparation method further includes: forming a bit line and a first electrode of the capacitor connected to the semiconductor layer based on the metal layers exposed in the through hole and relative to each other in the second direction; or, forming a source / drain electrode of the transistor based on the metal layers exposed in the through hole and relative to each other in the second direction.
[0095] In some embodiments, please continue to refer to Figure 5. Step S430 forms a first sub-semiconductor layer and a second sub-semiconductor layer on two side walls of the first isolation layer that are opposite to each other in the first direction, and forms a third sub-semiconductor layer and a fourth sub-semiconductor layer on two side walls of the second isolation layer that are opposite to each other in the first direction, and step S440 deposits a gate dielectric material on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer and the fourth sub-semiconductor layer to form a gate dielectric layer, including the following steps S431 and S441.
[0096] In step S431 , semiconductor material and gate dielectric material are sequentially deposited in each through hole.
[0097] Optionally, the semiconductor material includes a metal oxide semiconductor material.
[0098] In step S441, the gate dielectric material and the semiconductor material covering the insulating layer in the through hole are etched away to expose the insulating layer, and the semiconductor material remaining on the first isolation layer constitutes the first sub-semiconductor layer and the second sub-semiconductor layer respectively, the semiconductor material remaining on the second isolation layer constitutes the third sub-semiconductor layer and the fourth sub-semiconductor layer respectively, and the gate dielectric material remaining on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer and the fourth sub-semiconductor layer constitutes the gate dielectric layer.
[0099] It should be noted that in some embodiments, after step S441 etches away the gate dielectric material and semiconductor material covering the insulating layer within the through-hole to expose the insulating layer, redundant semiconductor material and redundant gate dielectric material remain on the inner sidewalls of the through-hole opposite to each other in the second direction parallel to the substrate. A row of the plurality of through-holes includes alternating first and second through-holes. Continuing with FIG. 5 , step S450 of forming a gate on the gate dielectric layer may include the following steps S451 and S452.
[0100] Step S451 , forming a gate material layer in each through hole to cover the gate dielectric layer, the redundant gate dielectric material and the insulating layer.
[0101] In step S452, based on the second through hole, the stacked structure is etched along a second direction parallel to the substrate and a direction perpendicular to the substrate, and the gate material layer, redundant gate dielectric material, and redundant semiconductor material on the opposite side walls of the second through hole in the second direction are removed to form a trench extending along the second direction, and the gate material layer retained in the first through hole and on the opposite side walls of the second through hole in the first direction constitutes the gate of the corresponding transistor and the word line connected to the gate.
[0102] In some embodiments, please continue to refer to FIG. 5 , the preparation method further includes step S453 .
[0103] Step S453: filling the first through hole and the trench with an isolation material.
[0104] In some embodiments, please continue to refer to FIG. 5 , before step S410 of etching the stacked structure in a direction perpendicular to the substrate to form a plurality of through holes arranged in an array, the preparation method further includes steps S401 and S402 .
[0105] Step S401: depositing a protective layer on the surface of the stacked structure.
[0106] Step S402 : removing the protective layer on the surface of a designated area, where the designated area is related to the position of the transistor.
[0107] Accordingly, the through hole in step S410 is formed in the designated area.
[0108] After step S453, the preparation method further includes step S454: removing the remaining protective layer on the surface of the laminated structure.
[0109] In some embodiments, please continue to refer to FIG. 5 , the preparation method further includes step S460 .
[0110] In step S460 , capacitors are respectively prepared on one side of each transistor in the stacked structure to form a semiconductor device; wherein the first electrodes of the capacitors are correspondingly connected to the semiconductor layers of the transistors.
[0111] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.
[0112] In order to more clearly illustrate the method for manufacturing the semiconductor device in the above embodiments, the following embodiments describe in detail a method for manufacturing a semiconductor device with reference to FIG. 5 to FIG. 15 .
[0113] Step 201 : alternately stacking a plurality of insulating layers and metal layers on a substrate to form a stacked structure.
[0114] Here, alternating stacking means stacking an insulating layer first and then a metal layer on the substrate, with the metal layers and insulating layers stacked alternately so that a metal layer is stacked between every two insulating layers. Optionally, the top layer of the stacked structure is a metal layer.
[0115] In some embodiments, based on oxidation characteristics, the metal layer can be formed of easily oxidized metals such as Ti (titanium), Mo (molybdenum), and Ta (tantalum).
[0116] With reference to FIG3 , FIG3 (A1) shows a three-dimensional structure diagram after a first insulating layer 301, a first metal layer 302, a second insulating layer 303, a second metal layer 304, a third insulating layer 305, and a third metal layer 306 are sequentially stacked on a substrate 100. Optionally, the first direction is the direction in which the bit lines extend. FIG3 (A2) shows a two-dimensional cross-sectional schematic diagram of the structure shown in (A1) along the first direction.
[0117] Step 401: depositing a protective layer on the surface of the stacked structure.
[0118] In some embodiments, the material of the protective layer may be Nitride (titanium nitride). The material of the protective layer may also be other substances that do not react with the metal stack. The present disclosure does not limit the selection of the protective layer.
[0119] In some embodiments, the surface of the stacked structure is covered with a protective layer by an ALD (Atomic Layer Deposition) process or a chemical vapor deposition technique.
[0120] 6 , FIG6 (A1) shows a three-dimensional structural diagram of a stacked structure deposited with a protective layer 300. FIG6 (A2) shows a two-dimensional cross-sectional schematic diagram of the structure shown in FIG6 (A1) observed along a first direction.
[0121] Step 402 : removing the protective layer on the surface of a designated area, where the designated area is related to the position of the transistor.
[0122] Here, the designated area is used to prepare a transistor, and the area is in the shape of a strip, the width of the strip matches the width of the transistor, and the length of the strip is consistent with the width of the stacked structure.
[0123] In some embodiments, based on a photolithography process, the protective layer is removed from the surface of designated areas according to the required size of the transistor. The number of designated areas is determined based on fabrication requirements and is not limited in the present disclosure.
[0124] 7 , FIG7 (A1) shows a three-dimensional structural diagram of the laminated structure without the surface protection layer in the designated area 600. FIG7 (A2) shows a two-dimensional cross-sectional schematic diagram of the structure shown in FIG7 (A1) observed along a first direction.
[0125] Step 410 , etching the stacked structure in a direction perpendicular to the substrate to form a plurality of through holes arranged in an array.
[0126] Optionally, based on a dry etching process, the stacked structure is etched in a designated area to obtain a plurality of through holes with the same width from top to bottom.
[0127] In some embodiments, a size of the through hole in a direction perpendicular to the substrate matches a size of the transistor.
[0128] With reference to Figure 8, Figure (A1) of Figure 8 shows a three-dimensional schematic diagram of a stacked structure with the same width of the through hole 700. Optionally, the vertical direction is the direction in which the word line extends, that is, the direction perpendicular to the substrate. Figure (A2) of Figure 8 shows a two-dimensional top view of the structure shown in (A1) observed along the vertical direction. In the process of constructing the transistor, due to the presence of the protective layer 300, the side walls of the through hole 700 other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure. Therefore, this part cannot be observed in the top view (Figure (A2) of Figure 8), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.
[0129] Step 415 , etching the metal layer based on the through holes to thin the metal layer between adjacent through holes in any column of through holes.
[0130] Optionally, the metal layer in the stacked structure is wet-etched based on the through-holes to narrow the metal layer exposed in the plurality of through-holes.
[0131] Based on the isotropy of wet etching, the etching width of the metal layer along the second direction parallel to the substrate can be close to the etching thickness of the metal layer along the first direction parallel to the substrate, thereby making the metal layers in the stacked structure uniformly narrower.
[0132] It can be understood that after the etching operation is performed, a through-hole structure for forming a transistor can be observed along the vertical direction.
[0133] With reference to Figure 9, Figure (A1) of Figure 9 shows a three-dimensional structural diagram after etching the stacked structure in the vertical direction. Figure (A2) of Figure 9 shows a two-dimensional top view of the structure shown in Figure (A1) of Figure 9 observed along the vertical direction. In the process of constructing the transistor, since the side walls of the through hole other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, this part cannot be observed in the top view (Figure (A2) of Figure 9), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed. As can be seen from Figure (A2) of Figure 9, the thickness of the metal layer 801 in the through hole (for example, the dimension along the first direction) is less than the thickness of the insulating layer 802 (for example, the dimension along the first direction).
[0134] In step 420, based on each through hole, the metal layer exposed in the through hole is oxidized to form a plurality of first isolation layers and a plurality of second isolation layers arranged alternately in a first direction; that is, the stacked structure is oxidized so that the metal layer exposed on the inner wall of the through hole is oxidized to form a first isolation layer and a second isolation layer.
[0135] Here, the vias are exposed outside the protective layer. Therefore, oxidation can transform the metal layer exposed by the vias into metal oxide, thereby forming the first and second isolation layers. Metal oxide is an insulator that can isolate the semiconductor layer materials subsequently deposited on both sides to form a multi-channel semiconductor device.
[0136] For example, based on the anodizing process, the electrochemical principle can be used to implement oxidation treatment of the metal layer to generate metal oxide.
[0137] In some embodiments, Ti (titanium), Mo (molybdenum) or Ta (tantalum) can be selected based on the metal in the metal layer. Accordingly, the oxide produced after oxidation can be TiO x (titanium oxide), MoO x (Molybdenum oxide) or TaO x (Tantalum oxide), etc. These metal oxides can be used as insulators to play an insulating supporting role.
[0138] With reference to FIG10 , FIG10 (A1) shows a three-dimensional structural diagram of the stacked structure after the metal layer is oxidized to obtain the metal oxide layer 900. FIG10 (A2) shows a two-dimensional top view of the structure shown in FIG10 (A1) observed along the vertical direction. In the process of constructing the transistor, since the sidewalls of the through hole other than the first isolation layer and the second isolation layer are embedded in the stacked structure, these parts cannot be observed in the top view shown in FIG10 (A2). Only the sidewalls of the through hole where the first isolation layer and the second isolation layer are located can be observed.
[0139] In addition, after the oxidation step, an etching process is performed before depositing the channel material to etch the metal oxide layer after the metal layer in the through hole is oxidized, so that the side wall of the through hole except the first isolation layer and the second isolation layer in the through hole exposes the metal layer. One side of the exposed metal layer can be used to form a bit line or a first source / drain electrode connecting the bit line, and the other side can be used to form a first electrode of a capacitor or a second source / drain electrode connected to the first electrode in the capacitor. The embodiments of the present disclosure are not limited to this.
[0140] Optionally, based on the metal layers exposed in the through hole and opposite to each other in the second direction, a bit line and a first electrode of the capacitor that are in contact with the semiconductor layer are formed respectively, which helps to simplify the manufacturing process.
[0141] Optionally, based on the metal layers exposed in the through hole and opposite to each other in the second direction, first source / drain electrodes and second source / drain electrodes of the transistor are formed respectively, which is conducive to achieving good electrical connection between the transistor and the bit line and the capacitor through the metal layer.
[0142] In step 430, a first sub-semiconductor layer and a second sub-semiconductor layer are respectively formed on two side walls of the first isolation layer that are opposite to each other in the first direction, and a third sub-semiconductor layer and a fourth sub-semiconductor layer are respectively formed on two side walls of the second isolation layer that are opposite to each other in the first direction, so as to form the first channel, the second channel, the third channel and the fourth channel of the transistor respectively.
[0143] In some embodiments, the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer and the fourth sub-semiconductor layer are generally made of metal oxide semiconductor materials with high electrical stability to maintain the electrical properties of the device during the stacking process. For example, they can be prepared using IGZO (Indium Gallium Zinc Oxide) semiconductor materials.
[0144] In some embodiments, semiconductor material is deposited on the surface of the through hole by using an ALD (Atomic Layer Deposition) process or a chemical vapor deposition technique.
[0145] With reference to FIG11 , FIG11 (A1) shows a three-dimensional structural diagram of the stacked structure after depositing the metal oxide semiconductor material 1000. FIG11 (A2) shows a two-dimensional top view of the structure shown in FIG11 (A1) observed along the vertical direction. FIG11 (A3) is an enlarged view of the area 1001 in FIG11 (A2), showing the first sub-semiconductor layer 1002, the second sub-semiconductor layer 1003, the third sub-semiconductor layer 1004, the fourth sub-semiconductor layer 1005, the first isolation layer 1006, and the second isolation layer 1007. The materials used for these four sub-semiconductor layers are all metal oxide semiconductor material 1000. In the process of constructing the transistor, since the sidewalls of the through hole other than the first isolation layer and the second isolation layer are embedded in the stacked structure, these parts cannot be observed in the top view shown in FIG11 (A2) and the enlarged view shown in FIG11 (A3). Only the sidewalls of the through hole where the first isolation layer and the second isolation layer are located can be observed.
[0146] Step 440 : depositing a gate dielectric material on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer, and the fourth sub-semiconductor layer to form a gate dielectric layer.
[0147] For example, a high-K material is selected as the gate dielectric material, which can be used as an insulating medium between the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer, and the fourth sub-semiconductor layer and the corresponding gate in the transistor.
[0148] In some embodiments, the gate dielectric material is deposited on the surface of the semiconductor layer by an ALD (Atomic Layer Deposition) process or a chemical vapor deposition technique.
[0149] With reference to FIG12 , FIG12 (A1) shows a three-dimensional structural diagram of the stacked structure after the gate dielectric material 1100 is deposited. FIG12 (A2) shows a two-dimensional top view of the structure shown in FIG12 (A1) observed along the vertical direction, and FIG12 (A3) is an enlarged view of the 1101 area in FIG12 (A2), showing that the gate dielectric material 1100 covering the semiconductor layer can constitute a gate dielectric layer. In the process of constructing the transistor, since the sidewalls of the through hole other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, such part cannot be observed in the top view shown in FIG12 (A2) and the enlarged view shown in FIG12 (A3), and only the sidewalls of the through hole where the first isolation layer and the second isolation layer are located can be observed.
[0150] It should be added that in step S430 and step S440, step S431 can be performed first to deposit semiconductor material and gate dielectric material in sequence in each through hole, and then step S441 can be performed to etch away the gate dielectric material and semiconductor material covering the insulating layer in the through hole to expose the insulating layer, and to make the semiconductor material retained on the first isolation layer constitute the first sub-semiconductor layer and the second sub-semiconductor layer respectively, the semiconductor material retained on the second isolation layer constitute the third sub-semiconductor layer and the fourth sub-semiconductor layer respectively, and the gate dielectric material retained on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer and the fourth sub-semiconductor layer constitute the gate dielectric layer.
[0151] In some embodiments, etching the protruding portion on the inner sidewall of the through-hole can expose the insulating layer on the sidewall of the through-hole. Since wet etching narrows the metal layer, the first and second isolation layers formed by oxidation are narrower than the insulating layer, so there will be a protruding portion at the location of the insulating layer in the through-hole. Thus, after the semiconductor material and gate dielectric material are deposited, semiconductor material and gate dielectric material will also be deposited on the protruding portion of the insulating layer. By etching away the gate dielectric material and semiconductor material deposited on the protruding portion in the through-hole, the semiconductor material in the through-hole can be separated by the insulating layer after the insulating layer is exposed. This etching operation can be used to remove parasitic MOSFETs (metal-oxide semiconductor field-effect transistors) in the vertical direction.
[0152] With reference to FIG13 , FIG13 (A1) shows a three-dimensional structural diagram of the stacked structure after etching the protruding insulating layer. FIG13 (A2) shows a two-dimensional top view of the structure shown in FIG13 (A1) observed along the vertical direction. FIG13 (A3) is an enlarged view of the 1200 area in FIG13 (A2), showing a three-dimensional structural diagram of the through hole after etching the protruding insulating layer. In the process of constructing the transistor, since the sidewalls of the through hole other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, such parts cannot be observed in the top view shown in FIG12 (A2) and the enlarged view shown in FIG12 (A3), and only the sidewalls of the through hole where the first isolation layer and the second isolation layer are located can be observed.
[0153] It should be noted that, in combination with the aforementioned oxidation etching process of the metal layer, the deposition process of the semiconductor material and the gate dielectric material, and the etching process of the protruding portion of the insulating layer, it can be understood that in step S441, after the gate dielectric material and the semiconductor material covering the insulating layer in the through hole are etched away to expose the insulating layer, redundant semiconductor material and redundant gate dielectric material still remain on the inner side walls relative to each other in the second direction parallel to the substrate.
[0154] 14 , the plurality of through holes arranged in a row along the first direction are considered to be a plurality of first through holes H1 and a plurality of second through holes H2 that are alternately distributed. The gate electrode formed on the gate dielectric layer in step S450 can be performed according to the following steps S451 and S452 .
[0155] Step S451 , forming a gate material layer in each through hole to cover the gate dielectric layer, the redundant gate dielectric material and the insulating layer.
[0156] Optionally, the gate material layer includes but is not limited to a metal material layer.
[0157] Optionally, the gate material layer is deposited by an ALD process.
[0158] With reference to FIG14 , FIG14 (A1) shows a three-dimensional structural diagram of the stacked structure after depositing the gate material layer 1301. FIG14 (A2) shows a two-dimensional top view of the structure shown in FIG14 (A1) observed along the vertical direction. FIG14 (A3) is an enlarged view of the area 1300 in FIG14 (A2), showing the gate material 1301 layer covering the gate dielectric layer for forming the gate and word line. In the process of constructing the transistor, since the sidewalls of the through hole other than the first isolation layer and the second isolation layer are embedded in the stacked structure, such parts cannot be observed in the top view shown in FIG14 (A2) and the enlarged view 4 shown in FIG14 (A3). Only the sidewalls of the through hole where the first isolation layer and the second isolation layer are located can be observed.
[0159] In step S452, based on the second through hole, the stacked structure is etched along a second direction parallel to the substrate and a direction perpendicular to the substrate, and the gate material layer, redundant gate dielectric material, and redundant semiconductor material on the opposite side walls of the second through hole in the second direction are removed to form a trench extending along the second direction, and the gate material layer retained in the first through hole and on the opposite side walls of the second through hole in the first direction constitutes the gate of the corresponding transistor and the word line connected to the gate.
[0160] Here, the trench is an isolation trench between adjacent transistors in the first direction.
[0161] With reference to FIG15 , FIG15 (A1) shows a three-dimensional structural diagram of the stacked structure after etching to form a groove, wherein 1400 is the formed groove. FIG15 (A2) shows a two-dimensional top view of the structure shown in FIG15 (A1) observed along the vertical direction. In the process of constructing the transistor, since the sidewalls of the through hole other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, these parts cannot be observed in the top view shown in FIG15 (A2). Only the sidewalls of the through hole where the first isolation layer and the second isolation layer are located can be observed.
[0162] In step 453 , the first via hole and the trench are filled with an isolation material.
[0163] It is understood that the trench is used to isolate adjacent transistors in the first direction. The trench can be filled with an insulating material, such as an oxide, to insulate and support the adjacent transistors. Furthermore, the gap within the first through hole can also be filled with an insulating material to support the transistors.
[0164] With reference to Figure 16, Figure 16 (A) shows a three-dimensional structural diagram of the stacked structure after filling with isolation material 1500 and grinding. It can be seen from Figure 16 that the protective layer 300 still exists in the unetched part of the stacked structure, and Figure 16 (B) shows a two-dimensional top view of the structure shown in Figure 16 (A) observed along the vertical direction. In the process of constructing the transistor, since the side walls of the through hole other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, this part cannot be observed in the top view shown in Figure 16 (B), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.
[0165] Step 454: remove the remaining protective layer on the surface of the laminated structure.
[0166] In some embodiments, the protective layer remaining on the surface of the stacked structure is etched using a dry etching process. The protective layer is used to protect portions of the stacked structure that do not need to be etched from being damaged during the etching process. Furthermore, the protective layer can protect the underlying metal layer from being oxidized during the oxidation process.
[0167] 17 , which shows a three-dimensional structure diagram of the stacked structure after removing the protective layer 300. As shown in FIG17 , after removing the protective layer 300, the top metal layer (eg, the third metal layer 306) of the stacked structure is exposed.
[0168] In step 460 , a capacitor is fabricated on one side of the transistor in the stacked structure to form a semiconductor device. The capacitor is connected to the transistor.
[0169] In some embodiments, after any of the above etching or filling steps, a CMP (Chemical Mechanical Polishing) process may be performed to smooth the stacked structure, thereby ensuring the airtightness of the device.
[0170] With reference to Figure 1 , Figure 1(A) illustrates a three-dimensional structure of a semiconductor device. As can be seen, capacitor 115 can be fabricated on the side of transistor 104 facing away from bit line 102. That is, capacitor 115 can be fabricated on one side of each transistor 104, with bit line 102 on the other side. In some embodiments, the structure and fabrication of the capacitors can be tailored to meet specific requirements.
[0171] The method provided by the embodiment of the present disclosure can prepare a semiconductor device that maintains electrical stability, such as a 3D memory. At the same time, based on the method of simultaneously preparing multi-channel transistors, a multi-channel memory is obtained, which can increase the current of the driving current. In addition, IGZO has amorphous properties. Selecting it as the semiconductor layer material of the transistor has a stable process and can stack more layers while maintaining stable electrical properties. In this way, the three-dimensional stacking design of the semiconductor device also makes it easy to increase the storage density of the 3D memory and reduce the production cost per GB.
[0172] On the other hand, the embodiments of the present disclosure further provide a transistor, the structure and preparation of which can refer to the relevant descriptions in some of the aforementioned embodiments.
[0173] For example, as understood in conjunction with FIG1 , transistor 104 includes: a first isolation layer 106, a second isolation layer 107, a semiconductor layer 108, a gate dielectric layer 109, and a gate 110. The first isolation layer 106 and the second isolation layer 107 are disposed opposite each other and spaced apart in a first direction parallel to the substrate 100. The semiconductor layer 108 includes a first sub-semiconductor layer 111 and a second sub-semiconductor layer 112, respectively covering two opposite sides of the first isolation layer 106, and a third sub-semiconductor layer 113 and a fourth sub-semiconductor layer 114, respectively covering two opposite sides of the second isolation layer 107 in the first direction. The gate dielectric layer 109 covers the semiconductor layer 108; the gate 110 covers the gate dielectric layer 109.
[0174] For example, the semiconductor layer 108 is made of a metal oxide semiconductor material.
[0175] In another aspect, embodiments of the present disclosure further provide an electronic device. The electronic device includes a logic device, which includes the semiconductor device provided in the above embodiments. The logic device can be applied to a logic operator, a memory, and the like.
[0176] Illustratively, the electronic device includes a memory, and the memory includes: a semiconductor device prepared according to the method for preparing a semiconductor device as described in any of the above embodiments; or, a semiconductor device as described in any of the above embodiments; or, a transistor as described in any of the above embodiments.
[0177] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0178] In this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and the term "plurality" refers to two or more, unless otherwise clearly defined.
[0179] In this disclosure, the term "and / or" simply describes an association relationship between related objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.
[0180] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.
Claims
1. A method for preparing a semiconductor device, comprising: Alternating multiple insulating layers and metal layers on a substrate to form a stacked structure; A plurality of transistors arranged in a multilayer array are formed in the stacked structure; the transistors include a first isolation layer, a second isolation layer, a semiconductor layer, a gate dielectric layer and a gate electrode; wherein the first isolation layer and the second isolation layer are arranged opposite to each other and spaced apart in a first direction parallel to the substrate; the semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer respectively covering two side walls of the first isolation layer opposite to each other in the first direction, and a third sub-semiconductor layer and a fourth sub-semiconductor layer respectively covering two side walls of the second isolation layer opposite to each other in the first direction; the gate dielectric layer covers the semiconductor layer; and the gate electrode covers the gate dielectric layer.
2. The method for preparing a semiconductor device according to claim 1, wherein: The plurality of transistors arranged in a multi-layer array in the stacked structure include: Etching the stacked structure in a direction perpendicular to the substrate to form a plurality of through holes arranged in an array; Based on each through hole, oxidizing the metal layer exposed in the through hole to form a plurality of first isolation layers and a plurality of second isolation layers alternately arranged in the first direction; forming the first sub-semiconductor layer and the second sub-semiconductor layer on two side walls of the first isolation layer that are opposite to each other in the first direction, and forming the third sub-semiconductor layer and the fourth sub-semiconductor layer on two side walls of the second isolation layer that are opposite to each other in the first direction; depositing a gate dielectric material on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer, and the fourth sub-semiconductor layer to form the gate dielectric layer; The gate is formed on the gate dielectric layer.
3. The method for preparing a semiconductor device according to claim 2, wherein: The plurality of through holes are arranged in a row along the first direction; Before oxidizing the metal layer exposed in each through-hole to form a plurality of first isolation layers and a plurality of second isolation layers, the preparation method further comprises: etching the metal layer based on the through-holes to thin the metal layer between adjacent through-holes in any column of the through-holes; The metal layer exposed in the through hole by oxidation includes the metal layer thinned by oxidation.
4. The method for preparing a semiconductor device according to claim 3, wherein: The metal layer is etched using a wet etching process.
5. The method for preparing a semiconductor device according to any one of claims 2 to 4, wherein: The step of oxidizing the metal layer exposed in each of the through holes to correspondingly form a plurality of the first isolation layers and a plurality of the second isolation layers comprises: oxidizing the metal layer exposed in the through hole to form a metal oxide layer; Based on the through hole, the metal oxide layer is etched along a second direction parallel to the substrate, so that the metal layer opposite to each other in the second direction is exposed in the through hole; wherein the metal oxide layers retained in the through hole and opposite to each other in the first direction respectively constitute the first isolation layer and the second isolation layer; the second direction intersects with the first direction.
6. The method for manufacturing a semiconductor device according to claim 5, wherein: Also includes: Based on the metal layers exposed in the through hole and facing each other in the second direction, a bit line connected to the semiconductor layer and a first electrode of a capacitor are formed respectively; Alternatively, source / drain electrodes of the transistor are formed respectively based on the metal layers exposed in the through hole and opposite to each other in the second direction.
7. The method for preparing a semiconductor device according to any one of claims 2 to 6, wherein: The method comprises: forming the first sub-semiconductor layer and the second sub-semiconductor layer on two side walls of the first isolation layer that are opposite to each other in the first direction, forming the third sub-semiconductor layer and the fourth sub-semiconductor layer on two side walls of the second isolation layer that are opposite to each other in the first direction, and depositing a gate dielectric material on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer, and the fourth sub-semiconductor layer to form the gate dielectric layer, including: Depositing semiconductor material and gate dielectric material in sequence in each of the through holes; The gate dielectric material and the semiconductor material covering the insulating layer in the through hole are etched away to expose the insulating layer, and the semiconductor material remaining on the first isolation layer constitutes the first sub-semiconductor layer and the second sub-semiconductor layer, respectively, the semiconductor material remaining on the second isolation layer constitutes the third sub-semiconductor layer and the fourth sub-semiconductor layer, respectively, and the gate dielectric material remaining on the first sub-semiconductor layer, the second sub-semiconductor layer, the third sub-semiconductor layer and the fourth sub-semiconductor layer constitutes the gate dielectric layer.
8. The method for preparing a semiconductor device according to claim 7, wherein: After the etching removes the gate dielectric material and the semiconductor material covering the insulating layer in the through hole to expose the insulating layer, redundant semiconductor material and redundant gate dielectric material remain on opposite inner sidewalls of the through hole in a second direction parallel to the substrate; Wherein, a row of the plurality of through holes includes first through holes and second through holes arranged alternately; and forming the gate on the gate dielectric layer includes: forming a gate material layer in each of the through holes, covering the gate dielectric layer, the redundant gate dielectric material and the insulating layer; Based on the second through hole, the stacked structure is etched along a second direction parallel to the substrate and a direction perpendicular to the substrate, and the gate material layer, the redundant gate dielectric material, and the redundant semiconductor material located on opposite side walls of the second through hole in the second direction are removed to form a trench extending along the second direction, and the gate material layer retained in the first through hole and on opposite side walls of the second through hole in the first direction constitutes the gate of the corresponding transistor and a word line connected to the gate.
9. The method for manufacturing a semiconductor device according to claim 8, wherein: Also includes: An isolation material is filled in the first through hole and the trench.
10. The method for manufacturing a semiconductor device according to claim 7, wherein: The semiconductor material includes a metal oxide semiconductor material.
11. The method for preparing a semiconductor device according to any one of claims 2 to 10, wherein: Before etching the stacked structure in a direction perpendicular to the substrate to form a plurality of through holes arranged in an array, the preparation method further includes: depositing a protective layer on the surface of the laminated structure; removing a protective layer from a surface of a designated area, wherein the designated area is associated with a position of the transistor; Wherein, the through hole is formed in the designated area.
12. The method for preparing a semiconductor device according to any one of claims 1 to 10, wherein: Also includes: Capacitors are respectively prepared on one side of each transistor in the stacked structure to form a semiconductor device; wherein the first electrode of the capacitor is correspondingly connected to the semiconductor layer of the transistor.
13. A semiconductor device comprising: Substrate and laminate structure; The stacked structure is located on the substrate; The stacked structure comprises: multiple layers of memory cell arrays stacked in a direction perpendicular to the substrate and a plurality of bit lines extending in a first direction parallel to the substrate, each layer of the memory cell array comprising a plurality of memory cells arranged in an array, and each of the bit lines being connected to at least one column of the memory cells arranged in the first direction; wherein each of the memory cells comprises a transistor; The transistor includes: a first isolation layer, a second isolation layer, a semiconductor layer, a gate dielectric layer and a gate; wherein the first isolation layer and the second isolation layer are arranged opposite to each other and spaced apart in a first direction parallel to the substrate; the semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer respectively covering two side walls of the first isolation layer opposite to each other in the first direction, and a third sub-semiconductor layer and a fourth sub-semiconductor layer respectively covering two side walls of the second isolation layer opposite to each other in the first direction; the gate dielectric layer covers the semiconductor layer; and the gate covers the gate dielectric layer.
14. The semiconductor device according to claim 13, wherein The storage unit further includes: a capacitor; The capacitor includes a first electrode connected to an end of the semiconductor layer in the memory cell that is away from the bit line.
15. The semiconductor device according to claim 13, wherein The stacked structure further includes: a plurality of word lines; The word line extends in a direction perpendicular to the substrate; In a row of the memory cells arranged perpendicular to the substrate, the gates of the transistors are connected to the same word line.
16. The semiconductor device according to any one of claims 13 to 15, wherein Two columns of memory cells arranged along the first direction and adjacent to each other along a second direction parallel to the substrate share one bit line, wherein the first direction intersects the second direction.
17. A transistor comprising: A first isolation layer, a second isolation layer, a semiconductor layer, a gate dielectric layer and a gate electrode; wherein the first isolation layer and the second isolation layer are arranged opposite to each other and spaced apart in a first direction parallel to the substrate; the semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer respectively covering two side walls of the first isolation layer opposite to each other in the first direction, and a third sub-semiconductor layer and a fourth sub-semiconductor layer respectively covering two side walls of the second isolation layer opposite to each other in the first direction; the gate dielectric layer covers the semiconductor layer; and the gate electrode covers the gate dielectric layer.
18. The transistor according to claim 17, wherein The material of the semiconductor layer is a metal oxide semiconductor material.
19. An electronic device comprising a memory; the memory comprising: A semiconductor device manufactured according to the method for manufacturing a semiconductor device according to any one of claims 1 to 12; or, a semiconductor device according to any one of claims 13 to 15; Or, a transistor as claimed in claim 17.
20. The electronic device according to claim 19, wherein The electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.