Optimization method and apparatus for oxide-based resistive random access memory, and retention test method and apparatus for oxide-based resistive random access memory

Abstract

An optimization method and apparatus for an oxide-based resistive random access memory, and a retention test method and apparatus for an oxide-based resistive random access memory, which relate to the technical field of microelectronics. The optimization method comprises: performing a forming operation on an oxide-based resistive random access memory, so as to obtain a first resistive random access memory in an active state (S110); performing a first preset number of first erase / write operations on the first resistive random access memory, so as to obtain a second resistive random access memory within a preset resistive state range (S120); and performing a second preset number of second erase / write operations on the second resistive random access memory, so as to obtain a target resistive random access memory within the preset resistive state range (S130), wherein a second reset voltage, which is used in the second erase / write operations, is obtained by finding the sum of a preset voltage value and an average value of first reset voltages, which are respectively used in the first preset number of first erase / write operations.

Description

Optimization method, retention detection method and device of oxide-based resistive random access memory Technical Field

[0001] The present disclosure relates to the field of microelectronics technology, and in particular to an optimization method, a retention detection method, and a device for an oxide-based resistive random access memory. Background Art

[0002] With the rapid development of edge computing technology, SOC chips (System-on-a-Chip) have placed higher demands on the performance and power consumption of embedded memory. However, with the further miniaturization of semiconductor process sizes, especially after entering the 28nm process node, the integration of traditional embedded flash memory with advanced logic processes such as high-k metal gate (HKMG) and FinFET (Fin Field-Effect Transistor) has become increasingly difficult. Not only has the cost of preparing embedded flash memory increased significantly, but the performance of embedded flash memory has also been severely degraded due to the reduction in device size. Therefore, it is difficult for traditional embedded flash memory to extend below 40nm.

[0003] Resistive Random Access Memory (RRAM) offers advantages such as simple structure, small size, and high integration. Its fabrication process is independent of the front-end process and is compatible with advanced logic processes such as HKMG and FinFET. Therefore, RRAM is a solution for embedded non-volatile memory at advanced nodes, such as 28nm and below.

[0004] In edge computing, RRAM's resistive state can be used to store the weights of neural network algorithms, enabling hardware acceleration of neural networks. Resistive state retention is a key characteristic of RRAM and a crucial indicator of its information storage stability. Therefore, RRAM's resistive state retention directly impacts the accuracy of neural network algorithms.

[0005] Oxide-based RRAM can be in different resistance states under pulse voltage stimulation of different polarities. To achieve the target resistance state, the oxide-based RRAM needs to be repeatedly set and reset. However, repeated set and reset operations will cause the retention of the oxide-based RRAM to decrease. Therefore, it is urgent to find a method to improve the resistance state retention of oxide-based RRAM.

[0006] Summary of the Invention

[0007] In view of the above problems, the present disclosure provides an optimization method, a retention detection method and a device for an oxide-based resistive random access memory.

[0008] According to a first aspect of the present disclosure, a method for optimizing an oxide-based resistive random access memory is provided, comprising:

[0009] Performing a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state;

[0010] Performing a first preset number of first erase and write operations on the first resistive random access memory to obtain a second resistive random access memory in a preset resistance state range;

[0011] A second preset number of second erase / write operations are performed on the second resistive random access memory to obtain a target resistive random access memory in a preset resistance state range, wherein the second reset voltage used in the second erase / write operation is obtained by summing the preset voltage value and the average value of the first reset voltages used in the first preset number of first erase / write operations.

[0012] According to an embodiment of the present disclosure, the preset voltage value is greater than or equal to 0.1V and less than or equal to 0.3V.

[0013] According to an embodiment of the present disclosure, the pulse width corresponding to the second reset voltage is greater than or equal to 0.9 us and less than or equal to 2 us.

[0014] According to an embodiment of the present disclosure, performing the second erase / write operation on the second resistive random access memory a second preset number of times to obtain a target resistive random access memory in a preset resistance state range includes iteratively performing the following operations until the number of iterations meets the second preset number of times:

[0015] Performing a set sub-operation on the i-th second resistive random access memory to obtain an i-th first set resistive random access memory, where i is an integer greater than or equal to 1 and less than a second preset number;

[0016] Performing a reset sub-operation on the i-th first set resistive random access memory to obtain an i-th target resistive random access memory, wherein a reset voltage used in the reset sub-operation is the second reset voltage;

[0017] The i-th target resistive random access memory is used as the i+1-th second resistive random access memory, and the i+1-th second erase / write operation is performed.

[0018] According to an embodiment of the present disclosure, the above-mentioned set sub-operation is the same as the set sub-operation included in the above-mentioned first erase operation.

[0019] According to an embodiment of the present disclosure, before performing a second preset number of second erase / write operations on the second resistive random access memory to obtain a target resistive random access memory in a preset resistance state range, the method further includes:

[0020] Obtaining a first reset voltage used in each of the first preset number of first erase and write operations;

[0021] averaging a first preset number of the first reset voltages to obtain a reset voltage average value;

[0022] The second reset voltage is obtained by adding the reset voltage average value and the preset voltage value.

[0023] According to an embodiment of the present disclosure, performing a first preset number of first erase / write operations on the first resistive random access memory to obtain a second resistive random access memory in a preset resistance state range includes:

[0024] A first preset number of incremental step pulse programming operations are performed on the first resistive memory to obtain a second resistive memory in a preset resistance state range.

[0025] A second aspect of the present disclosure provides a method for detecting the retention of an oxide-based resistive random access memory, comprising:

[0026] Baking M target resistive random access memories according to any one of claims 1 to 7 at a preset temperature for a preset time to obtain M baked resistive random access memories;

[0027] The resistance values ​​of the M baked resistive random access memories are respectively tested to obtain M target resistance values;

[0028] The M target resistance values ​​are compared with the preset resistance value to obtain a retention test result.

[0029] A third aspect of the present disclosure provides an optimization device for an oxide-based resistive random access memory, comprising:

[0030] A first obtaining module is used to perform a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state;

[0031] A second obtaining module is configured to perform a first preset number of first erase and write operations on the first resistive random access memory to obtain a second resistive random access memory in a preset resistance state range;

[0032] The third obtaining module is used to perform a second preset number of second erase and write operations on the above-mentioned second resistive random access memory to obtain a target resistive random access memory in a preset resistance state range, wherein the second reset voltage used in the above-mentioned second erase and write operation is obtained by summing the preset voltage value and the average value of the first reset voltages respectively used in the above-mentioned first preset number of first erase and write operations.

[0033] A fourth aspect of the present disclosure provides a device for detecting the retention of an oxide-based resistive random access memory, comprising:

[0034] A fourth obtaining module is configured to bake the M target resistive random access memories at a preset temperature for a preset time to obtain M baked resistive random access memories;

[0035] a fifth obtaining module, configured to respectively detect the resistance values ​​of the M baked resistive random access memories to obtain M target resistance values;

[0036] The sixth obtaining module is used to compare the M target resistance values ​​with a preset resistance value to obtain a retention detection result.

[0037] According to the embodiments of the present disclosure, since the second reset voltage used in the second erase / write operation is obtained by summing a preset voltage value and an average of the first reset voltages used in each of the first preset number of first erase / write operations, the second reset voltage is higher than the normal reset voltage. Therefore, after performing the first erase / write operation on the activated first resistive random access memory a first preset number of times, and then performing the second erase / write operation a second preset number of times, it is possible to perform a voltage pulse programming operation higher than the normal reset voltage on top of the conventional first erase / write operation on the first resistive random access memory to clear unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive random access memory, maintain the gaps between the hourglass-shaped oxygen vacancy conductive filaments, suppress longitudinal drift of oxygen ions in the oxygen storage layer, improve the retention of high-resistance state data in the target resistive random access memory, and reduce the volatility of high-resistance and low-resistance state data. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0039] FIG1 schematically shows a flow chart of a method for optimizing an oxide-based resistive random access memory according to an embodiment of the present disclosure;

[0040] FIG2 schematically shows a diagram of a first set voltage and a first reset voltage used in an incremental step pulse programming operation according to an embodiment of the present disclosure;

[0041] FIG3 schematically shows a second set voltage and a second reset voltage used in a second erase / write operation according to an embodiment of the present disclosure;

[0042] FIG4 schematically shows a flow chart of a method for detecting the retention of an oxide-based resistive random access memory according to an embodiment of the present disclosure;

[0043] FIG5 schematically shows a diagram of a retention test result of an oxide-based resistive random access memory according to an embodiment of the present disclosure;

[0044] FIG6 schematically shows a structural block diagram of an optimization device for an oxide-based resistive random access memory according to an embodiment of the present disclosure; and

[0045] FIG7 schematically shows a structural block diagram of an apparatus for detecting retention of an oxide-based resistive random access memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0047] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0048] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0049] When expressions such as "at least one of A, B and C, etc." are used, they should generally be interpreted in accordance with the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0050] In the process of applying oxide-based RRAM, in order to make the oxide-based RRAM reach the target resistance state, such as the high resistance state, the oxide-based RRAM needs to be repeatedly set and reset. In the set operation, after applying the set operation voltage to the oxide-based RRAM, the oxygen ions in the oxide-based RRAM will move to the oxygen storage layer at the upper electrode, thereby forming oxygen vacancy conductive filaments in the oxide-based RRAM, making the oxide-based RRAM in a low resistance state. In the reset operation, after applying the reset operation voltage to the oxide-based RRAM, the oxygen ions in the oxide-based RRAM will recombine with the oxygen vacancies, causing the oxygen vacancy conductive filaments to break, and the oxide-based RRAM is in a high resistance state.

[0051] However, repeated set and reset operations can make the oxygen storage layer in the oxide-based RRAM unstable, resulting in a decrease in the resistance state retention and stability of the oxide-based RRAM. Therefore, it is urgent to find a method to improve the resistance state retention of the oxide-based RRAM.

[0052] In order to at least partially solve the technical problems existing in the related art, the embodiments of the present disclosure provide an optimization method, a retention detection method and an apparatus for an oxide-based resistive random access memory, which can be applied in the field of microelectronics technology.

[0053] According to the embodiments of the present disclosure, since the decrease in the resistance state retention of the oxide-based RRAM mainly occurs in the high resistance state, the optimization method of the oxide-based resistive random access memory provided by the embodiments of the present disclosure mainly optimizes and detects the resistance state retention of the oxide-based resistive random access memory in the high resistance state.

[0054] The following will describe in detail the optimization method, retention detection method and device of the oxide-based resistive random access memory of the disclosed embodiment based on FIG. 1 to FIG. 7 .

[0055] FIG1 schematically shows a flow chart of a method for optimizing an oxide-based resistive random access memory according to an embodiment of the present disclosure.

[0056] As shown in FIG. 1 , the optimization method of the oxide-based resistive random access memory according to this embodiment includes operations S110 to S130 .

[0057] In operation S110 , a forming operation is performed on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state.

[0058] According to the embodiments of the present disclosure, since the storage array in the chip includes multiple oxide-based resistive random access memories, all of which are in a non-conductive state and have a resistance level of MΩ in their original factory state, before performing an erase or write operation on the oxide-based resistive random access memory, it is first necessary to perform a forming operation, i.e., a FORMING operation, on the oxide-based resistive random access memory.

[0059] According to an embodiment of the present disclosure, a FORMING operation is performed on an oxide-based resistive random access memory, with the purpose of soft-breaking the resistive random access layer of the oxide-based RRAM based on the FORMING operation process, obtaining a first resistive random access memory in an activated state, and forming oxygen vacancies in the first resistive random access memory, so that the motion state of the oxygen vacancies and oxygen ions in the first resistive random access memory can be adjusted by repeatedly setting and resetting the first resistive random access memory, so that the adjusted first resistive random access memory can be in a target resistance state.

[0060] According to an embodiment of the present disclosure, the target resistance state can be divided into a high resistance state and a low resistance state.

[0061] According to an embodiment of the present disclosure, a forming operation is performed on an oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state, including: applying a voltage pulse of 1.7V / 3us to a source line end (SL end) of the oxide-based resistive random access memory, and then reading the resistance value of the oxide-based resistive random access memory after the 1.7V / 3us voltage pulse is applied. When the read resistance value is at the KΩ level, it indicates that the forming operation is successful, and the first resistive random access memory in an activated state is obtained, and an indication of a successful forming operation is output.

[0062] According to an embodiment of the present disclosure, reading the resistance value of the oxide-based resistive random access memory after applying a voltage pulse of 1.7V / 3us includes: reading the resistance value of the oxide-based resistive random access memory after applying a voltage pulse of 0.3V / 700ns at the bit line end (BL end) of the oxide-based resistive random access memory.

[0063] For example, when the read resistance value is below 700 KΩ, it indicates that the forming operation is successful, a first resistive random access memory in an activated state is obtained, and a forming operation success flag "forming success" is output.

[0064] In operation S120 , a first preset number of first erase / write operations are performed on the first resistive memory to obtain a second resistive memory in a preset resistance state range.

[0065] According to an embodiment of the present disclosure, the preset resistance state may be a high resistance state. In this case, the preset resistance state range may include resistance states greater than or equal to 200 KΩ and less than 700 KΩ.

[0066] According to an embodiment of the present disclosure, when the second resistive memory is in a preset resistance range, the second resistive memory is characterized as being in a high resistance state. When the resistance value of the second resistive memory is less than 35KΩ, the second resistive memory is characterized as being in a low resistance state.

[0067] According to the embodiment of the present disclosure, the first preset number can be selected according to actual conditions and is not limited here.

[0068] For example, the first preset number may be 900, 1000, or 1500, etc.

[0069] According to an embodiment of the present disclosure, each first erase / write operation includes: performing a set sub-operation on the first resistive memory using at least one first set voltage, and then performing a reset sub-operation on the first resistive memory using at least one first reset voltage, to obtain a second resistive memory in a preset resistance state range each time.

[0070] In operation S130, a second erase / write operation is performed on the second resistive memory for a second preset number of times to obtain a target resistive memory in a preset resistance range, wherein a second reset voltage used in the second erase / write operation is obtained by summing a preset voltage value and an average value of the first reset voltages used in each of the first preset number of first erase / write operations.

[0071] According to the embodiment of the present disclosure, the second preset number can be selected according to actual conditions and is not limited here.

[0072] According to an embodiment of the present disclosure, the second preset number may be between 5 and 60.

[0073] For example, the second preset number may be 5, 10, 15, 20, or 50, etc.

[0074] According to an embodiment of the present disclosure, each second erase / write operation includes performing a set sub-operation on the second resistive random access memory using at least one second set voltage, and then performing a reset sub-operation using a second reset voltage.

[0075] According to an embodiment of the present disclosure, the target resistive random access memory in the preset resistance state range is a target resistive random access memory in a high resistance state.

[0076] According to the embodiment of the present disclosure, the high-resistance state of the target resistive memory has higher retention than the high-resistance state of the second resistive memory, and the high-resistance state is more stable.

[0077] According to the embodiments of the present disclosure, since the second reset voltage used in the second erase / write operation is obtained by summing a preset voltage value and an average of the first reset voltages used in each of the first preset number of first erase / write operations, the second reset voltage is higher than the normal reset voltage. Therefore, after performing the first erase / write operation on the activated first resistive random access memory a first preset number of times, and then performing the second erase / write operation a second preset number of times, it is possible to perform a voltage pulse programming operation higher than the normal reset voltage on top of the conventional first erase / write operation on the first resistive random access memory to clear unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive random access memory, maintain the gaps between the hourglass-shaped oxygen vacancy conductive filaments, suppress longitudinal drift of oxygen ions in the oxygen storage layer, improve the retention of high-resistance state data in the target resistive random access memory, and reduce the volatility of high-resistance and low-resistance state data.

[0078] According to an embodiment of the present disclosure, since the second reset voltage used in the second erase / write operation is obtained by summing a preset voltage value and an average of the first reset voltages used in the first preset number of first erase / write operations, the second reset voltage is higher than the normal reset voltage. Therefore, the optimization method of an oxide-based resistive random access memory provided by an embodiment of the present disclosure can be implemented by performing a conventional first erase / write operation on the first resistive random access memory to obtain a second resistive random access memory, and then adding a voltage pulse programming operation higher than the normal reset voltage to the second resistive random access memory to obtain a target resistive random access memory. Under the action of the electric field generated by the higher-than-normal reset voltage, unstable cations in the second resistive random access memory migrate toward the electrode and form a relatively stable oxygen storage layer near the electrode, thereby making the gaps between the hourglass-shaped oxygen vacancy conductive filaments of the target resistive random access memory relatively stable, ultimately resulting in a relatively stable high-resistance state of the target resistive random access memory, thereby improving the retention of the high-resistance state data of the obtained target resistive random access memory and reducing the volatility of the high and low resistance state data.

[0079] According to an embodiment of the present disclosure, the normal reset voltage represents a reset voltage that can put the oxide-based resistive random access memory into a high-resistance state multiple times without breaking down the oxide-based resistive random access memory.

[0080] According to an embodiment of the present disclosure, an average value of the first reset voltages respectively used in a first preset number of first erase and write operations may be used as the normal reset voltage.

[0081] According to the embodiments of the present disclosure, since the optimization method of the oxide-based resistive random access memory provided by the embodiments of the present disclosure can improve the retention of the high resistance value of the target resistive random access memory in the high resistance state, the optimization method of the oxide-based resistive random access memory provided by the embodiments of the present disclosure can optimize the retention of the high resistance state of the oxide-based resistive random access memory.

[0082] According to an embodiment of the present disclosure, performing a first preset number of first erase / write operations on a first resistive random access memory to obtain a second resistive random access memory in a preset resistance state range includes:

[0083] A first preset number of incremental step-pulse programming (ISPP) operations are performed on the first resistive memory to obtain a second resistive memory in a preset resistance state range.

[0084] FIG. 2 schematically illustrates a first set voltage and a first reset voltage used in an incremental step pulse programming operation according to an embodiment of the present disclosure.

[0085] As shown in FIG2 , in each incremental step pulse programming operation, the first resistive memory can be set sub-operated using at least one first set voltage as shown in FIG2 , and then the first resistive memory can be reset sub-operated using at least one first reset voltage as shown in FIG2 , to obtain a second resistive memory in a preset resistance state range each time, wherein, when two adjacent first reset voltages are not equal or two adjacent first set voltages are not equal, the voltage applied relatively later is obtained by adding the preset step increment Step to the voltage applied earlier, and the preset step increment Step in FIG2 is 0.1V.

[0086] Performing a set sub-operation on the first resistive memory using at least one first set voltage as shown in FIG2 includes iteratively performing the following operations until the number of iterations is less than a third preset number or the resistance of the first resistive memory is less than the first preset resistance: applying the first set voltage to the BL terminal of the first resistive memory for the mth time, and then reading the resistance of the first resistive memory after applying the first set voltage for the mth time; when the resistance of the first resistive memory is less than the first preset resistance, the set sub-operation is successful, and at least one subsequent reset sub-operation can be performed, wherein the initial value of the first set voltage is 1.2V; when the resistance of the first resistive memory is greater than or equal to the first preset resistance, increasing the mth first set voltage by 0.1V to obtain the m+1th first set voltage, and continuing to perform the set sub-operation on the first resistive memory according to the m+1th first set voltage, wherein m is an integer greater than or equal to 1 and less than the third preset number.

[0087] According to an embodiment of the present disclosure, if the setting sub-operation succeeds, a setting sub-operation success flag set success may be output, and if the setting sub-operation fails, a setting sub-operation failure flag set fail may be output.

[0088] According to the embodiment of the present disclosure, the third preset number can be selected according to actual conditions and is not limited here. For example, the third preset number can be 7.

[0089] According to an embodiment of the present disclosure, when the resistance value of the first resistive memory is less than the first preset resistance value, it indicates that the first resistive memory is in a low resistance state.

[0090] According to the embodiment of the present disclosure, the first preset resistance value can be selected according to actual conditions and is not limited here. For example, the first preset resistance value can be 35KΩ.

[0091] For example, the first set sub-operation on the first resistive memory may be: applying a voltage pulse of 1.2V / 700ns to the BL end of the first resistive memory, and then applying a voltage pulse of 0.3V / 700ns to the BL segment of the first resistive memory, and then reading the resistance value of the first resistive memory. When the resistance value of the first resistive memory is less than 35KΩ, the set sub-operation is successful, and at least one subsequent reset sub-operation can be performed. When the resistance value of the first resistive memory is greater than or equal to 35KΩ, the first set voltage of 1.2V is increased by 0.1V to obtain a second first set voltage of 1.3V. Subsequently, the set sub-operation on the first resistive memory can be continued based on the second first set voltage of 1.3V.

[0092] Performing a reset sub-operation on the first resistive memory using at least one first reset voltage as shown in FIG2 includes iteratively performing the following operations until the number of iterations is less than a fourth preset number of times or the resistance of the first resistive memory is greater than or equal to a second preset resistance: applying the first reset voltage to the SL terminal of the first resistive memory for an nth time, and then reading the resistance of the first resistive memory after applying the first reset voltage for the nth time; if the resistance of the first resistive memory is greater than or equal to the second preset resistance, the reset sub-operation is successful, and a second resistive memory is obtained, wherein an initial value of the first reset voltage is 1.6V; if the resistance of the first resistive memory is less than the second preset resistance, increasing the nth first reset voltage by 0.1V to obtain an n+1th first reset voltage, and continuing to perform the reset sub-operation on the first resistive memory according to the n+1th first reset voltage, wherein n is an integer greater than or equal to 1 and less than the fourth preset number.

[0093] According to an embodiment of the present disclosure, if the reset sub-operation succeeds, a reset sub-operation success flag reset success may be output, and if the reset sub-operation fails, a reset sub-operation failure flag reset fail may be output.

[0094] According to the embodiment of the present disclosure, the fourth preset number can be selected according to actual conditions and is not limited here. For example, the fourth preset number can be 7.

[0095] According to an embodiment of the present disclosure, when the resistance value of the first resistive memory is greater than or equal to the second preset resistance value, it indicates that the first resistive memory is in a high-resistance state.

[0096] According to the embodiment of the present disclosure, the second preset resistance value can be selected according to actual conditions and is not limited here. For example, the second preset resistance value can be 200KΩ.

[0097] For example, a first reset sub-operation on the first resistive random access memory may include applying a 1.6V / 700ns voltage pulse to the SL terminal of the first resistive random access memory, then applying a 0.3V / 700ns voltage pulse to the BL terminal of the first resistive random access memory, and then reading the resistance value of the first resistive random access memory. If the resistance value of the first resistive random access memory is greater than or equal to 200KΩ, the reset sub-operation is successful, and a second resistive random access memory is obtained. If the resistance value of the first resistive random access memory is less than 200KΩ, the first reset voltage of 1.6V is increased by 0.1V to obtain a second first reset voltage of 1.7V. Subsequently, the first resistive random access memory may continue to be reset sub-operated based on the second first reset voltage of 1.7V.

[0098] According to an embodiment of the present disclosure, before performing a second preset number of second erase / write operations on the second resistive random access memory to obtain a target resistive random access memory in a preset resistance state range, the method further includes:

[0099] Obtaining a first reset voltage used in each of a first preset number of first erase and write operations;

[0100] averaging a first preset number of first reset voltages to obtain a reset voltage average value;

[0101] The average reset voltage value and the preset voltage value are added to obtain a second reset voltage.

[0102] According to an embodiment of the present disclosure, in each first erase / write operation, the last first reset voltage applied to the first resistive memory is determined as the first reset voltage used in the first erase / write operation.

[0103] According to an embodiment of the present disclosure, the preset voltage value may be greater than or equal to 0.1V and less than or equal to 0.3V.

[0104] For example, the preset voltage value may be 0.2V.

[0105] For example, the average value of the reset voltage can be calculated by averaging 1000 first reset voltages to obtain the average reset voltage value. Then reset the voltage average Add 0.2V to get the second reset voltage

[0106] According to an embodiment of the present disclosure, the preset voltage value is greater than or equal to 0.1V and less than or equal to 0.3V, which can ensure that the second reset voltage obtained by summing the preset voltage and the average value of the first reset voltage used in the first preset number of first erase and write operations is greater than the normal reset voltage and will not break down the second resistive memory. It is ensured that the second erase and write operation can apply a voltage pulse programming operation higher than the normal reset voltage to the second resistive memory without breaking down the second resistive memory to clear unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive memory, maintain the gap in the middle of the hourglass-shaped oxygen vacancy conductive filaments, inhibit the longitudinal drift of oxygen ions in the oxygen storage layer, improve the retention of the high-resistance state data of the obtained target resistive memory, and reduce the volatility of high and low resistance state data.

[0107] According to an embodiment of the present disclosure, the pulse width corresponding to the second reset voltage may be greater than or equal to 0.9 us and less than or equal to 2 us.

[0108] For example, the pulse width corresponding to the second reset voltage may be 1 μs.

[0109] According to the embodiments of the present disclosure, the pulse width corresponding to the second reset voltage can be greater than or equal to 0.9 us and less than or equal to 2 us, which can ensure that in each second erase and write operation on the second resistive memory, the application time of the second reset voltage used in the second erase and write operation reaches a predetermined time length, and ensure that after the second preset number of second erase and write operations are performed on the second resistive memory, the unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive memory can be cleared, thereby better maintaining the gap in the middle of the hourglass-shaped oxygen vacancy conductive filaments, suppressing the longitudinal drift of oxygen ions in the oxygen storage layer, improving the retention of the high-resistance state data of the obtained target resistive memory, and reducing the volatility of the high and low resistance state data.

[0110] According to an embodiment of the present disclosure, performing a second erase / write operation on the second resistive random access memory a second preset number of times to obtain a target resistive random access memory in a preset resistance state range includes iteratively performing the following operations until the number of iterations meets the second preset number of times:

[0111] Performing a set sub-operation on the i-th second resistive random access memory to obtain an i-th first set resistive random access memory, where i is an integer greater than or equal to 1 and less than a second preset number;

[0112] Performing a reset sub-operation on the i-th first-set resistive random access memory to obtain an i-th target resistive random access memory, wherein a reset voltage used in the reset sub-operation is a second reset voltage;

[0113] The i-th target resistive random access memory is used as the i+1-th second resistive random access memory, and the i+1-th second erase / write operation is performed.

[0114] For example, the second preset number may be 15.

[0115] According to an embodiment of the present disclosure, the set sub-operation is the same as the set sub-operation included in the first erase operation.

[0116] According to an embodiment of the present disclosure, each set sub-operation performed on the second resistive memory is the same as each set sub-operation performed on the first resistive memory in each first erase / write operation.

[0117] FIG. 3 schematically shows a second set voltage and a second reset voltage used in a second erase / write operation according to an embodiment of the present disclosure.

[0118] As shown in Figure 3, at least one second set voltage as shown in Figure 3 can be used to perform a set sub-operation on the second resistive random access memory each time to obtain a first set resistive random access memory each time. The set sub-operation is the same as the set sub-operation performed on the first resistive random access memory using at least one first set voltage as shown in Figure 2.

[0119] As shown in FIG3 , after obtaining the second reset voltage After that, the reset sub-operation is performed on the first set resistive random access memory each time, and the target resistive random access memory each time is obtained, which includes: applying a reset sub-operation to the SL end of the first set resistive random access memory. The voltage pulse is used to obtain the target resistive memory each time.

[0120] According to an embodiment of the present disclosure, after obtaining the target resistive random access memory each time, the resistance value of the target resistive random access memory each time can be read. If the resistance value of the target resistive random access memory each time is greater than or equal to a second preset resistance value, a reset sub-operation success flag is output. If the resistance value of the target resistive random access memory each time is less than the second preset resistance value, a reset sub-operation failure flag is output.

[0121] According to an embodiment of the present disclosure, a set sub-operation is performed on the i-th second resistive random access memory to obtain an i-th first set resistive random access memory, wherein i is an integer greater than or equal to 1 and less than a second preset number; a reset sub-operation is performed on the i-th first set resistive random access memory to obtain an i-th target resistive random access memory, wherein the reset voltage used in the reset sub-operation is the second reset voltage; the i-th target resistive random access memory is used as the i+1-th second resistive random access memory to perform an i+1-th second erase / write operation, thereby performing a voltage pulse programming operation higher than the normal reset voltage on the basis of performing a traditional first erase / write operation on the first resistive random access memory to clear unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive random access memory, maintain the gap in the middle of the hourglass-shaped oxygen vacancy conductive filaments, suppress the longitudinal drift of oxygen ions in the oxygen storage layer, improve the retention of high-resistance state data of the obtained target resistive random access memory, and reduce the volatility of high and low resistance state data.

[0122] In the related art, when an oxide-based RRAM in a high-resistance state is placed in a high-temperature environment, the oxygen vacancy conductive filaments in the oxide-based RRAM are exposed to the high temperature environment, which intensifies the longitudinal drift of oxygen ions in the oxygen storage layer at the top electrode, causing the high-resistance state of the oxide-based RRAM to decay to a low-resistance state. Therefore, there is an urgent need to find a method to improve the retention of the high-resistance state of oxide-based RRAM in high-temperature environments.

[0123] 4 to 5 , the target resistive random access memory with a high resistance state obtained by the optimization method of the oxide-based resistive random access memory provided by the embodiment of the present disclosure is described below. The target resistive random access memory still has good high resistance state retention in a high temperature environment.

[0124] According to an embodiment of the present disclosure, the retention performance indicates the ability of the oxide-based resistive random access memory to maintain a high-resistance state within a preset time period when the oxide-based resistive random access memory is in a high-resistance state.

[0125] FIG4 schematically shows a flow chart of a method for detecting retention of an oxide-based resistive random access memory according to an embodiment of the present disclosure.

[0126] As shown in FIG. 4 , the method for detecting the retention of an oxide-based resistive random access memory according to this embodiment includes operations S410 to S430 .

[0127] In operation S410 , M target resistive random access memories are baked at a preset temperature for a preset time to obtain M baked resistive random access memories.

[0128] In operation S420 , the resistance values ​​of the M baked resistive random access memories are respectively detected to obtain M target resistance values.

[0129] In operation S430 , the M target resistance values ​​are compared with a preset resistance value to obtain a retention detection result.

[0130] According to an embodiment of the present disclosure, the retention test result indicates whether each baked resistive random access memory remains in a high-resistance state.

[0131] According to an embodiment of the present disclosure, before operation S410 is performed, M oxide-based resistive random access memories may be processed separately according to the optimization method of the oxide-based resistive random access memory shown in FIG1 to obtain M target resistive random access memories.

[0132] According to an embodiment of the present disclosure, M target resistance values ​​can be obtained by applying a 0.3V / 700ns voltage pulse to the BL terminals of M baked RRAMs and then reading the target resistance values ​​of the M baked RRAMs.

[0133] According to the embodiment of the present disclosure, M, the preset temperature and the preset duration can be selected according to the actual situation and are not limited here. For example, M can be 200, 300 or 400, the preset temperature can be 125°C, and the preset duration can be 1×10 6 s or 1×10 5 s et al.

[0134] According to an embodiment of the present disclosure, the preset resistance value may be 200KΩ. For each of the M target resistance values, if the target resistance value is greater than or equal to 200KΩ, it is considered that the target resistive random access memory corresponding to the target resistance value still has good high-resistance state retention in a high-temperature environment.

[0135] According to the embodiments of the present disclosure, since the M target resistive memories are obtained after performing a first preset number of first erase and write operations on the first resistive memories in the activated state respectively corresponding to the M target resistive memories, and then performing a second preset number of second erase and write operations, the second reset voltage used in the second erase and write operation is obtained by summing the preset voltage value and the average value of the first reset voltage used in the first preset number of first erase and write operations. Therefore, the oxygen ions and oxygen storage layers in the M target resistive memories are relatively stable, so that at a preset temperature, the M target resistive memories are baked for a preset time to obtain M baked resistive memories, and then the resistance values ​​of the M baked resistive memories are respectively tested to obtain M target resistance values. It can be obtained that more target resistance values ​​still remain in the high resistance state range, and a test result is obtained that indicates that more target resistive memories still have good high resistance state retention at high temperatures.

[0136] The following will illustrate, based on the experimental results of FIG. 5 , that the optimization method of the oxide-based resistive random access memory provided by the embodiment of the present disclosure can improve the retention of the oxide-based resistive random access memory.

[0137] FIG5 schematically shows a diagram of a retention test result of an oxide-based resistive random access memory according to an embodiment of the present disclosure.

[0138] FIG5( a ) shows a retention test result of the oxide-based resistive random access memory obtained by baking the oxide-based resistive random access memory after the forming operation and the ISPP operation are performed on the oxide-based resistive random access memory.

[0139] In the detection process of Figure 5(a), the preset temperature is 125°C and the baking time is 1×10 6 s, that is, the baking time is 1×10 6 s, the preset resistance value is 200KΩ, the horizontal axis represents the resistance value of the baked resistive random access memory, and the vertical axis represents the ratio of the number of baked resistive random access memories in each resistance state among the M baked resistive random access memories to M. Therefore, the vertical axis can also be called resistance distribution, where M is 300.

[0140] As shown in Figure 5(a), the dotted lines represent the process of forming 300 oxide-based resistive random access memories, performing 10 ISPP operations, and then baking 1×10 6 s, and the retention test results corresponding to 300 oxide-based resistive random access memories are obtained. The test processes corresponding to the square dotted line, the triangle dotted line, and the star dotted line are all based on the test process corresponding to the circular dotted line, but with the ISPP operation added. The ISPP operation is performed 100 times in the test process corresponding to the square dotted line, 500 times in the test process corresponding to the triangle dotted line, and 1000 times in the test process corresponding to the star dotted line.

[0141] As shown in Figure 5(a), 300 oxide-based resistive random access memories in high resistance state were placed at a high temperature of 125°C and baked for 1×10 6In the case of s, when the number of ISPP operations is 10 times, 27% of the oxide-based resistive random access memories are in a high-resistance failure state, when the number of ISPP operations is 100 times, 28.5% of the oxide-based resistive random access memories are in a high-resistance failure state, when the number of ISPP operations is 500 times, 32% of the oxide-based resistive random access memories are in a high-resistance failure state, and when the number of ISPP operations is 1000 times, 33% of the oxide-based resistive random access memories are in a high-resistance failure state.

[0142] From the analysis of FIG5(a), it can be seen that as the number of ISPP operations increases, the probability of the oxide-based resistive random access memory being in a high-resistance state and failing increases.

[0143] FIG5( b ) is a retention test result of the oxide-based resistive random access memory obtained by baking the target resistive random access memory obtained by the optimization method of the oxide-based resistive random access memory provided by the embodiment of the present disclosure.

[0144] In the detection process of Figure 5(b), the preset temperature is 125°C and the baking time is 1×10 5 s, that is, the baking time is 1×10 5 s, the preset resistance value is 200KΩ, the horizontal axis represents the resistance value of the baked resistive random access memory, and the vertical axis represents the ratio of the number of baked resistive random access memories in each resistance state among the M baked resistive random access memories to M. Therefore, the vertical axis can also be called resistance distribution, where M is 300.

[0145] As shown in Figure 5(b), the dotted lines represent the process of performing a forming operation on 300 oxide-based resistive random access memories, performing 1000 ISPP operations, and then performing 5 second erase and write operations. The 1×10 5 s, and the retention test results corresponding to 300 oxide-based resistive random access memories were obtained. The test processes corresponding to the square dotted line, the triangle dotted line, the diamond dotted line, and the star dotted line are all based on the test process corresponding to the circular dotted line, but with the second erase and write operation added. Specifically, in the test process corresponding to the square dotted line, the second erase and write operation was performed 10 times, in the test process corresponding to the triangle dotted line, the second erase and write operation was performed 15 times, in the test process corresponding to the diamond dotted line, the second erase and write operation was performed 20 times, and in the test process corresponding to the star dotted line, the second erase and write operation was performed 50 times.

[0146] It should be noted that, in order to improve the detection efficiency, in the detection process of Figure 5(b), the star-shaped dotted line in Figure 5(a) is subjected to 1000 ISPP operations and 1×10 6 s 125 ℃ high temperature baking 300 oxide-based resistive random access memories, respectively, the second preset number of second erase and write operations, and then respectively baked at 125 ℃ high temperature 1×10 5 s, the retention test results corresponding to the 300 oxide-based resistive random access memories are obtained. Therefore, the 300 oxide-based resistive random access memories tested in FIG5(b) have been baked for a longer time than the 300 oxide-based resistive random access memories tested in FIG5(a).

[0147] As shown in FIG5(b), after 1000 ISPP operations and the second preset number of second erase and write operations, 300 oxide-based resistive random access memories in a high resistance state were placed at a high temperature of 125°C and baked for 1×10 5 In the case of s, the number of oxide-based resistive random access memories with high resistance state failures corresponding to the number of operations 15 of the second erase and write operation is the least, and the number of oxide-based resistive random access memories with high resistance state failures corresponding to the number of operations 50 of the second erase and write operation is the greatest.

[0148] As shown in Figure 5(b), when the second erase and write operation is performed 15 times, 14.6% of the oxide-based resistive random access memories are in a high-resistance state failure state, and when the second erase and write operation is performed 50 times, 21.8% of the oxide-based resistive random access memories are in a high-resistance state failure state, both of which are less than the 33% number of oxide-based resistive random access memories that fail in the high-resistance state in Figure 5(a) when the second erase and write operation is not performed. Therefore, the experimental results in Figures 5(a) and 5(b) prove that the optimization method of the oxide-based resistive random access memory provided in the embodiment of the present disclosure can improve the retention of the high-resistance state of the oxide-based resistive random access memory in a high-resistance state at high temperature within a preset time, and the method for detecting the retention of the oxide-based resistive random access memory provided in the embodiment of the present disclosure can detect more target resistive random access memories that still have good high-resistance state retention at high temperatures.

[0149] It should be noted that, unless it is explicitly stated that there is a sequence of execution between different operations shown in the flowchart in the embodiments of the present disclosure, or there is a sequence of execution between different operations in technical implementation, otherwise, the execution order between multiple operations may not be prioritized, and multiple operations may also be executed simultaneously.

[0150] Based on the above-mentioned oxide-based resistive random access memory optimization method, the present disclosure further provides an oxide-based resistive random access memory optimization device, which will be described in detail below with reference to FIG6 .

[0151] FIG6 schematically shows a structural block diagram of an optimization device for an oxide-based resistive random access memory according to an embodiment of the present disclosure.

[0152] As shown in FIG. 6 , the device 600 for optimizing an oxide-based resistive random access memory according to this embodiment includes a first obtaining module 610 , a second obtaining module 620 and a third obtaining module 630 .

[0153] The first obtaining module 610 is used to perform a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state. In one embodiment, the first obtaining module 610 can be used to perform the operation S110 described above, which will not be repeated here.

[0154] The second obtaining module 620 is configured to perform a first preset number of first erase / write operations on the first resistive random access memory to obtain a second resistive random access memory in a preset resistance range. In one embodiment, the second obtaining module 620 may be configured to perform the operation S120 described above, which will not be described in detail here.

[0155] The third obtaining module 630 is configured to perform a second preset number of second erase / write operations on the second resistive random access memory to obtain a target resistive random access memory in a preset resistance range, wherein the second reset voltage used in the second erase / write operation is obtained by summing the preset voltage value and the average of the first reset voltages used in the first preset number of first erase / write operations. In one embodiment, the third obtaining module 630 can be configured to perform operation S130 described above and will not be further described herein.

[0156] Based on the above method for detecting the retention of an oxide-based resistive random access memory, the present disclosure further provides a device for detecting the retention of an oxide-based resistive random access memory, which will be described in detail below with reference to FIG.

[0157] FIG7 schematically shows a structural block diagram of an apparatus for detecting retention of an oxide-based resistive random access memory according to an embodiment of the present disclosure.

[0158] As shown in FIG. 7 , the apparatus 700 for detecting the retention of an oxide-based resistive random access memory according to this embodiment includes a fourth obtaining module 710 , a fifth obtaining module 720 and a sixth obtaining module 730 .

[0159] The fourth obtaining module 710 is configured to bake the M target resistive random access memories according to any one of claims 1 to 7 at a preset temperature for a preset time period to obtain M baked resistive random access memories. In one embodiment, the fourth obtaining module 710 can be configured to perform operation S410 described above and will not be further described herein.

[0160] The fifth obtaining module 720 is configured to detect the resistance values ​​of the M baked RRAMs respectively to obtain M target resistance values. In one embodiment, the fifth obtaining module 720 may be configured to execute the operation S420 described above, which will not be described in detail here.

[0161] The sixth obtaining module 730 is configured to compare the M target resistance values ​​with the preset resistance value to obtain a retention detection result. In one embodiment, the sixth obtaining module 730 can be configured to perform the operation S430 described above, which will not be described in detail here.

[0162] The accompanying drawings show some block diagrams and / or flow charts. It should be understood that some blocks in the block diagrams and / or flow charts, or combinations thereof, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when these instructions are executed by the processor, they can create a device for implementing the functions / operations described in the block diagrams and / or flow charts.

[0163] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or to implicitly specify the quantity of the technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of the features.

[0164] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or couplings are intended to fall within the scope of this disclosure.

[0165] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for optimizing an oxide-based resistive random access memory, comprising: Performing a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state; Performing a first preset number of first erase and write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range; A second preset number of second erase and write operations are performed on the second resistive memory to obtain a target resistive memory in a preset resistance state range, wherein a second reset voltage used in the second erase and write operation is obtained by summing a preset voltage value and an average value of first reset voltages respectively used in the first preset number of first erase and write operations.

2. The method according to claim 1, wherein: The preset voltage value is greater than or equal to 0.1V and less than or equal to 0.3V.

3. The method according to claim 1, wherein: The pulse width corresponding to the second reset voltage is greater than or equal to 0.9 us and less than or equal to 2 us.

4. The method according to claim 1, wherein: The performing a second erase / write operation on the second resistive memory for a second preset number of times to obtain a target resistive memory in a preset resistance state range comprises iteratively performing the following operations until the number of iterations meets the second preset number of times: Performing a set sub-operation on the i-th second resistive random access memory to obtain an i-th first set resistive random access memory, wherein i is an integer greater than or equal to 1 and less than a second preset number; Performing a reset sub-operation on the i-th first set resistive random access memory to obtain an i-th target resistive random access memory, wherein a reset voltage used in the reset sub-operation is the second reset voltage; The i-th target resistive random access memory is used as the i+1-th second resistive random access memory, and the i+1-th second erase / write operation is performed.

5. The method according to claim 4, wherein: The setting sub-operation is the same as the setting sub-operation included in the first erase operation.

6. The method according to claim 1, wherein: Before performing a second preset number of second erase / write operations on the second resistive memory to obtain a target resistive memory in a preset resistance state range, the method further includes: Obtaining a first reset voltage used in each of the first preset number of first erase and write operations; averaging a first preset number of the first reset voltages to obtain a reset voltage average value; The reset voltage average value and the preset voltage value are added to obtain the second reset voltage.

7. The method according to claim 1, wherein: The step of performing a first preset number of first erase / write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range comprises: Performing a first preset number of incremental step pulse programming operations on the first resistive memory to obtain a state in a preset resistance state A second resistive memory of the range.

8. A method for detecting the retention of an oxide-based resistive random access memory, comprising: At a preset temperature, baking M target resistive random access memories according to any one of claims 1 to 7 for a preset time to obtain M baked resistive random access memories; The resistance values ​​of the M baked resistive random access memories are detected respectively to obtain M target resistance values; The M target resistance values ​​are compared with a preset resistance value to obtain a retention detection result.

9. An optimization device for an oxide-based resistive random access memory, comprising: A first obtaining module is used to perform a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state; A second obtaining module is used to perform a first preset number of first erase and write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range; The third obtaining module is used to perform a second preset number of second erase and write operations on the second resistive memory to obtain a target resistive memory in a preset resistance state range, wherein the second reset voltage used in the second erase and write operation is obtained by summing a preset voltage value and an average value of the first reset voltages respectively used in the first preset number of first erase and write operations.

10. A device for detecting the retention of an oxide-based resistive random access memory, comprising: A fourth obtaining module, configured to bake the M target resistive random access memories according to any one of claims 1 to 7 for a preset time at a preset temperature to obtain M baked resistive random access memories; A fifth obtaining module is used to detect the resistance values ​​of the M baked resistive random access memories respectively to obtain M target resistance values; The sixth obtaining module is used to compare the M target resistance values ​​with a preset resistance value to obtain a retention detection result.

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