Semiconductor structure and preparation method therefor, and electronic device

Abstract

The present application relates to the technical field of semiconductors. Disclosed in the present disclosure are a semiconductor structure and a preparation method therefor, and an electronic device. The method comprises: providing a substrate, and forming a first laminated structure (104) on the substrate; forming a first mask layer (112) on the first laminated structure (104); using the first mask layer (112) as a mask, and forming in the first laminated structure (104) a first sacrificial layer (218) that extends from the upper surface of the first laminated structure (104) to the upper surface of a first electrically conductive layer (202); removing the first mask layer (112), and alternately forming second mask layers (114) on the first sacrificial layer (218); using the second mask layers (114) as masks, and removing the exposed first sacrificial layer (218); performing lateral etching to remove part of a channel sacrificial layer (204), so as to form first recesses (306) and channel layers (116); removing the second mask layers (114); and performing lateral etching to remove the remaining channel sacrificial layer (204), so as to form second recesses (310) and gate layers (120) that surround the channel layers (116). The requirements for the material of mask layers are reduced, the cost is low, and the manufacturing process is simple.

Description

Semiconductor structure and preparation method thereof, and electronic device

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2023113711138, filed on October 23, 2023, entitled “Semiconductor structure, preparation method thereof, and electronic device,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same, and an electronic device. Background Art

[0004] The statements herein merely provide background information related to the present application and do not necessarily constitute prior art.

[0005] In order to effectively solve the short channel effect, researchers have developed vertical channel transistors with vertically distributed source, gate, and drain, replacing horizontal transistors with horizontally distributed source, gate, and drain, thereby reducing the area occupied by semiconductor units under the same feature size conditions. Under the premise of occupying the same substrate area, vertical channel transistors can increase the effective channel length by increasing the height of the columnar semiconductor material, thereby overcoming the short channel effect. However, in the process of forming the gate layer of the vertical channel transistor in the traditional semiconductor process, the mandrel (core axis) and spacer (side wall) of the hard mask need to be retained for a long time, and the requirements for the materials and etching process of the core axis and side wall are high, making the process difficult and the production cost high.

[0006] Summary of the Invention

[0007] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, as well as an electronic device, which can reduce the process difficulty of vertical transistors and lower production costs.

[0008] The present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate, on which a first stacked structure is formed, the first stacked structure extending in a row direction and arranged at intervals in a column direction, the first stacked structure comprising a first conductive layer, a channel sacrificial layer, and a second conductive layer stacked from bottom to top; forming a first mask layer on the first stacked structure, the first mask layer extending in a column direction and arranged at intervals in a row direction; using the first mask layer as a mask, forming a first sacrificial layer extending from an upper surface of the first stacked structure to an upper surface of the first conductive layer in the first stacked structure; removing the first mask layer, and alternately forming a second mask layer on the first sacrificial layer; using the second mask layer as a mask, removing the exposed first sacrificial layer; laterally etching away a portion of the channel sacrificial layer to form a first groove and a channel layer; removing the second mask layer; laterally etching away the remaining channel sacrificial layer to form a second groove and a gate layer surrounding the channel layer, wherein adjacent gate layers are isolated in the row direction.

[0009] In one embodiment, a portion of the channel sacrificial layer is removed by lateral etching to form a first groove and a channel layer, including: removing a portion of the channel sacrificial layer by lateral etching to form the first groove; removing a portion of the second conductive layer by lateral etching to form a first filling groove connected to the first groove; and forming a channel layer at the bottom of the first groove and in the first filling groove.

[0010] In one embodiment, after removing a portion of the channel sacrificial layer by side etching to form the first groove and the channel layer, the method further includes: performing an annealing process on the channel layer.

[0011] In one embodiment, a first sacrificial layer extending from the upper surface of the first stacked structure to the upper surface of the first conductive layer is formed in the first stacked structure using the first mask layer as a mask, including: using the first mask layer as a mask, patterning the first stacked structure to obtain first grooves exposing the upper surface of the first conductive layer, the first grooves extending along the column direction and arranged at intervals along the row direction; and forming a first sacrificial layer in the first grooves.

[0012] In one embodiment, forming a first mask layer on the first stacked structure includes: forming a protective layer and a first mask layer on the upper surface of the first stacked structure, wherein the first mask layer is located on the protective layer; wherein the second mask layer extends along the row direction to the upper surfaces of the protective layers on both adjacent sides.

[0013] In one embodiment, before the lateral etching is performed to remove the remaining channel sacrificial layer to form the second groove, the process further includes: forming a third mask layer on the first stacked structure, the third mask layer extending along the column direction and exposing the remaining first sacrificial layer; using the third mask layer as a mask, etching to remove the remaining first sacrificial layer; and removing the third mask layer.

[0014] In one embodiment, before forming the third mask layer on the first stacked structure, the method further includes: forming a first dielectric layer at the filling position of the first sacrificial layer exposed by the second mask layer, and the third mask layer extends to cover the top surface of the first dielectric layer; and before forming the gate layer surrounding the channel layer, the method further includes: forming a second dielectric layer at the filling position of the first sacrificial layer covered by the second mask layer.

[0015] In one embodiment, before forming the first mask layer on the first stacked structure, the method further includes: forming a second stacked structure on the substrate between adjacent first stacked structures, the second stacked structure including a third dielectric layer and a second sacrificial layer stacked from bottom to top, the top surface of the third dielectric layer being flush with the top surface of the first conductive layer, and the etching rate of the third dielectric layer being lower than the etching rate of the second sacrificial layer; forming a gate layer surrounding the channel layer, further including: removing at least a portion of the second sacrificial layer between the first groove and the second groove to penetrate the first groove and the second groove to form a first annular groove surrounding the channel layer; wherein the gate layer is located in the first annular groove.

[0016] In one embodiment, removing at least a portion of the second sacrificial layer between the first groove and the second groove includes: simultaneously removing the second sacrificial layer between adjacent first grooves and between adjacent second grooves to form a word line groove; forming a gate layer surrounding the channel layer includes: forming a word line structure located in the word line groove, the word line structure including the gate layer.

[0017] In one embodiment, after forming the gate layer surrounding the channel layer, the process further includes: removing the first dielectric layer, the second dielectric layer, and the third dielectric layer; and forming a first filling layer on the substrate, wherein the bottom of the first filling layer is not lower than the top surface of the gate layer, so as to form a gap between adjacent word line structures and adjacent bit line structures.

[0018] In one embodiment, providing a substrate includes: providing an initial substrate; forming a first stacked structure material layer on the surface of the initial substrate, the first stacked structure material layer including a first conductive material layer, a channel sacrificial material layer, and a second conductive material layer stacked from bottom to top; forming a third trench in the first stacked structure material layer exposing the initial substrate to obtain a first stacked structure, the third trench being located between adjacent first stacked structures; forming a fourth dielectric layer on the sidewall of the third trench, and extending the third trench into the initial substrate; forming a bit line structure located at the bottom of the first stacked structure and a second filling layer located between adjacent bit line structures, the second filling layer being located in the third trench, the bit line structure extending along the row direction and arranged at intervals along the column direction.

[0019] In one embodiment, the upper surface layer of the initial substrate has a doped silicon material layer, and the third trench penetrates the silicon material layer and extends into the initial substrate; a bit line structure located at the bottom of the first stacked structure and a second filling layer located between adjacent bit line structures are formed, including: filling the bottom of the third trench to form a second filling layer and a metal material layer from bottom to top, the top surface of the second filling layer being lower than the top surface of the silicon material layer; using an annealing process to react the metal material layer with the silicon material layer to generate the bit line structure; and removing the remaining metal material layer and the fourth dielectric layer located on the sidewalls of the channel sacrificial layer and the sidewalls of the second conductive layer.

[0020] The present disclosure also provides a semiconductor structure, which is manufactured using the above-mentioned preparation method, and includes: a substrate; a first conductive layer, located on the substrate, extending in the row direction, and arranged at intervals in the column direction; a channel layer, arranged in an array on the top surface of the first conductive layer; a gate layer, located on the top surface of the first conductive layer, surrounding the channel layer, and isolating adjacent gate layers in the row direction; a second conductive layer, located on the top surface of the channel layer, arranged in an array on the channel layer, and in contact with the channel layer.

[0021] In one embodiment, the semiconductor structure further includes: a word line structure extending in the column direction and arranged at intervals in the row direction, surrounding the channel layer, and including a gate layer; a bit line structure located between the substrate and the first conductive layer, electrically connected to the first conductive layer, extending in the row direction and arranged at intervals in the column direction; a second filling layer located in the substrate, extending in the row direction and arranged at intervals in the column direction, and located between adjacent bit line structures. In one embodiment, the semiconductor structure further includes: a first filling layer located on the substrate, the bottom of the first filling layer not lower than the top surface of the gate layer; and gaps located between adjacent bit line structures and between adjacent word line structures. In one embodiment, the semiconductor structure further includes: a contact structure located on the second conductive layer, electrically connected to the second conductive layer, and distributed in an array in a plane parallel to the substrate.

[0022] The present disclosure also provides an electronic device comprising the above-mentioned semiconductor structure.

[0023] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0025] FIG1 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0026] FIG2 is a schematic top view of a semiconductor structure after a second filling layer is formed in one embodiment of the present disclosure;

[0027] FIG3 shows a side view of the semiconductor structure in FIG2 in the row direction;

[0028] FIG4 shows a schematic cross-sectional view of the semiconductor structure at line BB in FIG2 ;

[0029] FIG5 is a schematic top view of a semiconductor structure after a second stacked structure is formed in one embodiment of the present disclosure;

[0030] FIG6 shows a side view of the semiconductor structure in FIG5 in the row direction;

[0031] FIG7 shows a schematic cross-sectional view of the semiconductor structure at line BB in FIG5 ;

[0032] FIG8 is a schematic top view of a semiconductor structure after a first mask layer is formed in one embodiment of the present disclosure;

[0033] FIG9 shows a side view of the semiconductor structure in FIG8 in the row direction;

[0034] FIG10 shows a schematic cross-sectional view of the semiconductor structure at line BB in FIG8 ;

[0035] FIG11 is a schematic top view of a semiconductor structure after a second mask layer is formed in one embodiment of the present disclosure;

[0036] FIG12 shows a side view of the semiconductor structure in FIG11 in the row direction;

[0037] FIG13 is a schematic cross-sectional view of the semiconductor structure at line BB in FIG11 ;

[0038] FIG14 is a schematic top view of a semiconductor structure after a first groove is formed in one embodiment of the present disclosure;

[0039] FIG15 shows a side view of the semiconductor structure in FIG14 in the row direction;

[0040] FIG16 is a schematic cross-sectional view of the semiconductor structure at line BB in FIG14 ;

[0041] FIG17 is a schematic top view of the semiconductor structure after a third sacrificial layer is formed in one embodiment corresponding to FIG14 ;

[0042] FIG18 shows a side view of the semiconductor structure in FIG17 in the row direction;

[0043] FIG19 is a schematic cross-sectional view taken along line BB of the semiconductor structure in FIG17 ;

[0044] FIG20 is a schematic top view of the semiconductor structure after a third mask layer is formed in an embodiment corresponding to FIG17 ;

[0045] FIG21 shows a side view of the semiconductor structure in FIG20 in the row direction;

[0046] FIG22 is a schematic cross-sectional view of the semiconductor structure at line BB in FIG20 ;

[0047] FIG23 is a schematic top view of the semiconductor structure after forming a second dielectric layer in one embodiment corresponding to FIG20 ;

[0048] FIG24 shows a side view of the semiconductor structure in FIG23 in the row direction;

[0049] FIG25 is a schematic cross-sectional view of the semiconductor structure at line BB in FIG23 ;

[0050] FIG26 is a schematic top view of the semiconductor structure after the first annular groove is formed in one embodiment corresponding to FIG23;

[0051] FIG27 is a schematic cross-sectional view of the semiconductor structure in FIG26 taken along line AA;

[0052] FIG28 is a schematic cross-sectional view of the semiconductor structure in FIG26 taken along line BB;

[0053] FIG29 is a schematic top view of a semiconductor structure after a gate layer is formed in an embodiment corresponding to FIG26 ;

[0054] FIG30 is a schematic cross-sectional view of the semiconductor structure in FIG29 taken along line AA;

[0055] FIG31 is a schematic cross-sectional view of the semiconductor structure in FIG29 taken along line BB;

[0056] FIG32 is a schematic top view of the semiconductor structure after the first dielectric layer, the second dielectric layer, and the third dielectric layer are removed in one embodiment corresponding to FIG29 ;

[0057] FIG33 is a schematic cross-sectional view of the semiconductor structure in FIG32 taken along line AA;

[0058] FIG34 shows a schematic cross-sectional view of the semiconductor structure in FIG32 taken along line BB;

[0059] FIG35 shows a side view of the semiconductor structure in FIG32 in the row direction;

[0060] FIG36 shows a side view of the semiconductor structure in FIG32 in the column direction;

[0061] FIG37 is a schematic top view of the semiconductor structure after the first filling layer is formed in one embodiment corresponding to FIG32 ;

[0062] FIG38 is a schematic cross-sectional view of the semiconductor structure in FIG37 taken along line BB;

[0063] FIG39 shows a side view of the semiconductor structure in FIG37 in the row direction;

[0064] FIG. 40 shows a side view of the semiconductor structure in FIG. 37 in the column direction.

[0065] Explanation of reference numerals: 102, initial substrate; 104, first stacked structure; 106, second filling layer; 108, bit line structure; 110, second stacked structure; 112, first mask layer; 114, second mask layer; 116, channel layer; 118, third mask layer; 120, gate layer; 122, word line structure; 124, third filling layer; 126, first filling layer; 202, first conductive layer; 204, channel sacrificial layer; 206, second conductive layer; 208, fourth dielectric layer layer; 210, third dielectric layer; 212, second sacrificial layer; 214, protective layer; 218, first sacrificial layer; 220, third sacrificial layer; 222, first dielectric layer; 224, fourth sacrificial layer; 226, second dielectric layer; 302, third trench; 304, first trench; 306, first groove; 308, first filling groove; 310, second groove; 312, first annular groove; 314, first gap; 316, word line trench; 318, preset gap; 320, gap. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0067] To facilitate understanding of the embodiments of the present disclosure, a more comprehensive description of the embodiments of the present disclosure will be provided below with reference to the accompanying drawings. Preferred embodiments of the embodiments of the present disclosure are shown in the accompanying drawings. However, the embodiments of the present disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the embodiments of the present disclosure. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which the embodiments of the present disclosure pertain. The terms used herein in the description of the embodiments of the present disclosure are intended only to describe specific embodiments and are not intended to limit the embodiments of the present disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. In the description of the embodiments of the present disclosure, it should be understood that the terms "upper," "lower," "vertical," "horizontal," "inner," "outer," and the like, indicating positions or relationships, are based on the methods or relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the embodiments of the present disclosure. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present disclosure. It should be understood that the terms "first," "second," and so forth, as used herein, may be used to describe various elements herein, but these elements are not limited by these terms. These terms are used solely to distinguish a first element from another element. For example, a first dielectric layer may be referred to as a second dielectric layer, and similarly, a second dielectric layer may be referred to as a first dielectric layer, without departing from the scope of this disclosure. The first and second dielectric layers are both dielectric layers, but they are not the same dielectric layer. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance or to implicitly specify the number of technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout this disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. Throughout this disclosure, "several" means at least one, such as one, two, etc., unless otherwise specifically defined. As used herein, the terms "substrate" and "base" refer to and include the base material or structure of the transistors described herein. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.In the present disclosure, the upper surface of the substrate is the surface on which the first stacked structure is formed, the lower surface of the substrate is the surface arranged opposite to the upper surface, and the upper and lower surfaces of other structures or layers are relative to the upper surface of the substrate. For the structure or layer located in the substrate, the two surfaces parallel to the substrate surface, the one close to the upper surface of the substrate is the upper surface / top surface / top / top surface, and the one away from the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom surface. For the structure or layer located on the substrate, on the contrary, the two surfaces close to the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom surface, and the one away from the upper surface of the substrate is the upper surface / top surface / top / top surface. For the structure, trench, hole or layer formed in the semiconductor structure from the substrate surface in the direction away from the substrate, the surface in the longitudinal direction is the sidewall of the structure, trench, hole or layer, and the position where the trench or hole stops is the bottom of the trench or hole.

[0068] As shown in FIG1 , in this embodiment, a method for preparing a semiconductor structure includes:

[0069] S102, providing a substrate, on which a first stacked structure is formed.

[0070] A substrate is provided, on which a first stacked structure is formed. The first stacked structure extends in a row direction within a plane parallel to the substrate and is spaced apart in a column direction within a plane parallel to the substrate. The first stacked structure includes a first conductive layer, a channel sacrificial layer, and a second conductive layer stacked from bottom to top. The constituent materials of the substrate include, but are not limited to, undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the constituent material of the substrate is single crystal silicon. From bottom to top, the first conductive layer, the second conductive layer, and the channel sacrificial layer have the same morphology and are spaced apart so that adjacent first stacked structures do not touch each other. The semiconductor structure includes a vertical gate-all-around transistor. The first stacked structure is a material layer that will subsequently form the vertical gate-all-around transistor. The first conductive layer can serve as a material layer that will subsequently form the drain of the vertical transistor. The second conductive layer can serve as a material layer that will subsequently form the source of the vertical transistor. The channel sacrificial layer can serve as a placeholder layer for the conductive channel of the vertical transistor. It is understood that the source and drain of the vertical transistor can be interchangeable depending on the direction of current flow when the transistor is turned on.

[0071] S104 , forming a first mask layer on the first stacked structure.

[0072] A first mask layer is formed on the first stacked structure. The first mask layer extends along the column direction and is arranged at intervals along the row direction. The first mask layer defines the position of the vertical transistor.

[0073] S106 , using the first mask layer as a mask, forming a first sacrificial layer in the first stacked structure, the first sacrificial layer extending from the upper surface of the first stacked structure to the upper surface of the first conductive layer.

[0074] Using the first mask layer as a mask, the area not covered by the first mask layer is replaced with a first sacrificial layer to form a first sacrificial layer in the first stacked structure extending from the upper surface of the first stacked structure to the upper surface of the first conductive layer. The first sacrificial layer and the first mask layer are alternately arranged in the row direction, and there is a first mask layer located on the first stacked structure between adjacent first sacrificial layers. Through the first mask layer, the first stacked structure extending in the row direction is transformed into a preset transistor structure arranged at intervals in the row direction.

[0075] S108 , removing the first mask layer and alternately forming a second mask layer on the first sacrificial layer.

[0076] The first mask layer is removed, and a second mask layer is alternately formed on the first sacrificial layer. The second mask layer extends in the column direction and is arranged at intervals in the row direction. In the row direction, the second mask layer is not formed on the first sacrificial layer on both sides of the second mask layer. The first mask layer is only etched once in the process of forming the first sacrificial layer. Therefore, the material of the first mask layer only needs to be sufficient for one etching.

[0077] S110 , using the second mask layer as a mask, removing the exposed first sacrificial layer.

[0078] Using the second mask layer as a mask, the first sacrificial layer not covered by the second mask layer is etched until the upper surface of the first conductive layer is exposed.

[0079] S112 , removing a portion of the channel sacrificial layer by side etching to form a first groove and a channel layer.

[0080] The channel sacrificial layer in the preset transistor structure is laterally etched in a direction toward the second mask layer to form a first groove extending in the row direction. The bottom of the first groove exposes the channel sacrificial layer, and then a channel layer is formed. The bottom surface of the channel layer contacts the first conductive layer, and the top surface of the channel layer contacts the second conductive layer. The channel layer serves as a conduction channel of the vertical transistor corresponding to the preset transistor structure. By adjusting the distance between the bottom of the first groove and the adjacent first conductive layer, the positional relationship between the conduction channel (channel layer) of the vertical transistor and the source (second conductive layer) and the drain (first conductive layer) in a plane parallel to the substrate can be adjusted to achieve self-alignment of the conduction channel and the gate layer. The first groove exposes the top surface of the first conductive layer and the bottom surface of the second conductive layer.

[0081] S114, removing the second mask layer.

[0082] The second mask layer is only etched once during the process of removing the first sacrificial layer. The material of the second mask layer also meets the requirements of one etching. Spacing removal means that after the first mask layers are sorted in sequence, the first sacrificial layer with an odd number is removed while the first sacrificial layer with an even number is retained, or the first sacrificial layer with an odd number is retained while the first sacrificial layer with an even number is removed.

[0083] S116 , removing the remaining channel sacrificial layer by side etching to form a second groove and a gate layer surrounding the channel layer.

[0084] A wet etching process is used to laterally etch away the remaining channel sacrificial layer in contact with the channel layer in the predetermined transistor structure. A second recess is formed at the location filled by the remaining channel sacrificial layer, and a gate layer is formed surrounding the channel layer. The gate layer is located in the first recess and the second recess, with the bottom surface of the gate layer contacting the first conductive layer and the top surface of the gate layer contacting the second conductive layer. The gate layer at least partially fills the space between the first recess and the second recess. Adjacent gate layers are isolated in the row direction, i.e., the gate layers in adjacent vertical transistors in the row direction do not contact each other.

[0085] In the above-described method for fabricating a semiconductor structure, a first sacrificial layer extending from the upper surface of the first stacked structure to the upper surface of the first conductive layer is formed in the first stacked structure using a first mask layer as a mask. The first mask layer is removed, and a second mask layer is alternately formed on the first sacrificial layer. The exposed first sacrificial layer is removed using the second mask layer as a mask, and then the second mask layer is removed. The first and second mask layers are etched only once, resulting in a low number of mask layer etchings, which reduces the requirements for mask layer materials, reduces costs, and simplifies the manufacturing process. Furthermore, the semiconductor structure uses the first and second conductive layers as the source and drain of a vertical transistor, respectively, making it easy to control the doping concentrations of the source and drain, thereby improving the performance of the semiconductor structure. A portion of the channel sacrificial layer is removed by lateral etching to form a first recess and a channel layer. Therefore, by controlling the thickness of the channel sacrificial layer between the first and second conductive layers, the channel length between the source and drain can be precisely controlled, thereby improving the uniformity of the conductive channel and further enhancing the performance of the semiconductor structure. The remaining channel sacrificial layer is removed by lateral etching to form a second groove and a gate layer surrounding the channel layer, which simplifies gate alignment and further reduces the difficulty of the process.

[0086] In one embodiment, in the longitudinal direction Z, the thickness of the first conductive layer 202 is equal to the thickness of the second conductive layer 206, making the source and drain symmetrical, reducing the circuit complexity of the semiconductor structure and improving the performance of the semiconductor structure. For example, as shown in Figures 2-7, the X direction is the row direction, the Y direction is the column direction, and the Z direction is the longitudinal direction. As shown in Figures 2-7, in one embodiment, providing the substrate includes: Steps S202-S210.

[0087] S202 , providing an initial substrate 102 .

[0088] S204 , forming a first stacked structure material layer on the surface of the initial substrate 102 , wherein the first stacked structure material layer includes a first conductive material layer, a channel sacrificial material layer, and a second conductive material layer stacked from bottom to top.

[0089] In some embodiments, an epitaxial process is used to form the first conductive material layer, the channel sacrificial material layer, and the second conductive material layer. This process is simple and simplifies the process. Furthermore, the epitaxial process used to grow the first stacked structure material layer can also uniformly control the flatness and thickness of the epitaxial growth of each material layer, which is particularly beneficial for controlling the thickness of the channel sacrificial material layer, thereby controlling the channel length and thickness of the vertical all-around transistor formed in the subsequent process, improving the uniformity of the channel, and thus improving the process accuracy of the vertical all-around transistor. When the semiconductor structure is a memory device, the performance of each memory cell in the memory device can be improved. For example, an in-situ doping process is used to form the first conductive material layer and the second conductive material layer, thereby improving the uniformity of the distribution of dopant ions in the first conductive material layer and the second conductive material layer, reducing the difficulty of controlling the doping of the drain (formed by the first conductive layer 202) and the source (formed by the second conductive layer 206), reducing the difficulty of the process, and simultaneously obtaining symmetrical source and drain electrodes, reducing the circuit complexity of the semiconductor structure and improving the performance of the semiconductor structure.

[0090] S206 , forming a third trench in the first stacked structure material layer to expose the initial substrate, so as to obtain the first stacked structure 104 , wherein the third trench is located between adjacent first stacked structures.

[0091] The first stacked material layer is patterned to form a third trench 302 in the first stacked material layer. The third trench 302 penetrates the first conductive material layer. The bottom of the third trench 302 is lower than the bottom surface of the first conductive material layer or the bottom of the third trench 302 is flush with the bottom surface of the first conductive material layer. In the embodiment of the present disclosure, the bottom of the third trench 302 is flush with the bottom surface of the first conductive material layer for exemplary description. The third trenches 302 extend along the row direction X and are arranged at intervals along the column direction Y. The first stacked material layer between adjacent third trenches 302 serves as the first stacked structure 104. The shape and position of the vertical transistor in the semiconductor structure in the column direction Y are defined by forming the third trench 302. The first stacked structure 104 includes a first conductive layer 202 formed by the remaining first conductive material layer, a channel sacrificial layer 204 formed by the remaining channel sacrificial material layer, and a second conductive layer 206 formed by the remaining second conductive material layer. Exemplarily, the constituent materials of the first conductive layer 202 and the constituent materials of the second conductive layer 206 include, but are not limited to, a silicon-doped layer doped with first conductivity type dopant ions, wherein the first conductive layer 202 and the second conductive layer 206 have the same conductivity type, and the first conductivity type is N-type or P-type. The constituent materials of the channel sacrificial layer 204 include, but are not limited to, germanium silicon materials. It is understood that the channel sacrificial layer 204 can also be replaced with a placeholder layer composed of a material that is easily etched and removed. In some embodiments, the first conductive layer 202 and the second conductive layer 206 have the same dopant ions. In other embodiments, the first conductive layer 202 and the second conductive layer 206 have different dopant ions.

[0092] S208 , forming a fourth dielectric layer 208 on the sidewalls of the third trench 302 , and extending the third trench 302 into the initial substrate 102 .

[0093] Specifically, a fourth dielectric layer 208 is formed on the sidewalls of the third trench 302. A predetermined thickness of the initial substrate 102 exposed at the bottom of the third trench 302 is removed, allowing the third trench 302 to extend into the initial substrate 102. The predetermined thickness is sufficient to isolate the initial substrate 102 at the bottom of the first stacked structure 104. The fourth dielectric layer 208 protects the sidewalls of the first stacked structure 104, preventing the etching of the initial substrate 102 at the bottom of the third trench 302 from affecting the morphology of the first stacked structure 104. It also prevents the metal material layer from reacting with the first conductive layer 202 and the second conductive layer 206 during the subsequent formation of the bitline structure. The third trench 302 separates the upper surface layers of the initial substrate 102 at the bottom of the first stacked structure 104 from each other in the column direction Y.

[0094] In some embodiments, the step of forming the fourth dielectric layer 208 on the sidewalls of the third trench 302 includes: forming a fourth dielectric material layer on the inner wall of the third trench 302 using an atomic layer deposition process, wherein the fourth dielectric material layer extends along the sidewalls of the third trench and covers the top of the first stacked structure 104; and removing the fourth dielectric material layer from the bottom of the third trench 302 and the top of the first stacked structure 104, thereby forming the fourth dielectric layer 208 consisting of the fourth dielectric material layer on the sidewalls of the third trench 302. Exemplarily, removing the fourth dielectric material layer from the bottom of the third trench 302 and etching away a predetermined thickness of the initial substrate 102 exposed at the bottom of the third trench 302 are performed in the same process step. Exemplarily, the materials constituting the fourth dielectric layer 208 include, but are not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), and nitride (e.g., silicon nitride). Exemplarily, the material constituting the fourth dielectric layer 208 is silicon nitride.

[0095] S210 , forming a bit line structure 108 at the bottom of the first stacked structure 104 and a second filling layer 106 between adjacent bit line structures 108 . The second filling layer 106 is located in the third trench 302 . The bit line structures 108 extend along the row direction X and are arranged at intervals along the column direction Y.

[0096] As shown in Figures 5 to 7, step S210 illustratively includes: filling the third trench 302 with a second filling material layer, performing chemical mechanical polishing on the second filling material layer, and etching back to remove a portion of the second filling material layer in the third trench 302, thereby obtaining a second filling layer 106 consisting of the remaining second filling material layer at the bottom of the third trench 302. The second filling layer 106 is used to isolate two adjacent bit line structures 108 in the column direction Y. A bit line structure 108 is formed at the bottom of the first stacked structure 104, wherein the bit line structure 108 is electrically connected to the first conductive layer 202 in the first stacked structure 104. Exemplarily, the top surface of the bit line structure 108 contacts the bottom surface of the first conductive layer 202. In some embodiments, in the row direction, the central axis of the first stacked structure 104 and the central axis of the bit line structure 108 coincide.

[0097] In some embodiments, the initial substrate 102 includes bitline structures 108 and a second filling layer 106 located between adjacent bitline structures 108. The bitline structures 108 and the second filling layer 106 both extend along the row direction X and are spaced apart along the column direction Y. Adjacent bitline structures 108 are separated by the second filling layer 106, which is not limited in this disclosure. Exemplarily, the constituent material of the second filling layer 106 includes, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), and nitride (e.g., silicon nitride). Exemplarily, the constituent material of the second filling layer 106 is silicon dioxide.

[0098] As shown in Figures 2 to 7, in some embodiments, the upper surface layer of the initial substrate 102 has a silicon material layer. The initial substrate 102 above the dotted line L in the figure is a silicon material layer. Exemplarily, the conductivity type of the silicon material layer is the same as that of the first conductive layer. The initial substrate 102 includes an upper surface layer and a lower surface layer composed of a portion other than the upper surface layer. The lower surface layer has a second conductivity type. A PN junction (at the position of the dotted line L) is formed between the lower surface layer and the upper surface layer. The leakage between adjacent bit line structures 108 is reduced by the PN junction and the second filling layer 106. Optionally, an injection process is used to inject dopant ions into the initial substrate 102 to obtain a silicon material layer located on the upper surface layer of the initial substrate 102, or an in-situ doping process is used to form a silicon material layer on the upper surface of the lower surface layer to obtain the initial substrate 102. The present disclosure does not impose any restrictions on this. In this embodiment, the third trench 302 penetrates the silicon material layer and extends into the initial substrate 102 ; forming the bit line structure 108 at the bottom of the first stacked structure 104 and the second filling layer 106 between adjacent bit line structures 108 includes steps S302 to S306 .

[0099] S302 , forming a second filling layer 106 and a metal material layer from bottom to top at the bottom of the third trench 302 , wherein the top surface of the second filling layer 106 is lower than the top surface of the silicon material layer.

[0100] In some embodiments, after forming the second filling layer 106, the initial substrate 102 (silicon material layer) is laterally etched based on the third trench 302 to form a metal filling trench. This prevents the silicon material layer from remaining in the formed bitline structure 108, which would increase the resistance of the bitline structure 108 and delay, and also prevents contact between adjacent bitline structures 108 after the bitline structure 108 is formed. Exemplarily, the top surface of the second filling layer 106 is higher than the bottom surface of the silicon material layer. This arrangement increases the size of the bitline structure 108 in the column direction Y while preventing contact between adjacent bitline structures 108.

[0101] In some embodiments, an initial metal material layer filling the third trench 302 is formed on the second filling layer 106 by deposition and chemical mechanical polishing processes, and the fourth dielectric layer 208 realizes isolation between the initial metal material layer and the sidewalls of the first stacked structure 104. Then, a portion of the thickness of the initial metal material layer is removed by etching back to obtain a metal material layer composed of the remaining initial metal material layer. The metal material layer at least covers the sidewalls of the silicon material layer exposed by the third trench 302 (the inner wall of the metal filling groove or the sidewall of the third trench 302 close to the second filling layer 106). Exemplarily, the metal material layer fills the third trench 302 between the metal filling groove and the metal filling groove, and the top surface of the metal material layer is flush with the top surface of the silicon material layer or the top surface of the metal material layer is higher than the top surface of the silicon material layer. In some embodiments, the constituent material of the metal material layer includes but is not limited to titanium nitride, metal tungsten, metal molybdenum, metal cobalt, metal aluminum, etc. The metal material layer reacts with the silicon material layer to form metal silicide. The present disclosure does not limit the constituent material of the metal material layer.

[0102] S304 , using an annealing process to react the metal material layer with the silicon material layer to form a bit line structure.

[0103] Annealing is performed to react the metal material layer with the silicon material layer below the first conductive layer 202 to generate metal silicide as the bit line structure 108 . In the column direction, the metal silicides (bit line structures 108 ) below adjacent first conductive layers 202 do not contact each other.

[0104] S306 , removing the remaining metal material layer and the fourth dielectric layer located on the sidewalls of the channel sacrificial layer and the sidewalls of the second conductive layer.

[0105] A wet process is used to remove the metal material layer that has not reacted with the silicon material layer to isolate adjacent bit line structures 108 and avoid electrical connection problems between adjacent bit line structures 108. The fourth dielectric layer 208 located on the sidewalls of the channel sacrificial layer and the fourth dielectric layer 208 on the sidewalls of the second conductive layer are removed.

[0106] In some embodiments, before forming the first mask layer on the first stacked structure, the method further includes forming a second stacked structure on the substrate between adjacent first stacked structures, that is, forming the second stacked structure on the second filling layer. Specifically, a second stacked structure 110 is formed on the second filling layer 106. The second stacked structure 110 includes a third dielectric layer 210 and a second sacrificial layer 212 stacked from bottom to top. The top surface of the third dielectric layer 210 is flush with the top surface of the first conductive layer 202. The etching rate of the third dielectric layer 210 is lower than the etching rate of the second sacrificial layer 212. When the second sacrificial layer 212 is subsequently etched away, the third dielectric layer 210 acts as an etch stop layer. The bottom of the first trench 304 is flush with the top surface of the third dielectric layer 210. The bottom surface of the first sacrificial layer 218 is in contact with both the top surface of the third dielectric layer 210 and the top surface of the first conductive layer 202. Illustratively, the top surface of the second sacrificial layer 212 is flush with the top surface of the first stacked structure 104 .

[0107] It is understood that when the etching rate of the fourth dielectric layer 208 is greater than the etching rate of the second sacrificial layer 212, the fourth dielectric layer 208 on the sidewalls of the first conductive layer 202 can be removed or retained. In this case, the retained fourth dielectric layer 208 and the third dielectric layer 210 together serve as an etch stop layer for etching the second sacrificial layer 212. When the etching rate of the fourth dielectric layer 208 is less than or equal to the etching rate of the second sacrificial layer 212, the step of removing the fourth dielectric layer 208 on the sidewalls of the first conductive layer 202 is further included before forming the second stacked structure 110 on the second filling layer 106. The figures of this disclosure illustrate the exemplary embodiment of retaining the fourth dielectric layer 208 on the sidewalls of the first conductive layer 202 before forming the second stacked structure 110 on the second filling layer 106. Exemplary materials constituting the third dielectric layer 210 and the second sacrificial layer 212 include, but are not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), and nitride (e.g., silicon nitride). Optionally, the third dielectric layer 210 and the fourth dielectric layer 208 are made of the same material. For example, the third dielectric layer 210 is made of silicon nitride, and the second sacrificial layer 212 is made of silicon dioxide.

[0108] As shown in Figures 8-11, in one embodiment, forming a first mask layer on the first stacked structure includes: forming a protective layer 214 and a first mask layer 112 on the upper surface of the first stacked structure, with the first mask layer 112 located on the protective layer 214. Exemplarily, the protective layer 214 is formed of silicon nitride, and the first mask layer 112 is formed of a photoresist, a spin-on material, and an anti-reflective coating. The first mask layer 112 extends along the column direction Y and is arranged at intervals along the row direction X. The first mask layer 112 defines the shape and position of the vertical transistors in the semiconductor structure along the row direction X. Using the first mask layer 112 as a mask, a first sacrificial layer is formed in the first stacked structure 104, extending from the upper surface of the first stacked structure 104 to the upper surface of the first conductive layer 202, including steps S402 to S404.

[0109] S402 , using the first mask layer 112 as a mask, patterning the first stacked structure 104 to obtain first trenches 304 exposing the upper surface of the first conductive layer 202 . The first trenches 304 extend along the column direction Y and are arranged at intervals along the row direction X. Using the first mask layer 112 as a mask, the second conductive layer 206 not covered by the first mask layer 112, the channel sacrificial layer 204 exposed by the second conductive layer 206, and the second sacrificial layer 212 not covered by the first mask layer 112 are etched away to obtain first trenches 304 located on opposite sides of the first mask layer 112 in the row direction, and a preset transistor structure distributed in an array on a plane composed of the remaining second conductive layer 206, the channel sacrificial layer 204, and the first conductive layer 202 thereunder. The first conductive layers 202 in the preset transistor structures in the same row are in contact with each other, wherein the first trenches 304 extend along the column direction Y and are arranged at intervals along the row direction X, that is, the first trenches 304, the first mask layer 112, the first trenches 304, and the first mask layer 112 are arranged in sequence in the row direction X. Then the first mask layer 112 is removed. It can be understood that the first mask layer 112 can be removed while etching away the second conductive layer 206, the channel sacrificial layer 204 and the second sacrificial layer 212, or the first mask layer 112 can be removed after etching away the second conductive layer 206, the channel sacrificial layer 204 and the second sacrificial layer 212. For example, the first mask layer 112 can be removed before or after forming the first sacrificial layer 218. The present disclosure only provides an illustrative description of one of the methods. The first mask layer 112 is only used as a mask during the process of etching to form the first groove 304. Only one etching is required, and the material requirements for the first mask layer 112 are not high.

[0110] S404 , forming a first sacrificial layer 218 in the first trench 304 . The first sacrificial layer 218 is filled in the first trench 304 by deposition (atomic layer vapor deposition or chemical vapor deposition) and chemical mechanical polishing processes.

[0111] In some embodiments, second mask layers 114 are alternately formed on the first sacrificial layers 218, and the second mask layers 114 extend to the upper surfaces of the adjacent protective layers 214 on both sides. In the row direction X, second mask layers 114 are alternately formed on the first sacrificial layers 218 in the first trenches 304, and the second mask layers 114 extend along the top surfaces of the first sacrificial layers 218 to cover the upper surfaces of the adjacent protective layers 214. The second mask layers 114 also extend in the column direction Y and are arranged in intervals in the row direction X. In the row direction X, the first sacrificial layers 218 not covered by the second mask layers 114 are located between adjacent second mask layers 114. Exemplarily, the second mask layers 114 extend to the entire surface of the adjacent protective layers 214 on both sides, or to the portion of the surface adjacent to the first sacrificial layers 218 where the second mask layers 114 are formed. Using the second mask layer 114 as a mask, the exposed first sacrificial layer 218 is etched away to expose the unfilled first trench 304. The presence of the self-aligned protective layer 214 can prevent overlay errors in forming the second mask layer 114, which may cause damage to the second conductive layer in the predetermined transistor structure during the etching and removal of the first sacrificial layer 218 in the first trench 304 not covered by the second mask layer 114. The second mask layer 114 only needs to be etched once to remove the first sacrificial layer 218 not covered by the second mask layer 114. During the lateral etching and removal of a portion of the channel sacrificial layer 204, the presence or absence of the second mask layer 114 has no effect, thereby reducing the requirements for the material of the second mask layer 114. Exemplarily, the constituent materials of the second mask layer 114 include, but are not limited to, photoresist.

[0112] As shown in Figures 14 to 19, based on the lateral etching of the first groove 304 (the filling position of the first sacrificial layer 218 not covered by the second mask layer 114), the channel sacrificial layer 204 is exposed to form a first groove 306 located between the first conductive layer 202 and the second conductive layer 206. The sidewalls of the first groove 306 simultaneously expose the top surface of the first conductive layer 202 and the bottom surface of the second conductive layer 206, wherein the dimensions of the first groove 306 in the longitudinal direction Z and the column direction Y are the same as those of the channel sacrificial layer 204.

[0113] As shown in FIG14 to FIG19 , in one embodiment, the lateral etching is performed to remove a portion of the channel sacrificial layer 204 to form a first groove 306 and a channel layer 116, including: lateral etching to remove a portion of the channel sacrificial layer 204 to form the first groove 306; lateral etching to remove a portion of the second conductive layer 206 to form a first filling groove 308 connected to the first groove 306, that is, the second conductive layer 206 is lateral-etched based on the first groove 304 and the first groove 306 to form the first filling groove 308, the bottom of the first filling groove 308 exposing the second conductive layer 206; and the channel layer is formed at the bottom of the first groove 306 and in the first filling groove 308. Exemplarily, the channel layer 116 fills the first filling groove 308. FIG16 illustrates an example of lateral etching of the second conductive layer 206 (illustrated as an L-shaped groove on the sidewall of the second conductive layer 206 in the figure), wherein the first filling groove 308, the first recess 306, and the first trench 304 are interconnected. Forming the first filling groove 308 allows the channel layer 116 to be filled in the first filling groove 308 surrounding the sidewalls and a portion of the bottom of the second conductive layer 206 during the subsequent formation of the channel layer 116. This prevents the channel layer 116 from covering the sidewalls of the second conductive layer 206 exposed in the first trench 304, which would otherwise cause the vertical transistor sidewalls to partially protrude in the longitudinal direction Z and be asymmetric in the row direction, thus affecting subsequent process flow. Furthermore, the channel layer 116 located between the bottom surface of the second conductive layer 206 and the gate layer in the first filling groove 308 and the channel layer 116 located at the bottom of the first recess 306 together serve as the conduction channel of the vertical transistor, increasing the length of the conduction channel in the vertical transistor while maintaining the thickness of the channel sacrificial layer 204. It can be understood that in the process of etching to form the first filling groove 308 and the first groove 306, the top surface of the first conductive layer 202 is etched at the same time, so that the first groove 306 and the first groove 304 extend into the first conductive layer 202 in the longitudinal direction Z to form an extension groove (not shown in the figure), and the subsequently formed channel layer 116 is simultaneously filled in the extension groove. The channel layer 116 located between the top surface of the first conductive layer 202 and the gate layer in the extension groove and the channel layer 116 located at the bottom of the first groove 306 together serve as the conduction channel of the vertical transistor, further increasing the length of the conduction channel in the vertical transistor while keeping the thickness of the channel sacrificial layer 204 unchanged.

[0114] As shown in Figures 17 and 19, a channel layer 116 is formed at the bottom of the first groove 306. The channel layer 116 covers the sidewalls of the channel sacrificial layer 204 exposed by the first groove 306. The channel layer 116 is located between the top surface of the first conductive layer 202 and the bottom surface of the second conductive layer 206, and is in contact with the top surface of the first conductive layer 202 and the bottom surface of the second conductive layer 206, serving as a channel between the first conductive layer 202 and the second conductive layer 206. Exemplarily, silicon material is selected as the channel layer 116, and the channel layer 116 is formed by an epitaxial growth process.

[0115] As shown in Figures 17 to 19, in one embodiment, after removing part of the channel sacrificial layer 204 by lateral etching to form the first groove 306 and the channel layer 116, it also includes: performing an annealing process on the channel layer 116 to improve the contact between the channel layer 116 and the first conductive layer 202 and the second conductive layer 206.

[0116] As shown in Figures 17-19, in one embodiment, after forming the channel layer 116 at the bottom of the first groove 306, the process further includes filling the first groove 306 with a third sacrificial layer 220. Specifically, after forming the channel layer 116, a third sacrificial material layer is formed in the first trench 304. The third sacrificial material layer completely fills the first groove 306 and provides support. Exemplarily, the third sacrificial material layer is formed using a chemical deposition process and a chemical mechanical polishing process, with the top surface of the third sacrificial material layer being flush with the top surface of the second mask layer 114. The third sacrificial material layer in the first trench 304 is then removed to obtain a third sacrificial layer 220 consisting of the remaining third sacrificial material layer in the first groove 306. Filling the first groove 306 with the third sacrificial layer 220 prevents the subsequently formed first dielectric layer 222 from filling the first groove 206. This would result in excessive etching of the first dielectric layer 222 when forming the first annular groove for filling the gate layer, thereby affecting the isolation between adjacent gate layers in the row direction X. In some embodiments, the material constituting the third sacrificial layer 220 includes, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), and nitride (e.g., silicon nitride). Exemplarily, the material constituting the third sacrificial layer 220 is silicon dioxide. In one embodiment, after forming the channel layer 116, the step of removing the second mask layer 114 is further included. Exemplarily, the second mask layer 114 is removed after forming the third sacrificial layer 220.

[0117] As shown in FIG. 20 to FIG. 22 , in one embodiment, before the remaining channel sacrificial layer 204 is removed by side etching to form the second groove, steps S502 to S504 are further included.

[0118] S502 , forming a third mask layer 118 on the first stacked structure 104 . The third mask layer 118 extends along the column direction Y and is arranged at intervals along the row direction X, exposing the remaining first sacrificial layer 218 .

[0119] A third mask layer 118 is formed on the first stacked structure 104. The third mask layer 118 exposes the remaining first sacrificial layer 218. The third mask layer 118 extends along the column direction Y and is arranged at intervals along the row direction X. The same third mask layer 118 is located on the preset transistor structures arranged in the same column. The remaining first sacrificial layer 218 is the first sacrificial layer 218 covered (protected) by the second mask layer 114.

[0120] S504 , using the third mask layer 118 as a mask, etching away the remaining first sacrificial layer 218 .

[0121] Using the third mask layer 118 as a mask, all the first sacrificial layer 218 extending along the column direction in the first stacked structure 104 that is retained using the second mask layer 114 is etched away to expose the unfilled first trenches 304 .

[0122] As shown in Figures 20-22, in one embodiment, before forming the third mask layer 118 on the first stacked structure 104, the process further includes: forming a first dielectric layer 222 in the locations (first trenches 304) exposed by the second mask layer 114 where the first sacrificial layer 218 is filled. The etching rate of the first dielectric layer 222 is lower than the etching rate of the third sacrificial layer 220, and the third mask layer 118 extends to cover the top surface of the first dielectric layer 222. Exemplarily, the third mask layer 118 extends to the entire surface of the first dielectric layer 222, or to a portion of the surface of the first dielectric layer 222 adjacent to the third mask layer 118. Chemical vapor deposition and chemical mechanical polishing processes are used to form the first dielectric layer 222 in the locations (first trenches 304) exposed by the second mask layer 114 where the first sacrificial layer 218 is filled. The first dielectric layer 222 supports the third mask layer 118 while isolating the subsequently formed gate layers in the row direction, thereby isolating adjacent gate layers in the row direction. Exemplarily, the first dielectric layer 222 fills the first trench 304, and the top surface of the first dielectric layer 222 is flush with the top surface of the protective layer 214 (first sacrificial layer 218). The third mask layer 118 exposes the first sacrificial layer 218 covered by the second mask layer 114. In the row direction X, the protective layer 214 between adjacent first sacrificial layers 218 covered by the second mask layer 114 is located below the same third mask layer 118, that is, the first sacrificial layers 218 covered by the second mask layer 114 are located between adjacent third mask layers 118. During the removal of the first sacrificial layers 218 covered by the second mask layer 114, the self-aligned protective layer 214 can also avoid the problem of overlay error in the formation of the third mask layer 118, which may cause the predetermined transistor structure to be etched in the longitudinal direction Z during the etching and removal of the first sacrificial layer 218. Exemplarily, the constituent materials of the third mask layer 118 include, but are not limited to, photoresist and anti-reflective coating.

[0123] As shown in Figures 23-25, using the third mask layer 118 as a mask, the remaining first sacrificial layer 218 (the first sacrificial layer 218 covered by the second mask layer 114) is etched away, exposing the first trench 304 covered by the second mask layer 114. Lateral etching is performed based on the first trench 304 covered by the second mask layer 114 to remove the remaining channel sacrificial layer 204, that is, to remove the remaining channel sacrificial layer between the first conductive layer and the second conductive layer (the remaining channel sacrificial layer in the preset transistor structure), thereby forming a second groove located between the first conductive layer 202 and the second conductive layer 206. The bottom of the second groove exposes the channel layer 116, and the second groove and the first groove are arranged opposite each other in the row direction. The definition of the second groove can refer to the description of the first groove 306 in the above embodiment, and will not be repeated here. The third mask layer 118 only needs to be etched once to remove the first sacrificial layer 218 covered by the second mask layer 114. During the process of lateral etching to remove the remaining channel sacrificial layer 204, the presence or absence of the third mask layer 118 has no effect, which reduces the requirements for the material of the third mask layer 118.

[0124] As shown in Figures 23-25, in one embodiment, after forming the second groove exposing the channel layer 116, the process further includes filling the second groove with a fourth sacrificial layer 224. Specifically, after forming the second groove, a fourth sacrificial material layer is formed in the first trench 304 connected to the second groove. The fourth sacrificial material layer fills the second groove and provides support. Exemplarily, the fourth sacrificial material layer is formed using a chemical deposition process and a chemical mechanical polishing process, with the top surface of the fourth sacrificial material layer being flush with the top surface of the third mask layer 118. Then, the fourth sacrificial material layer in the first trench 304 connected to the second groove is removed to obtain a fourth sacrificial layer 224 composed of the fourth sacrificial material layer remaining in the second groove. Filling the second groove with the fourth sacrificial layer 224 prevents the subsequently formed second dielectric layer 226 from filling the second groove, which would result in excessive etching of the second dielectric layer 226 when forming the first annular groove for filling the gate layer, thereby affecting the isolation between adjacent gate layers in the row direction X. In some embodiments, the fourth sacrificial layer 224 is made of a material including, but not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), or nitride (e.g., silicon nitride). The material of the fourth sacrificial layer 224 may be the same as or different from the material of the third sacrificial layer 220. Exemplarily, the fourth sacrificial layer 224 is made of silicon dioxide. In some embodiments, the etching rate of the fourth sacrificial layer 224 is the same as the etching rate of the third sacrificial layer 220, thereby simultaneously removing the third sacrificial layer 220 in the first groove 306 and the fourth sacrificial layer 224 in the second groove, thereby reducing the difficulty of the process and lowering production costs.

[0125] Continuing to refer to Figures 23 to 25, in one embodiment, before forming the gate layer surrounding the channel layer 116, the process further includes: filling and forming a second dielectric layer 226 at the filling position (first trench 304) of the first sacrificial layer 218 covered by the second mask layer 114. The etching rate of the second dielectric layer 226 is lower than the etching rate of the fourth sacrificial layer 224. A chemical vapor deposition and chemical mechanical polishing process is used to fill and form the second dielectric layer 226 in the first trench 304 connected to the second groove. The second dielectric layer 226 isolates the subsequently formed gate layer in the row direction, that is, achieves isolation of adjacent gate layers in the row direction. Exemplarily, the second dielectric layer 226 fills the first trench 304 covered by the second mask layer 114, and the top surface of the second dielectric layer 226 is flush with the top surface of the protective layer 214.

[0126] As shown in Figures 26-28, in one embodiment, before forming the gate layer surrounding the channel layer 116, the steps further include: removing the third mask layer 118 to expose the first dielectric layer 222 below the third mask layer 118; removing the protective layer 214 and the first dielectric layer 222 above the top surface of the second conductive layer 206 so that the top surface of the first dielectric layer 222 is flush with the top surface of the second conductive layer 206. At this time, the second conductive layer 206 and the second sacrificial layer 212 below the protective layer 214 are exposed. When the channel layer 116 is formed on the sidewalls of the second conductive layer 206, the channel layer 116 below the protective layer 214 and located on the sidewalls of the second conductive layer 206 is also exposed. Exemplarily, the step of removing the third mask layer 118 occurs after etching away the remaining first sacrificial layer using the third mask layer as a mask, and before laterally etching away the remaining channel sacrificial layer to form the second recess.

[0127] As shown in Figures 26 to 28, in one embodiment, before forming the gate layer surrounding the channel layer 116 in the first groove and the second groove, it also includes: removing at least part of the second sacrificial layer 212 between the first groove 306 and the second groove 310 to penetrate the first groove 306 and the second groove 310 to form a first annular groove 312 surrounding the channel layer 116, the first annular groove 312 includes the first groove 306 and the second groove 310, and the gate layer is located in the first annular groove. Specifically, when the first groove 306 is filled with the third sacrificial layer 220 and the second groove 310 is filled with the fourth sacrificial layer 224, at least a portion of the second sacrificial layer 212 between the first groove 306 and the second groove 310 is removed to form a first gap 314 that exposes the sidewalls of the third sacrificial layer 220 and the sidewalls of the fourth sacrificial layer 224. Then, the third sacrificial layer 220 and the fourth sacrificial layer 224 are removed so that the first groove 306 and the second groove 310 are connected by the first gap, thereby forming a first annular groove 312 surrounding the channel layer 116. The first annular groove 312 includes the first groove 306, the second groove 310, and a portion of the first gap 314 between the first groove 306 and the second groove 310 (the first gap 314 is not higher than the bottom surface of the second conductive layer 206). In a plane parallel to the substrate (a plane where the X and Y directions are located), the first annular groove 312 exposes the sidewalls of the channel layer 116.

[0128] As shown in Figures 26 to 28, in one embodiment, at least a portion of the second sacrificial layer 212 between the first groove 306 and the second groove 310 is removed, including: simultaneously removing the second sacrificial layer 212 between adjacent first grooves 306 and between adjacent second grooves 310 to form word line grooves 316, the word line grooves 316 including adjacent first grooves 306 and adjacent second grooves 310, the word line grooves 316 extending along the column direction and arranged at intervals along the row direction, adjacent word line grooves 316 are isolated by the second dielectric layer 226 or the first dielectric layer 222, and the channel layers 116 arranged at intervals in the same column are surrounded by the same word line groove 316. At this time, the bottom of the first gap 314 is exposed to the third dielectric layer 210. The gate layer 120 surrounding the channel layer 116 is formed in the first groove and the second groove, including: forming a word line structure 122 located in the word line trench 316, the word line structure 122 includes a gate layer 120, and the gate layers 120 surrounding two adjacent channel layers 116 in the same column are connected to each other.

[0129] As shown in Figures 29-31, a gate layer 120 is formed in the first annular groove 312, surrounding the channel layer 116. The gate layer 120 is in contact with both the first conductive layer 202 and the second conductive layer 206, and fills the first groove 306 and the second groove 310. In the row direction X, adjacent gate layers 120 are isolated by the second dielectric layer 226 or the first dielectric layer 222. Specifically, a gate material layer is formed in the first annular groove 312 and the first gap 314, and the gate material layer above the top surface of the channel layer 116 (the bottom surface of the second conductive layer 206) is etched away to obtain a gate layer 120 composed of the remaining gate material layer. Exemplarily, the gate layer 120 fills the first annular groove 312, that is, the first groove 306, the second groove 310, and the portion of the first gap 314 located between the first groove 306 and the second groove 310 of the gate layer 120. In one embodiment, the gate layer 120 includes a gate dielectric layer conformally covering the inner wall of the first annular groove 312 and a gate conformally covering the gate dielectric layer. The gate contacts the first conductive layer 202 , the channel layer 116 and the second conductive layer 206 through the gate dielectric layer.

[0130] In some embodiments, the gate dielectric layer is formed of a material including, but not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (with a dielectric constant greater than 3.9), low-k dielectric material (with a dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (with a dielectric constant less than 2.5), ferroelectric material, anti-ferroelectric material, carbide (e.g., silicon carbide), or a combination thereof. Exemplary high-k materials include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). Optionally, the gate material includes but is not limited to one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0131] As shown in Figures 29 to 31, in one embodiment, after forming the gate layer 120 surrounding the channel layer 116 in the first groove and the second groove, the method further includes: forming a third filling layer 124 on the gate layer 120. Exemplarily, the third filling layer 124 fills the first gap 314, and the top surface of the third filling layer 124 is flush with the top surface of the second conductive layer 206. The third filling layer 124 protects the gate layer 120 from the external environment while obtaining a semiconductor structure with a smooth surface. Optionally, the constituent material of the third filling layer 124 includes, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), and nitride (e.g., silicon nitride). The constituent material of the third filling layer 124 is the same as or different from the constituent material of the second filling layer 106.

[0132] As shown in Figures 32 to 40, in one embodiment, after forming the gate layer 120 surrounding the channel layer 116, the process further includes: removing the first dielectric layer 222, the second dielectric layer 226, and the third dielectric layer 210, and forming a first filling layer 126 on the substrate. The bottom of the first filling layer 126 is not lower than the top surface of the gate layer 120, so as to form a gap between the first filling layer and the substrate (between adjacent word line structures and adjacent bit line structures). Specifically, the first dielectric layer 222, the second dielectric layer 226, and the third dielectric layer 210 are removed by wet etching to form a predetermined gap 318 located at the first dielectric layer 222, the second dielectric layer 226, and the third dielectric layer 210. Then, a deposition process with a high deposition rate is used to form a first filling layer 126 on the initial substrate 102. In this case, the first filling layer is filled between adjacent second conductive layers 206 and second conductive layers 206, and / or between adjacent second conductive layers 206 and channel layers 116. At the same time, the bottom surface of the first filling layer 126 is not lower than the top surface of the gate layer 120 (the bottom surface of the second conductive layer 206), thereby sealing the predetermined gap 318 and forming a gap 320 located between adjacent bit line structures 108 and adjacent word line structures 122, thereby reducing parasitic capacitance and minimizing RC delay of data in the semiconductor structure.

[0133] In one embodiment, a shallow trench isolation structure is formed in the substrate, which isolates a plurality of spaced active regions in the substrate. The semiconductor structure is located in the active region. The gap 320 is also located between the first filling layer 126 and the adjacent shallow trench isolation structure, between the bit line structure 108 and the adjacent shallow trench isolation structure, and between the word line structure 122 and the adjacent shallow trench isolation structure. It is understood that when the dielectric constant of the fourth dielectric layer 208 is less than the dielectric constant of air, the fourth dielectric layer 208 on the sidewalls of the first conductive layer 202 is retained. When the dielectric constant of the fourth dielectric layer 208 is greater than the dielectric constant of air, the fourth dielectric layer 208 on the sidewalls of the first conductive layer 202 is removed simultaneously with the removal of the first dielectric layer 222, the second dielectric layer 226, and the third dielectric layer 210. In some embodiments, the first dielectric layer 222 , the second dielectric layer 226 and the third dielectric layer 210 are made of the same material, such as silicon nitride, thereby reducing the difficulty of etching the first dielectric layer 222 , the second dielectric layer 226 and the third dielectric layer 210 and lowering the cost.

[0134] It should be understood that, although the various steps in the flowchart of FIG1 are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in FIG1 may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0135] As shown in Figures 32 to 40, the present disclosure also provides a semiconductor structure, including: a substrate (initial substrate 102), a first conductive layer 202, a channel layer 116, a gate layer 120 and a second conductive layer 206, wherein the first conductive layer 202 is located on the substrate, extends along the row direction X in a plane parallel to the substrate, and is arranged at intervals along the column direction Y in a plane parallel to the substrate; the channel layer 116 is arranged in an array on the top surface of the first conductive layer 202; the gate layer 120 is located on the top surface of the first conductive layer 202, surrounds the channel layer 116, and isolates adjacent gate layers 120 in the row direction X; the second conductive layer 206 is located on the top surface of the channel layer 116, is arranged in an array on the channel layer 116, and is in contact with the channel layer 116. The semiconductor structure includes a vertical gate-all-around transistor, wherein the first conductive layer 202 serves as the drain of the subsequent vertical transistor, the second conductive layer 206 serves as the source of the vertical transistor, and the channel layer 116 located between the first conductive layer 202 and the second conductive layer 206 serves as the channel of the vertical transistor. The limitations on the constituent materials of the first conductive layer 202, the second conductive layer 206, and the channel layer 116 in this disclosure are described in the corresponding descriptions in the above embodiments and are not limited here. The above-mentioned semiconductor structure, with the first conductive layer and the second conductive layer serving as the source and drain of the vertical transistor, makes it easy to control the doping of the source and drain, thereby reducing the circuit complexity of the semiconductor structure and improving the performance of the semiconductor structure.

[0136] In one embodiment, in the column direction Y, the size of the channel layer 116 is equal to the size of the first conductive layer 202. In one embodiment, in the longitudinal direction Z, the thickness of the first conductive layer 202 is equal to the thickness of the second conductive layer 206, so that the source and drain are symmetrical, reducing the circuit complexity of the semiconductor structure and improving the performance of the semiconductor structure.

[0137] In one embodiment, the semiconductor structure further includes: a bit line structure 108, located between the substrate and the first conductive layer 202, electrically connected to the first conductive layer 202, extending along the row direction X and arranged at intervals along the column direction Y; used to send data to be stored to the storage device corresponding to the first conductive layer 202 connected thereto or receive data stored in the corresponding storage device. In some embodiments, the top surface of the bit line structure 108 contacts the bottom surface of the first conductive layer 202. In some embodiments, in the row direction, the central axis of the second conductive layer 206 coincides with the central axis of the bit line structure 108. Optionally, the constituent material of the bit line structure 108 includes a metal silicide structure. In one embodiment, in the row direction X, the distances between the opposite sidewalls of the channel layer 116 and the second conductive layer 206 are equal.

[0138] As shown in Figures 32 to 34, in one embodiment, the semiconductor structure further includes: a second filling layer 106, located in the substrate, extending along the row direction X and arranged at intervals along the column direction Y, located between adjacent bit line structures 108, and used to isolate adjacent bit line structures 108 in the column direction Y.

[0139] As shown in Figures 32 to 34, in one embodiment, the semiconductor structure further includes: a word line structure 122, which extends along the column direction Y and is arranged at intervals along the row direction X, is located between adjacent channel layers 116, and surrounds the channel layer 116. The word line structure 122 includes a gate layer 120.

[0140] In one embodiment, the semiconductor structure further includes: a first filling layer 126 and a gap 320; the first filling layer 126 is located on the substrate, with the bottom of the first filling layer 126 not lower than the top surface of the gate layer 120; and the gap 320 is located between adjacent bitline structures 108 and between adjacent wordline structures 122. This reduces parasitic capacitance and minimizes the RC delay of data in the semiconductor structure. In one embodiment, a shallow trench isolation structure is formed in the substrate, which isolates a plurality of spaced active regions in the substrate. The semiconductor structure is located in the active region, and the gap 320 is located between the bitline structure 108 and the adjacent shallow trench isolation structure, and between the wordline structure 122 and the adjacent shallow trench isolation structure.

[0141] In one embodiment, the semiconductor structure further includes: a contact structure located on the second conductive layer 206 and electrically connected to the second conductive layer 206, distributed in an array in a plane parallel to the substrate, and configured to lead out the second conductive layer 206. Exemplarily, the bottom surface of the contact structure contacts the top surface of the second conductive layer 206. In one embodiment, the semiconductor structure further includes: a capacitor structure located on the contact structure and electrically connected to the second conductive layer 206 via the contact structure. Exemplarily, one electrode of the capacitor structure contacts the contact structure.

[0142] In one embodiment, a semiconductor structure is fabricated using the above-described fabrication method. During the fabrication of the semiconductor structure, a first sacrificial layer extending from the upper surface of the first stacked structure to the upper surface of the first conductive layer is formed in the first stacked structure using a first mask layer as a mask. The first mask layer is removed, and a second mask layer is alternately formed on the first sacrificial layer. The exposed first sacrificial layer is removed using the second mask layer as a mask, and then the second mask layer is removed. The first and second mask layers are etched only once, resulting in a reduced number of mask layer etchings, which reduces the requirements for mask layer materials, reduces costs, and simplifies the fabrication process. Furthermore, the semiconductor structure uses the first and second conductive layers as the source and drain of a vertical transistor, respectively, making it easy to control the doping concentrations of the source and drain, thereby improving the performance of the semiconductor structure. A portion of the channel sacrificial layer is removed by lateral etching to form a first recess and a channel layer. Therefore, by controlling the thickness of the channel sacrificial layer between the first and second conductive layers, the channel length between the source and drain can be precisely controlled, thereby improving the uniformity of the conductive channel and further enhancing the performance of the semiconductor structure. The remaining channel sacrificial layer is removed by lateral etching to form a second groove and a gate layer surrounding the channel layer, which simplifies gate alignment and further reduces the difficulty of the process. In some embodiments, the semiconductor structure includes but is not limited to a vertical gate-all-around transistor and a memory device.

[0143] The present disclosure also provides an electronic device comprising the aforementioned semiconductor structure. The electronic device may include a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal. The embodiments of the present disclosure do not impose any particular restrictions on the specific form of the aforementioned electronic device.

[0144] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. The above-mentioned embodiments only express several implementation methods of the embodiments of the present disclosure. The description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the embodiments of the present disclosure, several variations and improvements can be made, which all fall within the scope of protection of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, comprising: Providing a substrate, on which a first stacked structure is formed, the first stacked structure extending in a row direction and arranged at intervals in a column direction, the first stacked structure comprising a first conductive layer, a channel sacrificial layer, and a second conductive layer stacked from bottom to top; forming a first mask layer on the first stacked structure, wherein the first mask layer extends along the column direction and is arranged at intervals along the row direction; Using the first mask layer as a mask, forming a first sacrificial layer in the first stacked structure extending from the upper surface of the first stacked structure to the upper surface of the first conductive layer; removing the first mask layer, and alternately forming a second mask layer on the first sacrificial layer; Using the second mask layer as a mask, removing the exposed first sacrificial layer; Laterally etching and removing a portion of the channel sacrificial layer to form a first groove and a channel layer; removing the second mask layer; as well as The remaining channel sacrificial layer is removed by lateral etching to form a second groove and a gate layer surrounding the channel layer, and adjacent gate layers are isolated in the row direction.

2. The preparation method according to claim 1, wherein the lateral etching removes part of the channel sacrificial layer to form a first groove and a channel layer, comprising: Laterally etching and removing a portion of the channel sacrificial layer to form a first groove; Laterally etching and removing a portion of the second conductive layer to form a first filling groove connected to the first groove; as well as The channel layer is formed at the bottom of the first groove and in the first filling groove.

3. The preparation method according to claim 1, wherein after the side etching removes part of the channel sacrificial layer to form the first groove and the channel layer, the method further comprises: An annealing process is performed on the channel layer.

4. The preparation method according to claim 1, wherein the first mask layer is used as a mask to form a first sacrificial layer extending from the upper surface of the first stacked structure to the upper surface of the first conductive layer in the first stacked structure, comprising: Using the first mask layer as a mask, patterning the first stacked structure to obtain first trenches exposing the upper surface of the first conductive layer, wherein the first trenches extend along the column direction and are arranged at intervals along the row direction; as well as The first sacrificial layer is formed in the first trench.

5. The manufacturing method according to claim 1, wherein forming a first mask layer on the first stacked structure comprises: forming a protective layer and the first mask layer on the upper surface of the first stacked structure, wherein the first mask layer is located on the protective layer; Wherein, the second mask layer extends along the row direction to the upper surfaces of the protection layers on two adjacent sides.

6. The preparation method according to claim 1, wherein before the lateral etching removes the remaining channel sacrificial layer and forms the second groove, the method further comprises: forming a third mask layer on the first stacked structure, wherein the third mask layer extends along the column direction and exposes the remaining first sacrificial layer; Using the third mask layer as a mask, etching and removing the remaining first sacrificial layer; as well as The third mask layer is removed.

7. The manufacturing method according to claim 6, wherein before forming the third mask layer on the first stacked structure, it further comprises: forming a first dielectric layer at the filling position of the first sacrificial layer exposed by the second mask layer, wherein the third mask layer extends to cover the top surface of the first dielectric layer; Before forming the gate layer surrounding the channel layer, the method further includes: A second dielectric layer is formed at the filling position of the first sacrificial layer covered by the second mask layer.

8. The manufacturing method according to claim 7, wherein before forming the first mask layer on the first stacked structure, it further comprises: forming a second stacked structure located between adjacent first stacked structures on the substrate, the second stacked structure comprising a third dielectric layer and a second sacrificial layer stacked from bottom to top, the top surface of the third dielectric layer being flush with the top surface of the first conductive layer, and the etching rate of the third dielectric layer being lower than the etching rate of the second sacrificial layer; Before forming the gate layer surrounding the channel layer, the method further includes: and removing at least a portion of the second sacrificial layer between the first groove and the second groove to penetrate the first groove and the second groove to form a first annular groove surrounding the channel layer; Wherein, the gate layer is located in the first annular groove.

9. The preparation method according to claim 8, wherein the step of removing at least a portion of the second sacrificial layer between the first groove and the second groove comprises: Simultaneously removing the second sacrificial layer between adjacent first grooves and between adjacent second grooves to form a word line groove; The forming of a gate layer surrounding the channel layer comprises: A word line structure is formed in the word line trench, wherein the word line structure includes the gate layer.

10. The method according to claim 9, wherein after forming the gate layer surrounding the channel layer, the method further comprises: removing the first dielectric layer, the second dielectric layer and the third dielectric layer; as well as A first filling layer is formed on the substrate, wherein the bottom of the first filling layer is not lower than the top surface of the gate layer, so as to form a gap between adjacent word line structures and adjacent bit line structures.

11. The preparation method according to claim 1, wherein providing a substrate comprises: providing an initial substrate; Forming a first stacked structure material layer on the surface of the initial substrate, wherein the first stacked structure material layer includes a first conductive material layer, a channel sacrificial material layer, and a second conductive material layer stacked from bottom to top; Forming a third groove exposing the initial substrate in the first stacked structure material layer to obtain the first stacked structure, wherein the third groove is located between adjacent first stacked structures; forming a fourth dielectric layer on the sidewalls of the third trench, and extending the third trench into the initial substrate; as well as A bit line structure is formed at the bottom of the first stacked structure and a second filling layer is formed between adjacent bit line structures. The second filling layer is located in the third trench. The bit line structures extend along the row direction and are arranged at intervals along the column direction.

12. The preparation method according to claim 11, wherein the upper surface layer of the initial substrate has a doped silicon material layer, and the third groove penetrates the silicon material layer and extends into the initial substrate; The forming of the bit line structure at the bottom of the first stacked structure and the second filling layer between adjacent bit line structures comprises: Filling the bottom of the third trench to form the second filling layer and the metal material layer from bottom to top, wherein the top surface of the second filling layer is lower than the top surface of the silicon material layer; Using an annealing process to make the metal material layer react with the silicon material layer to generate the bit line structure; and The remaining metal material layer and the fourth dielectric layer located on the sidewalls of the channel sacrificial layer and the sidewalls of the second conductive layer are removed.

13. A semiconductor structure, manufactured by the method according to any one of claims 1 to 12, comprising: substrate; A first conductive layer is located on the substrate, extends along the row direction, and is arranged at intervals along the column direction; A channel layer arrayed on the top surface of the first conductive layer; A gate layer, located on a top surface of the first conductive layer, surrounding the channel layer, and isolating adjacent gate layers in the row direction; as well as The second conductive layer is located on the top surface of the channel layer, arranged in an array on the channel layer, and in contact with the channel layer.

14. The semiconductor structure according to claim 13, further comprising: A word line structure extending along the column direction and arranged at intervals along the row direction, surrounding the channel layer; A bit line structure, located between the substrate and the first conductive layer, electrically connected to the first conductive layer, extending along the row direction and arranged at intervals along the column direction; as well as The second filling layer is located in the substrate, extends along the row direction and is arranged at intervals along the column direction, and is located between adjacent bit line structures.

15. The semiconductor structure of claim 14, further comprising: A first filling layer, located on the substrate, wherein the bottom of the first filling layer is not lower than the top surface of the gate layer; as well as The gap is located between adjacent bit line structures and between adjacent word line structures.

16. The semiconductor structure according to claim 13, further comprising: The contact structures are located on the second conductive layer and electrically connected to the second conductive layer, and are distributed in an array in a plane parallel to the substrate.

17. An electronic device comprising the semiconductor structure according to any one of claims 13 to 16.

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