Thin film transistor, and manufacturing method therefor

Abstract

Disclosed are a thin film transistor and a manufacturing method therefor. The thin film transistor comprises a substrate; a source electrode, an active layer and a drain electrode which are sequentially stacked in the direction perpendicular to the substrate; and a first gate electrode part located on the side surface of the active layer and spaced apart from the active layer. The material of the active layer comprises a semiconductor material, the material of the first gate electrode part comprises a conductive semiconductor material, and the conductive semiconductor material contains all chemical elements contained in the semiconductor material.

Description

Thin film transistor and manufacturing method thereof Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor and a method for manufacturing the same. Background Art

[0002] As mainstream electronic display products (such as TVs, mobile phones, VR / AR, etc.) have increasingly higher requirements for display resolution, how to improve resolution by reducing the size of transistors has received increasing attention, and reducing the length of transistors is the key to reducing the size of transistors.

[0003] Compared to planar channel structures, since the length of the vertical channel structure is determined by the thickness of the active layer, the vertical channel structure can effectively reduce the length of the transistor, thereby effectively increasing the aspect ratio of the transistor and thus effectively reducing the size of the transistor. However, transistors with a vertical channel structure are often subject to the short channel effect, resulting in a negative threshold voltage, which affects the stability of the transistor's electrical performance. SUMMARY OF THE INVENTION

[0004] The present application provides a thin film transistor and a method for manufacturing the same, which can effectively suppress the short channel effect of a thin film transistor with a vertical channel structure, thereby improving the electrical performance stability of the transistor while reducing the size of the thin film transistor.

[0005] In a first aspect, the present application provides a thin film transistor, comprising:

[0006] substrate;

[0007] a source electrode, located on the substrate;

[0008] a first insulating layer covering at least the substrate; the first insulating layer is provided with a first through hole corresponding to the source electrode;

[0009] an active layer, located in the first through hole and electrically connected to the source electrode, wherein the material forming the active layer is a semiconductor material;

[0010] a first gate portion, located on the first insulating layer and spaced apart from the active layer; the first gate portion is disposed corresponding to at least a portion of a side surface of the active layer, and the material forming the first gate portion is a conductive semiconductor material, and the conductive semiconductor material contains all chemical elements contained in the semiconductor material;

[0011] a second insulating layer covering at least the first insulating layer and the first gate portion; the second insulating layer is provided with a second through hole corresponding to the active layer and a third through hole corresponding to the first gate portion; and

[0012] The drain electrode and the second gate portion are located on the second insulating layer and spaced apart from each other; the drain electrode is electrically connected to the active layer through the second through hole, and the second gate portion is electrically connected to the first gate portion through the third through hole.

[0013] In the thin film transistor provided in the present application, the active layer and the first gate portion are both made of metal oxide.

[0014] In the thin film transistor provided in the present application, the material of the active layer includes any one of zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide and aluminum indium tin zinc oxide.

[0015] In the thin film transistor provided in the present application, the maximum distance between the side of the first gate portion away from the substrate and the substrate is greater than or equal to the maximum distance between the side of the active layer away from the substrate and the substrate.

[0016] In the thin film transistor provided in the present application, the first gate portion is arranged around the active layer.

[0017] In the thin film transistor provided in the present application, the number of the third through holes is 2, and the number of the second gate portions is 2; the two third through holes are respectively arranged on opposite sides of the active layer, and the two second gate portions are respectively electrically connected to the first gate portion through the two third through holes.

[0018] In the thin film transistor provided in the present application, the first insulating layer includes an integrally formed first insulating portion and a second insulating portion; the first insulating portion is located only on the substrate and is arranged around the source electrode, and the second insulating portion is located on the first insulating portion and a portion of the source electrode; the spacing between the active layer on a side away from the substrate and the substrate is less than or equal to the spacing between the second insulating portion on a side away from the substrate and the substrate;

[0019] The first gate portion includes an integrally formed first oxide conductor portion and a second oxide conductor portion; the first oxide conductor portion is located only on the first insulating portion and is arranged around the second insulating portion; the second oxide conductor portion is located on the first oxide conductor portion and the second insulating portion.

[0020] In the thin film transistor provided in the present application, the source electrode includes a main portion stacked with the active layer and an extension portion extending from the main portion in a direction away from the main portion; at least a portion of the extension portion is not overlapped with the first gate portion and the second gate portion;

[0021] The thin film transistor further includes a connecting electrode located on the second insulating layer and disposed corresponding to the extending portion, and the connecting electrode is electrically connected to the extending portion via a fourth through hole penetrating the first insulating layer and the second insulating layer.

[0022] In the thin film transistor provided in the present application, the drain electrode and the second gate portion are made of the same material, and the material of the second gate portion includes a metal material.

[0023] In a second aspect, the present application further provides a method for manufacturing a thin film transistor, comprising the following steps:

[0024] providing a substrate;

[0025] A source electrode and a first insulating layer are sequentially formed on the substrate; wherein the first insulating layer at least covers the substrate, and the first insulating layer is provided with a first through hole corresponding to the source electrode;

[0026] An active layer and a first gate portion are formed, wherein the active layer is located in the first through hole and is electrically connected to the source electrode, and the first gate portion is located on the first insulating layer and is disposed corresponding to at least a portion of a side surface of the active layer; the active layer is formed of a semiconductor material, and the first gate portion is formed of a conductive semiconductor material, and the conductive semiconductor material contains all chemical elements contained in the semiconductor material;

[0027] forming a second insulating layer covering at least the first insulating layer and the first gate portion; wherein the second insulating layer is formed with a second through hole corresponding to the active layer and a third through hole corresponding to the first gate portion; and

[0028] A drain electrode and a second gate portion are formed on the second insulating layer and are spaced apart from each other; wherein the drain electrode is electrically connected to the active layer through the second through hole, and the second gate portion is electrically connected to the first gate portion through the third through hole.

[0029] In the method for manufacturing a thin film transistor provided in the present application, the active layer and the first gate portion are both metal oxides; forming the active layer and the first gate portion includes the following steps:

[0030] forming an oxide semiconductor film covering the first insulating layer and the source electrode; the oxide semiconductor film includes a first region corresponding to the source electrode and a second region corresponding to a portion of the first insulating layer, the second region being spaced apart from the first region;

[0031] patterning the oxide semiconductor film to retain only the oxide semiconductor film located in the first region and the second region; and

[0032] Conductive treatment is performed on the oxide semiconductor film located in the second region to form a first gate portion located in the second region and an active layer located in the first region.

[0033] In the method for manufacturing a thin film transistor provided in the present application, the material of the oxide semiconductor film includes any one of zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide and aluminum indium tin zinc oxide.

[0034] In the method for manufacturing a thin film transistor provided in the present application, the step of performing a conductor treatment on the oxide semiconductor thin film located in the second region includes the following steps:

[0035] forming a second insulating layer entirely covering the first insulating layer and the patterned oxide semiconductor film;

[0036] forming a mask layer corresponding to the first region on the second insulating layer;

[0037] performing a plasma induction treatment on the substrate having the mask layer formed thereon to make the oxide semiconductor thin film located in the second region conductive;

[0038] removing the mask layer; and

[0039] The second insulating layer is subjected to a hole-opening process to form a second through hole corresponding to the active layer and a third through hole corresponding to the first gate portion.

[0040] In the method for manufacturing a thin film transistor provided in the present application, the atmosphere used for the plasma induced treatment includes one or more of chlorine trifluoride, chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon and nitrogen.

[0041] In the method for manufacturing a thin film transistor provided in the present application, the material of the mask layer includes photoresist.

[0042] In the method for manufacturing a thin film transistor provided in the present application, the first gate portion is disposed around the active layer.

[0043] In the manufacturing method of the thin film transistor provided in the present application, the number of the third through holes is 2, and the number of the second gate portions is 2; the two third through holes are respectively arranged on opposite sides of the active layer, and the two second gate portions are respectively electrically connected to the first gate portion through the two third through holes.

[0044] In the method for manufacturing a thin film transistor provided in the present application, the first insulating layer includes an integrally formed first insulating portion and a second insulating portion; the first insulating portion is located only on the substrate and is disposed around the source electrode, and the second insulating portion is located on the first insulating portion and a portion of the source electrode; the spacing between the active layer on a side away from the substrate and the substrate is less than or equal to the spacing between the second insulating portion on a side away from the substrate and the substrate;

[0045] The first gate portion includes an integrally formed first oxide conductor portion and a second oxide conductor portion; the first oxide conductor portion is located only on the first insulating portion and is arranged around the second insulating portion; the second oxide conductor portion is located on the first oxide conductor portion and the second insulating portion.

[0046] In the method for manufacturing a thin film transistor provided in the present application, the source electrode includes a main portion stacked with the active layer and an extension portion extending from the main portion in a direction away from the main portion; at least a portion of the extension portion is arranged so as not to overlap with the first gate portion and the second gate portion;

[0047] The thin film transistor further includes a connecting electrode located on the second insulating layer and disposed corresponding to the extending portion, and the connecting electrode is electrically connected to the extending portion via a fourth through hole penetrating the first insulating layer and the second insulating layer.

[0048] In the method for manufacturing a thin film transistor provided in the present application, the drain electrode and the second gate portion are made of the same material, and the material of the second gate portion includes a metal material. Beneficial effects

[0049] Compared to the prior art, the present invention has the following advantages: First, the thin-film transistor has a vertical channel structure, meaning the channel length of the thin-film transistor is equal to the thickness of the active layer, effectively reducing the length of the thin-film transistor. Therefore, the present invention can form a thin-film transistor with a large width-to-length ratio in a smaller area, thereby effectively reducing the size of the thin-film transistor. Second, because the active layer of the thin-film transistor is made of a semiconductor material, and the first gate portion is made of a conductive semiconductor material, which contains all the chemical elements contained in the semiconductor material, the work function difference between the active layer and the first gate portion approaches zero, effectively suppressing the short-channel effect and thereby improving the electrical performance stability of the thin-film transistor. Therefore, the present invention can reduce the size of the thin-film transistor while improving the electrical performance stability of the thin-film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic diagram of a top view of a thin film transistor provided in an embodiment of the present application.

[0051] FIG2 is a schematic diagram of the cross-sectional structure at position AA in FIG1 .

[0052] FIG3 is a schematic flow chart of a method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0053] FIG4 is a schematic diagram of a top view of the source electrode in a method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0054] FIG5 is a schematic diagram of the cross-sectional structure at position AA in FIG4 .

[0055] FIG6 is a schematic diagram of a top view of the device structure after a first insulating layer is formed in a method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0056] FIG7 is a schematic diagram of the cross-sectional structure at position AA in FIG6 .

[0057] FIG8 is a schematic diagram of a top view of the structure of a device after patterning of an oxide semiconductor thin film in a method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0058] FIG9 is a schematic diagram of the cross-sectional structure at position AA in FIG8 .

[0059] FIG10 is a schematic diagram of a top view of the device structure after a second insulating layer covering the entire surface is formed in a method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0060] FIG11 is a schematic diagram of the cross-sectional structure at position AA in FIG10 .

[0061] FIG12 is a schematic diagram of a top view of the structure of a device after a mask layer is formed in a method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0062] FIG13 is a schematic diagram of the cross-sectional structure at position AA in FIG12 .

[0063] FIG14 is a schematic diagram of a top view of the device structure after the mask layer is removed in a method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0064] FIG15 is a schematic diagram of the cross-sectional structure at position AA in FIG14 .

[0065] FIG16 is a schematic diagram of a top view of the device after the second insulating layer is opened in a method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0066] FIG17 is a schematic diagram of the cross-sectional structure at position AA in FIG16 . Modes for Carrying Out the Invention

[0067] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0068] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0069] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0070] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0071] After research, the applicant found that oxide thin-film transistors have a wide band gap, which can suppress the short channel effect to a certain extent. Therefore, oxide semiconductor materials are a good choice for preparing active layers with vertical channels; and the ideal vertical channel structure usually hopes that ϕms=0, that is, the work function difference between the gate and the active layer of the oxide semiconductor material is zero. The best way to achieve ϕms=0 is to allow the oxide itself to serve as the gate, which requires that the oxide has good conductivity when used as a gate, and at the same time, the oxide has semiconductor properties when used as a channel of the active layer.

[0072] Based on the above research, the present application provides a thin film transistor with a vertical channel structure and a method for manufacturing the same, which can produce a thin film transistor with a large aspect ratio in a smaller area, thereby effectively reducing the size of the thin film transistor; and the materials of the active layer of the thin film transistor provided by the present application and the gate electrode corresponding to the active layer are composed of the same chemical elements, so that the work function difference between the corresponding active layer and the gate electrode approaches 0, which is conducive to suppressing the short channel effect; further, the present application uses an oxide semiconductor as the active layer and an oxide conductor as the oxide gate electrode, which can further effectively suppress the short channel effect. Therefore, the thin film transistor provided by the present application has a vertical channel structure and is less affected by the short channel effect, and can be applied to higher resolution display products.

[0073] As shown in Figures 1 and 2, an embodiment of the present application provides a thin film transistor 1, which includes a substrate 2, and a source electrode 3, a first insulating layer 4, an active layer 5, a first gate portion 6, a second insulating layer 7, a drain electrode 8 and a second gate portion 9 located on one side of the substrate 2.

[0074] Specifically, as shown in FIG2 , substrate 2 includes a base substrate 2a and a buffer layer 2b covering base substrate 2a. Base substrate 2a may be, but is not limited to, a glass substrate, a quartz substrate, a silicon substrate, or a flexible substrate. Buffer layer 2b includes, but is not limited to, a silicon nitride layer, a silicon oxide layer, or a stacked structure of a silicon nitride layer and a silicon oxide layer.

[0075] Specifically, the source electrode 3 is located on the substrate 2; the material of the source electrode 3 can be a metal element of molybdenum, copper, aluminum, titanium, niobium or nickel, can be a molybdenum-titanium, molybdenum-niobium or molybdenum-nickel alloy, or can be a combination stack of any of the above metals or alloys.

[0076] Specifically, the first insulating layer 4 at least covers the substrate 2 , and a first through hole 10 corresponding to the source 3 is provided on the first insulating layer 4 .

[0077] In a specific embodiment, the first insulating layer 4 also covers a portion of the source 3 , but is not limited thereto.

[0078] Specifically, the first insulating layer 4 is equivalent to the gate insulating layer, and the first insulating layer 4 can be a single layer structure of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide or scandium zirconium oxide, or a stacked structure of any two or three of the above.

[0079] In a specific embodiment, as shown in Figure 2, the orthographic projection of the first insulating layer 4 on the substrate 2 is partially overlapped with the orthographic projection of the source electrode 3 on the substrate 2, and the non-overlapping portion between the two is the area where the first through hole 10 is located; the orthographic projection of the first through hole 10 on the substrate 2 is completely covered by the orthographic projection of the source electrode 3 on the substrate 2.

[0080] In one embodiment, the shape of the first through hole 10 includes a circle, but is not limited thereto.

[0081] Specifically, the active layer 5 is located in the first through hole 10 and is electrically connected to the source electrode 3 . The material forming the active layer 5 is a semiconductor material.

[0082] In one embodiment, the material of the active layer 5 includes a metal oxide, but is not limited thereto. For example, the material of the active layer 5 includes any one of zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, and aluminum indium tin zinc oxide, but is not limited thereto.

[0083] Specifically, as shown in Figure 2, the first gate portion 6 is located on the first insulating layer 4 and spaced apart from the active layer 5. The first gate portion 6 is disposed corresponding to at least a portion of the side surface of the active layer 5. It can be understood that the first gate portion 6 is located outside the active layer 5 and is used to control the active layer 5 to achieve turning on and off of the thin film transistor 1.

[0084] It should be noted that the first gate portion 6 is arranged corresponding to at least part of the side surface of the active layer 5. It can be understood that the orthographic projection of the first gate portion 6 on the vertical plane perpendicular to the substrate 2 at least partially overlaps with the orthographic projection of the active layer 5 on the vertical plane.

[0085] In a specific embodiment, as shown in FIG1 , the first gate portion 6 is arranged around the active layer 5 . This design allows the first gate portion 6 to be arranged corresponding to the entire side surface of the active layer 5 , so that the first gate portion 6 can achieve maximum control over the active layer 5 , which is beneficial to improving the reaction efficiency of the thin film transistor 1 .

[0086] Of course, in other embodiments, the first gate portion 6 may be located only on one side of the active layer 5 or on two opposite sides. This design can also achieve the regulating effect of the first gate portion 6 on the active layer 5 and save material costs.

[0087] It should be noted that the side of the active layer 5 close to the substrate 2 is the lower surface, the side of the active layer 5 away from the substrate 2 is the upper surface, and the side of the active layer 5 refers to the surface connecting its upper and lower surfaces; it can be understood that the side of the active layer 5 is annular.

[0088] Specifically, the material forming the first gate portion 6 is a conductive semiconductor material, and the conductive semiconductor material contains all the chemical elements contained in the semiconductor material forming the active layer 5, so that the work function difference between the first gate portion 6 and the active layer 5 approaches 0, thereby suppressing the short channel effect.

[0089] It is understood that the material of the first gate portion 6 can be formed by conducting the semiconductor material used to form the active layer 5; that is, the aforementioned conducting semiconductor material refers to a conducting material formed by conducting the semiconductor material used to form the active layer 5. The conducting method includes any one of a plasma induction technique and a doping technique, but is not limited thereto.

[0090] Specifically, when the material of the active layer 5 is metal oxide, the material of the first gate portion 6 is also metal oxide.

[0091] In one embodiment, the first gate portion 6 and the active layer 5 are both metal oxides, and both are composed of the same chemical elements. It can be understood that the first gate portion 6 is a metal oxide conductor, and the active layer 5 is a metal oxide semiconductor.

[0092] It should be noted that although the chemical element composition of the first gate portion 6 and the active layer 5 is the same, the proportions of some chemical elements therein are different, for example, the proportions of hydrogen (H) and oxygen (O) are different, so that the first gate portion 6 is a conductor with high electrical conductivity, while the active layer 5 is a semiconductor.

[0093] Specifically, when the first gate portion 6 and the active layer 5 are both metal oxides, a metal oxide semiconductor made of the same material as the active layer 5 can be formed in the area used to make the first gate portion 6, and then the metal oxide semiconductor in the area can be made conductive by plasma induction technology to form a first gate portion 6 with higher conductivity.

[0094] It can be understood that the active layer 5 and the first gate portion 6 in the embodiment of the present application can be arranged in the same layer and spaced apart.

[0095] 2 , the second insulating layer 7 at least covers the first insulating layer 4 and the first gate portion 6 ; the second insulating layer 7 is provided with a second through hole 11 corresponding to the active layer 5 and a third through hole 12 corresponding to the first gate portion 6 .

[0096] Specifically, the material of the second insulating layer 7 can be the same as, but not limited to, the material of the first insulating layer 4. It is understandable that since the second insulating layer 7 covers the first insulating layer 4 and the first gate portion 6, the first gate portion 6 is equivalent to being wrapped by the first insulating layer 4 and the second insulating layer 7.

[0097] In a specific embodiment, the second insulating layer 7 may also cover the edge of the active layer 5 .

[0098] In one embodiment, the second through hole 11 has a circular shape, and the third through hole 12 has a rectangular shape, but the present invention is not limited thereto.

[0099] Specifically, the drain electrode 8 and the second gate portion 9 are located on the second insulating layer 7 and spaced apart from each other; wherein the drain electrode 8 is electrically connected to the active layer 5 via the second through-hole 11, and the second gate portion 9 is electrically connected to the first gate portion 6 via the third through-hole 12. It is understandable that the drain electrode 8 is also filled in the second through-hole 11, and the second gate portion 9 is also filled in the third through-hole 12.

[0100] It should be noted that the second gate portion 9 is used to transmit a gate signal to the first gate portion 6 .

[0101] In one specific embodiment, as shown in Figures 1 and 2, the number of third through holes 12 is two, and the number of second gate portions 9 is two; two third through holes 12 are respectively disposed on opposite sides of the active layer 5, and the two second gate portions 9 are electrically connected to the first gate portion 6 via the two third through holes 12. In other words, the two second gate portions 9 are located on opposite sides of the drain electrode 8. This design ensures that symmetrical positions of the first gate portion 6 can simultaneously receive gate signals, which helps improve the uniformity of electrical signals at different positions of the first gate portion 6, thereby improving the driving effect of the first gate portion 6.

[0102] Specifically, the drain electrode 8 and the second gate portion 9 are provided in the same layer and are made of the same material. For example, the drain electrode 8 and the second gate portion 9 can be a single metal layer of molybdenum, copper, aluminum, titanium, niobium, or nickel, or a molybdenum-titanium, molybdenum-niobium, or molybdenum-nickel alloy layer, or a combination of any of the above metals or alloys. It is understood that the source electrode 3, the drain electrode 8, and the second gate portion 9 can be made of the same metal material.

[0103] Specifically, the second gate portion 9 is made of metal material and is connected to the first gate portion 6 , so that the second gate portion 9 and the first gate portion 6 have the same potential.

[0104] Specifically, since the source electrode 3, the active layer 5 and the drain electrode 8 are stacked in sequence in a direction perpendicular to the substrate 2, and the first gate portion 6 is located on at least one side of the active layer 5, the thin film transistor 1 provided in the embodiment of the present application has a vertical channel structure, that is, the channel length of the thin film transistor 1 is equal to the height (or thickness) of the active layer 5 in a direction perpendicular to the substrate 2.

[0105] On the one hand, since the thin film transistor 1 has a vertical channel structure, the length of the thin film transistor can be effectively reduced, so a thin film transistor with a large width-to-length ratio can be formed in a smaller area, which can effectively reduce the size of the thin film transistor; on the other hand, since the material of the active layer 5 of the thin film transistor 1 is a semiconductor material, the material of the first gate portion 6 is a conductive semiconductor material, and the conductive semiconductor material contains all the chemical elements contained in the semiconductor material, the work function difference between the active layer 5 and the first gate portion 6 is close to 0, which can effectively suppress the short channel effect; on the other hand, the active layer 5 is a metal oxide, which makes the thin film transistor have a wider band gap, which can suppress the short channel effect to a certain extent; therefore, the thin film transistor 1 provided in the present application has a smaller size, and the cooperation between the active layer 5 and the first gate portion 6 is conducive to improving the electrical performance stability of the thin film transistor 1.

[0106] Specifically, the maximum distance between the side of the first gate portion 6 away from the substrate 2 and the substrate 2 is greater than or equal to the maximum distance between the side of the active layer 5 away from the substrate 2 and the substrate 2. This design ensures that the channel length of the active layer 5 (i.e., the thickness of the active layer 5) is less than or equal to the maximum thickness of the first gate portion 6, allowing the channel of the active layer 5 to be completely aligned with the first gate portion 6, which helps improve the efficiency of the first gate portion 6 in regulating the active layer 5.

[0107] It should be noted that the thickness mentioned above refers to the height in a direction perpendicular to the substrate 2 .

[0108] In one specific embodiment, as shown in Figure 2, the first insulating layer 4 includes an integrally formed first insulating portion 4a and a second insulating portion 4b. The first insulating portion 4a is located only on the substrate 2 and surrounds the source electrode 3, while the second insulating portion 4b is located on the first insulating portion 4a and a portion of the source electrode 3. It will be appreciated that the distance between the side of the first insulating portion 4a facing away from the substrate 2 and the substrate 2 is smaller than the distance between the side of the second insulating portion 4b facing away from the substrate 2 and the substrate 2, i.e., the first insulating portion 4a and the second insulating portion 4b form a stepped shape. The distance between the side of the active layer 5 facing away from the substrate 2 and the substrate 2 is smaller than or equal to the distance between the side of the second insulating portion 4b facing away from the substrate 2 and the substrate 2. Furthermore, the first gate portion 6 includes an integrally formed first oxide conductive portion 6a and a second oxide conductive portion 6b. The first oxide conductive portion 6a is located only on the first insulating portion 4a and surrounds the second insulating portion 4b, while the second oxide conductive portion 6b is located on the first oxide conductive portion 6a and the second insulating portion 4b.

[0109] Therefore, the maximum thickness of the first gate portion 6 can be adjusted by controlling the thicknesses of the first insulating portion 4 a and the second insulating portion 4 b , so that the channel of the active layer 5 can be completely disposed corresponding to the first gate portion 6 .

[0110] Specifically, the source electrode 3 includes a main portion 3a stacked with the active layer 5 and an extension portion 3b extending away from the main portion 3a. At least a portion of the extension portion 3b does not overlap with the first gate portion 6 and the second gate portion 9. The thin-film transistor 1 also includes a connecting electrode 13 located on the second insulating layer 7 and corresponding to the extension portion 3b. The connecting electrode 13 is electrically connected to the extension portion 3b via a fourth through hole 14 that penetrates the first insulating layer 4 and the second insulating layer 7.

[0111] It can be understood that the fourth through hole 14 , the second through hole 11 and the third through hole 12 are formed in the same process, and the connecting electrode 13 , the drain electrode 8 and the second gate portion 9 can also be formed in the same process.

[0112] Specifically, the connection electrode 13 is electrically connected to the source electrode 3 through the fourth through hole 14 , and is used to transmit a source signal to the source electrode 3 .

[0113] In one embodiment, the shape of the fourth through hole 14 includes a rectangle, but is not limited thereto.

[0114] In a specific embodiment, the drain electrode 8 further extends in a direction away from the connection electrode 13 to facilitate electrical connection with other devices or film layers.

[0115] In the embodiment of the present application, on the one hand, the thin film transistor 1 has a vertical channel structure, that is, the channel length of the thin film transistor 1 is equal to the thickness of the active layer 5, which effectively reduces the length of the thin film transistor 1. Therefore, the present application can form a thin film transistor 1 with a large width-to-length ratio in a smaller area, thereby effectively reducing the size of the thin film transistor. On the other hand, the material of the first gate portion 6 of the thin film transistor 1 contains all the chemical elements contained in the active layer 5, so that the work function difference between the active layer 5 and the first gate portion 6 approaches zero, which can effectively suppress the short channel effect and help improve the electrical performance stability of the thin film transistor 1. On the other hand, the active layer 5 of the thin film transistor 1 is a metal oxide, which gives the thin film transistor 1 a wide band gap, which can suppress the short channel effect to a certain extent and help further improve the electrical performance stability of the thin film transistor 1. Therefore, the present application can reduce the size of the thin film transistor 1 while improving the electrical performance stability of the thin film transistor 1.

[0116] As shown in FIG3 , the embodiment of the present application further provides a method for manufacturing the thin film transistor described in the aforementioned embodiment, and the manufacturing method includes steps S301 to S305 .

[0117] S301: Provide substrate.

[0118] Specifically, as shown in FIG5 , substrate 2 includes a base substrate 2a and a buffer layer 2b covering base substrate 2a. Base substrate 2a may be, but is not limited to, a glass substrate 2, a quartz substrate 2, a silicon substrate 2, or a flexible substrate 2. Buffer layer 2b includes, but is not limited to, a silicon nitride layer, a silicon oxide layer, or a stacked structure of a silicon nitride layer and a silicon oxide layer.

[0119] S302: forming a source electrode and a first insulating layer in sequence on the substrate; wherein the first insulating layer at least covers the substrate, and a first through hole corresponding to the source electrode is formed on the first insulating layer.

[0120] Specifically, step S302 includes the following steps:

[0121] A first metal electrode layer is deposited on the buffer layer 2b of the substrate 2, and the first metal electrode layer is patterned using a first photolithography process and a first etching process to form a source electrode 3. A top view of the formed source electrode 3 is shown in FIG4, and a cross-sectional view of the device structure after the source electrode 3 is formed is shown in FIG5.

[0122] As shown in FIG6 and FIG7, a first insulating layer 4 is deposited on the substrate 2 with the source electrode 3 formed thereon, and a second photolithography process and a second etching process are used to perform a hole opening process on the first insulating layer 4 to form a first through hole 10 corresponding to the source electrode 3.

[0123] Specifically, the material of the source electrode 3 can be a single metal substance of molybdenum, copper, aluminum, titanium, niobium or nickel, or a molybdenum-titanium, molybdenum-niobium or molybdenum-nickel alloy, or a combination laminate of any of the above metals or alloys.

[0124] Specifically, the exposure wavelength band used in the first photolithography process includes any one of extreme ultraviolet light, deep ultraviolet light, ultraviolet light, visible light, electron beam and ion beam.

[0125] Specifically, the first etching process can be a dry etching process, a wet etching process, or a mixed process of dry and wet etching. The dry etching process can be performed in a single gas component of chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon, or nitrogen, or in a combination of any of the above gases; the wet etching process can be performed using ammonia water, sodium hydroxide, potassium hydroxide, phosphoric acid, hydrofluoric acid, nitric acid, acetic acid, hydrochloric acid, sulfuric acid, hydrogen peroxide, aqua regia solution, or a mixture of any two or three of the above.

[0126] Specifically, the first insulating layer 4 may be a single layer of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide or scandium zirconium oxide, or a stacked layer of any two or three of the above.

[0127] Specifically, the exposure wavelength band used in the second photolithography process includes any one of extreme ultraviolet light, deep ultraviolet light, ultraviolet light, visible light, electron beam and ion beam.

[0128] Specifically, the second etching process can be a dry etching process, a wet etching process, or a mixed process of dry and wet etching. The dry etching process can be performed in a single gas component of chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon, or nitrogen, or in a combination of any of the above gases; the wet etching process can be performed using ammonia water, sodium hydroxide, potassium hydroxide, phosphoric acid, hydrofluoric acid, nitric acid, acetic acid, hydrochloric acid, sulfuric acid, hydrogen peroxide, aqua regia solution, or a mixture of any two or three of the above.

[0129] Specifically, the detailed description of the first insulating layer 4 and the first through hole 10 can be referred to the aforementioned embodiment, which will not be repeated here.

[0130] S303: forming an active layer and a first gate portion that are spaced apart; wherein, the active layer is located in the first through hole and is electrically connected to the source electrode, and the first gate portion is located on the first insulating layer and is arranged corresponding to at least a portion of the side surface of the active layer; the material forming the active layer is a semiconductor material, and the material forming the first gate portion is a conductive semiconductor material, and the conductive semiconductor material contains all chemical elements contained in the semiconductor material.

[0131] Specifically, the active layer and the first gate portion are both metal oxides, and step S303 includes the following steps:

[0132] An oxide semiconductor film 15 is formed covering the first insulating layer 4 and the source electrode 3 ; the oxide semiconductor film 15 includes a first region 16 corresponding to the source electrode 3 and a second region 17 corresponding to a portion of the first insulating layer 4 , wherein the second region 17 is spaced apart from the first region 16 ;

[0133] As shown in FIG8 and FIG9 , the oxide semiconductor film 15 is patterned to leave only the oxide semiconductor film 15 located in the first region 16 and the second region 17 ; and

[0134] As shown in FIG. 13 and FIG. 15 , the oxide semiconductor thin film 15 located in the second region 17 is subjected to a conductive treatment to form the first gate portion 6 located in the second region 17 and the active layer 5 located in the first region 16 .

[0135] It can be understood that the first gate portion 6 is formed by conducting the semiconductor material used to form the active layer 5 ; that is, the aforementioned conducted semiconductor material refers to a conductor material formed after conducting the semiconductor material used to form the active layer 5 .

[0136] Specifically, since the material for forming the first gate portion 6 and the material for forming the active layer 5 are provided in the same layer, the first gate portion 6 and the active layer 5 are provided in the same layer.

[0137] Specifically, the material of the oxide semiconductor film 15 includes any one of zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide and aluminum indium tin zinc oxide.

[0138] Specifically, the oxide semiconductor film 15 is patterned by a third photolithography process and a third etching process. The exposure band used in the third photolithography process includes any one of extreme ultraviolet light, deep ultraviolet light, ultraviolet light, visible light, electron beam and ion beam. The third etching process can be a dry etching process, a wet etching process, or a mixed process of dry and wet processes. Among them, the dry etching process can be carried out in a single gas component of chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon or nitrogen, or in a combination of any of the above gases; the wet etching process can use ammonia water, sodium hydroxide, potassium hydroxide, phosphoric acid, hydrofluoric acid, nitric acid, acetic acid, hydrochloric acid, sulfuric acid, hydrogen peroxide, aqua regia solution and a mixed solution of any two or three of the above.

[0139] In a specific embodiment, the oxide semiconductor film 15 in the second region 17 is subjected to a conductorization process after forming the second insulating layer and before forming the second through hole and the third through hole in step S304 , as described below.

[0140] S304: forming a second insulating layer covering at least the first insulating layer and the first gate portion; wherein the second insulating layer is formed with a second through hole corresponding to the active layer and a third through hole corresponding to the first gate portion.

[0141] Specifically, in the embodiment of the present application, step S303 and step S304 can be combined. It is understandable that after forming the second insulating layer 7 and before forming the second through hole 11 and the third through hole 12, the oxide semiconductor film 15 located in the second region 17 is subjected to a conductorization process, and the second insulating layer 7 can protect the underlying structure.

[0142] Specifically, the step of performing the conductor treatment on the oxide semiconductor film 15 located in the second region 17 is combined with step S304, and includes the following steps:

[0143] As shown in FIG10 and FIG11 , a second insulating layer 7 is formed to entirely cover the first insulating layer 4 and the patterned oxide semiconductor thin film 15 ;

[0144] As shown in FIG12 and FIG13 , a mask layer 18 corresponding to the first region 16 is formed on the second insulating layer 7;

[0145] As shown in FIG13 to FIG15 , the substrate 2 with the mask layer 18 formed thereon is subjected to plasma induction treatment to make the oxide semiconductor thin film 15 located in the second region 17 conductive, thereby forming the active layer 5 located in the first region 16 and the first gate portion 6 located in the second region 17 ;

[0146] removing the mask layer 18; and

[0147] As shown in FIG. 16 and FIG. 17 , the second insulating layer 7 is subjected to a hole-forming process to form a second through hole 11 corresponding to the active layer 5 and a third through hole 12 corresponding to the first gate portion 6 .

[0148] Specifically, after the second insulating layer 7 covering the entire surface is formed, the entire device needs to be annealed. The annealing treatment can oxidize the patterned oxide semiconductor film 15, thereby removing hydrogen and reducing oxygen vacancies, making the oxide semiconductor film 15 closer to its intrinsic state.

[0149] Specifically, the annealing process may be annealing in vacuum, annealing in nitrogen, annealing in oxygen, annealing in water vapor, annealing in argon, or annealing in air.

[0150] Specifically, the material of the mask layer 18 includes photoresist, which functions to protect the oxide semiconductor film 15 located in the first region 16 to prevent the oxide semiconductor film 15 in the region from being conductive.

[0151] Specifically, the mask layer 18 may be formed by using a fourth photolithography process.

[0152] Specifically, the plasma induction treatment is performed on the substrate 2 with the mask layer 18 formed thereon, and in fact, the plasma induction treatment is performed on the entire device from the side provided with the mask layer 18. The oxide semiconductor film 15 in the first region 16 covered and protected by the mask layer 18 will not be induced, and its semiconductor properties will remain unchanged. The oxide semiconductor film 15 in the second region 17 not covered and protected by the mask layer 18 will form a film layer with higher conductivity under the plasma induction treatment, that is, form a first gate portion 6 (also called an oxide gate).

[0153] Specifically, the orthographic projection of the mask layer 18 on the substrate 2 completely covers the first region 16. Furthermore, the coverage area of ​​the mask layer 18 can be larger than the first region 16 to prevent the edge of the oxide semiconductor film 15 located in the first region 16 from being induced by plasma. It is understood that the mask layer 18 is not arranged to overlap with the second region 17.

[0154] Specifically, the atmosphere used for plasma induction treatment can be one or more of chlorine trifluoride, chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon, and nitrogen. The equipment used for plasma induction treatment can be one or more of a dry etching machine, plasma-enhanced chemical vapor deposition, magnetron sputtering, and a desmearing machine. The operating power of the equipment used for plasma induction treatment is between 10W and 4000W.

[0155] Specifically, the second insulating layer 7 is opened by using a fifth photolithography process and a fourth etching process to form a second through hole 11 corresponding to the active layer 5 and a third through hole 12 corresponding to the first gate portion 6 .

[0156] Specifically, the fifth photolithography process uses an exposure wavelength band including any one of ultraviolet light, visible light, electron beam, and ion beam. The fourth etching process includes a dry etching process, which can be performed in a single gas component of chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon, or nitrogen, or in any combination of these gases.

[0157] Specifically, for the detailed description of the second insulating layer 7 , the second through hole 11 and the third through hole 12 , reference may be made to the description of the aforementioned embodiment, which is not limited here.

[0158] Specifically, as shown in FIG16 , a fourth through hole 14 penetrating the first insulating layer 4 and the second insulating layer 7 can be formed by performing a hole-opening process on the second insulating layer 7 . For a specific description of the fourth through hole 14 , reference can be made to the description of the aforementioned embodiment and no limitation is given here.

[0159] S305: forming a drain electrode and a second gate portion spaced apart from each other on the second insulating layer; wherein the drain electrode is electrically connected to the active layer through the second through hole, and the second gate portion is electrically connected to the first gate portion through the third through hole.

[0160] Specifically, as shown in FIG1 and FIG2 , step S305 includes the following steps:

[0161] Depositing a second metal electrode layer on a side of the second insulating layer 7 away from the substrate 2;

[0162] The second metal electrode layer is patterned using a sixth photolithography process and a fifth etching process to form a drain electrode 8 and a second gate portion 9; wherein the drain electrode 8 is electrically connected to the active layer 5 through a second through hole 11, and the second gate portion 9 is electrically connected to the first gate portion 6 through a third through hole 12.

[0163] Of course, when the second metal electrode layer is patterned, a connection electrode 13 corresponding to the fourth through hole 14 may be formed. The connection electrode 13 is electrically connected to the drain electrode 8 through the fourth through hole 14 .

[0164] Specifically, the second metal electrode layer can be a single metal of molybdenum, copper, aluminum, titanium, niobium or nickel, or a molybdenum-titanium, molybdenum-niobium or molybdenum-nickel alloy, or a combination layer of any of the above metals or alloys.

[0165] Specifically, the exposure wavelength band used in the sixth photolithography process includes any one of ultraviolet light, visible light, electron beam, and ion beam. The fifth etching process can be a dry etching process, a wet etching process, or a mixed process of dry and wet etching. The dry etching process can be carried out in a single gas component of chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon, and nitrogen, or in a combination of any of the above gases. The etching solution used in the wet etching process includes any one of ammonia water, sodium hydroxide, potassium hydroxide, phosphoric acid, hydrofluoric acid, nitric acid, acetic acid, hydrochloric acid, sulfuric acid, hydrogen peroxide, aqua regia, etc., or a mixed solution of any two or three of the above gases.

[0166] In the embodiment of the present application, plasma induction technology can be used to achieve the use of a highly conductive oxide conductor as the first gate portion 6 of the thin-film transistor 1, and an oxide semiconductor as the active layer 5 of the thin-film transistor 1, and the thin-film transistor 1 has a vertical channel structure. Therefore, the thin-film transistor 1 produced in the embodiment of the present application can control the vertical channel of the oxide semiconductor (i.e., the active layer 5) through the oxide conductor (i.e., the first gate portion 6), thereby achieving a φms approaching zero. Therefore, the present application can produce a thin-film transistor 1 with a large aspect ratio in a smaller area, thereby effectively reducing the size of the thin-film transistor. At the same time, compared to silicon-based thin-film transistors, the use of an oxide semiconductor as the active layer and an oxide conductor as the gate can further effectively suppress the short-channel effect.

[0167] It can be understood that the thin film transistor 1 provided in the present application has a vertical channel structure and is less affected by the short channel effect, and can be applied to display products with higher resolution.

[0168] An embodiment of the present application also provides an array substrate, which includes multiple thin film transistors described in the above embodiments. Since the thin film transistors provided in the above embodiments are small in size and have stable electrical properties, more thin film transistors can be arranged on an array substrate of fixed size, which is beneficial to increase the number of driving circuits, and thus is beneficial for application in display products with high pixel resolution.

[0169] Of course, the present application also provides a display panel including the array substrate described in the above embodiment. Since the array substrate can accommodate a larger number of thin film transistors, the display panel can have more pixels, thereby achieving a display with higher pixel resolution.

[0170] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0171] The above is a detailed introduction to a thin film transistor and a manufacturing method thereof provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A thin film transistor, comprising: substrate; A source electrode, located on the substrate; A first insulating layer at least covering the substrate; The first insulating layer is provided with a first through hole arranged corresponding to the source electrode; an active layer, located in the first through hole and electrically connected to the source electrode, wherein the material forming the active layer is a semiconductor material; a first gate portion, located on the first insulating layer and spaced apart from the active layer; the first gate portion is arranged corresponding to at least a part of the side surface of the active layer, and the material forming the first gate portion is a conductive semiconductor material, and the conductive semiconductor material contains all the chemical elements contained in the semiconductor material; a second insulating layer at least covering the first insulating layer and the first gate portion; the second insulating layer is provided with a second through hole corresponding to the active layer and a third through hole corresponding to the first gate portion; and The drain electrode and the second gate portion are located on the second insulating layer and are spaced apart from each other; the drain electrode is electrically connected to the active layer through the second through hole, and the second gate portion is electrically connected to the first gate portion through the third through hole.

2. The thin film transistor according to claim 1, wherein: The active layer and the first gate portion are both metal oxides.

3. The thin film transistor according to claim 2, wherein: The material of the active layer includes any one of zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide and aluminum indium tin zinc oxide.

4. The thin film transistor according to claim 1, wherein: A maximum distance between a side of the first gate portion away from the substrate and the substrate is greater than or equal to a maximum distance between a side of the active layer away from the substrate and the substrate.

5. The thin film transistor according to claim 1, wherein: The first gate portion is disposed around the active layer.

6. The thin film transistor according to claim 5, wherein: The number of the third through holes is 2, and the number of the second gate parts is 2; the two third through holes are respectively arranged on opposite sides of the active layer, and the two second gate parts are electrically connected to the first gate part through the two third through holes respectively.

7. The thin film transistor according to claim 5, wherein: The first insulating layer includes an integrally formed first insulating portion and a second insulating portion; the first insulating portion is only located on the substrate and is arranged around the source electrode, and the second insulating portion is located on the first insulating portion and a portion of the source electrode; The distance between the substrate and the side of the active layer away from the substrate is less than or equal to the distance between the substrate and the side of the second insulating portion away from the substrate; The first gate portion includes an integrally formed first oxide conductor portion and a second oxide conductor portion; the first oxide conductor portion is located only on the first insulating portion and is arranged around the second insulating portion; the second oxide conductor portion is located on the first oxide conductor portion and the second insulating portion.

8. The thin film transistor according to claim 1, wherein: The source electrode comprises a main body portion stacked with the active layer and an extension portion extending from the main body portion in a direction away from the main body portion; at least a portion of the extension portion is arranged without overlapping with the first gate portion and the second gate portion; The thin film transistor further includes a connection electrode located on the second insulating layer and arranged corresponding to the extension portion, and the connection electrode is electrically connected to the extension portion via a fourth through hole penetrating the first insulating layer and the second insulating layer.

9. The thin film transistor according to claim 1, wherein: The drain electrode and the second gate portion are made of the same material, and the second gate portion is made of a metal material.

10. A method for manufacturing a thin film transistor, comprising the following steps: providing a substrate; A source electrode and a first insulating layer are sequentially formed on the substrate; wherein the first insulating layer at least covers the substrate, and the first insulating layer is provided with a first through hole corresponding to the source electrode; An active layer and a first gate portion are formed which are arranged at intervals; wherein the active layer is located in the first through hole and is electrically connected to the source electrode, and the first gate portion is located on the first insulating layer and is arranged corresponding to at least part of the side surface of the active layer; the material forming the active layer is a semiconductor material, and the material forming the first gate portion is a conductive semiconductor material, and the conductive semiconductor material contains all chemical elements contained in the semiconductor material; forming a second insulating layer covering at least the first insulating layer and the first gate portion; wherein the second insulating layer is formed with a second through hole corresponding to the active layer and a third through hole corresponding to the first gate portion; and A drain electrode and a second gate portion are formed on the second insulating layer and are spaced apart from each other; wherein the drain electrode is electrically connected to the active layer through the second through hole, and the second gate portion is electrically connected to the first gate portion through the third through hole.

11. The method for manufacturing a thin film transistor according to claim 10, wherein: The active layer and the first gate portion are both metal oxides; forming the active layer and the first gate portion comprises the following steps: forming an oxide semiconductor film covering the first insulating layer and the source electrode; the oxide semiconductor film includes a first region corresponding to the source electrode and a second region corresponding to a portion of the first insulating layer, the second region being spaced apart from the first region; performing patterning on the oxide semiconductor film to retain only the oxide semiconductor film located in the first region and the second region; and The oxide semiconductor film located in the second region is subjected to a conductor treatment to form a first gate portion located in the second region and an active layer located in the first region.

12. The method for manufacturing a thin film transistor according to claim 11, wherein: The material of the oxide semiconductor film includes any one of zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide and aluminum indium tin zinc oxide.

13. The method for manufacturing a thin film transistor according to claim 11, wherein: The step of performing a conductor treatment on the oxide semiconductor film located in the second region comprises the following steps: forming a second insulating layer entirely covering the first insulating layer and the patterned oxide semiconductor film; forming a mask layer disposed corresponding to the first region on the second insulating layer; performing a plasma induction treatment on the substrate having the mask layer formed thereon, so as to make the oxide semiconductor thin film located in the second region conductive; removing the mask layer; and The second insulating layer is subjected to a hole-opening process to form a second through hole corresponding to the active layer and a third through hole corresponding to the first gate portion.

14. The method for manufacturing a thin film transistor according to claim 13, wherein: The atmosphere used in the plasma induction treatment includes one or more of chlorine trifluoride, chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon and nitrogen.

15. The method for manufacturing a thin film transistor according to claim 13, wherein: The material of the mask layer includes photoresist.

16. The method for manufacturing a thin film transistor according to claim 10, wherein: The first gate portion is disposed around the active layer.

17. The method for manufacturing a thin film transistor according to claim 16, wherein: The number of the third through holes is 2, and the number of the second gate parts is 2; the two third through holes are respectively arranged on opposite sides of the active layer, and the two second gate parts are electrically connected to the first gate part through the two third through holes respectively.

18. The method for manufacturing a thin film transistor according to claim 16, wherein: The first insulating layer includes an integrally formed first insulating portion and a second insulating portion; the first insulating portion is only located on the substrate and is arranged around the source electrode, and the second insulating portion is located on the first insulating portion and a portion of the source electrode; The distance between the substrate and the side of the active layer away from the substrate is less than or equal to the distance between the substrate and the side of the second insulating portion away from the substrate; The first gate portion includes an integrally formed first oxide conductor portion and a second oxide conductor portion; the first oxide conductor portion is located only on the first insulating portion and is arranged around the second insulating portion; the second oxide conductor portion is located on the first oxide conductor portion and the second insulating portion.

19. The method for manufacturing a thin film transistor according to claim 10, wherein: The source electrode comprises a main body portion stacked with the active layer and an extension portion extending from the main body portion in a direction away from the main body portion; at least a portion of the extension portion is arranged without overlapping with the first gate portion and the second gate portion; The thin film transistor further includes a connection electrode located on the second insulating layer and arranged corresponding to the extension portion, and the connection electrode is electrically connected to the extension portion via a fourth through hole penetrating the first insulating layer and the second insulating layer.

20. The method for manufacturing a thin film transistor according to claim 10, wherein: The drain electrode and the second gate portion are made of the same material, and the second gate portion is made of a metal material.

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