Capture circuit and microprocessor chip

Abstract

Provided in the present application are a capture circuit and a microprocessor chip. The capture circuit comprises one oscillator delay line and three capture delay lines, wherein clock signals are provided for the three capture delay lines by means of the oscillator delay line, and the three capture delay lines jointly determine the position where an edge of a signal to be subjected to detection occurs. The capture circuit provided in the embodiments of the present application at least has the following advantages: 1) clock signals are provided by means of an oscillator delay line without it being necessary to additionally provide a phase-locked loop circuit or rely on a system clock; 2) since the position where an edge of a signal to be subjected to detection occurs is jointly determined by means of three capture delay lines, the length of each capture delay line can be less than one clock period; and 3) a phase difference between clock signals corresponding to different capture delay lines is set by means of the ratio of the numbers of capture delay elements in different capture delay lines, and thus the design for the clock signals and the capture delay elements is more flexible.

Description

Capture circuit and microprocessor chip

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on October 26, 2023, with application number 202311404121.8 and application name “A Capture Circuit and Microprocessing Chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a capture circuit and a microprocessor chip. Background Art

[0003] A wide range of industrial and consumer devices and instruments require the measurement of signals such as voltage, current, capacitance, speed, and distance. Measurement accuracy directly impacts the precision of these devices and instruments. High-precision digital pulse width measurement is widely used in precision instruments, sonar, robotic servos, switching power supplies, power devices, touch screens, and other devices for applications such as pulse train period / duty cycle measurement, instantaneous speed measurement, voltage measurement across isolation boundaries, distance / sonar measurement and scanning, and capacitive touch sensing.

[0004] In digital signal processing devices, signal measurement generally involves first quantizing signals such as voltage, capacitance, speed, and distance through analog-to-digital conversion into digital pulse signals (referred to as "pulse signals"), and then measuring the pulse signals. Specifically, pulse signal width measurement uses a sampling clock (frequency f) and the clock period of a sampling clock as the base unit to express the width of a pulse signal as a real number containing an integer part and a decimal part. The decimal part is caused by the misalignment of the edge of the pulse signal with the edge of the sampling clock and comes from the head and tail of the pulse signal. The relationship between the width λ of the pulse signal and f, μ, α, and β is: λ = (μ + 1-α-β) × 1 / f. μ is the integer part and 1-α-β is the decimal part.

[0005] Traditional digital signal measurement circuits have a measurement accuracy of 1 / f, the clock period of a sampling clock. They can only measure the integer portion μ of the pulse signal's width λ, but cannot measure the fractional portion 1-α-β of the pulse signal's width. Improving measurement accuracy requires increasing the sampling clock frequency, which significantly increases the power consumption and complexity of the hardware circuit.

[0006] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art.

[0007] Summary of the Invention

[0008] The present application provides a capture circuit and a microprocessor chip to solve the problem in the prior art that if measurement accuracy is to be improved, the clock frequency of the sampling clock can only be increased, thereby greatly increasing the power consumption and complexity of the hardware circuit.

[0009] In a first aspect, an embodiment of the present application provides a capture circuit, comprising:

[0010] An oscillator delay line, the oscillator delay line comprising N sequential delay elements and logic gates, the N sequential delay elements and logic gates being coupled in a ring to generate an initial clock signal, N ≥ 2;

[0011] a first capture delay line comprising A capture delay elements coupled in sequence to transmit a first clock signal in a first direction along a first signal path and to transmit a signal to be detected in a second direction opposite to the first direction along a second signal path;

[0012] a second capture delay line comprising B capture delay elements coupled in sequence to transmit a second clock signal in the first direction along a third signal path and to transmit a signal to be detected in the second direction along a fourth signal path;

[0013] a third capture delay line comprising C capture delay elements coupled in sequence to transmit a third clock signal in the first direction along a fifth signal path and to transmit a signal to be detected in the second direction along a sixth signal path;

[0014] In which, each of the capture delay elements forms a trigger and provides a one-bit output, the output is determined by a clock signal and / or a signal to be detected, the first clock signal, the second clock signal and the third clock signal are clock signals generated based on the initial clock signal, there is a first phase difference between the first clock signal and the second clock signal, there is a second phase difference between the second clock signal and the third clock signal, the first phase difference is determined by the total number of capture delay elements in the capture delay line and the number of capture delay elements in the first capture delay line, and the second phase difference is determined by the total number of capture delay elements in the capture delay line and the number of capture delay elements in the second capture delay line.

[0015] The design of three capture delay lines is particularly suitable for scenarios where the number of capture delay elements 100 must be equally divided and the number of capture delay elements 100 (for example, 15, 18, etc.) cannot be divided into two equal parts. The design of three capture delay lines in this application can provide a good solution for this application scenario.

[0016] In some possible implementations, the method further includes: there is no phase difference between the first clock signal and the initial clock signal;

[0017] a first phase shifter, configured to shift the phase of the first clock signal (or the initial clock signal) and output a second clock signal;

[0018] The second phase shifter is used to shift the phase of the second clock signal and output a third clock signal; or to shift the phase of the first clock signal (or the initial clock signal) and output a third clock signal.

[0019] In some possible implementations, there is a first phase difference between the first clock signal and the second clock signal, and there is a second phase difference between the second clock signal and the third clock signal, N=A+B+C, the first phase difference is A / N*360°, and the second phase difference is B / N*360°.

[0020] In some possible implementations, A=B=C, and the first phase difference and the second phase difference are both 120°.

[0021] In some possible implementations, A≠B≠C.

[0022] In some possible implementations, A≠B=C, A=B≠C, or A=C≠B.

[0023] In some possible implementations, there is a phase difference α between the first clock signal and the initial clock signal, and the first phase shifter is used to shift the phase of the initial clock signal by A / (A+B+C)*360°+α to output the second clock signal;

[0024] The second phase shifter is used to phase shift the second clock signal by B / (A+B+C)*360° to output a third clock signal; or to phase shift the first clock signal by A / (A+B+C)*360°+B / (A+B+C)*360° to output a third clock signal; or to phase shift the initial clock signal by A / (A+B+C)*360°+B / (A+B+C)*360°+α to output a third clock signal.

[0025] The phase shift of the phase shifter can be adaptively designed according to the number of different capture delay units in the three capture delay lines, thereby improving the flexibility of the design.

[0026] In some possible implementations, the first clock signal, the second clock signal, and the third clock signal are delayed by a specified time period relative to the initial clock signal.

[0027] In some possible implementations, the capture delay element includes:

[0028] A first NAND gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the first NAND gate is used to receive a clock signal transmitted in the first direction;

[0029] a second NAND gate, comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second NAND gate is electrically connected to the output terminal of the first NAND gate, the second input terminal of the second NAND gate is set to 1, and the output terminal of the second NAND gate is used to output a clock signal in the first direction;

[0030] a third NAND gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the third NAND gate is used to receive the signal to be detected transmitted in the second direction;

[0031] a fourth NAND gate, comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the fourth NAND gate is set to 1, the second input terminal of the fourth NAND gate is electrically connected to the output terminal of the third NAND gate, and the output terminal of the fourth NAND gate is used to output the signal to be detected in the second direction;

[0032] The second input terminal of the first NAND gate is electrically connected to the second input terminal of the fourth NAND gate, and the first input terminal of the second NAND gate is electrically connected to the second input terminal of the third NAND gate.

[0033] In some possible implementations, the timing delay element includes:

[0034] a fifth NAND gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the fifth NAND gate is used to connect to the output terminal of the previous timing delay element, and the second input terminal of the fifth NAND gate is set to 1;

[0035] A sixth NAND gate includes a first input terminal, a second input terminal and an output terminal, the first input terminal of the sixth NAND gate is set to 1, the second input terminal of the sixth NAND gate is electrically connected to the output terminal of the fifth NAND gate, and the output terminal of the sixth NAND gate is used to connect to the input terminal of the next timing delay element.

[0036] Some possible implementations also include:

[0037] a multiplexer coupled to the signal to be detected input ends of the first capture delay line, the second capture delay line, and the third capture delay line, and configured to provide the signal to be detected, or an inverted signal of the signal to be detected, or a phase-shifted signal of the signal to be detected, to the first capture delay line, the second capture delay line, and the third capture delay line.

[0038] In a second aspect, an embodiment of the present application provides a microprocessor chip comprising the capture circuit described in any one of the first aspects.

[0039] The capture circuit provided by the embodiments of the present application has at least the following advantages:

[0040] 1) The clock signal is provided by the oscillator delay line, which does not require an additional phase-locked loop circuit and is independent of the system clock;

[0041] 2) Since the edge position of the signal to be detected is determined by three capture delay lines, the length of each capture delay line can be less than one clock cycle;

[0042] 3) The phase difference between clock signals corresponding to different capture delay lines is set by the ratio of the number of capture delay elements in different capture delay lines, which makes the design of clock signals and capture delay elements more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0044] FIG1 is a schematic structural diagram of a capture delay element provided in an embodiment of the present application;

[0045] FIG2 is a schematic diagram of the structure of a capture delay line provided in an embodiment of the present application;

[0046] FIG3 is a schematic diagram of the structure of a timing delay element provided in an embodiment of the present application;

[0047] FIG4 is a schematic diagram of the structure of an oscillator delay line provided in an embodiment of the present application;

[0048] FIG5 is a schematic diagram of the structure of a capture circuit provided in an embodiment of the present application;

[0049] FIG6 is a timing diagram of a clock signal provided in an embodiment of the present application;

[0050] FIG7 is a schematic diagram of the structure of another capture circuit provided in an embodiment of the present application;

[0051] FIG8 is a signal timing diagram of edge detection using the capture circuit shown in FIG7 ;

[0052] FIG9 is a schematic structural diagram of another capture circuit provided in an embodiment of the present application;

[0053] FIG10 is a schematic diagram of the structure of another capture circuit provided in an embodiment of the present application;

[0054] FIG11 is a schematic structural diagram of a microprocessor chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0056] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0057] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0058] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0059] Refer to Figure 1, which is a schematic diagram of the structure of a capture delay element provided in an embodiment of the present application. As shown in Figure 1, the capture delay element 100 includes a first NAND gate 110, a second NAND gate 120, a third NAND gate 130 and a fourth NAND gate 140. Among them, the first input terminal 111 of the first NAND gate 110 is used to receive a first signal transmitted in a first direction (from right to left), such as a clock signal; the first input terminal 121 of the second NAND gate 120 is electrically connected to the output terminal 113 of the first NAND gate 110, the second input terminal 122 of the second NAND gate 120 is set to 1, and the output terminal 123 of the second NAND gate 120 is used to output the first signal in the first direction; the first input terminal 131 of the third NAND gate 130 is used to receive a second signal transmitted in a second direction (from left to right). A signal, such as a signal to be detected, is provided; first input terminal 141 of fourth NAND gate 140 is set to 1, second input terminal 142 of fourth NAND gate 140 is electrically connected to output terminal 133 of third NAND gate 130, and output terminal 143 of fourth NAND gate 140 is configured to output a second signal in a second direction; second input terminal 112 of first NAND gate 110 is electrically connected to second input terminal 142 of fourth NAND gate 140, and first input terminal 121 of second NAND gate 120 is electrically connected to second input terminal 132 of third NAND gate 130. Furthermore, output terminal 143 of fourth NAND gate 140 provides an output bit. In other words, capture delay element 100 can receive two signals input in opposite directions and provide a single bit output.

[0060] It should be noted that FIG1 illustrates capture delay element 100 using a NAND gate as an example. However, those skilled in the art will appreciate that other logic circuits may be used in place of the NAND gate to implement the relevant functions of capture delay element 100, and all such circuits are intended to fall within the scope of protection of this application.

[0061] Referring to FIG2 , which is a schematic diagram of the structure of a capture delay line provided in an embodiment of the present application. As shown in FIG2 , the capture delay line 200 includes M capture delay elements 100, which are coupled together in sequence to form the capture delay line 200. A first signal (e.g., a clock signal SYSCLK, which may also be referred to as “SYNCIN” in other parts of this document) is received on the lower signal path of the capture delay line 200 and is transmitted from right to left through the lower signal path of the capture delay line 200. A second signal (e.g., a signal to be detected ECAPxIN[x], which may also be referred to as “ASYNCIN” in other parts of this document) is received on the upper signal path of the capture delay line 200 and is transmitted from left to right through the upper signal path of the capture delay line 200.

[0062] Specifically, the high ("1") input corresponding to the rising edge of the clock signal SYSCLK captures the delay element 100-(M-1), causing the first NAND gate 110-(M-1) of the capture delay element 100-(M-1) to generate a low ("0") output; the low ("0") input of the first NAND gate 110-(M-1) to the second NAND gate 120-(M-1) causes the second NAND gate 120-(M-1) to generate a high ("1") output, so that the rising edge is transmitted from right to left, as shown by the lower arrow in Figure 2. At the same time, in the absence of any other inputs, the low ("0") input of the first NAND gate 110-(M-1) is fed into the third NAND gate 120-(M-1), resulting in a high ("1") output from the third NAND gate 120-(M-1); the high ("1") input of the third NAND gate 120-(M-1) is fed into the fourth NAND gate 140-(M-1), resulting in a low ("0") output from the fourth NAND gate 140-(M-1). This means that the output bit HR(M-1) of the capture delay element 100-(M-1) is set to 0. As the rising edge propagates from right to left, the output bits of the corresponding capture delay elements are sequentially set to 0, meaning that the output is determined by the clock signal.

[0063] Similarly, the rising edge of the signal to be detected ECAPxIN[x] corresponds to a high ("1") input to the capture delay element 100-0, causing the third NAND gate 130-0 of the capture delay element 100-0 to produce a low ("0") output. The low ("0") input of the third NAND gate 130-0 to the fourth NAND gate 140-0 causes a high ("1") output from the fourth NAND gate 140-0, causing the rising edge to propagate from left to right, as indicated by the upper arrow in FIG2 . Simultaneously, in the absence of any other inputs, the output bit HR(0) of the capture delay element 100-0 is set to 1. As the rising edge propagates from left to right, the output bits of the corresponding capture delay elements are sequentially set to 1, meaning that the output is determined by the signal to be detected.

[0064] It can be understood that the clock signal SYSCLK and the signal to be detected ECAPxIN[x] will eventually meet. After this meeting, the state of the output bit of the capture delay element 100 no longer changes, and the clock signal SYSCLK and the signal to be detected ECAPxIN[x] do not propagate further. Therefore, the state of the output bit of the capture delay element 100 depends on which of the rising edges of the clock signal SYSCLK and the signal to be detected ECAPxIN[x] reaches the capture delay element 100 first. Specifically, if the rising edge of the clock signal SYSCLK reaches the capture delay element 100 first, the state of the output bit of the capture delay element 100 is low ("0"); if the rising edge of the signal to be detected ECAPxIN[x] reaches the capture delay element 100 first, the state of the output bit of the capture delay element 100 is high ("1"). Therefore, the shift of the two signals results in a string of "1s" starting from the capture delay element 100-0 and a string of "0s" starting from the capture delay element 100-(M-1). That is, the output is determined by the clock signal and the signal to be detected.

[0065] Because the clock signal SYSCLK always propagates through half of the capture delay line 200, the state of the output bits in the right half of the capture delay line 200 is always 0. For example, if the rising edges of the clock signal SYSCLK and the signal to be detected ECAPxIN[x] occur simultaneously, the capture delay line 200 is frozen in the middle, that is, the states of the output bits in the left half of the capture delay line 200 are all 1, and the states of the output bits in the right half are all 0. If the rising edge of the signal to be detected ECAPxIN[x] occurs later than the rising edge of the clock signal SYSCLK, the states of the output bits in the left half of the capture delay line 200 are partially 1 and partially 0, while the states of the output bits in the right half are all 0. The number of "1s" in the output bits in the left half of the capture delay line 200 will depend on the time difference between the clock signal SYSCLK and the signal to be detected ECAPxIN[x]. Therefore, by decoding the number of 1s in HR[M-1:0] of the capture delay line 200 , the position of the detected signal ECAPxIN[x] relative to the clock signal SYSCLK can be determined, thereby achieving high resolution of pulse width measurement.

[0066] Referring to FIG3 , which is a schematic diagram of the structure of a timing delay element provided in an embodiment of the present application, as shown in FIG3 , the timing delay element 300 includes a fifth NAND gate 310 and a sixth NAND gate 320 . The first input 311 of the fifth NAND gate 310 is used to connect to the output of the previous timing delay element, and the second input 312 of the fifth NAND gate 310 is set to 1; the first input 3231 of the sixth NAND gate 320 is set to 1, the second input 322 of the sixth NAND gate 320 is electrically connected to the output 313 of the fifth NAND gate 310, and the output 323 of the sixth NAND gate 320 is used to connect to the input of the next timing delay element.

[0067] It should be noted that FIG3 illustrates the sequential delay element 300 using a NAND gate as an example. However, those skilled in the art will appreciate that other logic circuits can be used in place of the NAND gate to implement the relevant functions of the sequential delay element 300, and all such circuits should fall within the scope of protection of this application.

[0068] Referring to FIG4 , a schematic diagram of the structure of an oscillator delay line provided in an embodiment of the present application is shown. As shown in FIG4 , the oscillator delay line 400 includes N sequential delay elements 300, where N≥2. The N sequential delay elements 300 are coupled together in sequence to form the oscillator delay line 400. In addition, the oscillator delay line 400 also includes a seventh NAND gate 401, wherein the first input end of the seventh NAND gate 401 is used to receive the enable control signal HRCLK_EN, the second input end of the seventh NAND gate 401 is electrically connected to the output end of the sequential delay element 300-(N-1) (the last sequential delay element), and the output end of the seventh NAND gate 401 is electrically connected to the first input end of the sequential delay element 300-0 (the frontmost sequential delay element), so that the N sequential units and the seventh NAND gate 401 form a ring loop.

[0069] When the enable control signal HRCLK_EN is high ("1"), the oscillator delay line 400 forms an oscillator and can generate a clock signal. To distinguish it from other clock signals described below, the clock signal generated by the oscillator delay line 400 is referred to as the "initial clock signal HRCLK." Assuming the delay generated by a timing delay element 300 is δ, the relationship between the clock period THRCLK of the initial clock signal HRCLK output after the oscillator stabilizes, the delay δ of the timing delay element 300, and the number of timing delay elements 300, N, is: THRCLK = 2*N*δ, where N is an even number.

[0070] It should be noted that those skilled in the art may also implement related functions by replacing the seventh NAND gate 401 with other logic gates as needed. Alternatively, the seventh NAND gate 401 may be omitted from the oscillator delay line 400, so that the output of the last sequential delay element 300 is electrically connected to the input of the first sequential delay element 300, forming a loop. However, in this case, if an oscillator is formed, the number N of sequential delay elements 300 in the oscillator delay line 400 should be an odd number.

[0071] Continuing with Figure 2, since the clock signal SYSCLK always propagates through half of the capture delay line 200, the length of the capture delay line 200 must span two clock periods of the clock signal SYSCLK to accurately capture the edge of the detection signal ECAPxIN[x]. Furthermore, the resolution of the pulse width measurement depends on the clock period TSYSCLK of the clock signal SYSCLK and the number M of capture delay elements 100: specifically, TSYSCLK divided by (M / 2). It should be noted that the length of the capture delay line 200 refers to the time it takes for a signal to propagate from one end of the capture delay line 200 to the other.

[0072] From another perspective, a capture delay line 200 of a specified length can only support a specific clock frequency. If it relies on the system clock, the length of the capture delay line 200 may not be flexibly adjusted. Furthermore, in some application scenarios, the system clock may run at a different frequency, making it unavailable for the circuit. By providing a dedicated clock for the capture delay line, independent of the system clock, greater flexibility can be achieved. However, this requires the addition of a phase-locked loop circuit to the dedicated clock circuit, increasing circuit cost.

[0073] In summary, the capture delay line 200 shown in FIG2 has at least the following problems: 1) Since a capture delay line with a specified length can only support a specific clock frequency, if it depends on the system clock, the length of the capture delay line cannot be flexibly adjusted; 2) If a dedicated clock independent of the system clock is set for the capture delay line, a phase-locked loop circuit needs to be added, thereby increasing the circuit cost; 3) The length of the capture delay line needs to be designed to be greater than two clock cycles to work properly.

[0074] In response to the above problems, an embodiment of the present application provides a capture circuit, including one oscillator delay line and three capture delay lines, wherein the oscillator delay line provides a clock signal to the three capture delay lines, and the three capture delay lines jointly determine the position where the edge of the signal to be detected occurs. The capture circuit provided by the embodiment of the present application has at least the following advantages: 1) The clock signal is provided by the oscillator delay line, and there is no need to set up an additional phase-locked loop circuit, and it does not rely on the system clock; 2) Since the position where the edge of the signal to be detected occurs is jointly determined by the three capture delay lines, the length of each capture delay line can be less than one clock cycle; 3) The phase difference between the clock signals corresponding to different capture delay lines is set by the ratio of the number of capture delay elements in different capture delay lines, which makes the design of the clock signal and the capture delay element more flexible. This will be described in detail below in conjunction with the specific implementation method.

[0075] See Figure 5, which is a schematic diagram of the structure of a capture circuit provided in an embodiment of the present application. As shown in Figure 5, the capture circuit includes an oscillator delay line 400 and three capture delay lines 200 (a first capture delay line 201, a second capture delay line 202, and a third capture delay line 203). The oscillator delay line 400 includes N timing delay elements 300, where N ≥ 2; the first capture delay line 201 includes A capture delay elements 100; the second capture delay line 202 includes B capture delay elements 100; and the third capture delay line 203 includes C capture delay elements 100.

[0076] When the oscillator delay line 400 is operating, it can generate an initial clock signal HRCLK. Furthermore, based on the initial clock signal HRCLK, it can generate a first clock signal HRCLK1, a second clock signal HRCLK2, and a third clock signal HRCLK3, which are provided to the three capture delay lines 200, respectively. In other words, in the embodiment of the present application, the clock signal is provided by the oscillator delay line 400. Therefore, an additional phase-locked loop circuit is not required, and the system clock is not dependent on the system clock.

[0077] Refer to Figure 6, which is a timing diagram of a clock signal provided in an embodiment of the present application. As shown in Figure 6, there is a first phase difference between the first clock signal HRCLK1 and the second clock signal HRCLK2, and a second phase difference between the second clock signal HRCLK2 and the third clock signal HRCLK3. In an embodiment of the present application, one clock cycle of the clock signal can be divided into three time intervals by the phase difference between different clock signals. In time interval A, the first capture delay line 201 provides the position where the edge of the signal to be detected ECAPxIN[x] occurs. Specifically, the first capture delay line 201 transmits the first clock signal HRCLK1 in a first direction (from right to left) along the first signal path, and transmits the signal to be detected ECAPxIN[x] in a second direction (from left to right) opposite to the first direction along the second signal path. In time interval B, the second capture delay line 202 provides the position where the edge of the signal to be detected ECAPxIN[x] occurs. Specifically, the second capture delay line 202 transmits the second clock signal HRCLK2 in the first direction along the third signal path, and transmits the signal to be detected ECAPxIN[x] in the second direction along the fourth signal path. In time interval C, the third capture delay line 203 provides the location of the edge of the signal to be detected ECAPxIN[x]. Specifically, the third capture delay line 203 transmits the third clock signal HRCLK3 in the first direction along the fifth signal path, and transmits the signal to be detected ECAPxIN[x] in the second direction along the sixth signal path.

[0078] That is, each capture delay line 200 is only responsible for detecting a certain time interval within a clock cycle, and the three capture delay lines 200 jointly determine the position where the edge of the signal to be detected ECAPxIN[x] occurs. As described above, when using a capture delay line 200 shown in Figure 2 for signal edge detection, in order to accurately capture the position where the edge of the signal to be detected ECAPxIN[x] occurs, the capture delay line 200 must span two clock cycles. In the embodiment of the present application, since the position where the edge of the signal to be detected ECAPxIN[x] occurs is jointly determined by the three capture delay lines 200, the length of each capture delay line 200 can be less than one clock cycle.

[0079] It is understood that the length of the capture delay line 200 can be characterized by the number of capture delay elements 100 in the capture delay line 200. Since the "ratio of the number of capture delay elements 100 in different capture delay lines 200" is associated with the "phase difference between the clock signals corresponding to different capture delay lines 200," the "phase difference between the clock signals corresponding to different capture delay lines 200" can be determined by the "ratio of the number of capture delay elements 100 in different capture delay lines 200." Specifically, the phase difference between the first clock signal HRCLK1 and the second clock signal HRCLK2, i.e., the first phase difference, is A / (A+B+C)*360°; the phase difference between the second clock signal HRCLK2 and the third clock signal HRCLK3, i.e., the second phase difference, is B / (A+B+C)*360°. A, B, and C are the numbers of capture delay elements 100 in the first capture delay line 201, the second capture delay line 202, and the third capture delay line 203, respectively. For example, when A=B=C, the first phase difference and the second phase difference are both 120°. When A=2B=C, the first phase difference is 90° and the second phase difference is 180°.

[0080] In addition, the embodiment of the present application does not limit the number of capture delay elements 100 in the three capture delay lines 200, nor the ratio of the number of capture delay elements 100 in different capture delay lines 200. For example, the number of capture delay elements 100 in the three capture delay lines 200 can be configured as follows: A=B=C, A≠B≠C, A≠B=C, or A=B≠C. Specifically, A=B=C=1, or A=1, B=2, C=3, or A≥2, B≥2, C≥2, or A=0, B≥1, C≥1. In this case, only two capture delay lines are in operation, N=2, and the phase difference of the phase shift is determined by the number of B and C, such as the phase difference B / (B+C)*360.

[0081] In summary, in the embodiments of the present application, the number of capture delay elements 100 in different capture delay lines 200 can be flexibly configured, and the phase difference between the clock signals corresponding to different capture delay lines 200 can be set by the ratio of the number of capture delay elements 100 in different capture delay lines 200, which makes the design of clock signals and capture delay elements 100 more flexible.

[0082] Furthermore, in some possible application scenarios, the number of capture delay elements 100 must be equally divided, meaning that the lengths of the different capture delay lines 200 must be equal. If there are only two capture delay lines 200 and the number of capture delay elements 100 (e.g., 15, 18, etc.) cannot be equally divided, the design requirements cannot be met. However, the design of three capture delay lines 200 in the embodiment of the present application can provide a good solution for this application scenario.

[0083] Continuing with FIG. 5 , in this embodiment of the present application, the capture circuit further includes a first phase shifter and a second phase shifter. After the oscillator delay line 400 generates the initial clock signal HRCLK, a first clock signal HRCLK1 can be determined based on the initial clock signal HRCLK. The first clock signal HRCLK1 can be identical to the initial clock signal HRCLK, or it can be a signal delayed by a predetermined time (e.g., by 1 / 6 of a clock cycle) from the initial clock signal HRCLK. Delaying the initial clock signal HRCLK allows time for subsequent phase shifting by the first and second phase shifters.

[0084] After obtaining the first clock signal HRCLK1, the first phase shifter can phase-shift the first clock signal HRCLK1 to obtain the second clock signal HRCLK2; the second phase shifter can phase-shift the second clock signal HRCLK2 to obtain the third clock signal HRCLK3. Of course, in some possible implementations, the second phase shifter can also directly phase-shift the first clock signal HRCLK1 to obtain the third clock signal HRCLK3. For example, if both the first phase difference and the second phase difference are 120°, the first phase shifter can phase-shift the first clock signal HRCLK1 by 120° to obtain the second clock signal HRCLK2; and the second phase shifter can phase-shift the second clock signal HRCLK2 by 120° to obtain the third clock signal HRCLK3. Alternatively, the first phase shifter can phase-shift the first clock signal HRCLK1 by 120° to obtain the second clock signal HRCLK2; and the second phase shifter can phase-shift the first clock signal HRCLK1 by 240° to obtain the third clock signal HRCLK3.

[0085] In some possible implementations, there is a phase difference α (α can be positive or negative) between the first clock signal and the initial clock signal. The first phase shifter is used to shift the initial clock signal by A / (A+B+C)*360°+α to output a second clock signal; the second phase shifter is used to shift the second clock signal by B / (A+B+C)*360° to output a third clock signal; or, shift the first clock signal by A / (A+B+C)*360°+B / (A+B+C)*360° to output a third clock signal; or, shift the initial clock signal by A / (A+B+C)*360°+B / (A+B+C)*360°+α.

[0086] In some possible implementations, the first clock signal HRCLK1, the second clock signal HRCLK2, and the third clock signal HRCLK3 having specified phase differences can be directly obtained at different nodes of the oscillator delay line 400. These signals also fall within the scope of "clock signals generated based on the initial clock signal HRCLK." It is understood that in this case, the first and second phase shifters in the capture circuit can be omitted.

[0087] Continuing with FIG5 , in this embodiment of the present application, the capture circuit further includes a multiplexer 510. A first input 511 of the multiplexer 510 is configured to receive the detection signal ECAPxIN[x], and a second input 512 is configured to receive an inverted version of the detection signal ECAPxIN[x]. An output 514 of the multiplexer 510 is electrically connected to the first capture delay line 201, the second capture delay line 202, and the third capture delay line 203, respectively. The control terminal 514 of the multiplexer 510 can receive the control signal CAPIN and, based on the control signal CAPIN, select the connection between the first input terminal 511 and the output terminal 514 to provide the first capture delay line 201, the second capture delay line 202, and the third capture delay line 203 with the detection signal ECAPxIN[x]; or, select the connection between the second input terminal 512 and the output terminal 514 to provide the first capture delay line 201, the second capture delay line 202, and the third capture delay line 203 with the inverted signal of the detection signal ECAPxIN[x].

[0088] In some possible implementations, the multiplexer 510 may also receive a phase-shifted signal of the signal to be detected ECAPxIN[x], and then select, through the control signal CAPIN, to provide the phase-shifted signal of the signal to be detected ECAPxIN[x] to the first capture delay line 201, the second capture delay line 202, and the third capture delay line 203. That is, in combination with FIG5 , the inverter design shown in the figure may be changed to one or more phase shifters, so that the phase-shifted signals of the signal to be detected ECAPxIN[x] are respectively input into the corresponding capture delay lines for subsequent data processing.

[0089] For ease of understanding, the technical solution provided in the embodiments of the present application is described in detail below in combination with specific implementation methods.

[0090] FIG7 is a schematic diagram illustrating the structure of another capture circuit according to an embodiment of the present application. As shown in FIG7 , the capture circuit includes one oscillator delay line 400 and three capture delay lines 200 (a first capture delay line 201, a second capture delay line 202, and a third capture delay line 203). The oscillator delay line 400 includes six sequential delay elements 300, and each capture delay line 200 includes six capture delay elements 100.

[0091] When the enable control signal HRCLK_EN of the seventh NAND gate 401 in the oscillator delay line 400 is low ("0"), the oscillator delay line 400 is inoperative. When the enable control signal HRCLK_EN of the oscillator delay line 400 is high ("1"), the oscillator delay line 400 forms an oscillator, generating an initial clock signal HRCLK. The first clock signal HRCLK1 can then be determined based on the initial clock signal HRCLK. Since the number of sequential delay elements 300 in the three capture delay lines 200 is equal, the first phase difference A / (A+B+C)*360°=120°. In other words, the first phase shifter can shift the first clock signal HRCLK1 by 120° to generate the second clock signal HRCLK2. Similarly, the second phase difference B / (A+B+C)*360°=120° allows the second phase shifter to shift the second clock signal HRCLK2 by 120° to generate the third clock signal HRCLK3. Accordingly, each capture delay line 200 is responsible for detection work for 1 / 3 of the clock cycle. Specifically, during the 0-1 / 3 period, the first capture delay line 201 determines the position of the edge of the detection signal ECAPxIN[x]; during the 1 / 3-2 / 3 period, the second capture delay line 202 determines the position of the edge of the detection signal ECAPxIN[x]; and during the 2 / 3-3 / 3 period, the third capture delay line 203 determines the position of the edge of the detection signal ECAPxIN[x].

[0092] FIG8 is a signal timing diagram illustrating edge detection using the capture circuit shown in FIG7 . As shown in FIG8 , during time interval A, the first clock signal HRCLK1 is high. The rising edge of the first clock signal HRCLK1 propagates from right to left along the first signal path in the first capture delay line 201. The detection signal ECAPxIN[x] goes high during time interval A, and the rising edge of the detection signal ECAPxIN[x] propagates from left to right along the second signal path in the first capture delay line 201. The output of the first capture delay line 201 is latched in HR1[5:0] and transmitted after a short delay. During time interval B, the second clock signal HRCLK2 is high. The rising edge of the second clock signal HRCLK2 propagates from right to left along the third signal path in the second capture delay line 202. During time interval B, the detection signal ECAPxIN[x] remains high, and this high level propagates from left to right along the fourth signal path in the second capture delay line 202. The output of the second capture delay line 202 is latched in HR2[5:0] and transmitted after a short delay. During time interval C, the third clock signal HRCLK3 is at a high level. The rising edge of the third clock signal HRCLK3 propagates from right to left along the fifth signal path in the third capture delay line 203. During time interval C, the detection signal ECAPxIN[x] is always at a high level. This high level propagates from left to right along the sixth signal path in the third capture delay line 203. The output of the third capture delay line 203 is latched in HR3[5:0] and transmitted after a short delay.

[0093] After the three values ​​of HR1[5:0], HR2[5:0], and HR3[5:0] are all captured, the three values ​​are connected as HROUT[5:0]. By counting the number of 1s in HROUT[5:0], the HR value can be determined. This HR value can represent the position of the rising edge of the signal to be detected ECAPxIN[x] in one clock cycle, and then the fractional part of the pulse width can be determined, achieving high-precision measurement of the pulse width.

[0094] As described above, because the clock signal always propagates through half of the capture delay line 200, the output bits in the right half of the capture delay line 200 are always in the state of 0. These values ​​do not need to be captured and transmitted. Therefore, only half of the output bits in HROUT[5:0] need to be counted. Accordingly, when the total number of capture delay elements 100 in the three capture delay lines 200 is M, the capture circuit's resolution is: the clock signal's clock period THRCLK divided by M / 2.

[0095] For example, in the capture circuit shown in FIG7 , each capture delay line 200 includes six capture delay elements 100. Therefore, three output bits need to be counted in each capture delay line 200. The relationship between the detection signal ECAPxIN[x], HROUT[5:0], HR value, and capture value is shown in Table 1. The data in the detection signal ECAPxIN[x] represents the relative position of the edge (e.g., rising edge) of the detection signal ECAPxIN[x] and the clock signal. For example, when the edge of the detection signal ECAPxIN[x] is at the 1 / 9 position of the clock signal, HROUT[5:0] captured by the capture circuit is 111_111_110. By counting the proportion of 1s in HROUT[5:0], the HR value can be determined to be 1 / 9, and the capture value can be determined to be (1 / 9)+5. The value "5" in this portion represents the integer portion of the pulse width of the detection signal ECAPxIN[x]. Similarly, when the edge of the signal to be detected ECAPxIN[x] is located at other positions of the clock signal, the corresponding capture value can be obtained by the capture circuit, thereby achieving high-precision measurement of the pulse width.

[0096] Table 1:

[0097] Refer to Figure 9, which is a schematic diagram of the structure of another capture circuit provided in an embodiment of the present application. As shown in Figure 9, the oscillator delay line 400 of the capture circuit includes 15 sequential delay elements 300, the first capture delay line 201 includes 5 capture delay elements 100; the second capture delay line 202 includes 5 capture delay elements 100; and the third capture delay line 203 includes 5 capture delay elements 100. In other words, the number N of sequential delay elements 300 in the oscillator delay line 400 = the number A of capture delay elements 100 in the first capture delay line 201 + the number B of capture delay elements 100 in the second capture delay line 202 + the number C of capture delay elements 100 in the third capture delay line 203.

[0098] In the embodiment of the present application, each timing delay element 300 and each capture delay element 100 have similar delays. It can be understood that in this case, when N = A + B + C, the lengths of the three capture delay lines 200 match the clock period of the clock signal generated by the oscillator delay line 400, and since A = B = C, each capture delay line 200 is used to detect a signal of 1 / 3 of the clock period.

[0099] For the specific contents of the embodiments of the present application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0100] Referring to FIG10 , a schematic diagram of the structure of another capture circuit provided in an embodiment of the present application is shown. As shown in FIG10 , the embodiment of the present application differs from the embodiment shown in FIG9 in that the second capture delay line 202 includes four capture delay elements 100. It is understood that if the capture delay line 200 includes five capture delay elements 100, a signal of 1 / 3 of the clock cycle can be detected. When the number of capture delay elements 100 is reduced by one (including four capture delay elements 100), it is estimated that a signal with a timing of (1 / 3 of the clock cycle) * (1 / 5) will be lost, which will have a certain impact on the final capture result. However, if a capture delay line 200 includes a large number of capture delay elements 100, for example 50, when the number of capture delay elements 100 is reduced by one (including 49 capture delay elements 100), it is estimated that a signal with a timing of (1 / 3 of the clock cycle) * (1 / 50) will be lost, which has a smaller impact on the final capture result and is generally within the acceptable signal loss range. That is, even if the length of the capture delay line 200 does not match the preset clock period, normal signal detection can be performed as long as the difference is not too large.

[0101] It should be noted that in the embodiments of the present application, A=C≠B is used as an example for illustration. Those skilled in the art may configure the capture delay elements 100 in the three capture delay lines 200 to have other numerical relationships, as needed. For example, A≠B=C, A=B≠C, or A≠B≠C. This embodiment of the present application does not impose any specific limitations on this.

[0102] For the specific contents of the embodiments of the present application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0103] Corresponding to the above embodiment, the embodiment of the present application further provides a microprocessor chip.

[0104] FIG11 is a schematic diagram illustrating the structure of a microprocessor chip according to an embodiment of the present application. As shown in FIG11 , the microprocessor chip includes a capture circuit. The details of the capture circuit can be found in the description of the above embodiment and will not be repeated here for the sake of brevity.

[0105] In a specific implementation, the microprocessor chip can be a control module, DSP, MPU, micro CPU, etc. that can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions, etc., a micro central control chip, an on-chip system chip, etc. The embodiment of this application does not limit its product form and specific functions.

[0106] For the specific contents of the embodiments of the present application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0107] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0108] Those skilled in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented using a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0110] In the several embodiments provided in this application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of this application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc., various media that can store program code.

[0111] The above description is merely a specific embodiment of the present application. Any person skilled in the art may easily conceive of variations or substitutions within the technical scope disclosed in this application, and such variations or substitutions shall be within the scope of protection of this application. The scope of protection of this application shall be subject to the scope of protection of the claims.

Claims

1. A capture circuit, characterized in that: include: An oscillator delay line, the oscillator delay line comprising N sequential delay elements and logic gates, the N sequential delay elements and logic gates being coupled in sequence into a ring to generate an initial clock signal, N≥2; a first capture delay line, the first capture delay line comprising A capture delay elements coupled in sequence to transmit a first clock signal in a first direction along a first signal path and to transmit a signal to be detected in a second direction opposite to the first direction along a second signal path; a second capture delay line, the second capture delay line comprising B capture delay elements coupled in sequence to transmit a second clock signal in the first direction along a third signal path and to transmit a signal to be detected in the second direction along a fourth signal path; a third capture delay line, the third capture delay line comprising C capture delay elements coupled in sequence to transmit a third clock signal in the first direction along a fifth signal path and to transmit a signal to be detected in the second direction along a sixth signal path; Wherein, each of the capture delay elements forms a trigger and provides a one-bit output, the output is determined by a clock signal and / or a signal to be detected, the first clock signal, the second clock signal and the third clock signal are clock signals generated according to the initial clock signal, there is a first phase difference between the first clock signal and the second clock signal, there is a second phase difference between the second clock signal and the third clock signal, the sum of the number of capture delay elements of the capture delay line and the number of capture delay elements of the first capture delay line determine the first phase difference, and the sum of the number of capture delay elements of the capture delay line and the number of capture delay elements of the second capture delay line determine the second phase difference.

2. The capture circuit according to claim 1, characterized in that: Also includes: A first phase shifter, used for shifting the phase of the first clock signal and outputting a second clock signal; A second phase shifter, used for phase shifting the second clock signal and outputting a third clock signal; Alternatively, the first clock signal is phase-shifted to output a third clock signal.

3. The capture circuit according to claim 1, characterized in that: There is a phase difference α between the first clock signal and the initial clock signal, and the first phase shifter is used to shift the phase of the initial clock signal by A / (A+B+C)*360°+α to output a second clock signal; A second phase shifter is used to shift the second clock signal by B / (A+B+C)*360° to output a third clock signal; or, to shift the first clock signal by A / (A+B+C)*360°+B / (A+B+C)*360° to output a third clock signal; or, to shift the initial clock signal by A / (A+B+C)*360°+B / (A+B+C)*360°+α to output a third clock signal.

4. The capture circuit according to claim 1, characterized in that: There is a first phase difference between the first clock signal and the second clock signal, and there is a second phase difference between the second clock signal and the third clock signal, N=A+B+C, the first phase difference is A / N*360°, and the second phase difference is B / N*360°.

5. The capture circuit according to claim 4, characterized in that: A=B=C, and the first phase difference and the second phase difference are both 120°.

6. The capture circuit according to claim 4, characterized in that: A≠B≠C, or A≠B=C, or A=B≠C, or A=C≠B.

7. The capture circuit according to claim 1, characterized in that: The first clock signal, the second clock signal and the third clock signal are delayed for a specified time period relative to the initial clock signal.

8. The capture circuit according to claim 1, characterized in that: The capture delay element comprises: A first NAND gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the first NAND gate is used to receive a clock signal transmitted in the first direction; A second NAND gate comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the second NAND gate is electrically connected to the output terminal of the first NAND gate, the second input terminal of the second NAND gate is set to 1, and the output terminal of the second NAND gate is used to output a clock signal in the first direction; A third NAND gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the third NAND gate is used to receive the signal to be detected transmitted in the second direction; a fourth NAND gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the fourth NAND gate is set to 1, the second input terminal of the fourth NAND gate is electrically connected to the output terminal of the third NAND gate, and the output terminal of the fourth NAND gate is used to output the signal to be detected in the second direction; The second input terminal of the first NAND gate is electrically connected to the second input terminal of the fourth NAND gate, and the first input terminal of the second NAND gate is electrically connected to the second input terminal of the third NAND gate.

9. The capture circuit according to claim 1, characterized in that: The timing delay element comprises: A fifth NAND gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the fifth NAND gate is used to connect to the output terminal of the previous timing delay element, and the second input terminal of the fifth NAND gate is set to 1; The sixth NAND gate comprises a first input terminal, a second input terminal and an output terminal, the first input terminal of the sixth NAND gate is set to 1, the second input terminal of the sixth NAND gate is electrically connected to the output terminal of the fifth NAND gate, and the output terminal of the sixth NAND gate is used to connect to the input terminal of the next timing delay element.

10. The capture circuit according to claim 1, characterized in that: Also includes: A multiplexer is coupled to the input ends of the signal to be detected of the first capture delay line, the second capture delay line and the third capture delay line, and is used to provide the signal to be detected, or an inverted signal of the signal to be detected, or a phase-shifted signal of the signal to be detected to the first capture delay line, the second capture delay line and the third capture delay line.

11. A microprocessor chip, characterized in that: The capture circuit comprises the capture circuit according to any one of claims 1 to 10.

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