Wafer stage with thermally-conditioned z-stage

Abstract

A system for controlling a temperature of a stage and reducing heat transfer from the stage to a sample is disclosed. The system may reduce a temperature difference between a first component of the stage and a second component of the stage to about 0.5 °C. A sample under inspection may not be exposed to significant changes in temperature and may not become contaminated via thermal-induced particle contamination.

Description

WAFER STAGE WITH THERMALLY-CONDITIONED Z-STAGECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of US application 63 / 592,418 which was filed on October 23, 2023 and which is incorporated herein in its entirety by reference.FIELD

[0002] The embodiments provided herein disclose a system for controlling a temperature of a stage and reducing heat transfer from the stage to a sample.BACKGROUND

[0003] When manufacturing semiconductor integrated circuit (IC) chips, pattern defects or uninvited particles (residuals) inevitably appear on a wafer or a mask during fabrication processes, thereby reducing the yield. For example, uninvited particles may be troublesome for patterns with smaller critical feature dimensions, which have been adopted to meet the increasingly more advanced performance requirements of IC chips.

[0004] Pattern inspection tools with a charged particle beam have been used to detect the defects or uninvited particles. These tools typically employ a scanning electron microscope (SEM). In a SEM, a beam of primary electrons having a relatively high energy is decelerated to land on a sample at a relatively low landing energy and is focused to form a probe spot thereon. Due to this focused probe spot of primary electrons, secondary electrons will be generated from the surface. The secondary electrons may comprise backscattered electrons, secondary electrons, or Auger electrons, resulting from the interactions of the primary electrons with the sample. By scanning the probe spot over the sample surface and collecting the secondary electrons, pattern inspection tools may obtain an image of the sample surface.

[0005] During operation of an inspection tool, the wafer is typically held by a wafer stage. The inspection tool may comprise a wafer positioning device for positioning the wafer stage and wafer relative to the e-beam. This may be used to position a target area on the wafer, e.g., an area to be inspected, in an operating range of the e-beam.SUMMARY

[0006] The embodiments provided herein disclose a system for controlling a temperature of a stage and reducing heat transfer from the stage to a sample.

[0007] Some embodiments of the present disclosure provide a system for reducing heat transfer to a sample. The system comprises a vacuum chamber configured to provide a vacuum environment, a sample holder located in the vacuum chamber and configured to hold a sample, and a stage located in the vacuum chamber and configured to hold the sample holder, wherein the stage comprises a firststage component moveable in a first direction, a second stage component moveable in a second direction, and a heat insulating component configured to reduce heat transfer from the stage to the sample holder.

[0008] In some embodiments, a system for controlling temperature and reducing heat transfer to a sample is provided. The system comprises a vacuum chamber configured to provide a vacuum environment, a sample holder located in the vacuum chamber and configured to hold a sample, and a stage located in the vacuum chamber and configured to hold the sample holder, wherein the stage comprises a first stage component moveable in a first direction, a second stage component moveable in a second direction, and a temperature adjusting element configured to control a temperature of the stage and to reduce heat transfer from the stage to the sample holder.

[0009] Other advantages of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.BRIEF DESCRIPTION OF FIGURES

[0010] The above and other aspects of the present disclosure will become more apparent from the description of exemplary embodiments, taken in conjunction with the accompanying drawings.

[0011] FIG. 1A is a schematic diagram illustrating an exemplary wafer deformation effect in a charged particle beam inspection system.

[0012] FIG. IB a schematic diagram illustrating an exemplary charged particle beam inspection system, consistent with embodiments of the present disclosure.

[0013] FIG. 1C is a schematic diagram illustrating an exemplary wafer loading sequence in the charged particle beam inspection system of FIG. IB, consistent with embodiments of the present disclosure.

[0014] FIG. 2 is a schematic diagram illustrating an example lithographic projection assembly to fabricate an IC, consistent with embodiments of the present disclosure.

[0015] FIG. 3 is a schematic diagram illustrating an exemplary electron beam tool, consistent with embodiments of the present disclosure.

[0016] FIG. 4 is an exemplary graph showing a wafer temperature change over time in a charged particle beam inspection system.

[0017] FIG. 5 is a schematic diagram illustrating a sample stage configuration employed in conventional systems and apparatuses.

[0018] FIG. 6A is a schematic diagram illustrating a system for reducing heat transfer to a sample, consistent with embodiments of the present disclosure.

[0019] FIGS. 6B and 6C are schematic diagrams illustrating enlarged views of a heat insulating component positioned between a first stage component and a second stage component, consistent with embodiments of the present disclosure.

[0020] FIG. 6D is a schematic diagram of a top view of a component of a stage with an integrated heat insulating component, consistent with embodiments of the present disclosure.

[0021] FIG. 6E is a schematic diagram illustrating a system for controlling stage temperature and reducing heat transfer to a sample, consistent with embodiments of the present disclosure.DETAILED DESCRIPTION

[0022] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the invention. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the invention as recited in the appended claims.

[0023] The enhanced computing power of electronic devices, while reducing the physical size of the devices, can be accomplished by significantly increasing the packing density of circuit components such as transistors, capacitors, diodes, etc. on an IC chip. For example, an IC chip of a smart phone, which is the size of a thumbnail, may include over 2 billion transistors, the size of each transistor being less than l / 1000th of a human hair. Thus, it is not surprising that semiconductor IC manufacturing is a complex and time-consuming process, with hundreds of individual steps. Errors in even one step have the potential to dramatically affect the functioning of the final product. Even one “killer defect” can cause device failure. The goal of the manufacturing process is to improve the overall yield of the process. For example, for a 50-step process to get to a 75% yield, each individual step must have a yield greater than 99.4%, and if the individual step yield is 95%, the overall process yield drops to 7%.

[0024] ICs may be manufactured using lithography, which is a fabrication process involving creating complex circuit patterns drawn on a mask deposited onto a substrate. Lithography may be performed by a lithographic apparatus, which is a machine that applies a source of radiation (e.g., light or X-ray) or a source of charged particles (e.g., electron beam) onto a target portion of the substrate to form a desired pattern. The target portion of the substrate may be covered with a pattern device (e.g., mask) that may be either eliminated or developed after exposure to the radiation source or charged particle source. This process of transferring the desired pattern to the substrate is called a patterning process. The patterning process may include a patterning step to transfer a pattern from a pattern device (e.g., a mask) to the substrate. There can also be one or more related pattern processing steps, such as mask development by a development apparatus, baking of the substrate using a bake tool, etching the pattern onto the substrate using an etch apparatus, or other chemical and physical processing steps involved in fabricating a pattern onto the substrate. Variations in experimental parameters (e.g., stochastic variations, errors, or noise due to an inspection tool or pattern processingtool) can potentially limit lithography implementation for high volume manufacturing (HVM), or process yield, of ICs and introduce defects into IC structures.

[0025] In the manufacture of ICs using a lithographic apparatus, typically many lithographic patterning steps are performed, thereby forming functional features in successive layers on the substrate. A critical aspect of performance of the lithographic apparatus is therefore the ability to place the applied pattern correctly and accurately in relation to features laid down in previous layers. For this purpose, the substrate is provided with one or more sets of alignment marks. Each mark is a structure whose position can be measured later using, for example, a charged particle beam inspection tool. Defects may occur in which an applied pattern structure or pattern layer is incorrectly placed in relation to a reference mark, or when the fabrication conditions are suboptimal. A reference mark or layout define the desired structure, structure dimensions, and the distance between IC structures (such as gates, capacitors, etc.) or interconnect lines. This may ensure that the IC devices or lines do not interact with one another in an undesirable way. The structure limitations provided by the reference layouts are typically referred to as critical dimensions. A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the critical dimension determines the overall size and packing density of the designed IC. A goal in IC fabrication is to faithfully reproduce the original IC design on the substrate. If an error occurs during fabrication where the created IC design pattern does not match the reference design, this may result in a defect in the IC structure and render the IC inoperable.

[0026] While high process yield is desirable in an IC chip manufacturing facility, maintaining a high wafer throughput, defined as the number of wafers processed per hour, is also essential. High process yield and high wafer throughput can be impacted by the presence of defects, especially if operator intervention is required for reviewing the defects. Thus, high throughput detection and identification of micro and nano-sized defects by inspection tools (such as a SEM) is essential for maintaining high yield and low cost.

[0027] A SEM scans the surface of a wafer with a focused beam of electrons. The electrons interact with the wafer and generate secondary electrons. By scanning the wafer with an electron beam and capturing the secondary electrons with a detector, a SEM creates an image of the wafer that shows the internal device structure in the area of the wafer being inspected.

[0028] A problem with a conventional lithography and inspection systems is uncontrolled change in sample temperature. A sample being scanned for IC fabrication via lithography, or a sample being scanned for inspection may change its shape or size while the scanning is in progress. For example, when the sample is placed on a stage, the temperature of sample can be different from the temperature of the stage. This temperature difference may cause a sample temperature drift (e.g., the temperature of the sample gradually and continuously changes towards a stable point, which is usually close to the temperature of the lithography or inspection system), thereby resulting in the change in the shape or size of the sample. If the sample temperature increases, the sample would expand; if the sampletemperature decreases, the sample would shrink. This change in the shape or size of the sample can cause uncontrollable linewidth variations in during lithography and can further cause inaccurate inspection results of a fabricated IC.

[0029] Therefore, an operator, who is inspecting a wafer using a conventional particle beam inspection system, needs to wait for the wafer to become temperature- stabilized before starting the inspection. This temperature stabilization is required because the wafer changes size as the temperature changes, which causes elements on the wafer to move as the wafer expands or contracts. For example, FIG. 1A shows that elements 180, 182, 184, and 186 can move to new locations 170, 172, 174, and 178 as a wafer 160 expands due to the temperature change. And when the precision for inspecting a wafer is in nanometers, this change in location is material. Accordingly, for the operator to precisely locate and inspect the elements on the wafer, the operator must wait until the wafer temperature stabilizes. Therefore, for high throughput inspection, some of the newer inspection systems perform a thermal conditioning of a wafer before placing the wafer on the inspection platform. By making the wafer temperature close to the temperature of the wafer stage before placing the wafer onto the wafer stage, the inspection can begin with much less delay. Therefore, the operator can inspect more wafers within a given period of time, thereby achieving an increased throughput.

[0030] If temperature of the sample can be controlled during lithography or inspection, then throughput and defect inspection can be improved. However, controlling the sample temperature during lithography or inspection is difficult. The sample is held by a stage, in which the stage may be comprised of a first stage component, a second stage component, and third stage component. The first stage component (e.g., a Z-stage) is often coupled to a sample holder and therefore may have the most critical influence on any changes to sample temperature. Movement of the second stage component (e.g., an X-stage) and the third stage component (e.g., a Y-stage) may generate a significant amount of heat when moving a sample during lithography or inspection, and this generated heat may propagate upward and heat up the first stage component. As the Z-stage is coupled to the sample holder, the sample may undesirably increase in temperature. This may result in detrimental consequences such as a loss of focus, uncontrolled variations in linewidth for fabricated IC structures, drift or shifting in a field of view during inspection, difficulty in image aligning, and backside particle contamination on the wafer due to thermal-induced friction. Some conventional inspection systems run a cooling line containing water through the second stage component (e.g., an X-stage) and the third stage component (e.g., a Y-stage), but since this cooling line is exposed to a high vacuum environment there may be a significant risk in water leaking from the cooling line and compromising the system or apparatus used for inspection. This may require venting the vacuum chamber to atmospheric conditions for repair, and thus significantly reduce throughput.

[0031] Embodiments of the present disclosure may provide systems and apparatuses that may provide improved temperature control and reduced heat transfer to a sample during inspection. In some embodiments, a delicate and accurate temperature adjustment of a first stage component (e.g., aZ-stage) may be achieved by a temperature adjusting element. In some embodiments, a sample may not be exposed to significant changes in temperature during lithography or inspection and therefore may not become contaminated via thermal-induced particle contamination or sample expansion. In some embodiments, a shift in inspection field of view of a sample may be minimized. In some embodiments, a heat insulating component, a temperature adjusting element, or a combination thereof may facilitate a temperature difference between a first stage component and a second stage component of about 0.5 °C. Moreover, some embodiments of the present disclosure may increase throughput of IC manufacturing. Some embodiments of the present disclosure may provide a system or apparatus to maintain defect inspection accuracy and yield of defect-free devices throughout high- volume manufacturing (HVM).

[0032] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described. As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a database can include A or B, then, unless specifically stated otherwise or infeasible, the database can include A, or B, or A and B. As a second example, if it is stated that a database can include A, B, or C, then, unless specifically stated otherwise or infeasible, the database can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C. It is appreciated that the terms “wafer” and “sample” may be used interchangeably throughout this disclosure.

[0033] Reference is now made to FIG. IB, which is a schematic diagram illustrating an exemplary charged particle beam inspection system 100, consistent with embodiments of the present disclosure. As shown in FIG. IB, charged particle beam inspection system 100 may include a main chamber 10, a load lock chamber 20, an electron beam tool 40, and an equipment front end module (EFEM) 30. Electron beam tool 40 may be located within main chamber 10. While the description and drawings are directed to an electron beam, it is appreciated that the embodiments are not used to limit the present invention to specific charged particles. It is further appreciated that electron beam tool 40 can be a single-beam tool utilizing a single electron beam or a multi-beam tool utilizing multiple electron beams.

[0034] EFEM 30 may include a first loading port 30a and a second loading port 30b. EFEM 30 may include additional loading port(s). First loading port 30a and second loading port 30b may, for example, receive wafer front opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (wafers and samples are collectively referred to as “wafers”). One or more robot arms (e.g., robot arm 11 shown in FIG. IC) in EFEM 30 transport the wafers to load lock chamber 20.

[0035] Load lock chamber 20 may be connected to a load lock vacuum pump system (not shown), which removes gas molecules in load lock chamber 20 to reach a first pressure below the atmosphericpressure. After reaching the first pressure, one or more robot arms (e.g., robot arm 12 shown in FIG. 1C) transport the wafer from load lock chamber 20 to main chamber 10. Main chamber 10 is connected to a main chamber vacuum pump system (not shown), which removes gas molecules in main chamber 10 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is subject to inspection by electron beam tool 40.

[0036] A controller 50 may be electronically connected to electron beam tool 40 or any other parts of charged particle beam inspection system 100. Controller 50 may be a computer configured to execute various controls of charged particle beam inspection system 100. Controller 50 may also include a processing circuitry configured to execute various signal and image processing functions. While controller 50 is shown in FIG. IB as being outside of the structure that includes main chamber 10, load lock chamber 20, and EFEM 30, it is appreciated that controller 50 may be part of the structure. While the present disclosure provides examples of main chamber 10 housing an electron beam inspection tool, it should be noted that aspects of the disclosure in their broadest sense are not limited to a chamber housing an electron beam inspection tool. Rather, it is appreciated that the foregoing principles may also be applied to other tools that operate under the second pressure.

[0037] Reference is now made to FIG. 1C, which is a schematic diagram illustrating an exemplary wafer loading sequence in charged particle beam inspection system 100 of FIG. IB, consistent with embodiments of the present disclosure. In some embodiments, charged particle beam inspection system 100 may include a robot arm 11 located in EFEM 30 and a robot arm 12 located in main chamber 10. In some embodiments, EFEM 30 may also include a pre-aligner 60 configured to position a wafer accurately before transporting the wafer to load lock chamber 20.

[0038] In some embodiments, first loading port 30a and second loading port 30b, for example, may receive wafer front opening unified pods (FOUPs) that contain wafers. Robot arm 11 in EFEM 30 may transport the wafers from any of the loading ports to pre-aligner 60 for assisting with the positioning. Pre-aligner 60 may use mechanical or optical aligning methods to position the wafers. After pre-alignment, robot arm 11 may transport the wafers to load lock chamber 20.

[0039] After the wafers are transported to load lock chamber 20, a load lock vacuum pump (not shown) may remove gas molecules in load lock chamber 20 to reach a first pressure below the atmospheric pressure. After reaching the first pressure, a robot arm 12 may transport the wafer from load lock chamber 20 to a wafer stage 80 of electron beam tool 40 in main chamber 10. Main chamber 10 is connected to a main chamber vacuum pump system (not shown), which removes gas molecules in main chamber 10 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer may be subject to inspection by electron beam tool.

[0040] In some embodiments, main chamber 10 may include a parking station 70 configured to temporarily store a wafer before inspection. For example, when the inspection of a first wafer is completed, the first wafer may be unloaded from wafer stage 80, and then robot arm 12 may transport a second wafer from parking station 70 to wafer stage 80. Afterwards, robot arm 12 may transport athird wafer from load lock chamber 20 to parking station 70 to temporarily store the third wafer until the inspection for the second wafer is finished.

[0041] In some embodiments, to improve the overall throughput of inspection system, charged particle beam inspection system 100 may perform a thermal conditioning of a wafer before loading the wafer onto wafer stage 80. This pre-inspection thermal conditioning may occur in pre-aligner 60, load lock chamber 20, parking station 70, or any other place suitable for thermally conditioning the wafer before moving it to wafer stage 80.

[0042] Reference is now made to FIG. 2, which is a schematic diagram illustrating an exemplary lithographic projection apparatus 200. Lithographic projection apparatus 200 may include an emission source 201, which may be a charged-particle emission source, deep-ultraviolet excimer laser source, or other type of source including an extreme ultraviolet (EUV) source and emits a beam 208. Illumination optics which may include illumination optics components 202 and 203 that shape emitted species from the emission source 201; a patterning device 204; and transmission optics 205 that project an image of the patterning device pattern onto a substrate 206. An adjustable filter or aperture 207 at the pupil plane of the projection optics may restrict the range of beam angles that impinge on substrate 206, where the largest possible angle defines the numerical aperture of the projection optics NA=sin(0maxThe area or region on substrate 206 where beam 208 impacts is called a target portion 209, in which the radiation beam impacts the top layer or mask (not shown).

[0043] Illumination optics components 202 and 203 may direct and shape beam 208 via patterning device 204 onto substrate 206 and may include any optical component that may alter the wavefront of beam 208. A resist layer on substrate 206 may be exposed and an intensity distribution at substrate 206 (i.e., an aerial image) may be transferred to the resist layer. Optical properties of the lithographic projection apparatus (e.g., properties of the source, the patterning device, and the projection optics) dictate this process. The resist layer may be removed and the applied pattern from beam 208 may then be applied to the substrate as discussed above. Substrate 206 is coupled to a stage 210, which may move substrate 206 during scanning.

[0044] Although reference may be made in the present disclosure to ICs, it is appreciated that the present disclosure may be applicable to other possible applications or designs. For example, the present disclosure may be applied to integrated optical systems, magnetic domain memories, liquidcrystal display panels, thin-film magnetic heads, and other nanoscale structures. It is further appreciated that the terms “reticle”, “wafer”, or “die” may be used interchangeably with the terms “mask”, “substrate” or “sample”, and “target portion”, respectively.

[0045] Reference is now made to FIG. 3, which is a schematic diagram illustrating an exemplary inspection system 300 that may be part of the charged particle beam inspection system of FIGS. IB and 1C, consistent with embodiments of the present disclosure. Inspection system 300 may include an electron beam tool 40 and a controller 50.

[0046] Electron beam tool 40 may include a motorized wafer stage 301 (similar to wafer stage 80 of FIG. 1C). Electron beam tool 40 may also include a wafer holder 302 supported by motorized wafer stage 301 to hold a wafer 303 to be inspected. Electron beam tool 40 may further include a compound objective lens 304, electron detector 306 (which includes electron sensor surfaces), an objective aperture 308, a condenser lens 310, a beam limit aperture 312, a gun aperture 314, an anode 316, and a cathode 318, one or more of which may be aligned with an optical axis 317 of electron beam tool 40. In some embodiments, detector 306 may be arranged off axis 217.

[0047] Compound objective lens 304, in some embodiments, may include a modified swing objective retarding immersion lens (SORIL), which may include a pole piece 304a, a control electrode 304b, a deflector or a set of deflectors 304c, and an exciting coil 304d. In some embodiments, electron beam tool 40 may additionally include an energy dispersive X-ray spectrometer (EDS) detector (not shown) to characterize the materials on the wafer.

[0048] A primary electron beam 320 may be emitted from cathode 318 by applying a voltage between anode 316 and cathode 318. Primary electron beam 320 may pass through gun aperture 314 and beam limit aperture 312, both of which may determine the current of electron beam entering condenser lens 310, which resides below beam limit aperture 312. Condenser lens 310 may focus primary electron beam 320 before the beam enters objective aperture 308 to set the current of the electron beam before entering compound objective lens 304.

[0049] Compound objective lens 304 may focus primary electron beam 320 onto wafer 303 for inspection and can form a probe spot 322 on surface of wafer 303. Deflector(s) 304c may deflect primary electron beam 320 to scan probe spot 322 over wafer 303. For example, in a scanning process, deflector(s) 304c may be controlled to deflect primary electron beam 320 sequentially onto different locations of top surface of wafer 303 at different time points, to provide data for image reconstruction for different parts of wafer 303. Moreover, in some embodiments, deflector 304c may also be controlled to deflect primary electron beam 320 onto different sides of wafer 303 at a particular location, at different time points, to provide data for stereo image reconstruction of the wafer structure at that location. Further, in some embodiments, anode 316 and cathode 318 may be configured to generate multiple primary electron beams 320, and electron beam tool 40 may include a plurality of deflectors 304c to project the multiple primary electron beams 320 to different parts / sides of wafer 303 at the same time.

[0050] When a current is applied onto exciting coil 304d, an axially-symmetric (i.e., symmetric around optical axis 317) magnetic field may be generated in the wafer surface area. A part of wafer 303 being scanned by primary electron beam 320 may be immersed in the magnetic field. In some embodiments, different voltages may be applied onto wafer 303, pole piece 304a, and control electrode 304b, to generate an axial symmetric retarding electric field near the wafer surface. The electric field may reduce the energy of impinging primary electron beam 320 near the surface of the wafer before electrons of the beam collide with wafer 303. Control electrode 304b, being electricallyisolated from pole piece 304a, may control an axially-symmetric electric field on the wafer to prevent micro-arcing of the wafer and to ensure proper beam focus at the wafer surface with the axially- symmetric magnetic field together.

[0051] A secondary electron beam 330 may be emitted from the part of wafer 303 upon receiving primary electron beam 320. Secondary electron beam 330 may comprise backscattered electrons, secondary electrons, or Auger electrons, resulting from the interactions of the primary electrons with wafer 303. Secondary electron beam 330 may be received by sensor surfaces of electron detector 306. In some embodiments, electron detector 306 may generate a signal (e.g., a voltage, a current, etc.) that represents an intensity of secondary electron beam 330 and may provide the signal to controller 50 in communication with electron detector 306. The intensity of secondary electron beam 330 may vary according to the external or internal structure of wafer 303, and thus may indicate whether wafer 303 includes defects. Moreover, as discussed above, primary electron beam 320 may be projected onto different locations of the top surface of wafer 303, or different sides of wafer 303 at a particular location, to generate secondary electron beams 330 of different intensities. Therefore, by mapping the intensity of secondary electron beam 330 with the areas of wafer 303, image processing circuitry in controller 50 may reconstruct an image that reflects the characteristics of internal or external structures of wafer 303.

[0052] In some embodiments, controller 50 may comprise image processing system that includes an image acquirer (not shown) and a storage (not shown). The image acquirer may comprise one or more processors. For example, the image acquirer may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, and the like, or a combination thereof. The image acquirer may be communicatively coupled to electron detector 306 of electron beam tool 40 through a medium such as an electrical conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, among others, or a combination thereof. In some embodiments, the image acquirer may receive a signal from electron detector 306 and may construct an image. The image acquirer may thus acquire images of wafer 303. The image acquirer may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, and the like. The image acquirer may be configured to perform adjustments of brightness and contrast, etc. of acquired images. In some embodiments, the storage may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer readable memory, and the like. The storage may be coupled with the image acquirer and may be used for saving scanned raw image data as original images, and post-processed images.

[0053] In some embodiments, the image acquirer may acquire one or more images of wafer 303 based on an imaging signal received from detector 306. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image comprising a plurality of imaging areas. The single image may be stored in the storage. Thesingle image may be an original image that may be divided into a plurality of regions. Each of the regions may comprise one imaging area containing a feature of wafer 303. The acquired images may comprise multiple images of a single imaging area of wafer 303 sampled multiple times over a time sequence. The multiple images may be stored in storage. In some embodiments, controller 50 may be configured to perform image processing steps with the multiple images of the same location of wafer 303.

[0054] In some embodiments, controller 50 may include measurement circuitries (e.g., analog-to- digital converters) to obtain a distribution of the detected secondary electrons. The electron distribution data collected during a detection time window, in combination with corresponding scan path data of primary electron beam 320 incident on the wafer surface, can be used to reconstruct images of the wafer structures under inspection. The reconstructed images can be used to reveal various features of the internal or external structures of wafer 303, and thereby can be used to reveal any defects that may exist in the wafer.

[0055] Moreover, although FIG. 3 shows that electron beam tool 40 uses a single primary electron beam, it is appreciated that electron beam tool 40 may also be a multi-beam inspection tool that uses multiple primary electron beams. The present disclosure does not limit the number of primary electron beams used in electron beam tool 40.

[0056] Reference is now made to FIG. 4, which is an exemplary graph showing a wafer temperature change over time for a charged particle beam inspection system. The vertical axis represents temperature change, and the horizontal axis represents passage of time. The graph shows that the wafer temperature changes over time while the wafer is processed through multiple stages of wafer load sequence. At time 430, the wafer is loaded to a load lock chamber. At time 440, the wafer is transported and loaded to wafer stage. At time 445, a wafer inspection begins. At time 450, the wafer inspection ends, and the wafer is unloaded from the wafer stage. During period 420, the wafer stays on the wafer stage.

[0057] According to the exemplary data shown in FIG. 4, when a wafer is loaded to the load lock chamber at time 430, the temperature of the wafer is approximately 22 degrees Celsius (annotated as 412). After the wafer is transported to a load lock chamber, the wafer temperature sharply drops from temperature 412 to temperature 414. Exemplary data show that this temperature drop, which occurs when the load lock chamber is pumped down to a vacuum, may be approximately one to two degrees. This sudden temperature drop is referred to as a pump-down effect.

[0058] Subsequently, when the wafer is transported and loaded onto the wafer stage (e.g., wafer stage 80 of FIG. 1C) at time 440, the wafer temperature (annotated 414) and the wafer stage temperature (not shown, but close to an equilibrium temperature 410) may be at different temperatures. Exemplary data show that this difference may be approximately up to three degrees.

[0059] This temperature difference between the wafer and the wafer stage causes wafer temperature drift towards the wafer stage temperature. For example, the graph in FIG. 4 shows that the wafertemperature changes during period 420. Under such circumstances, heat transfer occurs between the wafer and the wafer stage, thereby resulting in a deformation (e.g., a thermal expansion shown in FIG. 1A) of the wafer (or the wafer stage). While the wafer stage or wafer is undergoing a thermal deformation, the inspection of the target area may not be possible or may have a reduced accuracy. Thus, to perform a more accurate inspection, the system waits for a significant period of time (waiting period 425) until the wafer temperature stabilizes at an equilibrium temperature 410 before an inspection can commence at time 445. Therefore, reducing waiting period 425 may improve the throughput of the inspection system. In some embodiments, the wafer may be thermally preconditioned to reduce temperature difference 460, thereby resulting in shorter waiting period 425.

[0060] An example of wafer stage for quicker temperature stabilization may be found in European Patent Application No. EP18174642.1, titled PARTICLE BEAM APPARATUS and filed on May 28, 2018, which is incorporated by reference in its entirety. Another way to cope with this long stabilization time is conditioning the wafer temperature by pre-heating or pre-cooling the wafer to match the temperature of the wafer stage before the wafer is loaded onto the wafer stage. Examples of such embodiments may be found in U.S. Patent Application No. 62699643, titled PARTICLE BEAM INSPECTION APPARATUS and filed on July 17, 2018, which is incorporated by reference in its entirety.

[0061] Reference is now made to FIG. 5, which is a schematic diagram illustrating a sample stage configuration employed in conventional systems and apparatuses. FIG. 5 illustrates a vacuum chamber 501 containing a sample stage configured to hold a sample holder 502. Sample holder 502 is configured to hold a sample 503. The sample stage may include a Y-stage 504, an X-stage 505, and a Z-stage 506. Generally, Z-stage 506 is a topmost component of the sample stage and is coupled to sample holder 502. The conventional sample stage illustrated in FIG. 5 is used to carry and move a sample in vacuum chamber 501 for various processes (e.g., lithography, inspection, or metrology). As stages 504-506 move sample 503, heat is generated in each stage respectively. Y-stage 504 and X- stage 505 may generate a greater amount of heat compared to Z-stage 506 during operation. Therefore, in some conventional systems, an optional cooling line 507 is passed through Y-stage 504 and X-stage 505 to cool these stages and mitigate heat transfer toward sample 503. Optional cooling line 507 carries water through Y-stage 504 and X-stage 505. This configuration may be detrimental to vacuum operation, as water may leak through optional cooling line 507 and compromise the vacuum of vacuum chamber 501. If cooling line 507 is not present, heat may be dissipated, to an extent, from Y-stage 504 and X-stage 505 to vacuum chamber 501 and outside to the surrounding environment. However, heat generated in any one of Y-stage 504, X-stage 505, or Z-stage 506 will transfer to sample 503 and may detrimentally impact inspection via field of view drift or thermal-induced contamination as described above. Therefore, it may be difficult to mitigate heat transfer to a sample and control temperature of a sample during inspection using conventional systems or apparatuses.

[0062] Reference is now made to FIG. 6A, which is a schematic diagram illustrating a system for reducing heat transfer to a sample, consistent with embodiments of the present disclosure. A sample stage in a vacuum chamber 601 may include a first stage component 604 moveable in a first direction, a second stage component 605 moveable in a second direction, and a third stage component 606 moveable in a third direction. First stage component 604 may be coupled to a sample holder 602, where sample holder 602 is configured to hold a sample 603. While FIG. 6A illustrates three separate stage components (e.g., first stage component 604, second stage component 605, and third stage component 606), embodiments of the present disclosure are not so limited. For example, a sample stage may include first stage component 604 moveable in a first direction and second stage component 605 moveable in a second direction. In some embodiments, second stage component 605 is coupled to a lower surface of first component 604. In some embodiments, first stage component 604 is coupled to a lower surface of sample holder 602. In some embodiments, a sample stage may further include third stage component 606 moveable in a third direction where third stage component 606 is coupled to a lower surface of second stage component 605. Any one of first stage component 604, second stage component 605, or third stage component 606 may be moveable in a rotational direction or a translational direction. For example, in some embodiments first stage component 604 may be moveable in a rotational direction and second stage component 605 may be movable in a translational direction. In some embodiments, first stage component 604 may be moveable in a Z- direction. In some embodiments, second stage component 605 may be moveable in an X-direction. In some embodiments, third stage component 606 may be moveable in a Y-direction. In some embodiments, first stage component 604 may be a Z-stage, second stage component 605 may be an X-stage, and third stage component 606 may be a Y-stage.

[0063] One or more heat insulating components 607 may be positioned between first stage component 604 and second stage component 605. In some embodiments, one or more heat insulating components 607 may provide a separation 608 between first stage component 604 and second stage component 605. Separation 608 may be a space that is exposed to a vacuum and may hinder heat transfer from second stage component 605 to first stage component 604 at points of contact between second stage component 605 and first stage component 604. Because vacuum chamber 601 provides a vacuum environment, heat transfer may only occur via conduction. Therefore, one or more heat insulating components 607 may effectively reduce heat transfer from second stage component 605 or third stage component 606 and second stage component 605 to first stage component 604 and therefore sample 603. In some embodiments, one or more heat insulating components 607 may be one or more spacers or shims that separate second stage component 605 from first stage component 604. In some embodiments, the spacer may be a heat-insulating material with satisfactory heat insulation. In some embodiments, the spacer may be a ceramic material, a polymer material, a porcelain material, or any other material that has a desirably low heat conductivity. It is appreciated that FIG. 6A is illustrative in nature and should not be construed as limiting. In some embodiments, any number ofheat insulating components 607 may be positioned between first stage component 604 and second stage component 605. In some embodiments, one or more heat insulating component 607 may be positioned between second stage component 605 and third stage component 606. In some embodiments, one or more heat insulating components 607 may be positioned between first stage component 604 and sample holder 602.

[0064] Reference is now made to FIG. 6B and 6C, which are schematic diagrams illustrating enlarged views of a heat insulating component positioned between first stage component 604 and second stage component 605, consistent with embodiments of the present disclosure. FIG. 6B illustrates that one or more heat insulating components 607 may be an integrated part of first stage component 604 and may be a same material as first stage component 604. In some embodiments, one or more heat-insulating components 607 may be a feature of first stage component 604. FIG. 6B illustrates one or more heat insulating components 607 may be a feature protruding from a lower surface of first stage component 604 and contacting an upper surface of second stage component 605. It is appreciated that FIG. 6B is illustrative in nature and should not be construed as limiting in terms of shape, size, number, and position of the one or more heat insulating components when integrated as a feature of first stage component 604. Indeed, any shape, size, number, curvature, or position of the one or more heat insulating feature may be contemplated such that separation 608 is created between first stage component 604 and second stage component 605.

[0065] FIG. 6C illustrates the one or more heat insulating components 607 may be an integrated part of second stage component 605. In some embodiments, one or more heat- insulating components 607 may be a feature of second stage component 605. FIG. 6C illustrates one or more heat insulating components 607 may be a feature protruding from an upper surface of second stage component 605 and contacting a lower surface of second stage component 604 to create separation 608. The above description regarding the shape, size, number, curvature, or position of one or more heat insulating features may apply to FIG. 6C as well.

[0066] Reference is now made to FIG. 6D, which is a schematic diagram of a top view of second stage component 605 with an integrated heat insulating component (e.g., as in FIG. 6C), consistent with embodiments of the present disclosure. FIG. 6D illustrates example features 609 that may be integrated heat insulating components as described above. In some embodiments, second stage component 605 may include a void 610 positioned on an upper surface of second stage component 605. FIG. 6D illustrates void 610 on feature 609. In some embodiments, void 610 may be a heat insulating component because void 610 may decrease surface contact between second stage component 605 and first stage component 604 and reduce heat transfer to first stage component 604. It is appreciated that void 610 may be any shape, depth, or size, and may be positioned at any location on an upper surface of second stage component 605. In some embodiments, second stage component 605 may not include features 609 as illustrated in FIG. 6D and may instead contain voids 610 on an upper surface of second stage component 605. The term “void” may be understood to include anydepression, hole, crater, hollow space, or absence on an upper surface of second stage component 605 (or lower surface of first stage component 604) such that a separation (e.g., separation 608) is created between second stage component 605 and first stage component 604. FIG. 6D may also illustrate a lower surface of first stage component 604. The above descriptions may apply to a lower surface of first stage component 604 as well.

[0067] Reference is now made to FIG. 6E, which is a schematic diagram illustrating a system for controlling stage temperature and reducing heat transfer to a sample, consistent with embodiments of the present disclosure. FIG. 6E illustrates a temperature adjusting element 611 that may be positioned between second stage component 605 and first stage component 604. In some embodiments, temperature adjusting element 611 may provide a separation (e.g., separation 608) between second stage component 605 and first stage component 604. In some embodiments, temperature adjusting element 611 may control a temperature of first stage component 604. In some embodiments, temperature adjusting element 611 may be a thermoelectric temperature adjusting element. Nonlimiting examples of a thermoelectric temperature adjusting element may include a Peltier effect material, a Seebeck effect material, a Thomson effect material, or any other material that may reversibly generate a thermal gradient via an electrical signal. The electrical signal applied to temperature adjusting element 611 may be a voltage or a current. In some embodiments, temperature adjusting element 611 can be turned on by supplying an electrical signal to alter a direction of heat flow. In some embodiments, an electrical signal supplied to temperature adjusting element 611 may drive heat flow downward (e.g., negative Z-direction) and cool first stage component 604. In some embodiments, an electrical signal suppled to temperature adjusting element 611 may drive heat flow upward and heat first stage component 604. Temperature adjusting element 611 may be connected to a heat sink (not shown) of a larger thermal mass which may enable rapid transfer of heat from second stage component 605. Thus, temperature adjusting element 611 may provide an improved heat shielding effect to first stage component 604, especially if second stage component 605 and third stage component 606 are not cooled (e.g., by a cooling line such as cooling line 507 in FIG. 5). It is appreciated that the system illustrated in FIG. 6E may include one or more heat insulating components (e.g., one or more heat insulating components 607 as described in FIG. 6A-6D).

[0068] A benefit provided by embodiments of the present disclosure may be improved temperature control and reduced heat transfer to a sample during inspection. In some embodiments, a delicate and accurate temperature adjustment of a first stage component (e.g., a Z-stage) may be achieved by a temperature adjusting element (e.g., temperature adjusting element 611 in FIG. 6E). In some embodiments, a sample may not be exposed to significant changes in temperature during inspection and therefore may not become contaminated via thermal-induced particle contamination. In some embodiments, a shift in inspection field of view of a sample may be minimized. In some embodiments, a heat insulating component (e.g., one or more heat insulating components 607 as described in FIG. 6A-6D), a temperature adjusting element (e.g., temperature adjusting element 611in FIG. 6E), or a combination thereof may reduce a temperature difference between a first stage component and a second stage component from 3-5 °C to about 0.5 °C. Moreover, some embodiments of the present disclosure may increase throughput of IC manufacturing Some embodiments of the present disclosure may provide a method to maintain defect inspection accuracy and yield of defect- free devices throughout high-volume manufacturing (HVM).

[0069] It is appreciated that a controller of the heat transfer control system could use software to control the functionality described above. For example, the controller may supply an electrical signal to a temperature adjusting element based on measured temperature characteristics of the wafer stage. The controller may send instructions to a heater / cooler to adjust the temperature of heat transfer elements. The software may be stored on a non-transitory computer readable medium. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, cloud storage, a FLASH-EPROM or any other flash memory, NVRAM, a cache, a register, any other memory chip or cartridge, and networked versions of the same.

[0070] The embodiments may further be described using the following clauses:1. A system for reducing heat transfer to a sample, the system comprising: a vacuum chamber configured to provide a vacuum environment; a sample holder located in the vacuum chamber and configured to hold a sample; and a stage located in the vacuum chamber and configured to hold the sample holder, wherein the stage comprises: a first stage component moveable in a first direction, a second stage component moveable in a second direction, and a heat insulating component configured to reduce heat transfer from the stage to the sample holder.2. The system of clause 1, wherein the first stage component is moveable in a rotational direction.3. The system of clause 1, wherein the first stage component is moveable in a translational direction.4. The system of clause 3, wherein the first stage component is moveable in a Z- direction.5. The system of clause 3, wherein the first stage component is moveable in an X- direction or a Y-direction.6. The system of any one of clauses 1 to 5, wherein the second stage component is moveable in a translational direction.7. The system of clause 6, wherein the second stage component is moveable in an X- direction or a Y-direction.8. The system of any one of clauses 1 to 7, wherein the second stage component is coupled to a lower surface of the first stage component.9. The system of any one of clauses 1 to 8, wherein the first stage component is coupled to a lower surface of the sample holder.10. The system of any one of clauses 1 to 9, wherein the heat insulating component is positioned between the first stage component and the second stage component11. The system of clause 10, wherein the heat insulating component provides a separation between the first stage component and the second stage component.12. The system of clause 10 or 11, wherein the heat insulating component is a spacer.13. The system of clause 12, wherein the spacer is a heat-insulating material.14. The system of clause 10 or 11, wherein the heat insulating component is a feature of the first stage component protruding from a lower surface of the first stage component.15. The system of clause 10 or 11, wherein the heat insulating component is a feature of the second stage component protruding from an upper surface of the second stage component.16. The system of any one of clauses 10, 11, 14, or 15, wherein the heat insulating component is a void on a lower surface of the first stage component.17. The system of any one of clauses 10, 11, 14, or 15, wherein the heat insulating component is a void on an upper surface of the second stage component.18. The system of clause 16 or 17, wherein the void decreases surface contact between the first stage component and the second stage component.19. The system of any one of clauses 1 to 18, further comprising a temperature adjusting element positioned between the first stage component and the second stage component.20. The system of clause 19, wherein the temperature adjusting element is configured to reduce heat transfer from the stage to the sample holder.21. The system of clause 19 or 20, wherein the temperature adjusting element provides a separation between the first stage component and the second stage component.22. The system of any one of clauses 19 to 21, wherein the temperature adjusting element is configured to control a temperature of the first stage component.23. The system of any one of clauses 19 to 22, wherein the temperature adjusting element is a thermoelectric temperature adjusting element.24. The system of any one of clauses 19 to 23, further comprising a third stage component moveable in a third direction.25. The system of clause 24, wherein the third component is moveable in a translational direction.26. The system of clause 24 or 25, wherein the first stage component is moveable in a Z- direction, the second stage component is moveable in an X-direction, and the third stage component is moveable in a Y-direction.27. The system of any one of clauses 1 to 26, wherein the system is a lithography system.28. The system of any one of clauses 1 to 26, wherein the system is an inspection system.29. The system of clause 28, wherein the inspection system comprises an optical microscope.30. The system of clause 28, wherein the inspection system comprises a charged particle beam microscope.31. The system of clause 30, wherein the charged particle beam microscope is a scanning electron microscope.32. A system for controlling temperature and reducing heat transfer to a sample, the system comprising: a vacuum chamber configured to provide a vacuum environment; a sample holder located in the vacuum chamber and configured to hold a sample; and a stage located in the vacuum chamber and configured to hold the sample holder, wherein the stage comprises: a first stage component moveable in a first direction, a second stage component moveable in a second direction, and a temperature adjusting element configured to control a temperature of the stage and to reduce heat transfer from the stage to the sample holder.33. The system of clause 32, wherein the first stage component is moveable in a rotational direction.34. The system of clause 32, wherein the first stage component is moveable in a translational direction.35. The system of clause 34, wherein the first stage component is moveable in a Z- direction.36. The system of clause 34, wherein the first stage component is moveable in an X- direction or a Y-direction.37. The system of any one of clauses 32 to 36, wherein the second stage component is moveable in a translational direction.38. The system of clause 37, wherein the second stage component is moveable in an X- direction or a Y-direction.39. The system of any one of clauses 32 to 38, wherein the second stage component is coupled to a lower surface of the first stage component.40. The system of any one of clauses 32 to 39, wherein the first stage component is coupled to a lower surface of the sample holder.41. The system of any one of clauses 32 to 40, wherein the temperature adjusting element is positioned between the first stage component and the second stage component.42. The system of any one of clauses 32 to 41, wherein the temperature adjusting element provides a separation between the first stage component and the second stage component.43. The system of any one of clauses 32 to 42, wherein the temperature adjusting element is configured to control a temperature of the first stage component.44. The system of any one of clauses 32 to 43, wherein the temperature adjusting element is a thermoelectric temperature adjusting element.45. The system of any one of clauses 32 to 44, further comprising one or more heat insulating components configured to reduce heat transfer from the stage to the sample holder.46. The system of clause 45, wherein the one or more heat insulating components are positioned between the first stage component and the second stage component.47. The system of clause 46, wherein the one or more heat insulating components provide a separation between the first stage component and the second stage component.48. The system of any one of clauses 45 to 47, wherein the one or more heat insulating component is a spacer.49. The system of clause 48, wherein the spacer is a heat-insulating material.50. The system of any one of clauses 45 to 47, wherein the one or more heat insulating component is a void on a lower surface of the first stage component.51. The system of any one of clauses 45 to 47, wherein the one or more heat insulating component is a void on an upper surface of the second stage component.52. The system of clause 50 or 51, wherein the void decreases surface contact between the first stage component and the second stage component.53. The system of any one of clauses 32 to 52, further comprising a third stage component moveable in a third direction.54. The system of clause 53, wherein the third stage component is moveable in a translational direction.55. The system of clause 53 or 54, wherein the first stage component is moveable in a Z- direction, the second stage component is moveable in an X-direction, and the third stage component is moveable in a Y-direction.56. The system of any one of clauses 32 to 55, wherein the system is a lithography system.57. The system of any one of clauses 32 to 55, wherein the system is an inspection system.58. The system of clause 57, wherein the inspection system comprises an optical microscope.59. The system of clause 57, wherein the inspection system comprises a charged particle beam microscope.60. The system of clause 59, wherein the charged particle beam microscope is a scanning electron microscope.

[0071] Although the disclosed embodiments have been explained in relation to its preferred embodiments, it is to be understood that other modifications and variation can be made without departing the spirit and scope of the subject matter as hereafter claimed.

Claims

CLAIMS1. A system for reducing heat transfer to a sample, the system comprising: a vacuum chamber configured to provide a vacuum environment; a sample holder located in the vacuum chamber and configured to hold a sample; and a stage located in the vacuum chamber and configured to hold the sample holder, wherein the stage comprises: a first stage component moveable in a first direction, a second stage component moveable in a second direction, and a heat insulating component configured to reduce heat transfer from the stage to the sample holder.

2. The system of claim 1, wherein the first stage component is moveable in a translational direction.

3. The system of claim 2, wherein the first stage component is moveable in a Z- direction.

4. The system of claim 1, wherein the second stage component is moveable in a translational direction.

5. The system of claim 4, wherein the second stage component is moveable in an X- direction or a Y-direction.

6. The system of claim 1, wherein the second stage component is coupled to a lower surface of the first stage component.

7. The system of claim 1, wherein the first stage component is coupled to a lower surface of the sample holder.

8. The system of claim 1, wherein the heat insulating component is positioned between the first stage component and the second stage component9. The system of claim 8, wherein the heat insulating component provides a separation between the first stage component and the second stage component.

10. The system of claim 8, wherein the heat insulating component is a feature of the first stage component protruding from a lower surface of the first stage component.

11. The system of claim 8, wherein the heat insulating component is a feature of the second stage component protruding from an upper surface of the second stage component.

12. The system of claim 1, further comprising a temperature adjusting element positioned between the first stage component and the second stage component.

13. The system of claim 12, wherein the temperature adjusting element is configured to reduce heat transfer from the stage to the sample holder.

14. The system of claim 12, wherein the temperature adjusting element is a thermoelectric temperature adjusting element.

15. A system for controlling temperature and reducing heat transfer to a sample, the system comprising: a vacuum chamber configured to provide a vacuum environment; a sample holder located in the vacuum chamber and configured to hold a sample; and a stage located in the vacuum chamber and configured to hold the sample holder, wherein the stage comprises: a first stage component moveable in a first direction, a second stage component moveable in a second direction, and a temperature adjusting element configured to control a temperature of the stage and to reduce heat transfer from the stage to the sample holder.

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