Apparatus, system, and method of amplifier voltage clipping

Abstract

For example, an apparatus may include a Low Noise Amplifier (LNA). For example, the LNA may include an LNA core, which may be configured to provide an amplified LNA-core output signal by amplifying an LNA-core input signal. For example, LNA may include a voltage clipper connected in parallel to the LNA core between a pair of differential terminals of the LNA core. For example, the voltage clipper may be configured to clip at least part of a voltage level, which is above a clipping voltage threshold, of a voltage between a first differential terminal and a second differential terminal of the pair of differential terminals.

Description

APPARATUS, SYSTEM, AND METHOD OF AMPLIFIER VOLTAGE CLIPPINGCROSS REFERENCE

[0001] This application claims the benefit of, and priority from, US Provisional Patent Application No. 63 / 592,388 entitled “APPARATUS, SYSTEM, AND METHOD OF AMPLIFIER VOLTAGE CLIPPING”, filed October 23, 2023, the entire disclosure of which is incorporated herein by reference.BACKGROUND

[0002] Various types of devices and systems, for example, autonomous and / or robotic devices, e.g., autonomous vehicles and robots, may be configured to perceive and navigate through their environment using sensor data of one or more sensor types.

[0003] Conventionally, autonomous perception relies heavily on light-based sensors, such as image sensors, e.g., cameras, and / or Light Detection and Ranging (LiDAR) sensors. Such light-based sensors may perform poorly under certain conditions, such as, conditions of poor visibility, or in certain inclement weather conditions, e.g., rain, snow, hail, or other forms of precipitation, thereby limiting their usefulness or reliability.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] For simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity of presentation. Furthermore, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. The figures are listed below.

[0005] Fig. 1 is a schematic block diagram illustration of a vehicle implementing a radar, in accordance with some demonstrative aspects.

[0006] Fig. 2 is a schematic block diagram illustration of a robot implementing a radar, in accordance with some demonstrative aspects.

[0007] Fig. 3 is a schematic block diagram illustration of a radar apparatus, in accordance with some demonstrative aspects.

[0008] Fig. 4 is a schematic block diagram illustration of a Frequency-Modulated Continuous Wave (FMCW) radar apparatus, in accordance with some demonstrative aspects.

[0009] Fig. 5 is a schematic illustration of an extraction scheme, which may be implemented to extract range and speed (Doppler) estimations from digital reception radar data values, in accordance with some demonstrative aspects.

[0010] Fig. 6 is a schematic illustration of an angle-determination scheme, which may be implemented to determine Angle of Arrival (Ao A) information based on an incoming radio signal received by a receive antenna array, in accordance with some demonstrative aspects.

[0011] Fig. 7 is a schematic illustration of a Multiple-Input-Multiple-Output (MIMO) radar antenna scheme, which may be implemented based on a combination of Transmit (Tx) and Receive (Rx) antennas, in accordance with some demonstrative aspects.

[0012] Fig. 8 is a schematic block diagram illustration of elements of a radar device including a radar frontend and a radar processor, in accordance with some demonstrative aspects.

[0013] Fig. 9 is a schematic illustration of a radar system including a plurality of radar devices implemented in a vehicle, in accordance with some demonstrative aspects.

[0014] Fig. 10 is a schematic illustration of a Low Noise Amplifier (LNA), in accordance with some demonstrative aspects.

[0015] Fig. 11 is a schematic illustration of an LNA, in accordance with some demonstrative aspects.

[0016] Fig. 12A is a schematic illustration of a conductive path, which may be implemented as part of a voltage clipper, in accordance with some demonstrative aspects.

[0017] Fig. 12B is a schematic illustration of a conductive path, which may be implemented as part of a voltage clipper, in accordance with some demonstrative aspects.

[0018] Fig. 13 is a schematic illustration of a graph depicting current- voltage (I / V) curves of first and second conductive paths, in accordance with some demonstrative aspects.

[0019] Fig. 14 is a schematic illustration of a graph depicting curves representing a plurality of LNA core voltage levels versus an input power level of an input signal of an LNA core, in accordance with some demonstrative aspects.

[0020] Fig. 15 is a schematic flow chart illustration of a method of an amplifier voltage, in accordance with some demonstrative aspects.

[0021] Fig. 16 is a schematic illustration of a product of manufacture, in accordance with some demonstrative aspects.DETAILED DESCRIPTION

[0022] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of some aspects. However, it will be understood by persons of ordinary skill in the art that some aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components, units and / or circuits have not been described in detail so as not to obscure the discussion.

[0023] Discussions herein utilizing terms such as, for example, “processing”, “computing”, “calculating”, “determining”, “establishing”, “analyzing”, “checking”, or the like, may refer to operation(s) and / or process(es) of a computer, a computing platform, a computing system, or other electronic computing device, that manipulate and / or transform data represented as physical (e.g., electronic) quantities within the computer’s registers and / or memories into other data similarly represented as physical quantities within the computer’s registers and / or memories or other information storage medium that may store instructions to perform operations and / or processes.

[0024] The terms “plurality” and “a plurality”, as used herein, include, for example, “multiple” or “two or more”. For example, “a plurality of items” includes two or more items.

[0025] The words "exemplary" and “demonstrative” are used herein to mean "serving as an example, instance, demonstration, or illustration". Any aspect, aspect, or design described herein as "exemplary" or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects, aspects, or designs.

[0026] References to “one aspect”, “an aspect”, “demonstrative aspect”, “various aspects” etc., indicate that the aspect(s) so described may include a particular feature, structure, or characteristic, but not every aspect necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in one aspect” does not necessarily refer to the same aspect, although it may.

[0027] As used herein, unless otherwise specified the use of the ordinal adjectives “first”, “second”, “third” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to implythat the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

[0028] The phrases “at least one” and “one or more” may be understood to include a numerical quantity greater than or equal to one, e.g., one, two, three, four, [...], etc. The phrase "at least one of" with regard to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the phrase "at least one of" with regard to a group of elements may be used herein to mean one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of a multiple of individual listed elements.

[0029] The term “data” as used herein may be understood to include information in any suitable analog or digital form, e.g., provided as a file, a portion of a file, a set of files, a signal or stream, a portion of a signal or stream, a set of signals or streams, and the like. Further, the term “data” may also be used to mean a reference to information, e.g., in form of a pointer. The term “data”, however, is not limited to the aforementioned examples and may take various forms and / or may represent any information as understood in the art.

[0030] The terms “processor” or “controller” may be understood to include any kind of technological entity that allows handling of any suitable type of data and / or information. The data and / or information may be handled according to one or more specific functions executed by the processor or controller. Further, a processor or a controller may be understood as any kind of circuit, e.g., any kind of analog or digital circuit. A processor or a controller may thus be or include an analog circuit, digital circuit, mixed-signal circuit, logic circuit, processor, microprocessor, Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), integrated circuit, Application Specific Integrated Circuit (ASIC), and the like, or any combination thereof. Any other kind of implementation of the respective functions, which will be described below in further detail, may also be understood as a processor, controller, or logic circuit. It is understood that any two (or more) processors, controllers, or logic circuits detailed herein may be realized as a single entity with equivalent functionality or the like, and conversely that any single processor, controller, or logic circuit detailed herein may be realized as two (or more) separate entities with equivalent functionality or the like.

[0031] The term “memory” is understood as a computer-readable medium (e.g., a non-transitory computer-readable medium) in which data or information can be stored for retrieval. References to “memory” may thus be understood as referring to volatile or non-volatile memory, including random access memory (RAM), read-only memory (ROM), flash memory, solid-state storage, magnetic tape, hard disk drive, optical drive, among others, or any combination thereof. Registers, shift registers, processor registers, data buffers, among others, are also embraced herein by the term memory. The term “software” may be used to refer to any type of executable instruction and / or logic, including firmware.

[0032] A “vehicle” may be understood to include any type of driven object. By way of example, a vehicle may be a driven object with a combustion engine, an electric engine, a reaction engine, an electrically driven object, a hybrid driven object, or a combination thereof. A vehicle may be, or may include, an automobile, a bus, a mini bus, a van, a truck, a mobile home, a vehicle trailer, a motorcycle, a bicycle, a tricycle, a train locomotive, a train wagon, a moving robot, a personal transporter, a boat, a ship, a submersible, a submarine, a drone, an aircraft, a rocket, among others.

[0033] A “ground vehicle” may be understood to include any type of vehicle, which is configured to traverse the ground, e.g., on a street, on a road, on a track, on one or more rails, off-road, or the like.

[0034] An “autonomous vehicle” may describe a vehicle capable of implementing at least one navigational change without driver input. A navigational change may describe or include a change in one or more of steering, braking, acceleration / deceleration, or any other operation relating to movement, of the vehicle. A vehicle may be described as autonomous even in case the vehicle is not fully autonomous, for example, fully operational with driver or without driver input. Autonomous vehicles may include those vehicles that can operate under driver control during certain time periods, and without driver control during other time periods. Additionally or alternatively, autonomous vehicles may include vehicles that control only some aspects of vehicle navigation, such as steering, e.g., to maintain a vehicle course between vehicle lane constraints, or some steering operations under certain circumstances, e.g., not under all circumstances, but may leave other aspects of vehicle navigation to the driver, e.g., braking or braking under certain circumstances.Additionally or alternatively, autonomous vehicles may include vehicles that share the control of one or more aspects of vehicle navigation under certain circumstances, e.g., hands-on, such as responsive to a driver input; and / or vehicles that control one or more aspects of vehicle navigation under certain circumstances, e.g., hands-off, such as independent of driver input. Additionally or alternatively, autonomous vehicles may include vehicles that control one or more aspects of vehicle navigation under certain circumstances, such as under certain environmental conditions, e.g., spatial areas, roadway conditions, or the like. In some aspects, autonomous vehicles may handle some or all aspects of braking, speed control, velocity control, steering, and / or any other additional operations, of the vehicle. An autonomous vehicle may include those vehicles that can operate without a driver. The level of autonomy of a vehicle may be described or determined by the Society of Automotive Engineers (SAE) level of the vehicle, e.g., as defined by the SAE, for example in SAE J3016 2018: Taxonomy and definitions for terms related to driving automation systems for on road motor vehicles, or by other relevant professional organizations. The SAE level may have a value ranging from a minimum level, e.g., level 0 (illustratively, substantially no driving automation), to a maximum level, e.g., level 5 (illustratively, full driving automation).

[0035] An “assisted vehicle” may describe a vehicle capable of informing a driver or occupant of the vehicle of sensed data or information derived therefrom.

[0036] The phrase “vehicle operation data” may be understood to describe any type of feature related to the operation of a vehicle. By way of example, “vehicle operation data” may describe the status of the vehicle, such as, the type of tires of the vehicle, the type of vehicle, and / or the age of the manufacturing of the vehicle. More generally, “vehicle operation data” may describe or include static features or static vehicle operation data (illustratively, features or data not changing over time). As another example, additionally or alternatively, “vehicle operation data” may describe or include features changing during the operation of the vehicle, for example, environmental conditions, such as weather conditions or road conditions during the operation of the vehicle, fuel levels, fluid levels, operational parameters of the driving source of the vehicle, or the like. More generally, “vehicle operation data” may describe or include varying features or varying vehicle operation data (illustratively, time varying features or data).

[0037] Some aspects may be used in conjunction with various devices and systems, for example, a radar sensor, a radar device, a radar system, a vehicle, a vehicular system, an autonomous vehicular system, a vehicular communication system, a vehicular device, an airborne platform, a waterborne platform, road infrastructure, sports-capture infrastructure, city monitoring infrastructure, static infrastructure platforms, indoor platforms, moving platforms, robot platforms, industrial platforms, a sensor device, a User Equipment (UE), a Mobile Device (MD), a wireless station (STA), a sensor device, a non-vehicular device, a mobile or portable device, and the like.

[0038] Some aspects may be used in conjunction with Radio Frequency (RF) systems, radar systems, vehicular radar systems, autonomous systems, robotic systems, detection systems, or the like.

[0039] Some demonstrative aspects may be used in conjunction with an RF frequency in a frequency band having a starting frequency above 10 Gigahertz (GHz), for example, a frequency band having a starting frequency between 10GHz and 120GHz. For example, some demonstrative aspects may be used in conjunction with an RF frequency having a starting frequency above 30GHz, for example, above 45GHz, e.g., above 60GHz. For example, some demonstrative aspects may be used in conjunction with an automotive radar frequency band, e.g., a frequency band between 76GHz and 81 GHz. However, other aspects may be implemented utilizing any other suitable frequency bands, for example, a frequency band above 140GHz, a frequency band of 300GHz, a sub Terahertz (THz) band, a THz band, an Infra-Red (IR) band, and / or any other frequency band.

[0040] As used herein, the term "circuitry" may refer to, be part of, or include, an Application Specific Integrated Circuit (ASIC), an integrated circuit, an electronic circuit, a processor (shared, dedicated, or group), and / or memory (shared, dedicated, or group), that execute one or more software or firmware programs, a combinational logic circuit, and / or other suitable hardware components that provide the described functionality. In some aspects, some functions associated with the circuitry may be implemented by one or more software or firmware modules. In some aspects, circuitry may include logic, at least partially operable in hardware.

[0041] The term “logic” may refer, for example, to computing logic embedded in circuitry of a computing apparatus and / or computing logic stored in a memory of acomputing apparatus. For example, the logic may be accessible by a processor of the computing apparatus to execute the computing logic to perform computing functions and / or operations. In one example, logic may be embedded in various types of memory and / or firmware, e.g., silicon blocks of various chips and / or processors. Logic may be included in, and / or implemented as part of, various circuitry, e.g., radio circuitry, receiver circuitry, control circuitry, transmitter circuitry, transceiver circuitry, processor circuitry, and / or the like. In one example, logic may be embedded in volatile memory and / or non-volatile memory, including random access memory, read only memory, programmable memory, magnetic memory, flash memory, persistent memory, and / or the like. Logic may be executed by one or more processors using memory, e.g., registers, buffers, stacks, and the like, coupled to the one or more processors, e.g., as necessary to execute the logic.

[0042] The term “communicating” as used herein with respect to a signal includes transmitting the signal and / or receiving the signal. For example, an apparatus, which is capable of communicating a signal, may include a transmitter to transmit the signal, and / or a receiver to receive the signal. The verb communicating may be used to refer to the action of transmitting or the action of receiving. In one example, the phrase “communicating a signal” may refer to the action of transmitting the signal by a transmitter, and may not necessarily include the action of receiving the signal by a receiver. In another example, the phrase “communicating a signal” may refer to the action of receiving the signal by a receiver, and may not necessarily include the action of transmitting the signal by a transmitter.

[0043] The term “antenna”, as used herein, may include any suitable configuration, structure, and / or arrangement of one or more antenna elements, components, units, assemblies, and / or arrays. In some aspects, the antenna may implement transmit and receive functionalities using separate transmit and receive antenna elements. In some aspects, the antenna may implement transmit and receive functionalities using common and / or integrated transmit / receive elements. The antenna may include, for example, a phased array antenna, a MIMO (Multiple-Input Multiple-Output) array antenna, a single element antenna, a set of switched beam antennas, and / or the like. In one example, an antenna may be implemented as a separate element or an integratedelement, for example, as an on-module antenna, an on-chip antenna, or according to any other antenna architecture.

[0044] Some demonstrative aspects are described herein with respect to RF radar signals. However, other aspects may be implemented with respect to, or in conjunction with, any other radar signals, wireless signals, IR signals, acoustic signals, optical signals, wireless communication signals, communication scheme, network, standard, and / or protocol. For example, some demonstrative aspects may be implemented with respect to systems, e.g., Light Detection Ranging (LiDAR) systems, and / or sonar systems, utilizing light and / or acoustic signals.

[0045] Reference is now made to Fig. 1, which schematically illustrates a block diagram of a vehicle 100 implementing a radar, in accordance with some demonstrative aspects.

[0046] In some demonstrative aspects, vehicle 100 may include a car, a truck, a motorcycle, a bus, a train, an airborne vehicle, a waterborne vehicle, a cart, a golf cart, an electric cart, a road agent, or any other vehicle.

[0047] In some demonstrative aspects, vehicle 100 may include a radar device 101, e.g., as described below. For example, radar device 101 may include a radar detecting device, a radar sensing device, a radar sensor, or the like, e.g., as described below.

[0048] In some demonstrative aspects, radar device 101 may be implemented as part of a vehicular system, for example, a system to be implemented and / or mounted in vehicle 100.

[0049] In one example, radar device 101 may be implemented as part of an autonomous vehicle system, an automated driving system, an assisted vehicle system, a driver assistance and / or support system, and / or the like.

[0050] For example, radar device 101 may be installed in vehicle 100 for detection of nearby objects, e.g., for autonomous driving.

[0051] In some demonstrative aspects, radar device 101 may be configured to detect targets in a vicinity of vehicle 100, e.g., in a far vicinity and / or a near vicinity, for example, using RF and analog chains, capacitor structures, large spiral transformers and / or any other electronic or electrical elements, e.g., as described below.

[0052] In one example, radar device 101 may be mounted onto, placed, e.g., directly, onto, or attached to, vehicle 100.

[0053] In some demonstrative aspects, vehicle 100 may include a plurality of radar aspects, vehicle 100 may include a single radar device 101.

[0054] In some demonstrative aspects, vehicle 100 may include a plurality of radar devices 101, which may be configured to cover a field of view of 360 degrees around vehicle 100.

[0055] In other aspects, vehicle 100 may include any other suitable count, arrangement, and / or configuration of radar devices and / or units, which may be suitable to cover any other field of view, e.g., a field of view of less than 360 degrees.

[0056] In some demonstrative aspects, radar device 101 may be implemented as a component in a suite of sensors used for driver assistance and / or autonomous vehicles, for example, due to the ability of radar to operate in nearly all-weather conditions.

[0057] In some demonstrative aspects, radar device 101 may be configured to support autonomous vehicle usage, e.g., as described below.

[0058] In one example, radar device 101 may determine a class, a location, an orientation, a velocity, an intention, a perceptional understanding of the environment, and / or any other information corresponding to an object in the environment.

[0059] In another example, radar device 101 may be configured to determine one or more parameters and / or information for one or more operations and / or tasks, e.g., path planning, and / or any other tasks.

[0060] In some demonstrative aspects, radar device 101 may be configured to map a scene by measuring targets’ echoes (reflectivity) and discriminating them, for example, mainly in range, velocity, azimuth and / or elevation, e.g., as described below.

[0061] In some demonstrative aspects , radar device 101 may be configured to detect, and / or sense, one or more objects, which are located in a vicinity, e.g., a far vicinity and / or a near vicinity, of the vehicle 100, and to provide one or more parameters, attributes, and / or information with respect to the objects.

[0062] In some demonstrative aspects, the objects may include road users, such as other vehicles, pedestrians; road objects and markings, such as traffic signs, trafficlights, lane markings, road markings, road elements, e.g., a pavement-road meeting, a road edge, a road profile, road roughness (or smoothness); general objects, such as a hazard, e.g., a tire, a box, a crack in the road surface; and / or the like.

[0063] In some demonstrative aspects, the one or more parameters, attributes and / or information with respect to the object may include a range of the objects from the vehicle 100, an angle of the object with respect to the vehicle 100, a location of the object with respect to the vehicle 100, a relative speed of the object with respect to vehicle 100, and / or the like.

[0064] In some demonstrative aspects, radar device 101 may include a Multiple Input Multiple Output (MIMO) radar device 101, e.g., as described below.

[0065] In one example, the MIMO radar device may be configured to utilize “spatial filtering” processing, for example, beamforming and / or any other mechanism, for one or both of Transmit (Tx) signals and / or Receive (Rx) signals.

[0066] Some demonstrative aspects are described below with respect to a radar device, e.g., radar device 101, implemented as a MIMO radar. However, in other aspects, radar device 101 may be implemented as any other type of radar utilizing a plurality of antenna elements, e.g., a Single Input Multiple Output (SIMO) radar or a Multiple Input Single output (MISO) radar.

[0067] Some demonstrative aspects may be implemented with respect to a radar device, e.g., radar device 101, implemented as a MIMO radar, e.g., as described below. However, in other aspects, radar device 101 may be implemented as any other type of radar, for example, an Electronic Beam Steering radar, a Synthetic Aperture Radar (SAR), adaptive and / or cognitive radars that change their transmission according to the environment and / or ego state, a reflect array radar, or the like.

[0068] In some demonstrative aspects, radar device 101 may include an antenna arrangement 102, a radar frontend 103 configured to communicate radar signals via the antenna arrangement 102, and a radar processor 104 configured to generate radar information based on the radar signals, e.g., as described below.

[0069] In some demonstrative aspects, radar processor 104 may be configured to process radar information of radar device 101 and / or to control one or more operations of radar device 101, e.g., as described below.

[0070] In some demonstrative aspects, radar processor 104 may include, or may be implemented, partially or entirely, by circuitry and / or logic, e.g., one or more processors including circuitry and / or logic, memory circuitry and / or logic. Additionally or alternatively, one or more functionalities of radar processor 104 may be implemented by logic, which may be executed by a machine and / or one or more processors, e.g., as described below.

[0071] In one example, radar processor 104 may include at least one memory, e.g., coupled to the one or more processors, which may be configured, for example, to store, e.g., at least temporarily, at least some of the information processed by the one or more processors and / or circuitry, and / or which may be configured to store logic to be utilized by the processors and / or circuitry.

[0072] In other aspects, radar processor 104 may be implemented by one or more additional or alternative elements of vehicle 100.

[0073] In some demonstrative aspects, radar frontend 103 may include, for example, one or more (radar) transmitters, and a one or more (radar) receivers, e.g., as described below.

[0074] In some demonstrative aspects, antenna arrangement 102 may include a plurality of antennas to communicate the radar signals. For example, antenna arrangement 102 may include multiple transmit antennas in the form of a transmit antenna array, and multiple receive antennas in the form of a receive antenna array. In another example, antenna arrangement 102 may include one or more antennas used both as transmit and receive antennas. In the latter case, the radar frontend 103, for example, may include a duplexer or a circulator, e.g., a circuit to separate transmitted signals from received signals.

[0075] In some demonstrative aspects, as shown in Fig. 1, the radar frontend 103 and the antenna arrangement 102 may be controlled, e.g., by radar processor 104, to transmit a radio transmit signal 105.

[0076] In some demonstrative aspects, as shown in Fig. 1, the radio transmit signal 105 may be reflected by an object 106, resulting in an echo 107.

[0077] In some demonstrative aspects, the radar device 101 may receive the echo 107, e.g., via antenna arrangement 102 and radar frontend 103, and radar processor 104may generate radar information, for example, by calculating information about position, radial velocity (Doppler), and / or direction of the object 106, e.g., with respect to vehicle 100.

[0078] In some demonstrative aspects, radar processor 104 may be configured to provide the radar information to a vehicle controller 108 of the vehicle 100, e.g., for autonomous driving of the vehicle 100.

[0079] In some demonstrative aspects, at least part of the functionality of radar processor 104 may be implemented as part of vehicle controller 108. In other aspects, the functionality of radar processor 104 may be implemented as part of any other element of radar device 101 and / or vehicle 100. In other aspects, radar processor 104 may be implemented, as a separate part of, or as part of any other element of radar device 101 and / or vehicle 100.

[0080] In some demonstrative aspects, vehicle controller 108 may be configured to control one or more functionalities, modes of operation, components, devices, systems, and / or elements of vehicle 100.

[0081] In some demonstrative aspects, vehicle controller 108 may be configured to control one or more vehicular systems of vehicle 100, e.g., as described below.

[0082] In some demonstrative aspects, the vehicular systems may include, for example, a steering system, a braking system, a driving system, and / or any other system of the vehicle 100.

[0083] In some demonstrative aspects, vehicle controller 108 may configured to control radar device 101, and / or to process one or parameters, attributes and / or information from radar device 101.

[0084] In some demonstrative aspects, vehicle controller 108 may be configured, for example, to control the vehicular systems of the vehicle 100, for example, based on radar information from radar device 101 and / or one or more other sensors of the vehicle 100, e.g., Light Detection and Ranging (LIDAR) sensors, camera sensors, and / or the like.

[0085] In one example, vehicle controller 108 may control the steering system, the braking system, and / or any other vehicular systems of vehicle 100, for example, basedon the information from radar device 101, e.g., based on one or more objects detected by radar device 101.

[0086] In other aspects, vehicle controller 108 may be configured to control any other additional or alternative functionalities of vehicle 100.

[0087] Some demonstrative aspects are described herein with respect to a radar device 101 implemented in a vehicle, e.g., vehicle 100. In other aspects a radar device, e.g., radar device 101, may be implemented as part of any other element of a traffic system or network, for example, as part of a road infrastructure, and / or any other element of a traffic network or system. Other aspects may be implemented with respect to any other system, environment, and / or apparatus, which may be implemented in any other object, environment, location, or place. For example, radar device 101 may be part of a non- vehicular device, which may be implemented, for example, in an indoor location, a stationary infrastructure outdoors, or any other location.

[0088] In some demonstrative aspects, radar device 101 may be configured to support security usage. In one example, radar device 101 may be configured to determine a nature of an operation, e.g., a human entry, an animal entry, an environmental movement, and the like, to identity a threat level of a detected event, and / or any other additional or alternative operations.

[0089] Some demonstrative aspects may be implemented with respect to any other additional or alternative devices and / or systems, for example, for a robot, e.g., as described below.

[0090] In other aspects, radar device 101 may be configured to support any other usages and / or applications.

[0091] Reference is now made to Fig. 2, which schematically illustrates a block diagram of a robot 200 implementing a radar, in accordance with some demonstrative aspects.

[0092] In some demonstrative aspects, robot 200 may include a robot arm 201. The robot 200 may be implemented, for example, in a factory for handling an object 213, which may be, for example, a part that should be affixed to a product that is being manufactured. The robot arm 201 may include a plurality of movable members, for example, movable members 202, 203, 204, and a support 205. Moving the movablemembers 202, 203, and / or 204 of the robot arm 201, e.g., by actuation of associated motors, may allow physical interaction with the environment to carry out a task, e.g., handling the object 213.

[0093] In some demonstrative aspects, the robot arm 201 may include a plurality of joint elements, e.g., joint elements 207, 208, 209, which may connect, for example, the members 202, 203, and / or 204 with each other, and with the support 205. For example, a joint element 207, 208, 209 may have one or more joints, each of which may provide rotatable motion, e.g., rotational motion, and / or translatory motion, e.g., displacement, to associated members and / or motion of members relative to each other. The movement of the members 202, 203, 204 may be initiated by suitable actuators.

[0094] In some demonstrative aspects, the member furthest from the support 205, e.g., member 204, may also be referred to as the end-effector 204 and may include one or more tools, such as, a claw for gripping an object, a welding tool, or the like. Other members, e.g., members 202, 203, closer to the support 205, may be utilized to change the position of the end-effector 204, e.g., in three-dimensional space. For example, the robot arm 201 may be configured to function similarly to a human arm, e.g., possibly with a tool at its end.

[0095] In some demonstrative aspects, robot 200 may include a (robot) controller 206 configured to implement interaction with the environment, e.g., by controlling the robot arm’s actuators, according to a control program, for example, in order to control the robot arm 201 according to the task to be performed.

[0096] In some demonstrative aspects, an actuator may include a component adapted to affect a mechanism or process in response to being driven. The actuator can respond to commands given by the controller 206 (the so-called activation) by performing mechanical movement. This means that an actuator, typically a motor (or electromechanical converter), may be configured to convert electrical energy into mechanical energy when it is activated (i.e. actuated).

[0097] In some demonstrative aspects, controller 206 may be in communication with a radar processor 210 of the robot 200.

[0098] In some demonstrative aspects, a radar fronted 211 and a radar antenna arrangement 212 may be coupled to the radar processor 210. In one example, radarfronted 211 and / or radar antenna arrangement 212 may be included, for example, as part of the robot arm 201.

[0099] In some demonstrative aspects, the radar frontend 211, the radar antenna arrangement 212 and the radar processor 210 may be operable as, and / or may be configured to form, a radar device. For example, antenna arrangement 212 may be configured to perform one or more functionalities of antenna arrangement 102 (Fig. 1), radar frontend 211 may be configured to perform one or more functionalities of radar frontend 103 (Fig. 1), and / or radar processor 210 may be configured to perform one or more functionalities of radar processor 104 (Fig. 1), e.g., as described above.[000100] In some demonstrative aspects, for example, the radar frontend 211 and the antenna arrangement 212 may be controlled, e.g., by radar processor 210, to transmit a radio transmit signal 214.[000101] In some demonstrative aspects, as shown in Fig. 2, the radio transmit signal 214 may be reflected by the object 213, resulting in an echo 215.[000102] In some demonstrative aspects, the echo 215 may be received, e.g., via antenna arrangement 212 and radar frontend 211, and radar processor 210 may generate radar information, for example, by calculating information about position, speed (Doppler) and / or direction of the object 213, e.g., with respect to robot arm 201.[000103] In some demonstrative aspects, radar processor 210 may be configured to provide the radar information to the robot controller 206 of the robot arm 201, e.g., to control robot arm 201. For example, robot controller 206 may be configured to control robot arm 201 based on the radar information, e.g., to grab the object 213 and / or to perform any other operation.[000104] Reference is made to Fig. 3, which schematically illustrates a radar apparatus 300, in accordance with some demonstrative aspects.[000105] In some demonstrative aspects, radar apparatus 300 may be implemented as part of a device or system 301, e.g., as described below.[000106] For example, radar apparatus 300 may be implemented as part of, and / or may configured to perform one or more operations and / or functionalities of, the devices or systems described above with reference to Fig. 1 an / or Fig. 2. In other aspects, radar apparatus 300 may be implemented as part of any other device or system 301.[000107] In some demonstrative aspects, radar device 300 may include an antenna arrangement, which may include one or more transmit antennas 302 and one or more receive antennas 303. In other aspects, any other antenna arrangement may be implemented.[000108] In some demonstrative aspects, radar device 300 may include a radar frontend 304, and a radar processor 309.[000109] In some demonstrative aspects, as shown in Fig. 3, the one or more transmit antennas 302 may be coupled with a transmitter (or transmitter arrangement) 305 of the radar frontend 304; and / or the one or more receive antennas 303 may be coupled with a receiver (or receiver arrangement) 306 of the radar frontend 304, e.g., as described below.[000110] In some demonstrative aspects, transmitter 305 may include one or more elements, for example, an oscillator, a power amplifier and / or one or more other elements, configured to generate radio transmit signals to be transmitted by the one or more transmit antennas 302, e.g., as described below.[000111] In some demonstrative aspects, for example, radar processor 309 may provide digital radar transmit data values to the radar frontend 304. For example, radar frontend 304 may include a Digital-to-Analog Converter (DAC) 307 to convert the digital radar transmit data values to an analog transmit signal. The transmitter 305 may convert the analog transmit signal to a radio transmit signal which is to be transmitted by transmit antennas 302.[000112] In some demonstrative aspects, receiver 306 may include one or more elements, for example, one or more mixers, one or more filters and / or one or more other elements, configured to process, down-convert, radio signals received via the one or more receive antennas 303, e.g., as described below.[000113] In some demonstrative aspects, for example, receiver 306 may convert a radio receive signal received via the one or more receive antennas 303 into an analog receive signal. The radar frontend 304 may include an Analog-to-Digital Converter (ADC) 308 to generate digital radar reception data values based on the analog receive signal. For example, radar frontend 304 may provide the digital radar reception data values to the radar processor 309.[000114] In some demonstrative aspects, radar processor 309 may be configured to process the digital radar reception data values, for example, to detect one or more objects, e.g., in an environment of the device / system 301. This detection may include, for example, the determination of information including one or more of range, speed (Doppler), direction, and / or any other information, of one or more objects, e.g., with respect to the system 301.[000115] In some demonstrative aspects, radar processor 309 may be configured to provide the determined radar information to a system controller 310 of device / system 301. For example, system controller 310 may include a vehicle controller, e.g., if device / system 301 includes a vehicular device / system, a robot controller, e.g., if device / system 301 includes a robot device / system, or any other type of controller for any other type of device / system 301.[000116] In some demonstrative aspects, the radar information from radar processor 309 may be processed, e.g., by system controller 310 and / or any other element of system 301, for example, in combination with information from one or more other of information sources, for example, LiDAR information from a LiDAR processor, vision information from a vision-based processor, or the like.[000117] In some demonstrative aspects, an environmental model of an environment of system 301 may be determined, e.g., by system controller 310 and / or any other element of system 301, for example, based on the radar information from radar processor 309, and / or the information from one or more other of information sources.[000118] In some demonstrative aspects, a driving policy system, e.g., which may be implemented by system controller 310 and / or any other element of system 301, may process the environmental model, for example, to decide on one or more actions, which may be taken.[000119] In some demonstrative aspects, system controller 310 may be configured to control one or more controlled system components 311 of the system 301, e.g. a motor, a brake, steering, and the like, e.g. by one or more corresponding actuators, for example, based on the one or more action decisions.[000120] In some demonstrative aspects, radar device 300 may include a storage 312 or a memory 313, e.g., to store information processed by radar 300, for example, digitalradar reception data values being processed by the radar processor 309, radar information generated by radar processor 309, and / or any other data to be processed by radar processor 309.[000121] In some demonstrative aspects, device / system 301 may include, for example, an application processor 314 and / or a communication processor 315, for example, to at least partially implement one or more functionalities of system controller 310 and / or to perform communication between system controller 310, radar device 300, the controlled system components 311, and / or one or more additional elements of device / system 301.[000122] In some demonstrative aspects, radar device 300 may be configured to generate and transmit the radio transmit signal in a form, which may support determination of range, speed, and / or direction, e.g., as described below.[000123] For example, a radio transmit signal of a radar may be configured to include a plurality of pulses. For example, a pulse transmission may include the transmission of short high-power bursts in combination with times during which the radar device listens for echoes.[000124] For example, in order to more optimally support a highly dynamic situation, e.g., in an automotive scenario, a Continuous Wave (CW) may instead be used as the radio transmit signal. However, a continuous wave, e.g., with constant frequency, may support velocity determination, but may not allow range determination, e.g., due to the lack of a time mark that could allow distance calculation.[000125] In some demonstrative aspects, radio transmit signal 105 (Fig. 1) may be transmitted according to technologies such as, for example, Frequency-Modulated Continuous Wave (FMCW) radar, Phase-Modulated Continuous Wave (PMCW) radar, Orthogonal Frequency Division Multiplexing (OFDM) radar, and / or any other type of radar technology, which may support determination of range, velocity, and / or direction, e.g., as described below.[000126] Reference is made to Fig. 4, which schematically illustrates a FMCW radar apparatus, in accordance with some demonstrative aspects.[000127] In some demonstrative aspects, FMCW radar device 400 may include a radar frontend 401, and a radar processor 402. For example, radar frontend 304 (Fig. 3) mayinclude one or more elements of, and / or may perform one or more operations and / or functionalities of, radar frontend 401; and / or radar processor 309 (Fig. 3) may include one or more elements of, and / or may perform one or more operations and / or functionalities of, radar processor 402.[000128] In some demonstrative aspects, FMCW radar device 400 may be configured to communicate radio signals according to an FMCW radar technology, e.g., rather than sending a radio transmit signal with a constant frequency.[000129] In some demonstrative aspects, radio frontend 401 may be configured to ramp up and reset the frequency of the transmit signal, e.g., periodically, for example, according to a saw tooth waveform 403. In other aspects, a triangle waveform, or any other suitable waveform may be used.[000130] In some demonstrative aspects, for example, radar processor 402 may be configured to provide waveform 403 to frontend 401, for example, in digital form, e.g., as a sequence of digital values.[000131] In some demonstrative aspects, radar frontend 401 may include a DAC 404 to convert waveform 403 into analog form, and to supply it to a voltage-controlled oscillator 405. For example, oscillator 405 may be configured to generate an output signal, which may be frequency-modulated in accordance with the waveform 403.[000132] In some demonstrative aspects, oscillator 405 may be configured to generate the output signal including a radio transmit signal, which may be fed to and sent out by one or more transmit antennas 406.[000133] In some demonstrative aspects, the radio transmit signal generated by the oscillator 405 may have the form of a sequence of chirps 407, which may be the result of the modulation of a sinusoid with the saw tooth waveform 403.[000134] In one example, a chirp 407 may correspond to the sinusoid of the oscillator signal frequency-modulated by a “tooth” of the saw tooth waveform 403, e.g., from the minimum frequency to the maximum frequency.[000135] In some demonstrative aspects, FMCW radar device 400 may include one or more receive antennas 408 to receive a radio receive signal. The radio receive signal may be based on the echo of the radio transmit signal, e.g., in addition to any noise, interference, or the like.[000136] In some demonstrative aspects, radar frontend 401 may include a mixer 409 to mix the radio transmit signal with the radio receive signal into a mixed signal.[000137] In some demonstrative aspects, radar frontend 401 may include a filter, e.g., a Low Pass Filter (LPF) 410, which may be configured to filter the mixed signal from the mixer 409 to provide a filtered signal. For example, radar frontend 401 may include an ADC 411 to convert the filtered signal into digital reception data values, which may be provided to radar processor 402. In another example, the filter 410 may be a digital filter, and the ADC 411 may be arranged between the mixer 409 and the filter 410.[000138] In some demonstrative aspects, radar processor 402 may be configured to process the digital reception data values to provide radar information, for example, including range, speed (velocity / Doppler), and / or direction (AoA) information of one or more objects.[000139] In some demonstrative aspects, radar processor 402 may be configured to perform a first Fast Fourier Transform (FFT) (also referred to as “range FFT”) to extract a delay response, which may be used to extract range information, and / or a second FFT (also referred to as “Doppler FFT”) to extract a Doppler shift response, which may be used to extract velocity information, from the digital reception data values.[000140] In other aspects, any other additional or alternative methods may be utilized to extract range information. In one example, in a digital radar implementation, a correlation with the transmitted signal may be used, e.g., according to a matched filter implementation.[000141] Reference is made to Fig. 5, which schematically illustrates an extraction scheme, which may be implemented to extract range and speed (Doppler) estimations from digital reception radar data values, in accordance with some demonstrative aspects. For example, radar processor 104 (Fig. 1), radar processor 210 (Fig. 2), radar processor 309 (Fig. 3), and / or radar processor 402 (Fig. 4), may be configured to extract range and / or speed (Doppler) estimations from digital reception radar data values according to one or more aspects of the extraction scheme of Fig. 5.[000142] In some demonstrative aspects, as shown in Fig. 5, a radio receive signal, e.g., including echoes of a radio transmit signal, may be received by a receive antenna array 501. The radio receive signal may be processed by a radio radar frontend 502 togenerate digital reception data values, e.g., as described above. The radio radar frontend 502 may provide the digital reception data values to a radar processor 503, which may process the digital reception data values to provide radar information, e.g., as described above.[000143] In some demonstrative aspects, the digital reception data values may be represented in the form of a data cube 504. For example, the data cube 504 may include digitized samples of the radio receive signal, which is based on a radio signal transmitted from a transmit antenna and received by M receive antennas. In some demonstrative aspects, for example, with respect to a MIMO implementation, there may be multiple transmit antennas, and the number of samples may be multiplied accordingly.[000144] In some demonstrative aspects, a layer of the data cube 504, for example, a horizontal layer of the data cube 504, may include samples of an antenna, e.g., a respective antenna of the M antennas.[000145] In some demonstrative aspects, data cube 504 may include samples for K chirps. For example, as shown in Fig. 5, the samples of the chirps may be arranged in a so-called “slow time”-direction.[000146] In some demonstrative aspects, the data cube 504 may include L samples, e.g., L = 512 or any other number of samples, for a chirp, e.g., per each chirp. For example, as shown in Fig. 5, the samples per chirp may be arranged in a so-called “fast time”-direction of the data cube 504.[000147] In some demonstrative aspects, processor 504 may be configured to determine the range values, Doppler values, and / or Angle of Arrival (AoA) values, e.g., Azimuth values and / or Elevation values, for example, based on FFT techniques, e.g., as described below.[000148] In other aspects, processor 504 may be configured to determine the range values, Doppler values, and / or Angle of Arrival (AoA) values, e.g., Azimuth values and / or Elevation values, for example, based on Super-Resolution (SR) techniques, and / or any other suitable processing technique.[000149] In some demonstrative aspects, radar processor 503 may be configured to process a plurality of samples, e.g., L samples collected for each chirp and for eachantenna, by a first FFT. The first FFT may be performed, for example, for each chirp and each antenna, such that a result of the processing of the data cube 504 by the first FFT may again have three dimensions, and may have the size of the data cube 504 while including values for L range bins, e.g., instead of the values for the L sampling times.[000150] In some demonstrative aspects, radar processor 503 may be configured to process the result of the processing of the data cube 504 by the first FFT, for example, by processing the result according to a second FFT along the chirps, e.g., for each antenna and for each range bin.[000151] For example, the first FFT may be in the “fast time” direction, and the second FFT may be in the “slow time” direction.[000152] In some demonstrative aspects, the result of the second FFT may provide, e.g., when aggregated over the antennas, a range / Doppler (R / D) map 505. The R / D map may have FFT peaks 506, for example, including peaks of FFT output values (in terms of absolute values) for certain range / speed combinations, e.g., for range / Doppler bins. For example, a range / Doppler bin may correspond to a range bin and a Doppler bin. For example, radar processor 503 may consider a peak as potentially corresponding to an object, e.g., of the range and speed corresponding to the peak’s range bin and speed bin.[000153] In some demonstrative aspects, the extraction scheme of Fig. 5 may be implemented for an FMCW radar, e.g., FMCW radar 400 (Fig. 4), as described above. In other aspects, the extraction scheme of Fig. 5 may be implemented for any other radar type. In one example, the radar processor 503 may be configured to determine a range / Doppler map 505 from digital reception data values of a PMCW radar, an OFDM radar, or any other radar technologies. For example, in adaptive or cognitive radar, the pulses in a frame, the waveform and / or modulation may be changed over time, e.g., according to the environment.[000154] Referring back to Fig. 3, in some demonstrative aspects, receive antenna arrangement 303 may be implemented using a receive antenna array having a plurality of receive antennas (or receive antenna elements). For example, radar processor 309 may be configured to determine an angle of arrival of the received radio signal, e.g., echo 107 (Fig. 1) and / or echo 215 (Fig. 2). For example, radar processor 309 may beconfigured to determine a direction of a detected object, e.g., with respect to the device / system 301, for example, based on the angle of arrival of the received radio signal, e.g., as described below.[000155] Reference is made to Fig. 6, which schematically illustrates an angledetermination scheme, which may be implemented to determine Angle of Arrival (AoA) information based on an incoming radio signal received by a receive antenna array 600, in accordance with some demonstrative aspects.[000156] Fig. 6 depicts an angle-determination scheme based on received signals at the receive antenna array.[000157] In some demonstrative aspects, for example, in a virtual MIMO array, the angle-determination may also be based on the signals transmitted by the array of Tx antennas.[000158] Fig. 6 depicts a one-dimensional angle-determination scheme. Other multidimensional angle determination schemes, e.g., a two-dimensional scheme or a three- dimensional scheme, may be implemented.[000159] In some demonstrative aspects, as shown in Fig. 6, the receive antenna array 600 may include M antennas (numbered, from left to right, 1 to M).[000160] As shown by the arrows in FIG. 6, it is assumed that an echo is coming from an object located at the top left direction. Accordingly, the direction of the echo, e.g., the incoming radio signal, may be towards the bottom right. According to this example, the further to the left a receive antenna is located, the earlier it will receive a certain phase of the incoming radio signal.[000161] For example, a phase difference, denoted Acp, between two antennas of the receive antenna array 600 may be determined, e.g., as follows:2TT A< = — — ■ d ■ sin(0) A. wherein X denotes a wavelength of the incoming radio signal, d denotes a distance between the two antennas, and 0 denotes an angle of arrival of the incoming radio signal, e.g., with respect to a normal direction of the array.[000162] In some demonstrative aspects, radar processor 309 (Fig. 3) may be configured to utilize this relationship between phase and angle of the incoming radio signal, for example, to determine the angle of arrival of echoes, for example by performing an FFT, e.g., a third FFT (“angular FFT”) over the antennas.[000163] In some demonstrative aspects, multiple transmit antennas, e.g., in the form of an antenna array having multiple transmit antennas, may be used, for example, to increase the spatial resolution, e.g., to provide high-resolution radar information. For example, a MIMO radar device may utilize a virtual MIMO radar antenna, which may be formed as a convolution of a plurality of transmit antennas convolved with a plurality of receive antennas.[000164] Reference is made to Fig. 7, which schematically illustrates a MIMO radar antenna scheme, which may be implemented based on a combination of Transmit (Tx) and Receive (Rx) antennas, in accordance with some demonstrative aspects.[000165] In some demonstrative aspects, as shown in Fig. 7, a radar MIMO arrangement may include a transmit antenna array 701 and a receive antenna array 702. For example, the one or more transmit antennas 302 (Fig. 3) may be implemented to include transmit antenna array 701, and / or the one or more receive antennas 303 (Fig. 3) may be implemented to include receive antenna array 702.[000166] In some demonstrative aspects, antenna arrays including multiple antennas both for transmitting the radio transmit signals and for receiving echoes of the radio transmit signals, may be utilized to provide a plurality of virtual channels as illustrated by the dashed lines in Fig. 7. For example, a virtual channel may be formed as a convolution, for example, as a Kronecker product, between a transmit antenna and a receive antenna, e.g., representing a virtual steering vector of the MIMO radar.[000167] In some demonstrative aspects, a transmit antenna, e.g., each transmit antenna, may be configured to send out an individual radio transmit signal, e.g., having a phase associated with the respective transmit antenna.[000168] For example, an array of N transmit antennas and M receive antennas may be implemented to provide a virtual MIMO array of size N x M. For example, the virtual MIMO array may be formed according to the Kronecker product operation applied to the Tx and Rx steering vectors.[000169] Fig. 8 is a schematic block diagram illustration of elements of a radar device 800, in accordance with some demonstrative aspects. For example, radar device 101 (Fig. 1), radar device 300 (Fig. 3), and / or radar device 400 (Fig. 4), may include one or more elements of radar device 800, and / or may perform one or more operations and / or functionalities of radar device 800.[000170] In some demonstrative aspects, as shown in Fig. 8, radar device 800 may include a radar frontend 804 and a radar processor 834. For example, radar frontend 103 (Fig. 1), radar frontend 211 (Fig. 1), radar frontend 304 (Fig. 3), radar frontend 401 (Fig. 4), and / or radar frontend 502 (Fig. 5), may include one or more elements of radar frontend 804, and / or may perform one or more operations and / or functionalities of radar frontend 804.[000171] In some demonstrative aspects, radar frontend 804 may be implemented as part of a MIMO radar utilizing a MIMO radar antenna 881 including a plurality of Tx antennas 814 configured to transmit a plurality of Tx RF signals (also referred to as ”Tx radar signals”); and a plurality of Rx antennas 816 configured to receive a plurality of Rx RF signals (also referred to as ”Rx radar signals”), for example, based on the Tx radar signals, e.g., as described below.[000172] In some demonstrative aspects, MIMO antenna array 881, antennas 814, and / or antennas 816 may include or may be part of any type of antennas suitable for transmitting and / or receiving radar signals. For example, MIMO antenna array 881, antennas 814, and / or antennas 816, may be implemented as part of any suitable configuration, structure, and / or arrangement of one or more antenna elements, components, units, assemblies, and / or arrays. For example, MIMO antenna array 881, antennas 814, and / or antennas 816, may be implemented as part of a phased array antenna, a multiple element antenna, a set of switched beam antennas, and / or the like. In some aspects, MIMO antenna array 881, antennas 814, and / or antennas 816, may be implemented to support transmit and receive functionalities using separate transmit and receive antenna elements. In some aspects, MIMO antenna array 881, antennas 814, and / or antennas 816, may be implemented to support transmit and receive functionalities using common and / or integrated transmit / receive elements.[000173] In some demonstrative aspects, MIMO radar antenna 881 may include a rectangular MIMO antenna array, and / or curved array, e.g., shaped to fit a vehicle design.[000174] In other aspects, any other form, shape, and / or arrangement of MIMO radar antenna 881 may be implemented.[000175] In some demonstrative aspects, radar frontend 804 may include one or more radios configured to generate and transmit the Tx RF signals via Tx antennas 814; and / or to process the Rx RF signals received via Rx antennas 816, e.g., as described below.[000176] In some demonstrative aspects, radar frontend 804 may include at least one transmitter (Tx) 883 including circuitry and / or logic configured to generate and / or transmit the Tx radar signals via Tx antennas 814.[000177] In some demonstrative aspects, radar frontend 804 may include at least one receiver (Rx) 885 including circuitry and / or logic to receive and / or process the Rx radar signals received via Rx antennas 816, for example, based on the Tx radar signals.[000178] In some demonstrative aspects, transmitter 883, and / or receiver 885 may include circuitry; logic; Radio Frequency (RF) elements, circuitry and / or logic; baseband elements, circuitry and / or logic; modulation elements, circuitry and / or logic; demodulation elements, circuitry and / or logic; amplifiers; analog to digital and / or digital to analog converters; filters; and / or the like.[000179] In some demonstrative aspects, transmitter 883 may include a plurality of Tx chains 810 configured to generate and transmit the Tx RF signals via Tx antennas 814, e.g., respectively; and / or receiver 885 may include a plurality of Rx chains 812 configured to receive and process the Rx RF signals received via the Rx antennas 816, e.g., respectively.[000180] In some demonstrative aspects, radar processor 834 may be configured to generate radar information 813, for example, based on the radar signals communicated by MIMO radar antenna 881, e.g., as described below. For example, radar processor 104 (Fig. 1), radar processor 210 (Fig. 2), radar processor 309 (Fig. 3), radar processor 402 (Fig. 4), and / or radar processor 503 (Fig. 5), may include one or more elements ofradar processor 834, and / or may perform one or more operations and / or functionalities of radar processor 834.[000181] In some demonstrative aspects, radar processor 834 may be configured to generate radar information 813, for example, based on radar Rx data 811 received from the plurality of Rx chains 812. For example, radar Rx data 811 may be based on the radar Rx signals received via the Rx antennas 816.[000182] In some demonstrative aspects, radar processor 834 may include an input 832 to receive radar input data, e.g., including the radar Rx data 811 from the plurality of Rx chains 812.[000183] In some demonstrative aspects, radar processor 834 may include, or may be implemented, partially or entirely, by circuitry and / or logic, e.g., one or more processors including circuitry and / or logic, memory circuitry and / or logic. Additionally or alternatively, one or more functionalities of radar processor 834 may be implemented by logic, which may be executed by a machine and / or one or more processors, e.g., as described below.[000184] In some demonstrative aspects, radar processor 834 may include at least one processor 836, which may be configured, for example, to process the radar Rx data 811, and / or to perform one or more operations, methods, and / or algorithms.[000185] In some demonstrative aspects, radar processor 834 may include at least one memory 838, e.g., coupled to the processor 836. For example, memory 838 may be configured to store data processed by radar processor 834. For example, memory 838 may store, e.g., at least temporarily, at least some of the information processed by the processor 836, and / or logic to be utilized by the processor 836.[000186] In some demonstrative aspects, processor 836 may interface with memory 838, for example, via a memory interface 839.[000187] In some demonstrative aspects, processor 836 may be configured to access memory 838, e.g., to write data to memory 838 and / or to read data from memory 838, for example, via memory interface 839.[000188] In some demonstrative aspects, memory 838 may be configured to store at least part of the radar data, e.g., some of the radar Rx data or all of the radar Rx data, for example, for processing by processor 836, e.g., as described below.[000189] In some demonstrative aspects, memory 838 may be configured to store processed data, which may be generated by processor 836, for example, during the process of generating the radar information 813, e.g., as described below.[000190] In some demonstrative aspects, memory 838 may be configured to store range information and / or Doppler information, which may be generated by processor 836, for example, based on the radar Rx data. In one example, the range information and / or Doppler information may be determined based on a Cross-Correlation (XCORR) operation, which may be applied to the radar Rx data. Any other additional or alternative operation, algorithm, and / or procedure may be utilized to generate the range information and / or Doppler information.[000191] In some demonstrative aspects, memory 838 may be configured to store AoA information, which may be generated by processor 836, for example, based on the radar Rx data, the range information and / or Doppler information. In one example, the AoA information may be determined based on an AoA estimation algorithm. Any other additional or alternative operation, algorithm, and / or procedure may be utilized to generate the AoA information.[000192] In some demonstrative aspects, radar processor 834 may be configured to generate the radar information 813 including one or more of range information, Doppler information, and / or AoA information.[000193] In some demonstrative aspects, the radar information 813 may include Point Cloud 1 (PCI) information, for example, including raw point cloud estimations, e.g., Range, Radial Velocity, Azimuth, and / or Elevation.[000194] In some demonstrative aspects, the radar information 813 may include Point Cloud 2 (PC2) information, which may be generated, for example, based on the PCI information. For example, the PC2 information may include clustering information, tracking information, e.g., tracking of probabilities and / or density functions, bounding box information, classification information, orientation information, and the like.[000195] In some demonstrative aspects, the radar information 813 may include target tracking information corresponding to a plurality of targets in an environment of the radar device 800, e.g., as described below.[000196] In some demonstrative aspects, radar processor 834 may be configured to generate the radar information 813 in the form of four Dimensional (4D) image information, e.g., a cube, which may represent 4D information corresponding to one or more detected targets.[000197] In some demonstrative aspects, the 4D image information may include, for example, range values, e.g., based on the range information, velocity values, e.g., based on the Doppler information, azimuth values, e.g., based on azimuth AoA information, elevation values, e.g., based on elevation AoA information, and / or any other values.[000198] In some demonstrative aspects, radar processor 834 may be configured to generate the radar information 813 in any other form, and / or including any other additional or alternative information.[000199] In some demonstrative aspects, radar processor 834 may be configured to process the signals communicated via MIMO radar antenna 881 as signals of a virtual MIMO array formed by a convolution of the plurality of Rx antennas 816 and the plurality of Tx antennas 814.[000200] In some demonstrative aspects, radar frontend 804 and / or radar processor 834 may be configured to utilize MIMO techniques, for example, to support a reduced physical array aperture, e.g., an array size, and / or utilizing a reduced number of antenna elements. For example, radar frontend 804 and / or radar processor 834 may be configured to transmit orthogonal signals via one or more Tx arrays 824 including a plurality of N elements, e.g., Tx antennas 814, and processing received signals via one or more Rx arrays 826 including a plurality of M elements, e.g., Rx antennas 816.[000201] In some demonstrative aspects, utilizing the MIMO technique of transmission of the orthogonal signals from the Tx arrays 824 with N elements and processing the received signals in the Rx arrays 826 with M elements may be equivalent, e.g., under a far field approximation, to a radar utilizing transmission from one antenna and reception with N*M antennas. For example, radar frontend 804 and / or radar processor 834 may be configured to utilize MIMO antenna array 881 as a virtual array having an equivalent array size of N*M, which may define locations of virtual elements, for example, as a convolution of locations of physical elements, e.g., the antennas 814 and / or 816.[000202] In some demonstrative aspects, a radar system may include a plurality of radar devices 800. For example, vehicle 100 (Fig. 1) may include a plurality of radar devices 800, e.g., as described below.[000203] Reference is made to Fig. 9, which schematically illustrates a radar system 901 including a plurality of Radio Head (RH) radar devices (also referred to as RHs) 910 implemented in a vehicle 900, in accordance with some demonstrative aspects.[000204] In some demonstrative aspects, as shown in Fig. 9, the plurality of RH radar devices 910 may be located, for example, at a plurality of positions around vehicle 900, for example, to provide radar sensing at a large field of view around vehicle 900, e.g., as described below.[000205] In some demonstrative aspects, as shown in Fig. 9, the plurality of RH radar devices 910 may include, for example, six RH radar devices 910, e.g., as described below.[000206] In some demonstrative aspects, the plurality of RH radar devices 910 may be located, for example, at a plurality of positions around vehicle 900, which may be configured to support 360-degrees radar sensing, e.g., a field of view of 360 degrees surrounding the vehicle 900, e.g., as described below.[000207] In one example, the 360-degrees radar sensing may allow to provide a radarbased view of substantially all surroundings around vehicle 900, e.g., as described below.[000208] In other aspects, the plurality of RH radar devices 910 may include any other number of RH radar devices 910, e.g., less than six radar devices or more than six radar devices.[000209] In other aspects, the plurality of RH radar devices 910 may be positioned at any other locations and / or according to any other arrangement, which may support radar sensing at any other field of view around vehicle 900, e.g., 360-degrees radar sensing or radar sensing of any other field of view.[000210] In some demonstrative aspects, as shown in Fig. 9, vehicle 900 may include a first RH radar device 902, e.g., a front RH, at a front-side of vehicle 900.[000211] In some demonstrative aspects, as shown in Fig. 9, vehicle 900 may include a second RH radar device 904, e.g., a back RH, at a back-side of vehicle 900.[000212] In some demonstrative aspects, as shown in Fig. 9, vehicle 900 may include one or more of RH radar devices at one or more respective corners of vehicle 900. For example, vehicle 900 may include a first corner RH radar device 912 at a first comer of vehicle 900, a second comer RH radar device 914 at a second corner of vehicle 900, a third comer RH radar device 916 at a third corner of vehicle 900, and / or a fourth comer RH radar device 918 at a fourth comer of vehicle 900.[000213] In some demonstrative aspects, vehicle 900 may include one, some, or all, of the plurality of RH radar devices 910 shown in Fig. 9. For example, vehicle 900 may include the front RH radar device 902 and / or back RH radar device 904.[000214] In other aspects, vehicle 900 may include any other additional or alternative radar devices, for example, at any other additional or alternative positions around vehicle 900. In one example, vehicle 900 may include a side radar, e.g., on a side of vehicle 900.[000215] In some demonstrative aspects, as shown in Fig. 9, vehicle 900 may include a radar system controller 950 configured to control one or more, e.g., some or all, of the RH radar devices 910.[000216] In some demonstrative aspects, at least part of the functionality of radar system controller 950 may be implemented by a dedicated controller, e.g., a dedicated system controller or central controller, which may be separate from the RH radar devices 910, and may be configured to control some or all of the RH radar devices 910.[000217] In some demonstrative aspects, at least part of the functionality of radar system controller 950 may be implemented as part of at least one RH radar device 910.[000218] In some demonstrative aspects, at least part of the functionality of radar system controller 950 may be implemented by a radar processor of an RH radar device 910. For example, radar processor 834 (Fig. 8) may include one or more elements of radar system controller 950, and / or may perform one or more operations and / or functionalities of radar system controller 950.[000219] In some demonstrative aspects, at least part of the functionality of radar system controller 950 may be implemented by a system controller of vehicle 900. Forexample, vehicle controller 108 (Fig. 1) may include one or more elements of radar system controller 950, and / or may perform one or more operations and / or functionalities of radar system controller 950.[000220] In other aspects, one or more functionalities of system controller 950 may be implemented as part of any other element of vehicle 900.[000221] In some demonstrative aspects, as shown in Fig. 9, an RH radar device 910 of the plurality of RH radar devices 910, may include a baseband processor 930 (also referred to as a “Baseband Processing Unit (BPU)”), which may be configured to control communication of radar signals by the RH radar device 910, and / or to process radar signals communicated by the RH radar device 910. For example, baseband processor 930 may include one or more elements of radar processor 834 (Fig. 8), and / or may perform one or more operations and / or functionalities of radar processor 834 (Fig. 8).[000222] In other aspects, an RH radar device 910 of the plurality of RH radar devices 910 may exclude one or more, e.g., some or all, functionalities of baseband processor 930. For example, controller 950 may be configured to perform one or more, e.g., some or all, functionalities of the baseband processor 930 for the RH.[000223] In one example, controller 950 may be configured to perform baseband processing for all RH radar devices 910, and all RH radio devices 910 may be implemented without baseband processors 930.[000224] In another example, controller 950 may be configured to perform baseband processing for one or more first RH radar devices 910, and the one or more first RH radio devices 910 may be implemented without baseband processors 930; and / or one or more second RH radar devices 910 may be implemented with one or more functionalities, e.g., some or all functionalities, of baseband processors 930.[000225] In another example, one or more, e.g., some or all, RH radar devices 910 may be implemented with one or more functionalities, e.g., partial functionalities or full functionalities, of baseband processors 930.[000226] In some demonstrative aspects, baseband processor 930 may include one or more components and / or elements configured for digital processing of radar signals communicated by the RH radar device 910, e.g., as described below.[000227] In some demonstrative aspects, baseband processor 930 may include one or more FFT engines, matrix multiplication engines, DSP processors, and / or any other additional or alternative baseband, e.g., digital, processing components.[000228] In some demonstrative aspects, as shown in Fig. 9, RH radar device 910 may include a memory 932, which may be configured to store data processed by, and / or to be processed by, baseband processor 930. For example, memory 932 may include one or more elements of memory 838 (Fig. 8), and / or may perform one or more operations and / or functionalities of memory 838 (Fig. 8).[000229] In some demonstrative aspects, memory 932 may include an internal memory, and / or an interface to one or more external memories, e.g., an external Double Data Rate (DDR) memory, and / or any other type of memory.[000230] In other aspects, an RH radar device 910 of the plurality of RH radar devices 910 may exclude memory 932. For example, the RH radar device 910 may be configured to provide radar data to controller 950, e.g., in the form of raw radar data.[000231] In some demonstrative aspects, as shown in Fig. 9, RH radar device 910 may include one or more RF units, e.g., in the form of one or more RF Integrated Chips (RFICs) 920, which may be configured to communicate radar signals, e.g., as described below.[000232] For example, an RFIC 920 may include one or more elements of front-end 804 (Fig. 8), and / or may perform one or more operations and / or functionalities of frontend 804 (Fig. 8).[000233] In some demonstrative aspects, the plurality of RFICs 920 may be operable to form a radar antenna array including one or more Tx antenna arrays and one or more Rx antenna arrays.[000234] For example, the plurality of RFICs 920 may be operable to form MIMO radar antenna 881 (Fig. 8) including Tx arrays 824 (Fig. 8), and / or Rx arrays 826 (Fig. 8).[000235] In some demonstrative aspects, the plurality of RH radar devices 910 may be installed, for example, as integrated units around vehicle 900, for example, in the front, the rear, and / or corners of vehicle 900. For example, the plurality of RH radar devices 910 may be installed at a low position, e.g., at a bumper level of a bumper of vehicle900, and / or or at a high position, e.g., on top of the vehicle 900, for example, on a roof of the vehicle.[000236] In one example, radar devices may be positioned at dedicated high positions on vehicle 900, for example, to allow long-range detection and / or a clear Field of View (FoV).[000237] Referring back to Fig. 8, in some demonstrative aspects, an Rx chain 831 of Rx chains 812 may be configured to implement a voltage clipping mechanism to clip voltage levels of an amplifier, e.g., as described below.[000238] In some demonstrative aspects, the voltage clipping mechanism may be configured to provide a technical solution to support clipping of voltage levels of an interferer signal, for example, a relatively strong interferer signal, at an input of an amplifier, e.g., as described below.[000239] In one example, a strong interferer signal, which may be received from a nearby radar transmitter, may reach significant levels, which may cause irreversible damage for one or more components of an amplifier, e.g., a Low Noise Amplifier (LNA), for example, one or more amplification transistors and / or any other additional or alternative components of the LNA.[000240] In some demonstrative aspects, there may be one or more technical problems, disadvantages, and / or inefficiencies in an implementation for voltage clipping, which utilizes a power detector, for example, to disconnect a supply voltage of a first LNA stage of an LNA, for example, when an input power level of the first LNA stage crosses a specific power level.[000241] In one example, a response time of the power detector may be too slow. Accordingly, one or more LNA components may be damaged by the input power level, for example, before the power detector is able to respond.[000242] In another example, an activation power level of the power detector, e.g., the power level threshold or the specific power level, may be too high. Accordingly, one or more LNA components may be damaged by the input power level, for example, before the power detector is activated.[000243] In another example, the implementation of the power detector may utilize a power supply switch, which may be activated by the power detector to disconnect thesupply voltage of the first LNA stage For example, the implementation of the power supply switch may affect performance of the amplifier including the power detector.[000244] In some demonstrative aspects, an amplifier LNA of the Rx chain 831 may be configured to amplify radar Rx signals, for example, according to the voltage clipping mechanism, e.g., as described below.[000245] In some demonstrative aspects, an amplifier of the Rx chain 831 may include an LNA which may be configured according to the voltage clipping mechanism, e.g., as described below.[000246] In other aspects, the Rx chain 831 may include any other additional or alternative type of amplifier, which may be configured according to the voltage clipping mechanism.[000247] In some demonstrative aspects, the Rx chain 831 may be configured to implement the voltage clipping mechanism to clip a voltage level of signal, for example, based on a predefined clipping voltage threshold, e.g., as described below.[000248] In some demonstrative aspects, the Rx chain 831 may be configured to implement the voltage clipping mechanism to clip the voltage level of relatively strong signals, for example, relatively strong interferer signals, e.g., as described below.[000249] In some demonstrative aspects, the voltage clipping mechanism may be configured to provide a technical solution to protect a receiver, for example, substantially any CMOS receiver, which may be subject to relatively strong signals, e.g., from relatively strong blockers.[000250] In some demonstrative aspects, the voltage clipping mechanism may be configured to provide a technical solution for voltage clipping for an amplifier of any suitable receiver, for example, a radar receiver, a cellular receiver, and / or any other type of receiver for connectivity applications.[000251] In some demonstrative aspects, the voltage clipping mechanism may be configured to provide a technical solution for voltage clipping of Radio Frequency (RF) signals at an amplifier, e.g., as described below.[000252] In some demonstrative aspects, the voltage clipping mechanism may be configured to provide a technical solution for voltage clipping of RF signals in a millimeter wave (mmWave) frequency band, e.g., as described below.[000253] In other aspects, the voltage clipping mechanism may be configured to provide a technical solution for voltage clipping of RF signals in any other additional or alternative frequency band.[000254] Reference is made to Fig. 10, which schematically illustrates an LNA 1010, in accordance with some demonstrative aspects.[000255] In some demonstrative aspects, LNA 1010 may be implemented as part of an RX chain, for example, to amplify signals received by an antenna. For example, Rx chain 831 (Fig. 8) may include one or more elements of LNA 1010, and / or may perform one or more operations and / or functionalities of LNA 1010.[000256] In some demonstrative aspects, as shown in Fig. 10, LNA 1010 may include an LNA core 1020 configured to provide an amplified LNA-core output signal 1017, for example, by amplifying an LNA-core input signal 1015, e.g., as described below.[000257] In some demonstrative aspects, a frequency of the LNA-core input signal 1015 may be above 40 Gigahertz GHz, e.g., as described below.[000258] In other aspects, the LNA-core input signal 1015 may have any other frequency.[000259] In some demonstrative aspects, LNA-core input signal 1015 may be in a frequency bandwidth of 76-81 Gigahertz (GHz), e.g., as described below.[000260] In other aspects, the LNA-core input signal 1015 may be in any other suitable frequency bandwidth.[000261] In some demonstrative aspects, LNA-core input signal 1015 may include, or may be based on an RF Rx signal of an Rx chain.[000262] In some demonstrative aspects, LNA-core input signal 1015 may include, or may be based on a radar signal. For example, LNA-core input signal 1015 may include, or may be based on, a radar signal received via an Rx antenna 816 (Fig. 8), which may be connected to the Rx chain 831 (Fig. 8).[000263] In some demonstrative aspects, LNA 1010 may be implemented as part of a radar device or system, for example, as part of radar device 800 (Fig. 8), e.g., as described above.[000264] In some demonstrative aspects, LNA 1010 may be implemented as part of any other suitable device and / or system.[000265] For example, in some demonstrative aspects, LNA 1010 may be implemented as part of a device, for example, a mobile device, a computing device, and / or a wireless communication device, for example, to amplify RF Rx wireless communication signals.[000266] For example, in some demonstrative aspects, LNA 1010 may be implemented to process wireless communication signals communicated over mmWave frequencies.[000267] In some demonstrative aspects, LNA 1010 may be configured to implement a voltage clipping mechanism, for example, to clip voltage levels of the LNA 1010, e.g., as described below.[000268] In some demonstrative aspects, the voltage clipping mechanism may be configured to provide a technical solution to support clipping of voltage levels of signals, for example, relatively strong signals, at an input of the LNA 1010, e.g., as described below.[000269] In some demonstrative aspects, the voltage clipping mechanism may be configured to provide a technical solution to support clipping of voltage levels of an interferer signal, for example, a relatively strong interferer signal, at an input of the LNA 1010, e.g., as described below.[000270] In some demonstrative aspects, for example, each of Rx chains 812 (Fig. 8) may be configured according to the configuration of LNA 1010, e.g., including the voltage clipping mechanism.[000271] In other aspects, only some of Rx chains 812 (Fig. 8) may include the LNA 1010, while one or more other Rx chains of Rx chains 812 (Fig. 8) may include any other amplifier and / or LNA scheme.[000272] In some demonstrative aspects, as shown in Fig. 10, the LNA core 1020 may include an LNA-core input 1012, for example, to receive the LNA-core input signal 1015, e.g., as described below.[000273] In some demonstrative aspects, as shown in Fig. 10, the LNA core 1020 may include an LNA-core output 1014, for example, to output the amplified LNA-core output signal 1017, e.g., as described below.[000274] In some demonstrative aspects, LNA 1010 may include a voltage clipper 1002 connected in parallel to the LNA core 1020, e.g., as described below.[000275] In some demonstrative aspects, LNA 1010 may include a single LNA core 1020. For example, LNA 1010 may be implemented as a single-stage LNA, which may include a single LNA core 1010.[000276] In some demonstrative aspects, LNA 1010 may include a plurality of LNA cores 1020. For example, LNA 1010 is implemented as a multi-stage LNA including a plurality of LNA stages.[000277] In some demonstrative aspects, only some of LNA stages of the LNA 1010 may include the voltage clipper 1002, while one or more other LNA stages of the LNA 1010 may exclude the voltage clipper 1002. In one example, a first LNA stage, e.g., a first-in-order LNA stage, of the LNA 1010 may include the voltage clipper 1002, while one or more other LNA stages of the LNA 1010, e.g., one or more LNA stages which are after the first LNA stage, may exclude the voltage clipper 1002. In another example, a plurality of first LNA stages, e.g., a sequence of two or more first-in-order LNA stages, of the LNA 1010 may include the voltage clipper 1002, while one or more other LNA stages of the LNA 1010, e.g., one or more LNA stages which are after the plurality of first LNA stages, may exclude the voltage clipper 1002.[000278] In other aspects, each of the LNA stages of LNA 1010 may be configured to include a voltage clipper 1002 connected in parallel to an LNA core 1020 of the LNA stage.[000279] In some demonstrative aspects, the voltage clipper 1002 may be connected in parallel to the LNA core 1020, for example, between a pair of differential terminals of the LNA core 1020, e.g., as described below.[000280] In some demonstrative aspects, the voltage clipper 1002 may be configured to clip at least part of a voltage level, which is above a clipping voltage threshold, of a voltage between a first differential terminal and a second differential terminal of the pair of differential terminals, e.g., as described below.[000281] In some demonstrative aspects, the voltage clipper 1002 may be configured to clip sustainably an entirety of the voltage level, which is above the voltage clipping threshold, e.g., as described below.[000282] In some demonstrative aspects, the voltage clipping threshold may be no more than 0.7 Volt (V), e.g., as described below.[000283] In some demonstrative aspects, the voltage clipping threshold may be no more than 0.3V, e.g., as described below.[000284] In other aspects, the voltage clipping threshold may include any other voltage level.[000285] In some demonstrative aspects, voltage clipper 1002 may be configured to be connected in parallel to one or more differential inputs and / or outputs of one or more LNA stages of LNA 1010, e.g., as described below.[000286] In some demonstrative aspects, voltage clipper 1002 may be configured to provide a technical solution to clip voltage levels of RF signals to be amplified by LNA core 1020, e.g., as described below.[000287] In some demonstrative aspects, voltage clipper 1002 may be configured to provide a technical solution to clip only relatively strong amplitude signals, e.g., ideally, for example, while allowing desired, e.g., weaker, radar signals to be amplified by LNA core 1020, for example, without substantially any distortion, e.g., as described below.[000288] In some demonstrative aspects, voltage clipper 1002 may be configured to provide a technical solution, which may be simple and / or may be implemented with reduced, e.g., minimal cost, for example, zero cost e.g., as described below.[000289] In some demonstrative aspects, voltage clipper 1002 may be configured to provide a technical solution to support reduced, e.g., minimal, performance degradation.[000290] In some demonstrative aspects, voltage clipper 1002 may be configured to provide a technical solution to support reliable protection on sensitive LNA components of a radar LNA, e.g., LNA 1010, for example, from strong damaging signals, for example, strong interferer signals, e.g., as described below.[000291] In some demonstrative aspects, voltage clipper 1002 may be configured to provide a technical solution to support prolonged operation of a receiver, e.g., of a radar device, a wireless communication device and / or any other device implementing the LNA 1010, for example, for many years.[000292] In some demonstrative aspects, voltage clipper 1002 may be configured to provide a technical solution to limit a drain-gate voltage level on N-channel Metal Oxide Semiconductor (NMOS) components of LNA core 1020, e.g., as described below. For example, high voltage swings of the drain-gate voltage level on the NMOS components may exceed safe values and / or may cause heavy damage to LNA core 1020, for example, in case high input power signals are not clipped, e.g., as described below.[000293] Some demonstrative aspects, are described herein with respect to an LNA core including NMOS components. Other aspects may be implemented with respect to an LNA including any other type of components, e.g., P-Channel Metal-Oxide- Semiconductor (PMOS) components.[000294] In some demonstrative aspects, the voltage clipper 1002 may be configured to clip at least part of the voltage level between the pair of differential terminals of the LNA core 1020, e.g., as described below.[000295] In some demonstrative aspects, the voltage clipper 1002 may be configured to clip at least part of the voltage level, which is above the clipping voltage threshold, for example, such that a drain-gate voltage level of one or more amplification transistors of the LNA core 1020 is to be limited to a level of no more than 1.6V, e.g., for substantially any LNA core input signal 1015 having a power level up to at least 8 dBm, e.g., as described below.[000296] In other aspects, the voltage clipper 1002 may be configured to limit the drain-gate voltage level of one or more amplification transistors of the LNA core 1020 according to any other voltage limit, e.g., lower than 1.6V or higher than 1.6V, and / orwith respect to any other range of power levels for LNA core input signal 1015, e.g., less than 8dBm or higher than 8dBm, for example, based on specific implementation constraints.[000297] In some demonstrative aspects, the clipping voltage threshold may be configured, for example, such that a drain-gate voltage level of one or more amplification transistors of the LNA core 1020 may be limited to a level of no more than 1.6V, for example, for substantially any LNA core input signal 1015 having a power level up to at least 8 dBm, e.g., as described below.[000298] In other aspects, the clipping voltage threshold may be configured such that a drain-gate voltage level of one or more amplification transistors of the LNA core 1020 may be limited to any other voltage level, e.g., lower than 1.6V or higher than 1.6V, and / or with respect to any other range of power levels for LNA core input signal 1015, e.g., less than 8dBm or higher than 8dBm, for example, based on specific implementation constraints.[000299] In some demonstrative aspects, the voltage clipper 1002 may be configured to clip the at least part of the voltage level, which is above the clipping voltage threshold, for example, such that an output voltage level of the LNA core 1020 may be limited to a level of no more than 1.1V, for example, for substantially any LNA core input signal 1015 having a power level up to at least 8 dBm, e.g., as described below.[000300] In other aspects, the voltage clipper 1002 may be configured to clip the at least part of the voltage level, which is above the clipping voltage threshold, such that an output voltage level of the LNA core 1020 may be limited to any other voltage level, e.g., lower than 1.6V or higher than 1.6V, and / or with respect to any other range of power levels for LNA core input signal 1015, e.g., less than 8dBm or higher than 8dBm, for example, based on specific implementation constraints.[000301] In some demonstrative aspects, the clipping voltage threshold may be configured, for example, such that an output voltage level of the LNA core 1020 may be limited to a level of no more than 1. IV, for example, for substantially any LNA core input signal 1015 having a power level up to at least 8dBm, e.g., as described below.[000302] In other aspects, the clipping voltage threshold may be configured such that an output voltage level of the LNA core 1020 may be limited to any other voltage level,e.g., lower than 1.6V or higher than 1.6V, and / or with respect to any other range of power levels for LNA core input signal 1015, e.g., less than 8dBm or higher than 8dBm, for example, based on specific implementation constraints.[000303] In some demonstrative aspects, as shown in Fig. 10, the voltage clipper 1002 may include an input voltage clipper 1030, e.g., as described below.[000304] In some demonstrative aspects, as shown in Fig. 10, the voltage clipper 1002 may include an output voltage clipper 1040, e.g., as described below.[000305] In some demonstrative aspects, as shown in Fig. 10, LNA 1010 may include both the output voltage clipper 1040 and the input voltage clipper 1030, e.g., as described below.[000306] In some demonstrative aspects, LNA 1010 may include input voltage clipper 1030, e.g., while the output voltage clipper 1040 may be excluded.[000307] In some demonstrative aspects, LNA 1010 may include output voltage clipper 1040, e.g., while input voltage clipper 1030 may be excluded.[000308] In some demonstrative aspects, as shown in Fig. 10, input voltage clipper 1030 may be connected in parallel to the LNA-core input 1012 of the LNA core 1020, e.g., as described below.[000309] In some demonstrative aspects, input voltage clipper 1030 may be configured to clip an input- voltage level of the LNA core 1020, for example, according to an inputvoltage clipping threshold, e.g., as described below.[000310] In some demonstrative aspects, as shown in Fig. 10, output voltage clipper 1040 may be connected in parallel to the LNA-core output 1014 of the LNA core 1020, e.g., as described below.[000311] In some demonstrative aspects, output voltage clipper 1040 may be configured to clip an output- voltage level of the LNA core 1020, for example, according to an output-voltage clipping threshold, e.g., as described below.[000312] In some demonstrative aspects, the input-voltage clipping threshold and / or the output-voltage clipping threshold may be configured, for example, based on a draingate voltage threshold of a drain-gate voltage level of one or more amplification transistors of the LNA core 1020, as described below.[000313] In some demonstrative aspects, the input-voltage clipping threshold and / or the output-voltage clipping threshold may be configured, for example, such that the drain-gate voltage level of one or more amplification transistors of the LNA core 1020, may be limited to a level of no more than 1.6V, for example, for substantially any LNA core input signal 1015 having a power level up to at least 8 dBm, for example, e.g., as described below.[000314] In other aspects, the input- voltage clipping threshold and / or the outputvoltage clipping threshold may be configured such that the drain-gate voltage level of one or more amplification transistors of the LNA core 1020, may be limited to any other voltage level, e.g., lower than 1.6V or higher than 1.6V, and / or with respect to any other range of power levels for LNA core input signal 1015, e.g., less than 8dBm or higher than 8dBm, for example, based on specific implementation constraints.[000315] In some demonstrative aspects, as shown in Fig. 10, the input voltage clipper 1030 may be connected between a pair of differential input terminals of the LNA core 1020, e.g., as described below.[000316] In some demonstrative aspects, as shown in Fig. 10, the input voltage clipper 1030 may be connected between differential input terminals 1032 and 1034 of the LNA core 1020, e.g., as described below.[000317] In some demonstrative aspects, the input voltage clipper 1030 may be configured to clip at least part of the LNA-core input voltage level between differential input terminals 1032 and 1034, which is above the input-voltage clipping threshold, e.g., as described below.[000318] In some demonstrative aspects, the input-voltage clipping threshold may be in a range between 0.2V and 0.3V, e.g., as described below.[000319] In some demonstrative aspects, the input-voltage clipping threshold may be in a range between 0.22V and 0.28V, e.g., as described below.[000320] In some demonstrative aspects, the input-voltage clipping threshold may be in a range between 0.24V and 0.26V, e.g., as described below.[000321] For example, the input- voltage clipping threshold may be about 0.25V, e.g., as described below.[000322] In other aspects, any other input-voltage clipping threshold may be implemented.[000323] In some demonstrative aspects, as shown in Fig. 10, the output voltage clipper 1040 may be connected between a pair of differential output terminals of the LNA core 1020, e.g., as described below.[000324] In some demonstrative aspects, as shown in Fig. 10, the output voltage clipper 1030 may be connected between differential output terminals 1042 and 1044 of the LNA core 1020, e.g., as described below.[000325] In some demonstrative aspects, as shown in Fig. 10, the output voltage clipper 1030 may be configured to clip at least part of the LNA-core output voltage level between differential output terminals 1042 and 1044, which is above the outputvoltage clipping threshold, e.g., as described below.[000326] In some demonstrative aspects, the output-voltage clipping threshold may be in a range between 0.5V and 0.7V, e.g., as described below.[000327] In some demonstrative aspects, the output-voltage clipping threshold may be in a range between 0.55V and 0.65V, e.g., as described below.[000328] In some demonstrative aspects, the output-voltage clipping threshold may be in a range between 0.58V and 0.62V, e.g., as described below.[000329] For example, the output- voltage clipping threshold may be about 0.6V, e.g., as described below.[000330] In other aspects, any other output-voltage clipping threshold may be implemented.[000331] In some demonstrative aspects, input voltage clipper 1030 may be implemented to provide a technical solution to support, for example, attenuation of strong signals, e.g., a strong interferer signal, for example, to limit dangerous voltage swings, e.g., at the LNA core 1020.[000332] In some demonstrative aspects, output voltage clipper 1040 may be implemented to provide a technical solution to support, for example, improved attenuation of strong signals, e.g., a strong interferer signal. For example, implementing the output voltage clipper 1040 may provide the improved attenuation results, forexample, by clipping the LNA-core output voltage level between differential output terminals 1042 and 1044, for example, where a signal amplitude may be maximal.[000333] In some demonstrative aspects, the voltage clipper 1002 may include a first conductive path and a second conductive path connected in parallel between the pair of differential terminals of the LNA core 1020, e.g., as described below.[000334] In some demonstrative aspects, the first conductive path may be configured to conduct in a first direction from the first differential terminal of the pair of differential terminals to the second differential terminal of the pair of differential terminals, e.g., as described below.[000335] In some demonstrative aspects, the second conductive path may be configured to conduct in a second direction from the second differential terminal to the first differential terminal, e.g., as described below.[000336] In some demonstrative aspects, the first conductive path of the voltage clipper 1002 may include a first diode, and the second conductive path of the voltage clipper 1002 may include a second diode, e.g., as described below.[000337] In some demonstrative aspects, the first conductive path of the voltage clipper 1002 may include a first diode-connected transistor, e.g., as described below.[000338] In some demonstrative aspects, the second conductive path of the voltage clipper 1002 may include a second diode-connected transistor, e.g., as described below.[000339] In some demonstrative aspects, the first diode-connected transistor may include a first diode-connected NMOS transistor, e.g., as described below.[000340] In some demonstrative aspects, the second diode-connected transistor may include a second diode-connected NMOS transistor, e.g., as described below.[000341] In other aspects, the first diode-connected transistor and / or the second diode- connected transistor may include any other type of transistor, e.g., a PMOS transistor.[000342] In some demonstrative aspects, the first conductive path of the voltage clipper 1002 may include a first transistor, e.g., in addition to the first diode-connected transistor, e.g., as described below.[000343] In some demonstrative aspects, the first diode-connected transistor may be connected between a drain and a gate of the first transistor, e.g., as described below.[000344] In some demonstrative aspects, the second conductive path of the voltage clipper 1002 may include a second transistor, e.g., in addition to the second diode- connected transistor, e.g., as described below.[000345] In some demonstrative aspects, the second diode-connected transistor may be connected between a drain and a gate of the second transistor, e.g., as described below.[000346] In some demonstrative aspects, the first transistor of the first conductive path may include a first NMOS transistor, e.g., as described below.[000347] In some demonstrative aspects, the second transistor of the second conductive path may include a second NMOS transistor, e.g., as described below.[000348] In other aspects, the first transistor and / or the second transistor may include any other type of transistor, e.g., a PMOS transistor.[000349] Reference is made to Fig. 11, which schematically illustrates an LNA 1110, in accordance with some demonstrative aspects. For example, LNA 1010 (Fig. 10) may include one or more elements of LNA 1100, and / or may perform the functionally of LNA 1100.[000350] In some demonstrative aspects, as shown in Fig. 11, LNA 1110 may include an LNA core 1120 configured to provide an amplified LNA-core output signal 1117, for example, by amplifying an LNA-core input signal 1115, e.g., as described below.[000351] In some demonstrative aspects, a frequency of the LNA-core input signal 1115 may be above 40 Gigahertz GHz.[000352] In other aspects, the LNA-core input signal 1115 may have any other frequency.[000353] In some demonstrative aspects, LNA-core input signal 1115 may be in a frequency bandwidth of 76-81 GHz, e.g., as described below.[000354] In other aspects, the LNA-core input signal 1115 may be in any other suitable frequency bandwidth.[000355] In some demonstrative aspects, as shown in Fig. 11, the LNA core 1120 may include an LNA-core input 1112, which may be configured, for example, to receive the LNA-core input signal 1115.[000356] In some demonstrative aspects, as shown in Fig. 11, the LNA core 1120 may include an LNA-core output 1114, which may be configured, for example, to output the amplified LNA-core output signal 1117.[000357] In some demonstrative aspects, as shown in Fig. 11, LNA core 1120 may include a first amplification transistor 1122 and a second amplification transistor 1124, e.g., as described below.[000358] In some demonstrative aspects, LNA 1110 may include one or more voltage clippers connected in parallel to the LNA core 1120, e.g., as described below.[000359] In some demonstrative aspects, as shown in Fig. 11, LNA 1110 may include an input voltage clipper 1130, e.g., as described below.[000360] In some demonstrative aspects, as shown in Fig. 11, LNA 1110 may include an output voltage clipper 1140, e.g., as described below.[000361] In some demonstrative aspects, as shown in Fig. 11, LNA 1110 may include both the output voltage clipper 1140 and the input voltage clipper 1130, e.g., as described below.[000362] In some demonstrative aspects, LNA 1110 may include input voltage clipper 1130, e.g., while the output voltage clipper 1140 may be excluded.[000363] In some demonstrative aspects, LNA 1110 may include output voltage clipper 1140, e.g., while the input voltage clipper 1130 may be excluded.[000364] In some demonstrative aspects, input voltage clipper 1130 and / or output voltage clipper 1140, may be configured to provide a technical solution to limit voltage levels of LNA 1110, e.g., as described below.[000365] In some demonstrative aspects, input voltage clipper 1130 and / or output voltage clipper 1140, may be configured to provide a technical solution to limit a draingate voltage level on one or more NMOS devices of LNA 1110. For example, input voltage clipper 1130 and / or output voltage clipper 1140 may be configured to mitigate and / or obviate high voltage swings of the drain-gate voltage level on the NMOS devices, which may exceed safe values and / or may cause heavy damage to LNA 1110.[000366] In some demonstrative aspects, as shown in Fig. 11, input voltage clipper 1130 may be connected in parallel to the differential LNA-core input 1112 of the LNA core 1120, e.g., as described below.[000367] In some demonstrative aspects, input voltage clipper 1130 may be configured to clip an input-voltage level, which includes a gate voltage, denoted Vg, of the LNA core 1120, for example, according to an input-voltage clipping threshold, e.g., as described below.[000368] In some demonstrative aspects, as shown in Fig. 11, output voltage clipper 1140 may be connected in parallel to the differential LNA-core output 1114 of the LNA core 1120, e.g., as described below.[000369] In some demonstrative aspects, output voltage clipper 1140 may be configured to clip an output- voltage level, which includes a drain voltage, denoted Vd. of the LNA core 1120, for example, according to an output-voltage clipping threshold, e.g., as described below.[000370] In some demonstrative aspects, the input-voltage clipping threshold and / or the output-voltage clipping threshold may be configured based on a drain-gate voltage threshold of a drain-gate voltage level, denoted Vdg. of amplification transistor 1122 and / or amplification transistor 1124, e.g., as described below.[000371] In some demonstrative aspects, the input-voltage clipping threshold and / or the output-voltage clipping threshold may be configured, for example, such that the drain-gate voltage level of amplification transistors 1122 and / or 1124, may be limited to a level of no more than 1.6V, for example, for sustainably any LNA core input signal 1115 having a power level up to at least 8 dBm, for example, e.g., as described below.[000372] In other aspects, the input-voltage clipping threshold and / or the outputvoltage clipping threshold may be configured, for example, such that the drain-gate voltage level of amplification transistors 1122 and / or 1124, may be limited to any other voltage level, for example, lower than 1.6V or higher than 1.6V, and / or with respect to any other range of power levels for LNA core input signal 1115, e.g., less than 8dBm or higher than 8dBm, for example, based on specific implementation constraints.[000373] In some demonstrative aspects, as shown in Fig. 11, the input voltage clipper 1130 may be connected between a pair of differential input terminals of the LNA core 1120, e.g., as described below.[000374] In some demonstrative aspects, as shown in Fig. 11, the input voltage clipper 1130 may be connected between differential input terminals 1132 and 1134 of the LNA core 1120, e.g., as described below.[000375] In some demonstrative aspects, as shown in Fig. 11, the input voltage clipper 1130 may be configured to clip at least part of the LNA-core input voltage level, which is above the input-voltage clipping threshold, e.g., as described below.[000376] In some demonstrative aspects, input voltage clipper 1130 may be configured to clip sustainably an entirety of the input voltage level, which is above the inputvoltage clipping threshold.[000377] In some demonstrative aspects, the input-voltage clipping threshold may be in a range between 0.2V and 0.3V, e.g., as described below.[000378] In some demonstrative aspects, the input-voltage clipping threshold may be in a range between 0.22V and 0.28V, e.g., as described below.[000379] In some demonstrative aspects, the input-voltage clipping threshold may be in a range between 0.24V and 0.26V, e.g., as described below.[000380] For example, the input- voltage clipping threshold may be about 0.25V, e.g., as described below.[000381] In other aspects, any other input- voltage clipping threshold may be implemented. In some demonstrative aspects, as shown in Fig. 11, the output voltage clipper 1140 may be connected between a pair of differential output terminals of the LNA core 1120, e.g., as described below.[000382] In some demonstrative aspects, as shown in Fig. 11, the output voltage clipper 1130 may be connected between differential output terminals 1142 and 1144 of the LNA core 1120, e.g., as described below.[000383] In some demonstrative aspects, as shown in Fig. 11, the output voltage clipper 1130 may be configured to clip at least part of the LNA-core output voltagelevel between differential output terminals 1142 and 1144, which is above the outputvoltage clipping threshold, e.g., as described below.[000384] In some demonstrative aspects, output voltage clipper 1130 may be configured to clip sustainably an entirety of the output voltage level, which is above the output- voltage clipping threshold.[000385] In some demonstrative aspects, the output-voltage clipping threshold may be in a range between 0.5V and 0.7V, e.g., as described below.[000386] In some demonstrative aspects, the output-voltage clipping threshold may be in a range between 0.55V and 0.65V, e.g., as described below.[000387] In some demonstrative aspects, the output-voltage clipping threshold may be in a range between 0.58V and 0.62V, e.g., as described below.[000388] For example, the output-voltage clipping threshold may be about 0.6V, e.g., as described below.[000389] In other aspects, any other output- voltage clipping threshold may be implemented.[000390] In some demonstrative aspects, as shown in Fig. 11, first amplification transistor 1122 and / or second amplification transistor 1124 may include an N-channel Metal Oxide Semiconductor (NMOS) transistor.[000391] In other aspects, first amplification transistor 1122 and / or second amplification transistor 1124 may include any other type of transistor, e.g., a PMOS transistor.[000392] In some demonstrative aspects, as shown in Fig. 11, a source of the first amplification transistor 1122 and a source of the second amplification transistor 1124 may be connected to a common ground, for example, in case of an NMOS implementation, e.g., as described below.[000393] In some demonstrative aspects, as shown in Fig. 11, a gate of the first amplification transistor 1122 may be connected to a first differential input 1132 of the LNA core 1120.[000394] In some demonstrative aspects, as shown in Fig. 11, a gate of the second amplification transistor 1124 may be connected to a second differential input 1134 of the LNA core 1120.[000395] In some demonstrative aspects, as shown in Fig. 11, a drain of the first amplification transistor 1122 may be connected to a first differential output 1142 of the LNA core 1120.[000396] In some demonstrative aspects, as shown in Fig. 11, a drain of the second amplification transistor 1124 may be connected to a second differential output 1144 of the LNA core 1120.[000397] In some demonstrative aspects, as shown in Fig. 11, LNA core 1120 may implement a mmWave LNA Complementary MOS (CMOS) stage topology, for example, with neutralization cross-coupled capacitors, for example, to support expected waveforms under strong input signal conditions, e.g., as described below.[000398] In other aspects, LNA 1110 may implement any other suitable LNA topology.[000399] In some demonstrative aspects, as shown in Fig. 11, LNA 1110 may include first and second cross-coupled capacitance neutralization paths 1125, e.g., as described below.[000400] In some demonstrative aspects, as shown in Fig. 11, a first capacitance neutralization path 1129 of the first and second cross-coupled capacitance neutralization paths 1125 may be connected in parallel between the first differential input 1132 and the second differential output 1144, e.g., as described below.[000401] In some demonstrative aspects, as shown in Fig. 11, a second capacitance neutralization path 1127 of the first and second cross-coupled capacitance neutralization paths 1125 may be connected in parallel between the second differential input 1134 and the first differential output 1142, e.g., as described below.[000402] In some demonstrative aspects, as shown in Fig. 11, the first and second cross-coupled capacitance neutralization paths 1125 may be implemented utilizing capacitors, e.g., a first capacitor for the first capacitance neutralization path 1129, and / or a second capacitor for the second capacitance neutralization path 1127.[000403] In some demonstrative aspects, the first and second cross-coupled capacitance neutralization paths 1125 may be implemented utilizing NMOS transistors, e.g., a first NMOS transistor for the first capacitance neutralization path 1129, and / or a second NMOS transistor for the second capacitance neutralization path 1127. For example, the NMOS transistor of first capacitance neutralization path 1129 may have a configuration similar to a configuration of amplification transistor 1124, and / or the NMOS transistor of first capacitance neutralization path 1127 may have a configuration similar to a configuration of amplification transistor 1122.[000404] In other aspects, the first and second cross-coupled capacitance neutralization paths 1125 may be implemented utilizing PMOS transistors, e.g., a first PMOS transistor for the first capacitance neutralization path 1129, and / or a second PMOS transistor for the second capacitance neutralization path 1127.[000405] In some demonstrative aspects, input voltage clipper 1130 may be configured to clip at least part of the input voltage level and / or output voltage clipper 1140 may be configured to clip at least part of the output voltage level, for example, such that a draingate voltage level of amplification transistors 1122 and / or 1124 may be limited to a level of no more than 1.6V, for example, for substantially any LNA core input signal 1115 having a power level up to at least 8 dBm, e.g., as described below.[000406] In other aspects, input voltage clipper 1130 may be configured to clip at least part of the input voltage level and / or output voltage clipper 1140 may be configured to clip at least part of the output voltage level, for example, such that a drain-gate voltage level of amplification transistors 1122 and / or 1124, may be limited to any other voltage level, e.g., lower than 1.6V or higher than 1.6V, and / or with respect to any other range of power levels for LNA core input signal 1115, e.g., less than 8dBm or higher than 8dBm, for example, based on specific implementation constraints.[000407] In some demonstrative aspects, input voltage clipper 1130 may be configured to clip at least part of the input voltage level and / or output voltage clipper 1140 may be configured to clip at least part of the output voltage level, for example, such that an output voltage level of the LNA core 1120 may be limited to a level of no more than 1.1V, for example, for substantially any LNA core input signal 1115 having a power level up to at least 8 dBm, e.g., as described below.[000408] In other aspects, input voltage clipper 1130 may be configured to clip at least part of the input voltage level and / or output voltage clipper 1140 may be configured to clip at least part of the output voltage level, for example, such that an output voltage level of the LNA core 1120 may be limited to any other voltage level, e.g., lower than 1.1V or higher than 1.1V, and / or with respect to any other range of power levels for LNA core input signal 1115, e.g., less than 8dBm or higher than 8dBm, for example, based on specific implementation constraints.[000409] In some demonstrative aspects, as shown in Fig. 11, the input voltage clipper 1130 may include a first diode, denoted DI, and a second diode, denoted D2, which are connected in an anti-parallel connection.[000410] In some demonstrative aspects, as shown in Fig. 11, the output voltage clipper 1140 may include a first diode, denoted D3, and a second diode, denoted D4, which are connected in an anti-parallel connection.[000411] In some demonstrative aspects, as shown in Fig. 11, the input voltage clipper1130 may include a first conductive path 1131 and a second conductive path 1133, which may be connected in parallel between the pair of differential terminals 1132 and 1134 of the LNA core 1120, e.g., as described below.[000412] In some demonstrative aspects, as shown in Fig. 11, the first conductive path1131 may be configured to conduct in a first direction from the first differential terminal1132 to the second differential terminal 1134, e.g., as described below.[000413] In some demonstrative aspects, as shown in Fig. 11, the second conductive path 1133 may be configured to conduct in a second direction from the second differential terminal 1134 to the first differential terminal 1132, e.g., as described below.[000414] In some demonstrative aspects, as shown in Fig. 11, conductive path 1131 may include the diode DI, and / or conductive path 1133 may include the diode D2.[000415] In some demonstrative aspects, as shown in Fig. 11, the output voltage clipper 1140 may include a first conductive path 1141 and a second conductive path 1143, which may be connected in parallel between the pair of differential terminals 1142 and 1144 of the LNA core 1120, e.g., as described below.[000416] In some demonstrative aspects, as shown in Fig. 11, the first conductive path1141 may be configured to conduct in a first direction from the first differential terminal1142 to the second differential terminal 1144, e.g., as described below.[000417] In some demonstrative aspects, as shown in Fig. 11, the second conductive path 1143 may be configured to conduct in a second direction from the second differential terminal 1144 to the first differential terminal 1142, e.g., as described below.[000418] In some demonstrative aspects, as shown in Fig. 11, conductive path 1141 may include the diode D3, and / or conductive path 1143 may include the diode D4.[000419] In some demonstrative aspects, input voltage clipper 1130 and / or output voltage clipper 1140 may be implemented utilizing conductive paths including diodes, e.g., as described above.[000420] In some demonstrative aspects, as shown in Fig. 11, input voltage clipper 1130 may include a pair of diodes, e.g., the diodes DI and D2, which may be connected symmetrically, and / or output voltage clipper 1140 may include a pair of diodes, e.g., the diodes D3 and D4, which may be connected symmetrically, e.g., according to a differential structure of LNA core 1120.[000421] In some demonstrative aspects, as shown in Fig. 11, connecting the pair of diodes DI and D2 in parallel to the differential input 1112, and / or connecting the pair of diodes D3 and D4 in parallel to the differential output 1114 of the LNA core 1120 may be an ideal solution in some use cases and / or implementations, e.g., theoretically.[000422] For example, in some use cases and / or implementations, the pair of diodes DI and D2 and / or the pair of diodes D3 and D4 may cut-off a strong signal, e.g., a strong interferer signal, for example, while weaker signals may not be substantially affected, for example, in an ideal solution.[000423] In some demonstrative aspects, a pair of diodes of a voltage clipper, e.g., the pair of diodes DI and D2 and / or the pair of diodes D3 and D4, may be implemented by a pair of NMOS devices, e.g., a pair of diode-connected NMOS devices. For example, a voltage clipper may be implemented using a first diode-connected NMOS device on a first conductive path of the voltage clipper, and / or a second diode-connected NMOS device on a second conductive path of the voltage clipper, e.g., as described below.[000424] In some demonstrative embodiments, the pair of NMOS devices, e.g., the pair of diode-connected NMOS devices may have a configuration similar to the configuration of amplification transistors in the LNA core 1120, e.g., amplification transistors 1124 and / or 1122, for example, to provide improved high frequency modelling.[000425] In other aspects, a pair of diodes of a voltage clipper, e.g., the pair of diodes DI and D2 and / or the pair of diodes D3 and D4, may be implemented by a pair of PMOS devices, e.g., a pair of diode-connected PMOS devices. For example, a voltage clipper may be implemented using a first diode-connected PMOS device on a first conductive path of the voltage clipper, and / or a second diode-connected PMOS device on a second conductive path of the voltage clipper.[000426] In some demonstrative aspects, input voltage clipper 1130 and / or output voltage clipper 1140 may be implemented utilizing conductive paths including diode- connected transistors, for example, instead of one or more of the diodes, e.g., as described above.[000427] In some demonstrative aspects, conductive path 1131 may include a first diode-connected transistor, e.g., instead of the diode DI, e.g., as described below.[000428] In some demonstrative aspects, conductive path 1133 may include a second diode-connected transistor, e.g., instead of the diode D2, e.g., as described below.[000429] In some demonstrative aspects, conductive path 1141 may include a third diode-connected transistor, e.g., instead of the diode D3, e.g., as described below.[000430] In some demonstrative aspects, conductive path 1143 may include a fourth diode-connected transistor, e.g., instead of the diode D4, e.g., as described below.[000431] In some demonstrative aspects, the first diode-connected transistor, the second diode-connected transistor, the third diode-connected transistor and / or the fourth diode-connected transistor may include an NMOS transistor, e.g., as described below.[000432] In other aspects, the first diode-connected transistor, the second diode- connected transistor, the third diode-connected transistor and / or the fourth diode- connected transistor may include any other type of transistor, e.g., a PMOS transistor.[000433] Reference is made to Fig. 12A, which schematically illustrates a conductive path 1233, which may be implemented as part of a voltage clipper, in accordance with some demonstrative embodiments.[000434] In some demonstrative aspects, as shown in Fig. 12A, conductive path 1233 may include a diode-connected NMOS transistor 1239. In other aspects, conductive path 1233 may include a diode-connected PMOS transistor.[000435] In some demonstrative aspects, as shown in Fig. 12A, conductive path 1233 may be implemented by diode-connected NMOS transistor 1239, for example, instead of a conductive path 1235 implemented by a diode.[000436] In some demonstrative aspects, one or more pairs of conductive paths of a voltage clipper, e.g., voltage clipper 1020 (Fig. 10), may be implemented by conductive path 1233.[000437] In some demonstrative aspects, a first conductive path of a pair of conductive paths of the voltage clipper may include a first conductive path 1233 including a first diode-connected NMOS transistor 1239, and / or a second conductive path of the pair of conductive paths may include a second conductive path 1233 including a second diode- connected NMOS transistor 1239. In other aspects, diode-connected PMOS transistors may be implemented.[000438] In one example, a pair of conductive paths of input voltage clipper 1130 (Fig. 11) may be implemented using conductive path 1233, e.g., instead of conductive path 1235. For example, conductive path 1131 (Fig. 11) may be implemented by a first conductive path 1233 including a first diode-connected transistor 1239, e.g., instead of the diode DI; and / or conductive path 1133 (Fig. 11) may be implemented by a second conductive path 1233 including a second diode-connected transistor 1239, e.g., instead of the diode D2, e.g., as described above.[000439] In one example, a pair of conductive paths of output voltage clipper 1140 (Fig. 11) may be implemented using conductive path 1233, e.g., instead of conductive path 1235. For example, conductive path 1141 (Fig. 11) may be implemented by a third conductive path 1233 including a third diode-connected transistor 1239, e.g., instead of the diode D4; and / or conductive path 1143 (Fig. 11) may be implemented by a fourthconductive path 1233 including a fourth diode-connected transistor 1239, e.g., instead of the diode D4, e.g., as described above.[000440] In one example, in some use cases and / or implementations, e.g., practically in a CMOS process, some NMOS devices may suffer from parasitic leakage. Accordingly, some weaker signals may be slightly attenuated.[000441] In some demonstrative aspects, a pair of diodes of a voltage clipper, e.g., the pair of diodes DI and D2 and / or the pair of diodes D3 and D4, ay be implemented by cascaded pairs of NMOS devices. For example, a first cascaded pair of NMOS devices may be implemented for a first conductive path of the voltage clipper, and / or a second cascaded pair of NMOS devices may be implemented for a second conductive path of the voltage clipper, e.g., as described below.[000442] In other aspects, a pair of diodes of a voltage clipper, e.g., the pair of diodes DI and D2 and / or the pair of diodes D3 and D4, _may be implemented by cascaded pairs of PMOS devices.[000443] In some demonstrative aspects, the voltage clipper may implement the pair cascaded pairs of NMOS devices, for example, to provide a technical solution to support decreased parasitic effects, e.g., parasitic leakages.[000444] Reference is made to Fig. 12B, which schematically illustrates a conductive path 1243, which may be implemented as part of a voltage clipper, in accordance with some demonstrative embodiments.[000445] In some demonstrative aspects, as shown in Fig. 12B, conductive path 1243 may include a diode-connected transistor 1244, e.g., a diode-connected NMOS transistor 1244.[000446] In some demonstrative aspects, as shown in Fig. 12B, conductive path 1243 may include a transistor 1242, e.g., an NMOS transistor 1242, which may be connected to the diode-connected transistor 1244.[000447] In some demonstrative aspects, as shown in Fig. 12B, the diode-connected NMOS transistor 1244 may be cascaded to NMOS transistor 1242, e.g., to form a cascaded pair of NMOS transistors.[000448] In some demonstrative aspects, as shown in Fig. 12B, the NMOS diode- connected transistor 1244 may be connected between a drain and a gate of the NMOS transistor 1242.[000449] In some demonstrative aspects, the diode-connected transistor 1244 and / or the transistor 1242 may include NMOS devices.[000450] In other aspects, the diode-connected transistor 1244 and / or the transistor 1242 may include any other type of transistor, e.g., a PMOS transistor.[000451] In some demonstrative aspects, as shown in Fig. 12B, conductive path 1243 may be implemented by a cascaded pair of transistors e.g., NMOS or PMOS devices, for example, instead of the conductive path 1235 implemented by a diode and / or instead of conductive path 1233 implemented by a single transistor, e.g., a single NMOS transistor or a single PMOS transistor, e.g., NMOS diode-connected transistor 1239.[000452] In some demonstrative aspects, one or more pairs of conductive paths of a voltage clipper, e.g., voltage clipper 1020 (Fig. 10), may be implemented by conductive path 1243.[000453] In some demonstrative aspects, a first conductive path of a pair of conductive paths of the voltage clipper may include a first conductive path 1243 including a first diode-connected NMOS transistor 1244 (or PMOS transistor) cascaded to a first NMOS transistor 1242 (or PMOS transistor), and / or a second conductive path of the pair of conductive paths may include a second conductive path 1243 including a second diode- connected NMOS transistor 1244 (or PMOS transistor) cascaded to a second NMOS transistor 1242 (or PMOS transistor).[000454] In one example, a pair of conductive paths of input voltage clipper 1130 (Fig. 11) may be implemented using conductive path 1243, e.g., instead of conductive path 1235. For example, conductive path 1131 (Fig. 11) may be implemented by a first conductive path 1243 including a first diode-connected NMOS transistor 1244 (or PMOS transistor) cascaded to a first NMOS transistor 1242 (or PMOS transistor), e.g., instead of the diode DI; and / or conductive path 1133 (Fig. 11) may be implemented by a second conductive path 1243 including a second diode-connected NMOS transistor 1244 (or PMOS transistor) cascaded to a second NMOS transistor 1242 (or PMOS transistor), e.g., instead of the diode D2, e.g., as described above.[000455] In one example, a pair of conductive paths of output voltage clipper 1140 (Fig. 11) may be implemented using conductive path 1243. For example, conductive path 1141 (Fig. 11) may be implemented by a third conductive path 1243 including a third diode-connected NMOS transistor 1244 (or PMOS transistor) cascaded to a third NMOS transistor 1242 (or PMOS transistor), e.g., instead of the diode D3; and / or conductive path 1143 (Fig. 11) may be implemented by a fourth conductive path 1243 including a fourth diode-connected NMOS transistor 1244 (or PMOS transistor) cascaded to a fourth NMOS transistor 1242 (or PMOS transistor), e.g., instead of the diode D4, e.g., as described above.[000456] Reference is made to Fig. 13, which schematically illustrates a graph 1300 depicting current-voltage (W) curves of first and second conductive paths, in accordance with some demonstrative aspects.[000457] In one example, the graph 1300 depicts the current- voltage W curves of an LNA input signal at a frequency of 80 GHz.[000458] In some demonstrative aspects, as shown in Fig. 13, a first I / V curve 1314 depicts an I / V curve of a conductive path including a diode-connected transistor.[000459] In one example, I / V curve 1314 may depict the I / V curve of conductive path 1223 (Fig. 12A), e.g., including the NMOS diode-connected transistor 1239 (Fig. 12A).[000460] In some demonstrative aspects, as shown in Fig. 13, a second I / V curve 1312 depicts an I / V curve of a conductive path including a cascaded pair of NMOS devices, e.g., an NMOS diode-connected transistor cascaded to an NMOS transistor.[000461] In one example, I / V curve 1312 may depict the I / V curve of conductive path 1243 (Fig. 12B) including the NMOS diode-connected transistor 1244 (Fig. 12B) and the NMOS transistor 1242 (Fig. 12B).[000462] In some demonstrative aspects, as shown in Fig. 13, the I / V curve 1312 of the conductive path including the cascaded pair of NMOS devices may provide improved results, for example, as shown by the step-like shape of the I / V curve 1312 at lower voltages.[000463] In some demonstrative aspects, an LNA including a voltage clipper implementing conductive path 1243 (Fig. 12B) may be configured to provide a technical solution to prolong an expected lifetime of an LNA, for example, underlOdBm interferer conditions, for example, by 10,000 times, for example, compared to an LN A excluding a voltage clipper.[000464] Reference is made to Fig. 14, which schematically illustrates a graph 1400 depicting curves representing a plurality of LNA core voltage levels versus an input power level of an input signal of an LNA core, in accordance with some demonstrative aspects.[000465] In some demonstrative aspects, as shown in Fig. 14, a first curve 1414 depicts an output-voltage level of an LNA core of an LNA including a voltage clipper (“a voltage-clipped LNA”) versus the input power level of the LNA core input signal.[000466] In some demonstrative aspects, as shown in Fig. 14, a second curve 1412 depicts an output-voltage level of an LNA core of an LNA excluding a voltage clipper (“a non-voltage-clipped LNA”) versus the input power level of the LNA core input signal.[000467] In some demonstrative aspects, as shown in Fig. 14, a third curve 1424 depicts a drain-gate voltage level of one or more amplification transistors of the LNA core of the voltage-clipped LNA versus the input power level of the LNA core input signal.[000468] In some demonstrative aspects, as shown in Fig. 14, a fourth curve 1422 depicts a drain-gate voltage level of one or more amplification transistors of the LNA core of the non-voltage-clipped LNA versus the input power level of the LNA core input signal.[000469] In some demonstrative aspects, as shown by curve 1424, the voltage-clipped LNA may limit the drain-gate voltage level of the one or more amplification transistors of the LNA core, e.g., LNA core 1120 (Fig. 11), to a level of no more than about 1.6V for substantially any LNA core input signal having a power level up to at least 8dBm, e.g., compared to the non-voltage-clipped LNA, (curve 1422) in which the drain-gate voltage level exceeds the level of 1.6V for LNA core input signals having a power level well below 8dBm.[000470] In some demonstrative aspects, as shown by curve 1414, the voltage-clipped LNA may limit the output voltage level of the LNA core, e.g., LNA core 1120 (Fig. 11), to a voltage level of no more than about 1.1V for substantially any LNA core inputsignal having a power level up to at least 8dBm, e.g., compared to the non-voltageclipped LNA, (curve 1412) in which the output voltage level exceeds the level of 1.1 V for LNA core input signals having a power level well below 8dBm.[000471] Reference is made to Fig. 15, which schematically illustrates a method of amplifier voltage clipping, in accordance with some demonstrative aspects. For example, one or more of the operations of the method of Fig. 15 may be performed by a radar system, e.g., radar system 900 (Fig. 9); a radar device, e.g., radar device 800 (Fig. 8); an Rx chain, e.g., Rx chain 1013 (Fig. 10); and / or an LNA, e.g., LNA 1010 (Fig. 10) and / or LNA 1110 (Fig. 11).[000472] As indicated at block 1502, the method may include clipping by a voltage clipper of an LNA at least part of a voltage level, which is above a clipping voltage threshold, of a voltage between a first differential terminal and a second differential terminal of a pair of differential terminals of an LNA core of the LNA. For example, the voltage clipper may be connected in parallel to the LNA core between the pair of differential terminals.[000473] In one example, voltage clipper 1002 (Fig. 10) may be configured to clip the at least part of the voltage level, which is above the clipping voltage threshold, of the voltage between the first differential terminal and the second differential terminal of the pair of differential terminals of the LNA core 1020 (Fig. 10), e.g., as described above.[000474] In another example, input voltage clipper 1130 (Fig. 11) may be configured to clip the at least part of the LNA-core input voltage level, which is above the inputclipping voltage threshold, of the voltage between the pair of input differential terminals 1132 and 1134 (Fig. 11), e.g., as described above.[000475] In another example, output voltage clipper 1140 (Fig. 11) may be configured to clip the at least part of the LNA-core output voltage level, which is above the outputvoltage clipping threshold, of the voltage between the pair of output differential terminals 1142 and 1144 (Fig. 11), e.g., as described above.[000476] As indicated at block 1504, the method may include providing by the LNA core of the LNA an amplified LNA-core output signal by amplifying an LNA-core input signal. For example, LNA core 1020 (Fig. 10) may provide the amplified LNA-coreoutput signal 1017 (Fig. 10), for example, by amplifying the LNA-core input signal 1015 (Fig. 10), e.g., as described above.[000477] Reference is made to Fig. 16, which schematically illustrates a product of manufacture 1600, in accordance with some demonstrative aspects. Product 1600 may include one or more tangible computer-readable (“machine -readable”) non-transitory storage media 1602, which may include computer-executable instructions, e.g., implemented by logic 1604, operable to, when executed by at least one computer processor, enable the at least one computer processor to implement one or more operations and / or functionalities described with reference to any of the Figs. 1-15, and / or one or more operations described herein. The phrases “non-transitory machine- readable medium” and “computer-readable non-transitory storage media” may be directed to include all machine and / or computer readable media, with the sole exception being a transitory propagating signal.[000478] In some demonstrative aspects, product 1600 and / or machine-readable storage media 1602 may include one or more types of computer-readable storage media capable of storing data, including volatile memory, non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and the like. For example, machine-readable storage media 1602 may include, RAM, DRAM, Double-Data-Rate DRAM (DDR-DRAM), SDRAM, static RAM (SRAM), ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory (e.g., NOR or NAND flash memory), content addressable memory (CAM), polymer memory, phase-change memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, a disk, a hard drive, and the like. The computer-readable storage media may include any suitable media involved with downloading or transferring a computer program from a remote computer to a requesting computer carried by data signals embodied in a carrier wave or other propagation medium through a communication link, e.g., a modem, radio or network connection.[000479] In some demonstrative aspects, logic 1604 may include instructions, data, and / or code, which, if executed by a machine, may cause the machine to perform a method, process and / or operations as described herein. The machine may include, for example, any suitable processing platform, computing platform, computing device,processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware, software, firmware, and the like.[000480] In some demonstrative aspects, logic 1604 may include, or may be implemented as, software, a software module, an application, a program, a subroutine, instructions, an instruction set, computing code, words, values, symbols, and the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a processor to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language, machine code, and the like.EXAMPLES[000481] The following examples pertain to further aspects.[000482] Example 1 includes an apparatus comprising a Low Noise Amplifier (LNA) comprising an LNA core configured to provide an amplified LNA-core output signal by amplifying an LNA-core input signal; and a voltage clipper connected in parallel to the LNA core between a pair of differential terminals of the LNA core, wherein the voltage clipper is configured to clip at least part of a voltage level, which is above a clipping voltage threshold, of a voltage between a first differential terminal and a second differential terminal of the pair of differential terminals.[000483] Example 2 includes the subject matter of Example 1, and optionally, wherein the voltage clipper comprises an input voltage clipper connected between a pair of differential input terminals of the LNA core, wherein the voltage clipper is configured to clip at least part of an LNA-core input voltage level, which is above an input-voltage clipping threshold.[000484] Example 3 includes the subject matter of Example 2, and optionally, wherein the input-voltage clipping threshold is in a range between 0.2 Volt (V) and 0.3V.[000485] Example 4 includes the subject matter of Example 2 or 3, and optionally, wherein the input-voltage clipping threshold is in a range between 0.22 Volt (V) and 0.28V.[000486] Example 5 includes the subject matter of any one of Example 2-4, and optionally, wherein the input- voltage clipping threshold is in a range between 0.24 Volt (V) and 0.26V.[000487] Example 6 includes the subject matter of any one of Examples 1-5, and optionally, wherein the voltage clipper comprises an output voltage clipper connected between a pair of differential output terminals of the LNA core, wherein the voltage clipper is configured to clip at least part of an LNA-core output voltage level, which is above an output-voltage clipping threshold.[000488] Example 7 includes the subject matter of Example 6, and optionally, wherein the output- voltage clipping threshold is in a range between 0.5 Volt (V) and 0.7 V.[000489] Example 8 includes the subject matter of Example 6 or 7, and optionally, wherein the output-voltage clipping threshold is in a range between 0.55 Volt (V) and 0.65V.[000490] Example 9 includes the subject matter of any one of Example 6-8, and optionally, wherein the output-voltage clipping threshold is in a range between 0.58 Volt (V) and 0.62V.[000491] Example 10 includes the subject matter of any one of Examples 1-9, and optionally, comprising an input voltage clipper connected in parallel to a differential LNA-core input of the LNA core, the input voltage clipper is configured to clip an input-voltage level of the LNA core according to an input-voltage clipping threshold; and an output voltage clipper connected in parallel to a differential LNA-core output of the LNA core, the output voltage clipper is configured to clip an output-voltage level of the LNA core according to an output-voltage clipping threshold.[000492] Example 11 includes the subject matter of Example 10, and optionally, wherein the input-voltage clipping threshold and the output-voltage clipping threshold are configured based on a drain-gate voltage threshold of a drain-gate voltage level of one or more amplification transistors of the LNA core.[000493] Example 12 includes the subject matter of Example 10 or 11, and optionally, wherein the input-voltage clipping threshold and the output-voltage clipping threshold are configured such that a drain-gate voltage level of one or more amplification transistors of the LNA core is to be limited to a level of no more than 1.6 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).[000494] Example 13 includes the subject matter of any one of Examples 1-12, and optionally, wherein the voltage clipper is configured to clip sustainably an entirety of the voltage level, which is above the voltage clipping threshold.[000495] Example 14 includes the subject matter of any one of Examples 1-13, and optionally, wherein the voltage clipper comprises a first conductive path and a second conductive path connected in parallel between the pair of differential terminals of the LNA core, the first conductive path is configured to conduct in a first direction from the first differential terminal to the second differential terminal, and the second conductive path is configured to conduct in a second direction from the second differential terminal to the first differential terminal.[000496] Example 15 includes the subject matter of Example 14, and optionally, wherein the first conductive path comprises a first diode, and the second conductive path comprises a second diode.[000497] Example 16 includes the subject matter of Example 15, and optionally, wherein the first conductive path comprises a first diode-connected transistor, and the second conductive path comprises a second diode-connected transistor.[000498] Example 17 includes the subject matter of Example 16, and optionally, wherein the first diode-connected transistor comprises a first diode-connected N- channel Metal Oxide Semiconductor (NMOS) transistor, and the second diode- connected transistor comprises a second diode-connected NMOS transistor.[000499] Example 18 includes the subject matter of Example 16, and optionally, wherein the first diode-connected transistor comprises a first diode-connected P- Channel Metal- Oxide- Semiconductor (PMOS) transistor, and the second diode- connected transistor comprises a second diode-connected PMOS transistor.[000500] Example 19 includes the subject matter of any one of Examples 16-18, and optionally, wherein the first conductive path comprises a first transistor, and the second conductive path comprises a second transistor, wherein the first diode-connected transistor is connected between a drain and a gate of the first transistor, wherein the second diode-connected transistor is connected between a drain and a gate of the second transistor.[000501] Example 20 includes the subject matter of Example 19, and optionally, wherein the first transistor comprises a first NMOS transistor, and the second transistor comprises a second NMOS transistor.[000502] Example 21 includes the subject matter of Example 19, and optionally, wherein the first transistor comprises a first PMOS transistor, and the second transistor comprises a second PMOS transistor.[000503] Example 22 includes the subject matter of any one of Examples 1-21, and optionally, wherein the voltage clipper comprises a first diode and a second diode, which are connected in an anti-parallel connection.[000504] Example 23 includes the subject matter of any one of Examples 1-22, and optionally, wherein the voltage clipper is configured to clip the at least part of the voltage level, which is above the clipping voltage threshold, such that a drain-gate voltage level of one or more amplification transistors of the LNA core is to be limited to a level of no more than 1.6 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).[000505] Example 24 includes the subject matter of any one of Examples 1-23, and optionally, wherein the clipping voltage threshold is configured such that a drain-gate voltage level of one or more amplification transistors of the LNA core is to be limited to a level of no more than 1.6 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).[000506] Example 25 includes the subject matter of any one of Examples 1-24, and optionally, wherein the voltage clipper is configured to clip the at least part of the voltage level, which is above the clipping voltage threshold, such that an output voltage level of the LNA core is to be limited to a level of no more than 1.1 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).[000507] Example 26 includes the subject matter of any one of Examples 1-25, and optionally, wherein the clipping voltage threshold is configured such that an output voltage level of the LNA core is to be limited to a level of no more than 1.1 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).[000508] Example 27 includes the subject matter of any one of Examples 1-26, and optionally, wherein the voltage clipping threshold is no more than 0.7 Volt (V).[000509] Example 28 includes the subject matter of any one of Examples 1-27, and optionally, wherein the voltage clipping threshold is no more than 0.3 Volt (V).[000510] Example 29 includes the subject matter of any one of Examples 1-28, and optionally, wherein a frequency of the LNA-core input signal is above 40 (GHz).[000511] Example 30 includes the subject matter of any one of Examples 1-29, and optionally, wherein the LNA-core input signal is in a frequency bandwidth of 76-81 Gigahertz (GHz).[000512] Example 31 includes the subject matter of any one of Examples 1-30, and optionally, wherein the LNA core comprises a first amplification transistor and a second amplification transistor, wherein a source of the first amplification transistor and a source of the second amplification transistor are connected to a common ground, a gate of the first amplification transistor is connected to a first differential input of the LNA core, a gate of the second amplification transistor is connected to a second differential input of the LNA core, a drain of the first amplification transistor is connected to a first differential output of the LNA core, and a drain of the second amplification transistor is connected to a second differential output of the LNA core.[000513] Example 32 includes the subject matter of Example 31, and optionally, wherein the LNA core comprises first and second cross-coupled capacitance neutralization paths, wherein the first capacitance neutralization path is connected in parallel between the first differential input and the second differential output, and the second capacitance neutralization path is connected in parallel between the second differential input and the first differential output.[000514] Example 33 includes the subject matter of any one of Examples 1-32, and optionally, wherein the LNA core comprises an LNA-core input to receive the LNA-core input signal; and an LNA-core output to output the amplified LNA-core output signal.[000515] Example 34 includes a device comprising a Radio Frequency (RF) chain to process RF signals, the RF chain comprising the Eow Noise Amplifier (ENA) of any of Examples 1-33.[000516] Example 35 includes the subject matter of any one of Examples 1-34, and optionally, comprising a radar device, the radar device comprising a plurality of Transmit (Tx) antennas connected to a plurality of Tx chains, a plurality of Rx antennas connected to a plurality of Rx chains, and a radar processor to generate radar information based on radar Rx signals processed by the Rx chains, wherein a radar Rx chain comprises the LNA.[000517] Example 36 includes a radar device comprising the apparatus of any of Examples 1-35.[000518] Example 37 includes a radar system comprising the apparatus of any of Examples 1-35.[000519] Example 38 includes a vehicle comprising the apparatus of any of Examples 1-35.[000520] Example 39 includes an apparatus comprising means for performing any of the described operations of any of Examples 1-35.[000521] Example 40 includes a machine-readable medium that stores instructions for execution by a processor to perform any of the described operations of any of Examples 1-35.[000522] Example 41 comprises a product comprising one or more tangible computer- readable non-transitory storage media comprising computer-executable instructions operable to, when executed by at least one processor, enable the at least one processor to cause a device to perform any of the described operations of any of Examples 1-35.[000523] Example 42 includes an apparatus comprising a memory; and processing circuitry configured to perform any of the described operations of any of Examples 1- 35.[000524] Example 43 includes a method including any of the described operations of any of Examples 1-35.[000525] Functions, operations, components and / or features described herein with reference to one or more aspects, may be combined with, or may be utilized in combination with, one or more other functions, operations, components and / or features described herein with reference to one or more other aspects, or vice versa.[000526] While certain features have been illustrated and described herein, many modifications, substitutions, changes, and equivalents may occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the disclosure.

Claims

CLAIMSWhat is claimed is:

1. An apparatus comprising: a Low Noise Amplifier (LNA) comprising: an LNA core configured to provide an amplified LNA-core output signal by amplifying an LNA-core input signal; and a voltage clipper connected in parallel to the LNA core between a pair of differential terminals of the LNA core, wherein the voltage clipper is configured to clip at least part of a voltage level, which is above a clipping voltage threshold, of a voltage between a first differential terminal and a second differential terminal of the pair of differential terminals.

2. The apparatus of claim 1, wherein the voltage clipper comprises an input voltage clipper connected between a pair of differential input terminals of the LNA core, wherein the voltage clipper is configured to clip at least part of an LNA-core input voltage level, which is above an input- voltage clipping threshold.

3. The apparatus of claim 2, wherein the input-voltage clipping threshold is in a range between 0.2 Volt (V) and 0.3V.

4. The apparatus of claim 2, wherein the input-voltage clipping threshold is in a range between 0.22 Volt (V) and 0.28V.

5. The apparatus of claim 2, wherein the input-voltage clipping threshold is in a range between 0.24 Volt (V) and 0.26V.

6. The apparatus of claim 1, wherein the voltage clipper comprises an output voltage clipper connected between a pair of differential output terminals of the LNA core, wherein the voltage clipper is configured to clip at least part of an LNA-core output voltage level, which is above an output- voltage clipping threshold.

7. The apparatus of claim 6, wherein the output-voltage clipping threshold is in a range between 0.5 Volt (V) and 0.7V.

8. The apparatus of claim 6, wherein the output-voltage clipping threshold is in a range between 0.55 Volt (V) and 0.65V.

9. The apparatus of claim 6, wherein the output-voltage clipping threshold is in a range between 0.58 Volt (V) and 0.62V.

10. The apparatus claim 1 comprising: an input voltage clipper connected in parallel to a differential LNA-core input of the LNA core, the input voltage clipper is configured to clip an input-voltage level of the LNA core according to an input-voltage clipping threshold; and an output voltage clipper connected in parallel to a differential LNA-core output of the LNA core, the output voltage clipper is configured to clip an outputvoltage level of the LNA core according to an output-voltage clipping threshold.

11. The apparatus of claim 10, wherein the input-voltage clipping threshold and the output-voltage clipping threshold are configured based on a drain-gate voltage threshold of a drain-gate voltage level of one or more amplification transistors of the LNA core.

12. The apparatus of claim 10, wherein the input-voltage clipping threshold and the output- voltage clipping threshold are configured such that a drain-gate voltage level of one or more amplification transistors of the LNA core is to be limited to a level of no more than 1.6 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).

13. The apparatus of claim 1, wherein the voltage clipper is configured to clip sustainably an entirety of the voltage level, which is above the voltage clipping threshold.

14. The apparatus of any one of claims 1-13, wherein the voltage clipper comprises a first conductive path and a second conductive path connected in parallel between the pair of differential terminals of the LNA core, the first conductive path is configured to conduct in a first direction from the first differential terminal to the second differential terminal, and the second conductive path is configured to conduct in a second direction from the second differential terminal to the first differential terminal.

15. The apparatus of claim 14, wherein the first conductive path comprises a first diode, and the second conductive path comprises a second diode.

16. The apparatus of claim 15, wherein the first conductive path comprises a first diode-connected transistor, and the second conductive path comprises a second diode- connected transistor.

17. The apparatus of claim 16, wherein the first diode-connected transistor comprises a first diode-connected N-channel Metal Oxide Semiconductor (NMOS) transistor, and the second diode-connected transistor comprises a second diode- connected NMOS transistor.

18. The apparatus of claim 16, wherein the first diode-connected transistor comprises a first diode-connected P-channel Metal Oxide Semiconductor (PMOS) transistor, and the second diode-connected transistor comprises a second diode- connected PMOS transistor.

19. The apparatus of claim 16, wherein the first conductive path comprises a first transistor, and the second conductive path comprises a second transistor, wherein the first diode-connected transistor is connected between a drain and a gate of the first transistor, wherein the second diode-connected transistor is connected between a drain and a gate of the second transistor.

20. The apparatus of claim 19, wherein the first transistor comprises a first N- channel Metal Oxide Semiconductor (NMOS) transistor, and the second transistor comprises a second NMOS transistor.

21. The apparatus of claim 19, wherein the first transistor comprises a first P- channel Metal Oxide Semiconductor (PMOS) transistor, and the second transistor comprises a second PMOS transistor.

22. The apparatus of any one of claims 1-13, wherein the voltage clipper comprises a first diode and a second diode, which are connected in an anti-parallel connection.

23. The apparatus of any one of claims 1-13, wherein the voltage clipper is configured to clip the at least part of the voltage level, which is above the clipping voltage threshold, such that a drain-gate voltage level of one or more amplification transistors of the LNA core is to be limited to a level of no more than 1.6 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).

24. The apparatus of any one of claims 1-13, wherein the clipping voltage threshold is configured such that a drain-gate voltage level of one or more amplification transistors of the LNA core is to be limited to a level of no more than 1.6 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).

25. The apparatus of any one of claims 1-13, wherein the voltage clipper is configured to clip the at least part of the voltage level, which is above the clipping voltage threshold, such that an output voltage level of the LNA core is to be limited to a level of no more than 1.1 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).

26. The apparatus of any one of claims 1-13, wherein the clipping voltage threshold is configured such that an output voltage level of the LNA core is to be limited to a level of no more than 1.1 Volt (V) for any LNA core input signal having a power level up to at least 8 decibel milliwatts (dBm).

27. The apparatus of any one of claims 1-13, wherein the voltage clipping threshold is no more than 0.7 Volt (V).

28. The apparatus of any one of claims 1-13, wherein the voltage clipping threshold is no more than 0.3 Volt (V).

29. The apparatus of any one of claims 1-13, wherein a frequency of the LNA- core input signal is above 40 (GHz).

30. The apparatus of any one of claims 1-13, wherein the LNA-core input signal is in a frequency bandwidth of 76-81 Gigahertz (GHz).

31. The apparatus of any one of claims 1-13, wherein the LNA core comprises a first amplification transistor and a second amplification transistor, wherein a source of the first amplification transistor and a source of the second amplification transistor are connected to a common ground, a gate of the first amplification transistor is connected to a first differential input of the LNA core, a gate of the second amplification transistor is connected to a second differential input of the LNA core, a drain of the first amplification transistor is connected to a first differential output of the LNA core, and a drain of the second amplification transistor is connected to a second differential output of the LNA core.

32. The apparatus of claim 31, wherein the LNA core comprises first and second cross-coupled capacitance neutralization paths, wherein the first capacitance neutralization path is connected in parallel between the first differential input and the second differential output, and the second capacitance neutralization path is connected in parallel between the second differential input and the first differential output.

33. The apparatus of any one of claims 1-13, wherein the LNA core comprises: an LNA-core input to receive the LNA-core input signal; and an LNA-core output to output the amplified LNA-core output signal.

34. The apparatus of any one of claims 1-13 comprising a Radio Frequency (RF) chain to process RF signals, the RF chain comprising the LNA.

35. The apparatus of any one of claims 1-13 comprising a radar device, the radar device comprising a plurality of Transmit (Tx) antennas connected to a plurality of Tx chains, a plurality of Rx antennas connected to a plurality of Rx chains, and a processor to generate radar information based on radar Rx signals processed by the Rx chains, wherein a radar Rx chain of the plurality of Rx antennas comprises the LNA.

36. The apparatus of claim 35 comprising a vehicle, the vehicle comprising the radar device, and a system controller to control one or more systems of the vehicle based on the radar information.

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