Coil device

Abstract

This coil device comprises: a first base film having a first main surface and a second main surface opposite the first main surface; first wiring disposed on the first main surface; and second wiring disposed on the second main surface. The first wiring includes a first coil that is composed of a section of the first-wiring wound in a coil in plan view. The second wiring includes a second coil that is composed of a section of the second-wiring portion wound in a coil in plan view. In a cross-sectional view orthogonal to the direction in which the section of the first wiring line constituting the first coil extends, a value obtained by dividing a positional offset between the section of the first wiring line constituting the first coil and the section of the second wiring line constituting the second coil by 1 / 2 of the pitch of the section of the first wiring line constituting the first coil is 0.06 or more and less than 0.50.

Description

Coil Device

[0001] This application claims priority to Japanese Patent Application No. 2023-182036, filed on October 23, 2023, and incorporates by reference all of the contents of said Japanese application.

[0002] For example, Japanese Patent Laid-Open Publication No. 2021-197408 (Patent Document 1) describes a coil device. The coil device described in Patent Document 1 has a first base film, a second base film, a first wiring, a second wiring, a third wiring, and an adhesive layer. The first base film has a first main surface and a second main surface. The first wiring and the second wiring are arranged on the first main surface and the second main surface, respectively. The first wiring has a first planar coil portion that is wound in a coil shape in a planar view. The second wiring has a second planar coil portion that is wound in a coil shape in a planar view. The second base film has a third main surface. The third main surface faces the first main surface. The third wiring is arranged on the third main surface. The third wiring has a third planar coil portion that is wound in a coil shape in a planar view. The adhesive layer is interposed between the first main surface and the third main surface, and bonds the first base film and the second base film.

[0003] In a cross-sectional view perpendicular to the direction in which the portion of the first wiring constituting the first planar coil section extends, the portion of the first wiring constituting the first planar coil section and the portion of the second wiring constituting the second planar coil section overlap in the thickness direction, and the portion of the first wiring constituting the first planar coil section and the portion of the third wiring constituting the third planar coil section overlap. That is, in a cross-sectional view perpendicular to the direction in which the portion of the first wiring constituting the first planar coil section extends, the amount of misalignment between the portion of the first wiring constituting the first planar coil section and the portion of the second wiring constituting the second planar coil section and the amount of misalignment between the portion of the first wiring constituting the first planar coil section and the portion of the third wiring constituting the third planar coil section are zero.

[0004] Patent Publication No. 2021-197408

[0005] The coil device of the present disclosure includes a first base film having a first main surface and a second main surface opposite the first main surface, a first wiring disposed on the first main surface, and a second wiring disposed on the second main surface. The first wiring has a first coil portion constituted by a portion of the first wiring wound in a coil shape in a plan view. The second wiring has a second coil portion constituted by a portion of the second wiring wound in a coil shape in a plan view. In a cross-sectional view perpendicular to the direction in which the portion of the first wiring constituting the first coil portion extends, a value obtained by dividing the amount of misalignment between the portion of the first wiring constituting the first coil portion and the portion of the second wiring constituting the second coil portion by half the pitch of the portion of the first wiring constituting the first coil portion is equal to or greater than 0.06 and less than 0.50.

[0006] FIG. 1A is a plan view of the coil device 100, omitting the illustration of the adhesive layer 60 and the base film 70. FIG. 1B is a plan view of the coil device 100, viewed from the opposite side of FIG. 1A, omitting the illustration of the adhesive layer 61 and the base film 71. FIG. 2A is a plan view of the coil device 100, omitting the illustration of the adhesive layer 30, the base film 40, the wiring 50, the adhesive layer 60, and the base film 70. FIG. 2B is a plan view of the coil device 100, viewed from the opposite side of FIG. 2A, omitting the illustration of the adhesive layer 31, the base film 41, the wiring 51, the adhesive layer 61, and the base film 71. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1A. FIG. 4A is a plan view of the coil device 200A. FIG. 4B is a plan view of the coil device 200B. FIG. 5 is a manufacturing process diagram of the coil device 100. FIG. 6 is a cross-sectional view illustrating the conductive treatment step S2. FIG. 7 is a cross-sectional view illustrating the resist pattern formation step S3. FIG. 8 is a cross-sectional view illustrating the electroplating step S4. FIG. 9 is a cross-sectional view illustrating the resist pattern removing step S5. FIG. 10 is a cross-sectional view illustrating the etching step S6. FIG. 11 is a cross-sectional view illustrating the base film attaching step S7. FIG. 12 is a cross-sectional view illustrating the conductive treatment step S8. FIG. 13 is a cross-sectional view illustrating the resist pattern forming step S9. FIG. 14 is a cross-sectional view illustrating the electroplating step S10. FIG. 15 is a cross-sectional view illustrating the resist pattern removing step S11. FIG. 16 is a cross-sectional view illustrating the etching step S12. FIG. 17 is a cross-sectional view of a coil device 100 according to a modified example. FIG. 18 is a graph showing simulation results of the temperature rise amount on the main surface 70b when the first misalignment amount is changed. FIG. 19 is a graph showing simulation results showing the relationship between the current value that can be passed through the wiring and the first misalignment amount when the temperature rise on the main surface 70b is 65°C. Fig. 20 is a graph showing the relationship between the thermal stress at the interface between the main surface 71a and the adhesive layer 61 and the value obtained by dividing the first misalignment amount by 1 / 2 the pitch P1 in the simulations of Tables 3 and 4. Fig. 21 is a graph showing the relationship between the temperature rise amount and the value obtained by dividing the first misalignment amount by 1 / 2 the pitch P1 in the simulations of Tables 5 and 6. Fig. 22 is an enlarged cross-sectional view of a coil device 100 according to a modified example.Fig. 23 is an enlarged view of a portion of the cross-sectional view taken along line III-III in Fig. 1A, and is a view for explaining the amount of misalignment. Fig. 24 is a cross-sectional view of the periphery of the first through hole. Fig. 25 is a cross-sectional view of the periphery of the second blind via. Fig. 26 is a cross-sectional view of the periphery of the third blind via.

[0007] [Problem to be Solved by the Present Disclosure] In the coil device described in Patent Document 1, the above-mentioned misalignment amount is zero, so heat generated in each wiring is easily transferred along the thickness direction, and good heat dissipation is achieved. In the coil device described in Patent Document 1, when the temperature rises due to reflow soldering, thermal stress at the interface between the adhesive layer and the base film (first base film, second base film) increases, and there is a possibility that the base film will peel off from the adhesive layer due to the thermal stress.

[0008] The present disclosure provides a coil device that can maintain heat dissipation while preventing the base film from peeling off from the adhesive layer when the temperature rises. Here, "when the temperature rises" refers to a temperature rise during reflow soldering during mounting, for example.

[0009] Effect of the Present Disclosure According to the coil device of the present disclosure, it is possible to prevent the base film from peeling off from the adhesive layer when the temperature rises, while maintaining heat dissipation properties.

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0011] (1) A coil device according to an embodiment includes a first base film having a first main surface and a second main surface opposite the first main surface, a first wiring disposed on the first main surface, and a second wiring disposed on the second main surface. The first wiring has a first coil portion configured from a portion of the first wiring wound in a coil shape in a plan view. The second wiring has a second coil portion configured from a portion of the second wiring wound in a coil shape in a plan view. In a cross-sectional view perpendicular to the direction in which the portion of the first wiring forming the first coil portion extends, a value obtained by dividing the amount of misalignment between the portion of the first wiring forming the first coil portion and the portion of the second wiring forming the second coil portion by half the pitch of the portion of the first wiring forming the first coil portion is equal to or greater than 0.06 and less than 0.50.

[0012] The coil device of (1) above can maintain heat dissipation while preventing the base film from peeling off from the adhesive layer when the temperature rises. Here, "when the temperature rises" refers to a temperature rise during reflow soldering during mounting, for example.

[0013] (2) The coil device of (1) above may further include a first adhesive layer disposed on the first main surface so as to cover the first wiring, a second base film disposed on the first adhesive layer and having a third main surface facing the first adhesive layer and a fourth main surface opposite the third main surface, and a third wiring disposed on the fourth main surface. The third wiring may have a third coil portion formed of a portion of the third wiring that is spirally wound in a plan view. In a cross-sectional view perpendicular to the direction in which the portion of the first wiring that constitutes the first coil portion extends, a value obtained by dividing the amount of misalignment between the portion of the first wiring that constitutes the first coil portion and the portion of the third wiring that constitutes the third coil portion by half the pitch of the portion of the first wiring that constitutes the first coil portion may be 0.06 or more and less than 0.50.

[0014] According to the coil device of (2) above, it is possible to prevent the base film from peeling off from the adhesive layer when the temperature rises while maintaining heat dissipation properties.

[0015] (3) The coil device of (2) may further include a second adhesive layer disposed on the second main surface so as to cover the second wiring, a third base film disposed on the second adhesive layer and having a fifth main surface facing the second adhesive layer and a sixth main surface opposite the fifth main surface, and a fourth wiring disposed on the sixth main surface. The fourth wiring may have a fourth coil portion constituted by a portion of the fourth wiring wound in a coil shape in a plan view. In a cross-sectional view perpendicular to the direction in which the portion of the first wiring constituting the first coil portion extends, a value obtained by dividing the amount of misalignment between the portion of the second wiring constituting the second coil portion and the portion of the fourth wiring constituting the fourth coil portion by half the pitch of the portion of the second wiring constituting the second coil portion may be 0.06 or more and less than 0.50.

[0016] According to the coil device of (3) above, it is possible to prevent the base film from peeling off from the adhesive layer when the temperature rises, while maintaining heat dissipation properties.

[0017] (4) The coil device of (3) may further include a third adhesive layer disposed on the fourth main surface so as to cover the third wiring, a fourth base film disposed on the third adhesive layer, a fourth adhesive layer disposed on the sixth main surface so as to cover the fourth wiring, and a fifth base film disposed on the fourth adhesive layer. The fourth base film may have a seventh main surface facing the third adhesive layer and an eighth main surface opposite the seventh main surface. When a current of 0.43 amperes flows through the first wiring, the second wiring, the third wiring, and the fourth wiring and reaches a steady state, the temperature rise at the eighth main surface may be 65°C or less, and the thermal stress at the interface between the third adhesive layer and the fourth base film due to the temperature rise may be 46 MPa or less.

[0018] According to the coil device of (4) above, it is possible to prevent the base film from peeling off from the adhesive layer when the temperature rises while maintaining heat dissipation properties.

[0019] (5) In any of the coil devices (1) to (4) above, each of the first wiring and the second wiring may include a seed layer disposed on the first main surface, a conductive layer disposed on the seed layer, and an electroplated layer disposed on the conductive layer.

[0020] (6) A coil device according to another embodiment includes a first base film having a first main surface and a second main surface opposite the first main surface, a first wiring disposed on the first main surface, a first adhesive layer disposed on the first main surface so as to cover the first wiring, a second base film disposed on the first adhesive layer and having a third main surface facing the first adhesive layer and a fourth main surface opposite the third main surface, and a third wiring disposed on the fourth main surface. The first wiring has a first coil portion formed of a portion of the first wiring wound in a coil shape in a plan view. The third wiring has a third coil portion formed of a portion of the third wiring wound in a coil shape in a plan view. In a cross-sectional view perpendicular to the direction in which the portion of the first wiring forming the first coil portion extends, a value obtained by dividing the amount of misalignment between the portion of the first wiring forming the first coil portion and the portion of the third wiring forming the third coil portion by half the pitch of the portion of the first wiring forming the first coil portion is equal to or greater than 0.06 and less than 0.50.

[0021] According to the coil device of (6) above, it is possible to prevent the base film from peeling off from the adhesive layer when the temperature rises, while maintaining heat dissipation properties.

[0022] [Details of the embodiment of the present disclosure] Next, details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are given the same reference numerals, and redundant description will not be repeated. The coil device according to the embodiment is referred to as coil device 100.

[0023] (Configuration of Coil Device 100) The configuration of the coil device 100 will be described below.

[0024] FIG. 1A is a plan view of the coil device 100, omitting the illustration of the adhesive layer 60 and the base film 70. FIG. 1A is a view of the wiring 50 in FIG. 3, viewed from the base film 70 to the base film 71. FIG. 1B is a plan view of the coil device 100, viewed from the opposite side of FIG. 1A, omitting the illustration of the adhesive layer 61 and the base film 71. FIG. 2A is a plan view of the coil device 100, omitting the illustration of the adhesive layer 30, the base film 40, the wiring 50, the adhesive layer 60, and the base film 70. FIG. 2A is a view of the wiring 20 in FIG. 3, viewed from the base film 70 to the base film 71. FIG. 2B is a plan view of the coil device 100, viewed from the opposite side of FIG. 2A, omitting the illustration of the adhesive layer 31, the base film 41, the wiring 51, the adhesive layer 61, and the base film 71. FIG. 3 is a cross-sectional view taken along III-III in FIG. 1A. As shown in Figures 1A to 3, the coil device 100 has a base film 10, wiring 20, wiring 21, adhesive layer 30, adhesive layer 31, base film 40, base film 41, wiring 50, wiring 51, adhesive layer 60, adhesive layer 61, base film 70, and base film 71.

[0025] The base film 10 is made of a flexible, electrically insulating material. A specific example of the material of the base film 10 is polyimide. The base film 10 has a main surface 10a and a main surface 10b. The main surface 10a and the main surface 10b are end surfaces of the base film 10 in the thickness direction. The main surface 10b is the surface opposite to the main surface 10a.

[0026] The wiring 20 is disposed on the main surface 10a. The wiring 20 has a coil portion 20a. The coil portion 20a is composed of a portion of the wiring 20. The coil portion 20a is wound in a coil shape in a plan view. The wiring 20 has a land 20b at a first end of the wiring 20 and a land 20c at a second end. The land 20b and the land 20c are located at the outermost and innermost peripheries of the coil portion 20a, respectively.

[0027] The wiring 21 is disposed on the main surface 10b. The wiring 21 has a coil portion 21a. The coil portion 21a is composed of a portion of the wiring 21. The coil portion 21a is wound in a coil shape in a plan view. The wiring 21 has a land 21b at a first end of the wiring 21 and a land 21c at a second end. The land 21b and the land 21c are located at the outermost and innermost peripheries of the coil portion 21a, respectively. The land 21b overlaps with the land 20b in a plan view.

[0028] Each of the wiring 20 and the wiring 21 has a seed layer 22, a conductive layer 23, and an electrolytic plating layer 24. The seed layer 22 of the wiring 20 is disposed on the main surface 10a. The seed layer 22 of the wiring 21 is disposed on the main surface 10b. The constituent material of the seed layer 22 may be, for example, a metal mainly composed of copper, but may also be a nickel-chromium alloy in terms of weather resistance. In the seed layer 22, copper may be formed on the nickel-chromium alloy by sputtering or the like.

[0029] The conductive layer 23 is disposed on the seed layer 22. As shown in FIG. 24 , first through holes are formed in the base film 10, the seed layer 22 of the land 20b, and the seed layer 22 of the land 21b. The conductive layer 23 is also disposed on the inner wall surfaces of the first through holes. The conductive layer 23 is, for example, an electroless plated layer (a layer formed by electroless plating). The conductive layer 23 is made of, for example, copper.

[0030] The electrolytic plating layer 24 is disposed on the conductive layer 23. The constituent material of the electrolytic plating layer 24 is, for example, copper. The wiring 20 and the wiring 21 are electrically connected to each other by the conductive layer 23 disposed on the inner wall surface of the first through hole and the electrolytic plating layer 24 disposed on the conductive layer 23.

[0031] The adhesive layer 30 is disposed on the main surface 10a so as to cover the wiring 20. The adhesive layer 31 is disposed on the main surface 10b so as to cover the wiring 21. The constituent material of the adhesive layer 30 and the adhesive layer 31 is, for example, a thermosetting adhesive.

[0032] The base film 40 is disposed on the adhesive layer 30. The base film 40 has a main surface 40a and a main surface 40b. The main surfaces 40a and 40b are end surfaces of the base film 40 in the thickness direction. The main surface 40a faces the adhesive layer 30. The main surface 40b is the surface opposite to the main surface 40a. The base film 40 is made of a flexible, electrically insulating material. A specific example of the material of the base film 40 is polyimide.

[0033] The base film 41 is disposed on the adhesive layer 31. The base film 41 has a main surface 41a and a main surface 41b. The main surface 41a and the main surface 41b are end surfaces of the base film 41 in the thickness direction. The main surface 41a faces the adhesive layer 31. The main surface 41b is the surface opposite to the main surface 41a. The base film 41 is made of a flexible, electrically insulating material. A specific example of the material of the base film 41 is polyimide.

[0034] The wiring 50 is disposed on the main surface 40b. The wiring 50 has a coil portion 50a that is composed of a portion of the wiring 50 that is wound in a coil shape in a plan view. The wiring 50 has a land 50b at a first end of the wiring 50 and a land 50c at a second end. The lands 50b and 50c are located at the outermost and innermost peripheries of the coil portion 50a, respectively. The land 50c overlaps with the land 20c in a plan view and is connected to the land 20c by a second blind via, which will be described later.

[0035] The wiring 51 is disposed on the main surface 41b. The wiring 51 has a coil portion 51a that is formed by a portion of the wiring 51 that is wound in a coil shape in a plan view. The wiring 51 has a land 51b at a first end of the wiring 51 and a land 51c at a second end. The land 51b and the land 51c are located at the outermost and innermost peripheries of the coil portion 51a, respectively. The land 51c overlaps with the land 21c in a plan view and is connected to the land 21c by a third blind via, which will be described later.

[0036] Each of the wiring 50 and the wiring 51 has a seed layer 52, a conductive layer 53, and an electrolytic plating layer 54. The seed layer 52 of the wiring 50 is disposed on the main surface 40b. The seed layer 52 of the wiring 51 is disposed on the main surface 41b. The constituent material of the seed layer 52 may be, for example, a metal mainly containing copper, but may also be a nickel-chromium alloy in terms of weather resistance. In the seed layer 52, copper may be formed on the nickel-chromium alloy by sputtering or the like.

[0037] The conductive layer 53 is disposed on the seed layer 52. As shown in FIG. 25, a second blind via is formed by providing a hole penetrating the thickness direction through the adhesive layer 30, the base film 40, and the seed layer 52 of the land 50c. The land 20c is located below (inside) the second blind via. As shown in FIG. 26, a third blind via is formed by providing a hole penetrating the thickness direction through the adhesive layer 31, the base film 41, and the seed layer 52 of the land 51c. The land 21c is located above (inside) the third blind via. The conductive layer 53 is also disposed on the inner wall surface of the second blind via, on the land 20c located below the second blind via, on the inner wall surface of the third blind via, and on the land 21c located above the third blind via. The conductive layer 53 is, for example, an electroless plating layer. The conductive layer 53 is made of, for example, copper.

[0038] The electrolytic plating layer 54 is disposed on the conductive layer 53. The constituent material of the electrolytic plating layer 54 is, for example, copper. The wiring 50 and the wiring 20 are electrically connected to each other by the conductive layer 53 and the electrolytic plating layer 54, which are disposed on the inner wall surface of the second blind via and on the land 20c located at the bottom of the second blind via. The wiring 51 and the wiring 21 are electrically connected to each other by the conductive layer 53 and the electrolytic plating layer 54, which are disposed on the inner wall surface of the third blind via and on the land 21c located at the top of the third blind via. Therefore, when a voltage is applied between the land 50b and the land 51b, a current flows in a coil shape through the coil portion 50a, the coil portion 20a, the coil portion 21a, and the coil portion 51a, generating a magnetic flux.

[0039] The adhesive layer 60 is disposed on the main surface 40b so as to cover the wiring 50. The adhesive layer 61 is disposed on the main surface 41b so as to cover the wiring 51. The constituent material of the adhesive layer 60 and the adhesive layer 61 is, for example, a thermosetting adhesive.

[0040] The base film 70 is disposed on the adhesive layer 60. The base film 70 has a main surface 70a and a main surface 70b. The main surface 70a and the main surface 70b are end surfaces of the base film 70 in the thickness direction. The main surface 70a faces the adhesive layer 60. The main surface 70b is the surface opposite to the main surface 70a. The base film 70 is made of a flexible, electrically insulating material. A specific example of the material of the base film 70 is polyimide.

[0041] The base film 71 is disposed on the adhesive layer 61. The base film 71 has a main surface 71a and a main surface 71b. The main surface 71a and the main surface 71b are end surfaces of the base film 71 in the thickness direction. The main surface 71a faces the adhesive layer 61. The main surface 71b is the surface opposite to the main surface 71a. The base film 71 is made of a flexible, electrically insulating material. A specific example of the material of the base film 71 is polyimide.

[0042] The width of the portion of the wiring 20 that constitutes the coil portion 20a is defined as width L1. The height of the portion of the wiring 20 that constitutes the coil portion 20a is defined as height H1. The spacing between adjacent portions of the wiring 20 that constitute the coil portion 20a is defined as spacing SP1. The pitch between adjacent portions of the wiring 20 that constitute the coil portion 20a is defined as pitch P1. The pitch is the distance between the first center and the second center of each portion of the wiring that is adjacent in the width direction of the wiring. Pitches other than pitch P1 are defined in the same manner.

[0043] The width of the portion of the wiring 21 that constitutes the coil portion 21a is defined as width L2. The height of the portion of the wiring 21 that constitutes the coil portion 21a is defined as height H2. The spacing between adjacent portions of the wiring 21 that constitute the coil portion 21a is defined as spacing SP2. The pitch between adjacent portions of the wiring 21 that constitute the coil portion 21a is defined as pitch P2.

[0044] The width of the portion of the wiring 50 that constitutes the coil portion 50a is defined as width L3. The height of the portion of the wiring 50 that constitutes the coil portion 50a is defined as height H3. The spacing between adjacent portions of the wiring 50 that constitute the coil portion 50a is defined as spacing SP3. The pitch between adjacent portions of the wiring 50 that constitute the coil portion 50a is defined as pitch P3.

[0045] The width of the portion of the wiring 51 that constitutes the coil portion 51a is defined as width L4. The height of the portion of the wiring 51 that constitutes the coil portion 51a is defined as height H4. The spacing between adjacent portions of the wiring 51 that constitute the coil portion 51a is defined as spacing SP4. The pitch between adjacent portions of the wiring 51 that constitute the coil portion 51a is defined as pitch P4.

[0046] The thickness of base film 10 is defined as thickness T1. The thickness of base film 40 is defined as thickness T2, and the thickness of base film 41 is defined as thickness T3. The thickness of base film 70 is defined as thickness T4, and the thickness of base film 71 is defined as thickness T5. The thickness of adhesive layer 30 between wiring 20 and base film 40 is defined as thickness T6, and the thickness of adhesive layer 31 between wiring 21 and base film 41 is defined as thickness T7. The thickness of adhesive layer 60 between wiring 50 and base film 70 is defined as thickness T8, and the thickness of adhesive layer 61 between wiring 51 and base film 71 is defined as thickness T9.

[0047] FIG. 23 is referred to. A cross section perpendicular to the direction in which the portion of the wiring 20 constituting the coil portion 20a extends is referred to as a cross-sectional view. In the cross-sectional view, the amount of misalignment between the portion of the wiring 20 constituting the coil portion 20a and the portion of the wiring 21 constituting the coil portion 21a is referred to as a first misalignment amount. In FIG. 23, the misalignment amount is indicated by D. Hatching in the cross-sectional view is omitted to indicate the misalignment amount D. In the cross-sectional view, the direction in which the portions of the wiring 20 constituting the coil portion 20a are lined up is referred to as an arrangement direction. In the cross-sectional view, one of the portions of the wiring 20 constituting the coil portion 20a is referred to as a first portion, and one of the portions of the wiring 21 constituting the coil portion 21a is referred to as a second portion. In the cross-sectional view, the distance in the arrangement direction between the center of the first portion in the arrangement direction and the center of the second portion in the arrangement direction is referred to as the first misalignment amount. The second portion selected to determine the first positional deviation amount is a portion of the wiring 21 that constitutes the coil portion 21a in a cross-sectional view and that is closer to the first portion in the arrangement direction than other portions of the wiring 21.

[0048] In a cross-sectional view, the amount of misalignment between the portion of the wiring 20 that constitutes the coil portion 20a and the portion of the wiring 50 that constitutes the coil portion 50a is defined as the second misalignment amount. One of the portions of the wiring 50 that constitute the coil portion 50a is defined as the third portion. In a cross-sectional view, the distance in the arrangement direction between the center in the arrangement direction of the first portion and the center in the arrangement direction of the third portion is defined as the second misalignment amount. The third portion selected to calculate the distance is a portion of the wiring 50 that constitutes the coil portion 50a in a cross-sectional view that is closer to the first portion in the arrangement direction than the other portions of the wiring 50.

[0049] In a cross-sectional view, the amount of misalignment between the portion of the wiring 21 that constitutes the coil portion 21a and the portion of the wiring 51 that constitutes the coil portion 51a is defined as the third misalignment amount. One of the portions of the wiring 51 that constitutes the coil portion 51a is defined as the fourth portion. In a cross-sectional view, the distance in the arrangement direction between the center in the arrangement direction of the second portion and the center in the arrangement direction of the fourth portion is defined as the third misalignment amount. The fourth portion selected to calculate the distance is a portion of the wiring 51 that constitutes the coil portion 51a in a cross-sectional view that is closer to the first portion in the arrangement direction than the other portions of the wiring 51.

[0050] The coil device according to the first reference example is referred to as coil device 200A, and the coil device according to the second reference example is referred to as coil device 200B. Fig. 4A is a plan view of coil device 200A. Fig. 4B is a plan view of coil device 200B. As shown in Fig. 4A, coil device 200A and coil device 200B have a base film 110, wiring 120, and wiring 121. Wiring 120 and wiring 121 are respectively arranged on a first main surface and a second main surface of base film 110. In Fig. 4A and Fig. 4B, the center position of wiring 121 in the width direction (arrangement direction) is indicated by a dotted line.

[0051] The wiring 120 has a coil portion 120a composed of a portion of the wiring 120 wound in a coil shape in a planar view. The wiring 121 has a coil portion 121a wound in a coil shape in a planar view. To enhance magnetic force, the wirings 120 and 121 are arranged overlapping each other in the thickness direction. Meanwhile, the direction of the magnetic flux generated by the current flowing through the coil portion 120a must be aligned with the direction of the magnetic flux generated by the current flowing through the coil portion 121a. Therefore, the winding direction of the wiring 120 when viewed along the normal direction to the first main surface of the base film 110 is opposite to the winding direction of the wiring 121 when viewed along the normal direction to the second main surface of the base film 110. As a result, the wiring 121 includes a portion with a pitch different from the other portions. The cross section used to measure the misalignment (a cross section perpendicular to the portion of the wiring 20 that constitutes the coil portion 20a) does not include the portion with a pitch different from the other portions.

[0052] The value obtained by dividing the first positional deviation amount by half the pitch P1 is 0.06 or more and less than 0.50, may be 0.13 or more and less than 0.50, or may be 0.16 or more and less than 0.50.

[0053] Furthermore, the value obtained by dividing the second positional deviation amount by half the pitch P1 may be 0.06 or more and less than 0.50, 0.13 or more and less than 0.50, or 0.16 or more and less than 0.50. The value obtained by dividing the third positional deviation amount by half the pitch P2 may be 0.06 or more and less than 0.50, 0.13 or more and less than 0.50, or 0.16 or more and less than 0.50.

[0054] The widths L1, L2, L3, and L4 may be equal to or different from one another. The heights H1, H2, H3, and H4 may be equal to or different from one another. The intervals SP1, SP2, SP3, and SP4 may be equal to or different from one another.

[0055] The pitches P1, P2, P3, and P4 may be equal to or different from one another. The thicknesses T1, T2, T3, T4, and T5 may be equal to or different from one another. The thicknesses T6, T7, T8, and T9 may be equal to or different from one another.

[0056] The pitches P1, P2, P3, and P4 are, for example, 35 μm or more and 60 μm or less. The intervals SP1, SP2, SP3, and SP4 are, for example, 5 μm to 30 μm or less. The heights H1, H2, H3, and H4 are, for example, 45 μm to 65 μm or less. The thicknesses T1, T2, T3, T4, and T5 are, for example, 2.5 μm to 7.5 μm or less. The thicknesses T6, T7, T8, and T9 are, for example, 2.5 μm to 7.5 μm or less.

[0057] When a current of 0.43 amperes flows through the wiring 20, wiring 21, wiring 50, and wiring 51 and reaches a steady state, the temperature rise on the main surface 70b is, for example, 65°C or less. The thermal stress at the interface between the adhesive layer 61 and the base film 71 that accompanies the temperature rise during reflow soldering during mounting is, for example, 46 MPa or less. The temperature during the temperature rise is, for example, 240°C. This makes it possible to suppress the temperature rise during use of the coil device 100 while also preventing the base film from peeling off from the adhesive layer due to the thermal stress that occurs during the temperature rise.

[0058] (Method of Manufacturing Coil Device 100) A method of manufacturing the coil device 100 will be described below.

[0059] Fig. 5 is a manufacturing process diagram of the coil device 100. As shown in Fig. 5, the manufacturing method of the coil device 100 includes a preparation step S1, a conductive treatment step S2, a resist pattern formation step S3, an electrolytic plating step S4, a resist pattern removal step S5, an etching step S6, a base film attachment step S7, a conductive treatment step S8, a resist pattern formation step S9, an electrolytic plating step S10, a resist pattern removal step S11, an etching step S12, and a base film attachment step S13.

[0060] In the preparation step S1, a base film 10 is prepared. In the base film 10 prepared in the preparation step S1, seed layers 22 are disposed on the main surfaces 10a and 10b. After the preparation step S1, a conductive treatment step S2 is performed. After the preparation step S1 and before the conductive treatment step S2, first through holes are formed in the base film 10, the seed layer 22 on the main surface 10a, and the seed layer 22 on the main surface 10b. The first through holes are formed by, for example, laser processing.

[0061] 6 is a cross-sectional view illustrating the conductive treatment step S2. As shown in FIG. 6, in the conductive treatment step S2, a conductive layer 23 is formed on the seed layer 22 by, for example, electroless plating. In the conductive treatment step S2, the conductive layer 23 is also formed on the inner wall surface of the first through hole. After the conductive treatment step S2, a resist pattern formation step S3 is performed.

[0062] 7 is a cross-sectional view illustrating the resist pattern forming step S3. As shown in FIG. 7, in the resist pattern forming step S3, a resist pattern 80 is formed on the conductive layer 23. The resist pattern 80 has openings 80a. The conductive layer 23 is partially exposed through the openings 80a. The resist pattern 80 is formed, for example, by applying a dry film resist to the conductive layer 23 and then exposing and developing the applied dry film resist. After the resist pattern forming step S3, an electrolytic plating step S4 is performed.

[0063] FIG. 8 is a cross-sectional view illustrating the electrolytic plating step S4. As shown in FIG. 8, in the electrolytic plating step S4, electrolytic plating is performed to form an electrolytic plated layer 24 on the conductive layer 23 exposed from the opening 80a. After the electrolytic plating step S4, a resist pattern removing step S5 is performed. FIG. 9 is a cross-sectional view illustrating the resist pattern removing step S5. As shown in FIG. 9, in the resist pattern removing step S5, the resist pattern 80 is removed from the conductive layer 23. After the resist pattern removing step S5, an etching step S6 is performed.

[0064] 10 is a cross-sectional view illustrating the etching step S6. As shown in FIG. 10, in the etching step S6, the conductive layer 23 and the seed layer 22 that were present under the resist pattern 80 are removed by etching. This forms the wiring 20 and the wiring 21. After the etching step S6, the base film attaching step S7 is performed.

[0065] 11 is a cross-sectional view illustrating the base film bonding step S7. As shown in FIG. 11 , in the base film bonding step S7, the base film 40 is bonded by the adhesive layer 30. Also, in the base film bonding step S7, the base film 41 is bonded by the adhesive layer 31. In the base film bonding step S7, first, the base film 40 and the base film 41 are prepared. The base film 40 prepared in the base film bonding step S7 has an uncured adhesive layer 30 disposed on the main surface 40a and a seed layer 52 disposed on the main surface 40b. The base film 41 prepared in the base film bonding step S7 has an uncured adhesive layer 31 disposed on the main surface 41a and a seed layer 52 disposed on the main surface 41b.

[0066] Second, a base film 40 is disposed on main surface 10a with adhesive layer 30 interposed therebetween, and a base film 41 is disposed on main surface 10b with adhesive layer 31 interposed therebetween. Third, base films 40 and 41 are heated and pressed toward base film 10. This hardens adhesive layers 30 and 31, and base films 40 and 41 are attached. After base film attaching step S7, a conductive treatment step S8 is performed. After base film attaching step S7 and before conductive treatment step S8, a second blind via is formed that penetrates seed layer 52 and base film 40 and reaches at least the surface of electrolytic plated layer 24. After base film attaching step S7 and before conductive treatment step S8, a third blind via is formed that penetrates seed layer 52 and base film 41 and reaches at least the surface of electrolytic plated layer 24. The second blind via and the third blind via are formed, for example, by laser processing.

[0067] 12 is a cross-sectional view illustrating the conductive treatment step S8. As shown in FIG. 12, in the conductive treatment step S8, a conductive layer 53 is formed on the seed layer 52 by, for example, electroless plating. In the conductive treatment step S8, the conductive layer 53 is also formed on the inner wall surfaces of the second blind via and the third blind via. After the conductive treatment step S8, a resist pattern formation step S9 is performed.

[0068] 13 is a cross-sectional view illustrating the resist pattern forming step S9. As shown in FIG. 13, in the resist pattern forming step S9, a resist pattern 81 is formed on the conductive layer 53. The resist pattern 81 has openings 81a. The conductive layer 53 is partially exposed through the openings 81a. The resist pattern 81 is formed, for example, by applying a dry film resist to the conductive layer 53 and then exposing and developing the applied dry film resist. After the resist pattern forming step S9, an electrolytic plating step S10 is performed.

[0069] FIG. 14 is a cross-sectional view illustrating the electrolytic plating step S10. As shown in FIG. 14, in the electrolytic plating step S10, electrolytic plating is performed to form an electrolytic plated layer 54 on the conductive layer 53 exposed from the opening 81 a. After the electrolytic plating step S10, a resist pattern removal step S11 is performed. FIG. 15 is a cross-sectional view illustrating the resist pattern removal step S11. As shown in FIG. 15, in the resist pattern removal step S11, the resist pattern 81 is removed from the conductive layer 53. After the resist pattern removal step S11, an etching step S12 is performed.

[0070] 16 is a cross-sectional view illustrating the etching step S12. As shown in FIG. 16, in the etching step S12, the conductive layer 53 and the seed layer 52 that were present under the resist pattern 81 are removed by etching. This forms the wiring 50 and the wiring 51. After the etching step S12, a base film attaching step S13 is performed.

[0071] In the base film attaching step S13, the base film 70 is attached by the adhesive layer 60, and the base film 71 is attached by the adhesive layer 61. In the base film attaching step S13, first, the base films 70 and 71 are prepared. The base film 70 prepared in the base film attaching step S13 has an uncured adhesive layer 60 disposed on its main surface 70a. The base film 71 prepared in the base film attaching step S7 has an uncured adhesive layer 61 disposed on its main surface 71a.

[0072] Second, the base film 70 is disposed on the main surface 40a with the adhesive layer 60 interposed therebetween, and the base film 71 is disposed on the main surface 41a with the adhesive layer 31 interposed therebetween. Third, the base films 70 and 71 are heated and pressed toward the base film 10. This hardens the adhesive layers 60 and 61, bonding the base films 70 and 71 together, and the structure of the coil device 100 shown in FIGS. 1A to 3 is formed.

[0073] <Modification> Fig. 17 is a cross-sectional view of a coil device 100 according to a modification. As shown in Fig. 17, wiring 21 may be arranged on main surface 41a instead of main surface 10b. Wiring 51 may be arranged on main surface 71a instead of main surface 41b. That is, although Fig. 3 shows the configuration of coil device 100 in which a double-sided board is sandwiched between two single-sided boards, coil device 100 may have a configuration in which multiple single-sided boards (four single-sided boards in the example of Fig. 17) are stacked in the thickness direction. The number of stacked single-sided boards may be four, five or more, or six or more.

[0074] (Effects of the Coil Device 100) The effects of the coil device 100 will be described below.

[0075] Table 1 shows the results of a simulation (two-dimensional steady-state temperature analysis) of the temperature rise on the main surface 70b when the first misalignment amount is changed. In the simulation of Table 1, the second misalignment amount and the third misalignment amount are set equal to the first misalignment amount, simulating a state in which the main surface 71b is cooled by contacting it with a metal plate.

[0076] In the simulation of Table 1, the widths L1, L2, L3, and L4 are set to 30 μm. In the simulation of Table 1, the heights H1, H2, H3, and H4 are set to 50 μm. In the simulation of Table 1, the spacings SP1, SP2, SP3, and SP4 are set to 30 μm. In the simulation of Table 1, the thicknesses T1, T2, T3, T4, and T5 are set to 5 μm. In the simulation of Table 1, the thicknesses T6, T7, T8, and T9 are set to 5 μm. In the simulation of Table 1, the pitches P1, P2, P3, and P4 are set to 60 μm. In the simulation of Table 1, the thermal conductivity of the wiring 20, wiring 21, wiring 50, and wiring 51 is set to 400 W / m·K. In the simulation of Table 1, the thermal conductivity of base film 10, base film 40, base film 41, base film 70, and base film 71 is set to 0.1 W / m·K. In the simulation of Table 1, the thermal conductivity of adhesive layer 30, adhesive layer 31, adhesive layer 60, and adhesive layer 61 is set to 0.1 W / m·K.

[0077]

[0078] 18 is a graph showing the results of a simulation of the temperature rise on the main surface 70b when the first positional deviation amount is changed. The graph in FIG. 18 was created based on Table 1 (the heat generation amount is 2 W / mm ３ 18, the temperature rise on the main surface 70b increases as the first positional deviation increases.

[0079] Table 2 shows the results of a simulation (thermal expansion analysis) of the equivalent stress at the interface between the main surface 71 a and the adhesive layer 61 when the first misalignment amount is changed. In the simulation of Table 2, the structure of FIG. 17 is simulated, and the thermal stress at a temperature rise (240° C.) that occurs during reflow soldering is calculated.

[0080] In the simulation of Table 2, the widths L1, L2, L3, and L4 are set to 30 μm. In the simulation of Table 2, the heights H1, H2, H3, and H4 are set to 50 μm. In the simulation of Table 2, the spacings SP1, SP2, SP3, and SP4 are set to 30 μm. In the simulation of Table 2, the thicknesses T1, T2, T3, T4, and T5 are set to 5 μm. In the simulation of Table 2, the thicknesses T6, T7, T8, and T9 are set to 5 μm. In the simulation of Table 2, the pitches P1, P2, P3, and P4 are set to 60 μm. In the simulation of Table 2, the thermal conductivity of the wiring 20, wiring 21, wiring 50, and wiring 51 is set to 400 W / m·K. In the simulation of Table 2, the thermal conductivity of base film 10, base film 40, base film 41, base film 70, and base film 71 is set to 0.1 W / m·K. In the simulation of Table 2, the thermal conductivity of adhesive layer 30, adhesive layer 31, adhesive layer 60, and adhesive layer 61 is set to 0.1 W / m·K.

[0081] In the simulation of Table 2, the thermal expansion coefficients of the wiring 20, the wiring 21, the wiring 50, and the wiring 51 are 16.8×10 －６ In the simulation of Table 2, the thermal expansion coefficients of the base films 10, 40, 41, 70, and 71 are 13.0×10 －６ In the simulation of Table 2, the thermal expansion coefficients of the adhesive layers 30, 31, 60, and 61 are 45.0×10 －６ / K is said to be.

[0082]

[0083] As shown in Table 2, as the first positional deviation amount increases, the equivalent stress at the interface between the main surface 71a and the adhesive layer 61 decreases.

[0084] In this way, as the first misalignment amount increases, the heat dissipation performance decreases, while the thermal stress at the interface between the main surface 71 a and the adhesive layer 61 decreases. In the coil device 100, by setting the value obtained by dividing the first misalignment amount by half the pitch P1 to be equal to or greater than 0.06 and less than 0.50, peeling of the base film 70 (base film 71) from the adhesive layer 60 (adhesive layer 61) is suppressed while maintaining the heat dissipation performance.

[0085] 19 is a graph showing the relationship between the amount of current that can be passed through the wiring and the first misalignment amount when the temperature rise on the main surface 70b is 65°C. In the simulation of FIG. 19, the widths L1, L2, L3, and L4 are set to 30 μm. In the simulation of FIG. 19, the heights H1, H2, H3, and H4 are set to 50 μm, the spacing SP1, SP2, SP3, and SP4 are set to 30 μm, and the pitches P1, P2, P3, and P4 are set to 60 μm. In the simulation of FIG. 19, the total length of the wiring 20, wiring 21, wiring 50, and wiring 51 is set to 666.3 mm, and the total electrical resistance of the wiring 20, wiring 21, wiring 50, and wiring 51 is set to 9.9 Ω.

[0086] As shown in Figure 19, when the first positional misalignment amount is less than 15 μm (when the value obtained by dividing the first positional misalignment amount by 1 / 2 of the pitch P1 is less than 0.50), the temperature rise on the main surface 70b when a current of 0.43 amperes is flowing can be kept to 65°C or less.

[0087] Tables 3 and 4 show simulation results of the equivalent stress at the interface between the main surface 71a and the adhesive layer 61 when the pitch P1, spacing SP1, height H1, thickness T1, and thickness T6 are changed. In the simulations of Tables 3 and 4, conditions other than those shown in Tables 3 and 4 were the same as those in the simulation of Table 2. In Samples 1 to 6 shown in Tables 3 and 4, the pitch P1 to pitch P4 are equal, the height H1 to height H4 are equal, the thickness T1 to thickness T5 are equal, and the thickness T6 to thickness T9 are equal. In Table 3, L1 indicates the wiring width, and is the value obtained by subtracting the spacing SP1 from the pitch P1 (width L1 = pitch P1 - spacing SP1).

[0088]

[0089]

[0090] FIG. 20 is a graph showing the relationship between the thermal stress at the interface between the main surface 71a and the adhesive layer 61 and the value obtained by dividing the first misalignment amount by half the pitch P1 in the simulations of Tables 3 and 4. The values ​​obtained by dividing the first misalignment amount by half the pitch P1 were 0, 0.066, 0.167, 0.333, and 0.5. As shown in FIG. 20 , the smaller the thickness T1 and thickness T6, the greater the thermal stress at the interface between the main surface 71a and the adhesive layer 61. When the height H1 is greater or less than 50 μm, the greater the thermal stress at the interface between the main surface 71a and the adhesive layer 61. When the spacing SP1 is smaller, the thermal stress at the interface between the main surface 71a and the adhesive layer 61 decreases. As shown in Figure 20 and Tables 3 and 4, if the value obtained by dividing the first positional misalignment amount by half the pitch P1 is 0.06 or more and less than 0.50, the thermal stress at the interface between the adhesive layer 61 and the base film 71 due to temperature rise can be kept to 46 MPa or less, while the temperature rise at the main surface 70b when a current of 0.43 amperes is flowing can be kept to 65°C or less.

[0091] Tables 5 and 6 show the results of simulations of the amount of temperature rise when the pitch P1, the interval SP1, the height H1, the thickness T1, and the thickness T6 are changed. In the simulations of Tables 5 and 6, the conditions other than those shown in Tables 5 and 6 were the same as those in the simulation of Table 1. However, in the simulations of Tables 5 and 6, the heat generation amount was 2.0 W / mm ３ In Samples 1 to 6 shown in Tables 5 and 6, pitches P1 to P4 are equal, heights H1 to H4 are equal, thicknesses T1 to T5 are equal, and thicknesses T6 to T9 are equal. In Table 5, L1 indicates the wiring width, which is the value obtained by subtracting spacing SP1 from pitch P1 (width L1 = pitch P1 - spacing SP1).

[0092]

[0093]

[0094] FIG. 21 is a graph showing the relationship between the temperature rise and the value obtained by dividing the first misalignment amount by half the pitch P1 in the simulations of Tables 5 and 6. The values ​​obtained by dividing the first misalignment amount by half the pitch P1 were 0, 0.066, 0.167, 0.333, 0.5, and 1.0. As shown in FIG. 21, the temperature rise decreases as the thickness T1 and thickness T6 decrease. Furthermore, the temperature rise increases as the spacing SP1 decreases. Samples 1 and 6 are omitted from the graph in FIG. 21 because they generally overlap with Sample 5. In other words, height H1 has no effect on the temperature rise.

[0095] (Modification) Fig. 22 is an enlarged cross-sectional view of a coil device 100 according to a modification. As shown in Fig. 22, the wiring 20 and the wiring 21 (not shown in Fig. 22) may further have an electrolytic plating layer 25. The electrolytic plating layer 25 covers the side surfaces of the seed layer 22, the side surfaces of the conductive layer 23, the side surfaces of the electrolytic plating layer 24, and the upper surface of the electrolytic plating layer 24. The electrolytic plating layer 25 is formed by electrolytic plating performed after the etching step S6 and before the base film attaching step S7.

[0096] Although not shown, wiring 50 and wiring 51 may also have an electrolytic plating layer separate from electrolytic plating layer 54, and this separate electrolytic plating layer covers the side surfaces of seed layer 52, the side surfaces of conductive layer 53, the side surfaces of electrolytic plating layer 54, and the top surface of electrolytic plating layer 54. The separate electrolytic plating layer is formed by electrolytic plating performed after etching step S12 and before base film attachment step S13.

[0097] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims.

[0098] 10, 40, 41, 70, 71, 110 Base film 10a, 10b, 40a, 40b, 41a, 41b, 70a, 70b, 71a, 71b Main surface 20, 21, 50, 51, 120, 121 Wiring 20a, 21a, 50a, 51a, 120a, 121a Coil portion 20b, 20c, 21b, 21c, 50b, 50c, 51b, 51c Land 22, 52 Seed layer 23, 53 Conductive layer 24, 54 Electrolytic plating layer 25 Electrolytic plating layer 30, 31, 60, 61 Adhesion layer 80, 81 Resist pattern 80a, 81a Opening 100, 200A, 200B Coil device D Positional deviation amount H1, H2, H3, H4 Height L1, L2, L3, L4 Width P1, P2, P3, P4 Pitch S1 Preparation process S2, S8 Conductive treatment process S3, S9 Resist pattern formation process S4, S10 Electrolytic plating process S5, S11 Resist pattern removal process S6, S12 Etching process S7, S13 Base film attachment process SP1, SP2, SP3, SP4 Spacing T1, T2, T3, T4, T5, T6, T7, T8, T9 Thickness

Claims

1. A coil device comprising: a first base film having a first main surface and a second main surface opposite to the first main surface; a first wiring arranged on the first main surface; and a second wiring arranged on the second main surface, wherein the first wiring has a first coil portion constituted by a portion of the first wiring wound in a coil shape in a planar view; and the second wiring has a second coil portion constituted by a portion of the second wiring wound in a coil shape in a planar view, and in a cross-sectional view perpendicular to a direction in which the portion of the first wiring that constitutes the first coil portion extends, a value obtained by dividing an amount of misalignment between the portion of the first wiring that constitutes the first coil portion and the portion of the second wiring that constitutes the second coil portion by half the pitch of the portion of the first wiring that constitutes the first coil portion is 0.06 or more and less than 0.

50.

2. A coil device as described in claim 1, further comprising: a first adhesive layer disposed on the first main surface so as to cover the first wiring; a second base film disposed on the first adhesive layer and having a third main surface facing the first adhesive layer and a fourth main surface which is the opposite surface of the third main surface; and a third wiring disposed on the fourth main surface, wherein the third wiring has a third coil portion constituted by a portion of the third wiring which is wound in a coil shape in a planar view, and wherein, in a cross-sectional view perpendicular to the direction in which the portion of the first wiring which constitutes the first coil portion extends, a value obtained by dividing an amount of positional deviation between the portion of the first wiring which constitutes the first coil portion and the portion of the third wiring which constitutes the third coil portion by half the pitch of the portion of the first wiring which constitutes the first coil portion is 0.06 or more and less than 0.

50.

3. A coil device as described in claim 2, further comprising: a second adhesive layer disposed on the second main surface so as to cover the second wiring; a third base film disposed on the second adhesive layer and having a fifth main surface facing the second adhesive layer and a sixth main surface which is the opposite surface of the fifth main surface; and a fourth wiring disposed on the sixth main surface, wherein the fourth wiring has a fourth coil portion constituted by a portion of the fourth wiring which is wound in a coil shape in a planar view, and in a cross-sectional view perpendicular to the direction in which the portion of the first wiring constituting the first coil portion extends, a value obtained by dividing an amount of positional deviation between the portion of the second wiring constituting the second coil portion and the portion of the fourth wiring constituting the fourth coil portion by half the pitch of the portion of the second wiring constituting the second coil portion is 0.06 or more and less than 0.

50.

4. A coil device as described in claim 3, further comprising a third adhesive layer arranged on the fourth main surface so as to cover the third wiring, a fourth base film arranged on the third adhesive layer, a fourth adhesive layer arranged on the sixth main surface so as to cover the fourth wiring, and a fifth base film arranged on the fourth adhesive layer, wherein the fourth base film has a seventh main surface facing the third adhesive layer and an eighth main surface which is the opposite side to the seventh main surface, and wherein the amount of temperature rise at the eighth main surface when a steady state is reached when a current of 0.43 amperes flows through the first wiring, the second wiring, the third wiring, and the fourth wiring is 65°C or less, and the thermal stress at the interface between the third adhesive layer and the fourth base film due to the temperature rise is 46 MPa or less.

5. A coil device as described in any one of claims 1 to 4, wherein each of the first wiring and the second wiring comprises a seed layer disposed on the first main surface, a conductive layer disposed on the seed layer, and an electrolytic plating layer disposed on the conductive layer.

6. A coil device comprising: a first base film having a first main surface and a second main surface that is the opposite surface to the first main surface; a first wiring arranged on the first main surface; a first adhesive layer arranged on the first main surface so as to cover the first wiring; a second base film arranged on the first adhesive layer and having a third main surface facing the first adhesive layer and a fourth main surface that is the opposite surface to the third main surface; and a third wiring arranged on the fourth main surface, wherein the first wiring has a first coil portion consisting of a portion of the first wiring that is wound in a coil shape in a planar view, and the third wiring has a third coil portion consisting of a portion of the third wiring that is wound in a coil shape in a planar view, and a value obtained by dividing an amount of positional deviation between the portion of the first wiring that constitutes the first coil portion and the portion of the third wiring that constitutes the third coil portion by half the pitch of the portion of the first wiring that constitutes the first coil portion in a cross-sectional view perpendicular to a direction in which the portion of the first wiring that constitutes the first coil portion extends is equal to or greater than 0.06 and less than 0.50.

Images