Embedded substrate, power supply apparatus, and electronic device

Abstract

An embedded substrate, a power supply apparatus, and an electronic device. The embedded substrate comprises a front first additional layer, which is joint with a first surface of a chip holding body, wherein a conduction structure which is electrically connected to a circuit layer of the front first additional layer is provided in a dielectric layer of the front first additional layer, the conduction structure comprising a first conduction structure electrically connected to a pad on a chip; the dielectric layer of the front first additional layer is made of an exposable and developable material, and openings for constructing the conduction structure are formed by means of exposure and development; and a window of an outer protection layer has a first projection on the first surface, a first opening for constructing the first conduction structure has a second projection on the first surface, and the second projection covers the first projection. By means of such arrangements, a first conduction structure having a relatively large through-flow section is constructed by using the size of a window on a chip side, thereby effectively improving a through-flow capability, and achieving a good thermal conductivity capability. In addition, the joining stress between a circuit layer and the front surface of the chip can be reduced, thereby lowering the risk of delamination, and providing relatively good reliability.

Description

Embedded substrates, power supply devices and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 1, 2023, with application number 202311450995.7 and invention name “Buried substrate, power supply device and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the technical field of electronic component packaging, and in particular to an embedded substrate, a power supply device, and an electronic device. Background Art

[0003] Embedded substrate technology embeds electronic components, such as but not limited to chips, resistors, capacitors, and inductors, within the substrate. These components are interconnected via peripheral circuitry, creating highly integrated, high-density functional modules. Embedded substrate technology can be used in a variety of applications. As product functionality continues to evolve, achieving high current, high heat dissipation, and high reliability have become core requirements for embedded substrates.

[0004] A typical power chip packaging module, in which the chip and other components are embedded in the core board structure, and the core board surface is laminated with a build-up layer to realize a highly integrated circuit for interconnection. Usually, the pad on the front of the chip is exposed to the window of the PI layer (outer protective layer), and a blind hole is formed in the build-up layer next to the chip through a laser process to establish an electrical connection between the chip side and the build-up layer side. However, due to the limitations of the position accuracy of the chip layout and the position accuracy of the blind hole processing, a ring width needs to be reserved between the blind hole and the window of the PI layer, and the diameter of the blind hole is smaller than the window size of the chip PI layer. The window size of the chip material is fixed, which limits the flow and thermal conductivity of the blind hole to the design bottleneck, which directly affects the flow and thermal conductivity of the front of the chip.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide an embedded substrate, a power supply device, and an electronic device, which achieve high current, high heat dissipation, and high reliability through optimization of the embedded substrate structure.

[0007] According to a first aspect of an embodiment of the present application, there is provided an embedded substrate, which includes a core retaining body, a build-up layer and a chip embedded in the core retaining body; wherein the core retaining body includes a first surface and a second surface, and the front surface of the chip is arranged toward the first surface of the core retaining body; an outer protective layer is provided on the outer side of the solder pad of the chip, and the outer protective layer has a window arranged corresponding to the solder pad on the chip; wherein the build-up layer includes a front build-up layer covering the first surface of the core retaining body, the front build-up layer includes a front first build-up layer bonded to the first surface of the core retaining body and the front surface of the chip, and the front first build-up layer includes The present invention comprises a dielectric layer and a circuit layer that are stacked together, and a conductive structure electrically connected to its circuit layer is provided in the dielectric layer of the first build-up layer on the front side, and the conductive structure includes a first conductive structure electrically connected to the pad on the chip; wherein, the dielectric layer of the first build-up layer on the front side is made of an exposeable and developable material, and an opening for constructing the conductive structure is formed by exposure and development, and the opening for constructing the first conductive structure is a first opening; the window of the outer protective layer has a first projection on the first surface, and the first opening corresponding to the window has a second projection on the first surface, and the second projection covers the first projection.

[0008] This arrangement maximizes the use of the chip-side window size to construct the first conductive structure, providing a larger flow cross-section, effectively improving flow capacity while also providing excellent thermal conductivity. Furthermore, the first opening of the first conductive structure is formed through an exposure and development process, avoiding the difficulties associated with traditional laser drilling, resulting in improved manufacturability.

[0009] Furthermore, compared to solutions that improve the substrate's thermal conductivity by plating a copper layer on the chip's front-side outer protective layer, in this embodiment, both the dielectric layer of the front-side first build-up layer and the chip-side outer protective layer are made of organic materials. This dielectric layer can reduce the bonding stress between the circuit layer and the chip's front side, lowering the risk of interlayer interface delamination. Overall, this results in better reliability.

[0010] Exemplarily, the light-exposed and developable material may be a dry film, which may be formed by lamination; in another exemplary embodiment, the light-exposed and developable material may be a liquid photosensitive adhesive, which may be coated or spin-coated on the core retainer.

[0011] Based on the first aspect, the present application also provides a first implementation of the first aspect: the embedded substrate further includes an electronic component embedded in the core retaining body, the conductive structure further includes a second conductive structure electrically connected to the pins of the electronic component, and the opening for constructing the second conductive structure is a second opening. This allows for flexible configuration based on product functional requirements.

[0012] In practical applications, multiple electronic components are provided, and at least one of the multiple electronic components is a capacitor or a resistor.

[0013] Based on the first aspect, or the first embodiment of the first aspect, the present application also provides a second embodiment of the first aspect: the embedded substrate further includes a flow-through structure embedded in the core retaining body, the conductive structure further includes a third conductive structure electrically connected to the flow-through structure, and the opening for constructing the third conductive structure is a third opening. In this way, the external connection relationship on the first side of the core retaining body can be opened through the exposure and development process, and the overall processability is good.

[0014] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the embodiment of the present application also provides a third embodiment of the first aspect: the core retaining body is a core plate made of organic material.

[0015] For example, the matrix of the core board may be made of glass cloth reinforced epoxy phenolic resin (Flame Resistant 4, FR4), bismaleimide triazine resins (BT) or BT-like organic materials.

[0016] Based on the third embodiment of the first aspect, the embodiment of the present application also provides a fourth embodiment of the first aspect: the flow-through structure in the core board is a plated through hole (PTH) or copper column arranged through the core board substrate, or the flow-through structure in the core board is a multi-layer hole structure in the core board substrate.

[0017] In practical applications, the PTH through-hole has a flat morphology, good processability, and controllable cost. In this way, based on the PTH through-hole, a reliable blind hole stacking connection can be achieved, which is conducive to the rapid transmission of signals, heat, and current.

[0018] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the present application also provides a fifth embodiment of the first aspect: the core retainer is a core plate made of glass. Thus, based on the glass substrate frame, the overall strength of the substrate is improved. Furthermore, due to the adjustable coefficient of thermal expansion (CTE) of the glass material, in a specific implementation, a glass with a CTE close to that of the chip substrate can be selected, effectively reducing structural stress.

[0019] Based on the fifth embodiment of the first aspect, the present application also provides a sixth embodiment of the first aspect: the flow structure in the core plate is a TGV. Here, due to the good through-glass via (TGV) hole density and hole filling capability, heat transfer and flow capacity can be further improved.

[0020] Based on the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, the embodiment of the present application further provides a seventh embodiment of the first aspect: the chip and the electronic components embedded in the core board are aligned with the first surface of the core board, or aligned with the second surface of the core board. In a specific implementation, the situation where the chip and the electronic components are aligned with the first surface of the core board can facilitate the specific implementation of the exposure and development process; the situation where the chip and the electronic components are aligned with the second surface of the core board is conducive to the high thermal conductivity of the product architecture without a back-side build-up layer.

[0021] Based on the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, the embodiments of the present application further provide an eighth embodiment of the first aspect: the embedded material around the chip and electronic components is Ajinomoto Build-up Film (ABF). This has the characteristic of controllable cost. Alternatively, the embedded material around the chip and electronic components is an exposeable and developable material. This improves overall processability.

[0022] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, the embodiment of the present application further provides a ninth embodiment of the first aspect: the build-up layer further includes a back-side build-up layer covering the second surface of the core retaining body. Flexible arrangement can be used to achieve flow paths and heat conduction paths between the embedded substrate and the outside.

[0023] Based on the ninth embodiment of the first aspect, the present application also provides a tenth embodiment of the first aspect: a heat conducting portion is provided in the backside build-up layer, wherein the inner end of the heat conducting portion abuts the backside of the chip, and the outer end of the heat conducting portion extends to the surface of the backside build-up layer. In this way, the heat conducting portion effectively reduces the thermal resistance of the backside of the chip, quickly dissipates heat from the chip, and exhibits excellent high thermal conductivity.

[0024] Exemplarily, the heat conducting portion may be a copper block, or may be blind holes or copper bars arranged in an array.

[0025] In practical applications, the back side of the chip can have a copper backing layer to ensure that the inner end of the heat conducting portion abuts against the copper backing layer. This copper backing layer provides good heat dissipation, further improving the back side's heat conduction and lowering the chip's operating temperature. For example, in power modules, this can improve power efficiency.

[0026] Based on the ninth embodiment of the first aspect, or the tenth embodiment of the first aspect, the embodiment of the present application also provides the eleventh embodiment of the first aspect: the back-side build-up layer includes a first back-side build-up layer, and the first back-side build-up layer is bonded to the second surface of the core retaining body; wherein, the first back-side build-up layer includes a dielectric layer and a circuit layer arranged in a stacked manner, and a conductive structure electrically connected to its circuit layer is provided in the dielectric layer of the first back-side build-up layer.

[0027] In practical applications, the dielectric layer of the first back build-up layer can also be made of an exposable and developable material, and openings for constructing the conductive structure are formed by exposure and development. This simplifies the manufacturing process of the embedded substrate.

[0028] Based on the eleventh embodiment of the first aspect, the present application also provides a twelfth embodiment of the first aspect: the dielectric layer of the first back-side build-up layer is made of prepreg (PP). This arrangement, on the one hand, the PP material has good strength and high-temperature resistance, thereby enhancing the overall strength of the substrate; on the other hand, the inner end of the heat conductive portion abuts the chip, while the outer end of the heat conductive portion extends to the surface of the back-side build-up layer. In other words, taking ABF as the embedding material, the heat conductive portion sequentially passes through the ABF filling layer and the PP build-up layer, creating a pinning effect at the interface between the two, reducing the risk of delamination between the ABF embedding material and the PP build-up layer, and further improving reliability.

[0029] Based on the eleventh embodiment of the first aspect, or the twelfth embodiment of the first aspect, the embodiment of the present application also provides the thirteenth embodiment of the first aspect: the back side build-up layer includes at least one back side second build-up layer, the back side second build-up layer is stacked on the back side first build-up layer, the back side second build-up layer includes a stacked dielectric layer and a circuit layer, and the dielectric layer of the back side second build-up layer is made of ABF, PP or an exposeable and developable material.

[0030] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, or the ninth embodiment of the first aspect, or the tenth embodiment of the first aspect, or the eleventh embodiment of the first aspect, or the twelfth embodiment of the first aspect, or the thirteenth embodiment of the first aspect, the embodiment of the present application also provides the fourteenth embodiment of the first aspect: the front build-up layer includes at least one front second build-up layer, the front second build-up layer is sequentially stacked on the front first build-up layer, the front second build-up layer includes a dielectric layer and a circuit layer stacked, and the dielectric layer of the front second build-up layer is made of ABF, PP or an exposeable and developable material.

[0031] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the present application also provides a fifteenth embodiment of the first aspect: the core retaining body is a filling dielectric layer made of a filling dielectric material. This configuration simplifies the process and can reasonably control manufacturing costs.

[0032] For example, the filling dielectric material may be an exposable and developable material, so that the dielectric layer of the front first build-up layer can be formed simultaneously with the formation of the core retainer, which has good processability.

[0033] In practical applications, the flow-through structure in the filling medium layer can be a copper column, which has good thermal conductivity and flow-through capacity.

[0034] Based on the fifteenth implementation of the first aspect, the embodiment of the present application further provides a sixteenth implementation of the first aspect: the chip and the electronic components embedded in the core board are aligned with the second surface of the filling dielectric layer.

[0035] A second aspect of an embodiment of the present application provides a power supply device, which includes a chip, an inductor element and multiple electronic components. The chip and some of the multiple electronic components use the embedded substrate as described above to form a first package body, and the inductor element and another part of the multiple electronic components form a second package body, and the second package body is arranged to overlap with the first package body.

[0036] A third aspect of an embodiment of the present application provides an electronic device, which includes a system board and a power supply device. The power supply device is arranged on the system board, and the power supply device is the power supply device described above.

[0037] A fourth aspect of an embodiment of the present application provides an electronic device, which includes a mainboard and an embedded component. The embedded component is arranged on the mainboard, and the embedded component is made of the embedded substrate as described above.

[0038] In practical applications, the electronic device can be a server, a computer or a high-performance computing cluster, for high-power, highly integrated, ultra-large-scale data center servers; in addition, the electronic device can also be a switch, a router or an edge device, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a cross-sectional view of a structure of an embedded substrate provided in an embodiment of the present application;

[0040] FIG2 is a schematic diagram of the projection relationship between the first opening and the corresponding window shown in FIG1 ;

[0041] FIG3 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG1 ;

[0042] FIG4 is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application;

[0043] FIG5 is a schematic diagram of the arrangement of an array heat conduction structure provided in an embodiment of the present application;

[0044] FIG6 is a schematic diagram of the arrangement of an array heat conduction structure provided in an embodiment of the present application;

[0045] FIG7 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG4;

[0046] FIG8 is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0047] FIG9 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG8 ;

[0048] FIG10 is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0049] FIG11 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG10;

[0050] FIG12 is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application;

[0051] FIG13 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG12;

[0052] FIG14 is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0053] FIG. 15 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG. 14

[0054] FIG16 is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application;

[0055] FIG17 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG16;

[0056] FIG18 is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0057] FIG19 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG18;

[0058] FIG20 is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application;

[0059] FIG21 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG20;

[0060] FIG22 is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0061] FIG23 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG22;

[0062] FIG24 is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0063] FIG25 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG24;

[0064] FIG26 is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0065] FIG27 is a schematic diagram of the process of manufacturing the embedded substrate shown in FIG26;

[0066] FIG28 is a schematic diagram of an application scenario of a power module provided in an embodiment of the present application;

[0067] FIG29 is a schematic diagram of an application scenario of another power module provided in an embodiment of the present application;

[0068] Figure 30 is a schematic diagram of an electronic setting provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] The embodiments of the present application provide an embedded substrate implementation solution that can achieve high current, high heat dissipation and high reliability, which can be applied to different high-integration and high-density application scenarios.

[0070] Embedded substrate technology, which embeds electronic components within a substrate, shortens the connection paths between components, reduces transmission losses, increases product integration, and reduces module size. Embedded substrate technology can be used in a variety of applications. As product functionality continues to evolve, achieving high current, high heat dissipation, and high reliability have become core requirements for embedded substrates.

[0071] Take the embedded substrate used in the power chip packaging module as an example. A typical embedded substrate architecture, in which the chip and components such as capacitors and / or resistors can be embedded in the core board, and the core board surface is laminated with a build-up layer to achieve interconnection between components and connection to the external circuit. Usually, the pads on the front side (welding surface) of the chip are exposed to the window opening of the PI layer (outer protective layer). Accordingly, a laser process is used to open holes on the build-up layer, and blind holes corresponding to the pads are formed to establish an electrical connection between the chip side and the build-up layer side. Usually, a ring width needs to be reserved between the blind hole and the window opening of the PI layer, and the window size of the chip material is fixed. The diameter of the blind hole formed thereby is smaller than the window size of the chip PI layer, which limits the improvement of the flow capacity and thermal conductivity of the blind hole.

[0072] Based on this, an embodiment of the present application provides an embedded substrate, which includes a core retaining body, a build-up layer and a chip embedded in the core retaining body. The core retaining body includes a first surface and a second surface, and the front of the chip is arranged toward the first surface of the core retaining body. The front of the chip includes an outer protective layer located outside its solder pad, and the outer protective layer has windows arranged corresponding to the solder pads on the chip. The build-up layer includes a front build-up layer covering the first surface of the core retaining body, the front build-up layer includes a front first build-up layer bonded to the first surface of the core retaining body, and the front first build-up layer is bonded to the front of the chip; the front first build-up layer includes a dielectric layer and a circuit layer arranged in a stacked manner, and a first conductive structure electrically connected to the circuit layer is provided in the dielectric layer, and the first conductive structure is arranged corresponding to and electrically connected to the solder pads on the chip. In the embodiment of the present application, the dielectric layer of the front-side first build-up layer is made of an exposable and developable material. Exposure and development are performed to form a first opening for constructing a first conductive structure. The window opening on the outer protective layer has a first projection on the first surface, and the first opening corresponding to the window opening has a second projection on the first surface, with the second projection overlapping the first projection. In this way, the exposure and development process allows for the formation of a relatively large first opening, which is larger than the window opening on the chip's outer protective layer, fully utilizing the chip-side window opening to form the first conductive structure for current flow. For example, but not limited to, the first conductive structure can be a blind via formed using copper plating or electroplating. This arrangement, on the one hand, maximizes the size of the chip-side window opening to construct the first conductive structure, resulting in a larger flow cross-section, effectively improving flow capacity while also providing good thermal conductivity. On the other hand, the formation of the first opening of the first conductive structure through exposure and development avoids the process difficulties associated with traditional laser hole opening, resulting in better manufacturability.

[0073] Furthermore, compared to solutions that improve the substrate's thermal conductivity by plating a copper layer on the chip's front-side outer protective layer (PI layer), in this embodiment, both the dielectric layer of the front-side first build-up layer and the chip-side outer protective layer are made of organic materials. This dielectric layer can reduce the bonding stress between the circuit layer and the chip's front surface, lowering the risk of interlayer interface delamination. Overall, this provides better reliability.

[0074] In order to better understand the technical solution and technical effects of the present application, without loss of generality, a specific embodiment will be described in detail below with reference to the accompanying drawings.

[0075] As shown in Figure 1, the embedded substrate 100 uses a core plate 1 as a core retaining body, and a chip 2 and an electronic component 5 are embedded in the core plate 1. In order to clearly illustrate the basic architectural relationship of the embedded substrate, two chips 2 and two electronic components 5 are illustrated in the figure. In a specific implementation, the number of chips 2 and electronic components 5 can be determined according to the overall design requirements of the product. In addition, in the case of providing multiple electronic components 5, at least one electronic component 5 is a capacitor element or a resistor element. This is not limited in the embodiments of the present application.

[0076] In a specific implementation, the substrate of the core board 1 can be made of organic materials, such as but not limited to FR4, BT, or BT-like materials. Devices such as the chip 2 and electronic components 5 embedded in the embedded grooves on the core board 1 can be assembled and fixed using ABF filling.

[0077] In this embodiment, the front side of the chip 2 is arranged toward the first side 1A of the core board 1, and the outer protective layer on the front side is the PI layer 21, and the PI layer 21 is aligned with the first side 1A of the core board 1. The "aligned arrangement" here includes the situation where the first side 1A of the core board 1 is completely flush with the surface of the PI layer 21, and also includes the situation where the first side 1A of the core board 1 and the surface of the PI layer 21 are close to flush within the tolerance range. Correspondingly, the back side of the chip 2 is arranged toward the first side 1A of the core board 1. There is a window 211 on the PI layer 21, and the window 211 is arranged corresponding to the pad 22 located in the inner layer, and the pad 22 is exposed to the corresponding window 211 to achieve electrical connection with the external circuit.

[0078] In other possible implementations, the outer protective layer may also be made of other organic materials, as long as it can provide physical isolation to prevent oxidation of the chip substrate and meet the functional requirements of the chip's external electrical performance.

[0079] The core board 1 of the embedded substrate 100 is covered with build-up layers on both sides. These build-up layers connect the circuit layers to the embedded components in the core board 1, enabling more complex circuit connections and functions. In this embodiment, the first side 1A of the core board 1 is covered with a front build-up layer T, and the second side 1B of the core board 1 is covered with a back build-up layer B, enabling double-sided interconnection and heat dissipation.

[0080] As shown in Figure 1, the front build-up layer T comprises three layers stacked sequentially: one first front build-up layer 3 and two second front build-up layers 4. The first front build-up layer 3 is located within the inner layer of the front build-up layer T and is bonded to the PI layer 21 on the front of the core board 1 and chip 2, respectively. The second front build-up layer 4 is located on the outer layer of the front build-up layer T relative to the first front build-up layer 3. In a specific implementation, the number of layers of the second front build-up layer 4 can be set as needed, and is not limited to the two layers shown in the figure.

[0081] Each build-up layer includes a dielectric layer and a circuit layer that are stacked together. The circuit layer 32 of the first front build-up layer 3 is stacked on the dielectric layer 31 , and the circuit layer 42 of the second front build-up layer 4 is stacked on the dielectric layer 41 .

[0082] The dielectric layer 31 of the front first build-up layer 3 is made of an exposable and developable material, and the dielectric layer 41 of the front second build-up layer 4 can be made of ABF or PP.

[0083] In a specific implementation, the exposable and developable material can be a dry film, which can be selected based on the overall design of the embedded substrate architecture. Based on the exposure and development characteristics of the material, corresponding openings can be formed in the dielectric layer 31 to form a conductive structure that can realize the corresponding connectivity function; in other words, openings for constructing a conductive structure can be formed in the dielectric layer 31 of the first front build-up layer 3 through exposure and development processes. Here, the layout position of the conductive structure is determined according to the electrical connection requirements between the build-up layer side and the core board 1 side, thereby realizing electrical connection and conduction of the corresponding device or circuit.

[0084] In other possible implementations, the exposable and developable material may also be a liquid photoresist, which may be coated or spin-coated on the core board 1 .

[0085] In this embodiment, for the chip 2 embedded in the core board 1, its pad 22 is connected to the circuit layer 32 of the front build-up layer T through the first conductive structure 33. The pin side of the electronic component 5 is also aligned with the first surface 1A of the core board 1. For the electronic component 5 embedded in the core board 1, its pin can be connected to the circuit layer 32 of the front build-up layer T through the second conductive structure 34. For other interfaces on the first surface of the core board 1, such as but not limited to, the interface pad 111 shown in the figure, it can be connected to the circuit layer 32 of the front build-up layer T through the third conductive structure 35. It can be understood that for the conductive structure of each configuration function, corresponding openings can be formed at the location of the conductive structure through exposure and development processes. In a specific implementation, it can be a blind hole or a copper pillar. This embodiment is specifically described with a conductive structure in the form of a blind hole.

[0086] Among them, on the dielectric layer 31 of the first front build-up layer 3, the opening used to construct the first conductive structure 33 is the first opening 311, and the second projection of the first opening 311 on the first surface 1A covers the first projection of the corresponding window 211 of the PI layer 21 on the first surface 1A.

[0087] The "first surface" here is a reference surface used to illustrate the comparison relationship between the first opening and the corresponding window size. The reference plane can also be other reference surfaces parallel to the first surface. It should be understood that the first surface as a reference plane does not constitute a substantial limitation on the core board described in this embodiment.

[0088] The "coverage" here includes the situation where the first projected outline d of the window 211 on the first surface 1A is completely within the second projected outline D of the first opening 311 on the first surface 1A, and also includes the situation where the first projected outline d of the window 211 on the first surface 1A partially overlaps with the second projected outline D of the first opening 311 on the first surface 1A, for example but not limited to, the two projected outlines have a local overlapping point, or the two projected outlines have a local overlapping line segment.

[0089] Please also refer to Figure 2, which shows a schematic diagram of the projection relationship between the first opening 311 and the corresponding window 211 of the PI layer. Figure 2 uses a set of correspondingly arranged first openings 311 and windows 211 as an example to illustrate the projection relationship between the two. For ease of description, the cross-sections of the first openings 311 and windows 211 shown in the figure are both circular.

[0090] In a possible implementation, the cross-sectional shape of the first opening 311 and the window 211 may be an ellipse, a rectangle, or other polygons, or may be an irregular shape according to the actual layout of the panel space, which is not limited in the present embodiment.

[0091] In addition, as shown in FIG2 , the second projection of the first opening 311 coincides with the center of the first projection of the window 211. In other possible implementations, as long as the second projection of the first opening 311 on the dielectric layer 31 of the front first build-up layer 3 covers the first projection of the corresponding window 211 on the PI layer 21, the relative positional relationship between the second projection of the first opening 311 and the first projection of the window 211 within the reference plane may also be non-centrally coincident. This is not limited in the present embodiment.

[0092] As shown in Figure 1 , the back build-up layer B in this embodiment includes three build-up layers. The first back build-up layer 7 is located within the back build-up layer B and is bonded to the second surface of the core board 1. The other two build-up layers are sequentially stacked on the first back build-up layer 7. Each build-up layer includes a stacked dielectric layer and a circuit layer. The dielectric layers of each build-up layer in the back build-up layer B can be made of ABF. That is, the dielectric layers of each build-up layer in the back build-up layer B can be made of the same material configuration as the second front build-up layer 4 on the side of the front build-up layer T.

[0093] In a specific implementation, the specific number of layers of the front build-up layer T and the back build-up layer B can be determined according to product design requirements, and is not limited to the three layers shown in the figure.

[0094] In other possible implementations, the backside build-up layer B may be selectively provided as needed.

[0095] In this embodiment, a PTH through-hole 11 is provided on the substrate of the core board 1 to achieve electrical connectivity between the first side 1A and the second side 1B of the core board 1, providing power supply, signal transmission, and heat conduction. The PTH through-hole 11 can be formed using a brushing and electroplating process, resulting in a smooth opening. This provides good processability and manageable costs. Thus, the PTH through-hole 11 enables reliable blind via stacking, facilitating the rapid transmission of signals, heat, and current.

[0096] The following briefly describes the process of manufacturing the embedded substrate 100 described in FIG. 1 with reference to FIG. 3 .

[0097] Step S301: preparing a core board 1.

[0098] First, after the organic core board is received, holes are drilled at the locations where the PTH through-holes 11 are to be formed, and the adhesive is removed. Next, the PTH through-holes 11 are electroplated using a copper deposition process, and then plugged and brushed. In specific implementations, this can be done with resin plugging or conductive copper paste. Then, after a seed layer is formed on the board surface, top copper is electroplated. In specific implementations, this seed layer can be formed using a copper deposition process or sputtering. Finally, the top copper layer is patterned to form the interface pads 111.

[0099] Step S302: Preparation for embedding and mounting.

[0100] An embedded groove 1-1 is formed on the core board 1 and then debonded. In practice, this can be done using a UV laser, CO2 laser, or other mechanical process. Then, a tape 1-2 is applied to the first surface 1A of the core board 1.

[0101] Step S303: Mounting chips and electronic components, and pressing and filling.

[0102] Specifically, the chip 2 and electronic component 5 are placed within the embedding groove 1-1 and mounted on the adhesive film 1-2. Here, the electronic component 5 can be a capacitor, resistor, or inductor. Next, a filling and pressing operation is performed. The embedding filler material 1-3 can be ABF, or other materials selected according to actual process conditions.

[0103] Here, while laminating and filling the gaps between the components and between the components and the embedded grooves, the embedded filling material 1-3 also forms a dielectric layer 71 of the back first build-up layer 7 bonded to the second surface 1B of the core board 1. The back first build-up layer 7 here, that is, the build-up layer structure of the back build-up layer B bonded to the second surface of the core board 1.

[0104] Step S304 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0105] The adhesive film 1 - 2 is removed, and the exposable and developable material is pressed onto the core board 1 to form a dielectric layer 31 , which is then bonded to the front surface of the chip 2 and the electronic component 5 .

[0106] Step S305: forming holes on the front side and forming holes on the back side by using exposure and development processes.

[0107] Specifically, on the dielectric layer 31 of the first front build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through-hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to form a conductive structure.

[0108] Based on the laser hole forming process, a third opening 313 is formed on the embedded filling material layers 1 to 3 on the back side of the chip 2 , corresponding to the interface pad 111 of the PTH through hole 11 .

[0109] Step S306 , forming each conductive structure, and the surface copper of the first front build-up layer and the first back build-up layer.

[0110] First, a debonding process is performed, followed by forming a seed layer. In practice, this can be achieved by copper plating or sputtering. Then, the walls of the first opening 311, second opening 312, and third opening 313 are electroplated to form conductive blind vias, forming the first conductive structure 33, second conductive structure 34, and third conductive structure 35, respectively.

[0111] At the same time, copper is electroplated on the front and back surfaces. The front copper layer is used to form the circuit layer 32 of the front first build-up layer, and the back copper layer is used to form the circuit layer 72 of the back first build-up layer.

[0112] Step S307 , patterning the front copper layer and the back copper layer.

[0113] After the surface treatment, lamination, exposure, development, etching and stripping processes may be performed in sequence to form corresponding circuit layers, thereby completing the front first build-up layer 3 and the back first build-up layer 7 .

[0114] Step S308 , forming the outer layers of the front build-up layer T and the back build-up layer B, forming the outer solder resist layer 6 at the same time, and processing the surface of the outer metal layer.

[0115] In a specific implementation, the number of layers of each outer layer can be determined according to the overall design requirements of the product, and corresponding process steps can be formulated. This embodiment of the present application is not limited thereto.

[0116] To further enhance the backside thermal conductivity of the chip, a corresponding heat conducting portion can be provided on the backside of the chip in other specific implementations. Please refer to Figure 4, which is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application. To clearly illustrate the differences and connections between this embodiment and the embodiment described in Figure 1, components or structures with the same functions are indicated with the same reference numerals in the figure.

[0117] As shown in FIG4 , the core board 1 of the embedded substrate 100a has a chip 2a and an electronic component 5 embedded therein. The front surface of the chip 2a faces the first surface 1A of the core board 1, and the PI layer 21 on the front surface of the chip 2a is aligned with the first surface 1A of the core board 1. The first surface 1A of the core board 1 is covered with a front build-up layer T, and the second surface 1B of the core board 1 is covered with a back build-up layer B.

[0118] The dielectric layer 31 of the front first build-up layer 3 is made of an exposable and developable material, and the dielectric layer 41 of the front second build-up layer 4 can be made of ABF; similarly, the dielectric layers of each build-up layer of the back build-up layer B can also be made of ABF.

[0119] The pad 22 of the chip 2a is connected to the circuit layer 32 of the front build-up layer T via a first conductive structure 33. On the dielectric layer 31 of the first front build-up layer 3, the opening for constructing the first conductive structure 33 is a first opening 311. The second projection of the first opening 311 on the first surface 1A covers the first projection of the corresponding window 211 of the PI layer 21 on the first surface 1A.

[0120] This allows the first conductive structure 33 to be constructed using the maximum possible size of the first opening 311 on the chip 2a side. The first conductive structure 33, with its larger flow cross-section, also offers excellent thermal conductivity. Furthermore, because the dielectric layer 31 of the front-side first build-up layer 3 and the PI layer 21 on the chip 2a side have similar material thermal expansion coefficients, the bonding stress between the circuit layer and the front side of the chip 2a can be reduced.

[0121] In this embodiment, the pins of the electronic components 5 embedded in the core board 1 can be connected to the circuit layer 32 of the front build-up layer T through the second conductive structure 34. The substrate of the core board 1 is provided with a PTH through-hole 11, which is connected to the circuit layers of the front build-up layer T and the back build-up layer B through the pads at both ends.

[0122] As shown in the figure, the backside of chip 2a abuts against the array of thermally conductive structures 8. In this embodiment, the inner end of each thermally conductive structure 8 abuts against the back copper layer 23 of chip 2a, while the outer end of each thermally conductive structure 8 extends to the surface of the back build-up layer B. As a result, the thermally conductive portion formed by the array of thermally conductive structures 8 effectively reduces the Z-direction thermal resistance of the backside of chip 2a, quickly dissipating heat generated by the chip, and exhibiting excellent high thermal conductivity.

[0123] In a specific implementation, the back copper layer 23 of the chip 2a can be the back copper layer that is already set when the chip leaves the factory, or the back copper layer of the chip can be formed during the memory module manufacturing process, which provides better chip selectivity. The specific method can be determined based on the specific product design and process conditions, and is not limited in the present embodiment.

[0124] Of course, the back copper layer 23 is an optional structural layer. That is, even without a back copper layer on the back of the chip 2a, the heat generated by the chip can still be quickly dissipated through the heat conduction portion. In comparison, for a chip 2a with a back copper layer 23, the back copper layer 23 provides excellent heat dissipation, further improving the backside thermal conductivity and lowering the chip's operating temperature. For example, in a power module, this can improve power efficiency.

[0125] The array-arranged heat-conducting structure 8 can adopt different structural forms in specific implementations. The following illustrates two structural forms of array heat-conducting structures from the perspective of the AA section in FIG4 .

[0126] Please refer to Figure 5, which shows a schematic diagram of the arrangement of the array of thermally conductive blind vias. As an example, Figure 5 shows that the array of thermally conductive blind vias 8a is arranged in four rows and four columns relative to the back copper layer 23 of the chip. In other possible implementations, the array of thermally conductive blind vias 8a can be determined as needed. For example, but not limited to, the array of thermally conductive blind vias (Cu) can account for 10% of the width of the chip back surface, rather than being limited to the configuration shown in Figure 5.

[0127] Please refer to Figure 6, which shows a schematic diagram of the arrangement of the array of thermally conductive copper strips. As an example, Figure 6 shows the arrangement of the thermally conductive copper strips 8b in five rows, one in each column, relative to the chip's back copper layer 23. In other possible implementations, the arrangement of the array of thermally conductive copper strips 8b can be customized as needed. For example, but not limited to, the array of thermally conductive copper strips (Cu) can comprise 30% of the chip's back surface area, rather than being limited to the configuration shown in Figure 6.

[0128] The following briefly describes the process of manufacturing the embedded substrate 100 a described in FIG. 4 in conjunction with FIG. 7 .

[0129] Step S701: preparing a core board.

[0130] Step S702: Preparation for embedding and mounting.

[0131] Step S703: Mount the chips and electronic components, and press and fill them.

[0132] Step S704 , laminating the dielectric layer of the first front build-up layer.

[0133] For the above steps S701 to S704 , please refer to the process diagram of steps S301 to S304 in FIG3 .

[0134] Step S705: forming holes on the front side by exposure and development process; and forming holes on the back side.

[0135] Through exposure and development processes, a first opening 311 is formed in the dielectric layer 31 of the first front build-up layer 3, corresponding to the pad 22 of the chip 2a; a second opening 312 is formed corresponding to the pin of the electronic component 5; and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through-hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings, thereby forming the corresponding conductive structure.

[0136] Using a laser hole forming process, fourth openings 314 are formed on the layers 1-3 of the embedded filler material on the back side of chip 2a, corresponding to the array thermal conductive structure, to construct the corresponding thermal conductive structure 8. In a specific implementation, fourth openings of appropriate size and shape can be formed for the thermal conductive blind vias or thermal conductive copper strips.

[0137] Step S706 , forming each conductive structure and the heat-conducting structure arranged in an array, as well as the surface copper of the front first build-up layer and the back first build-up layer.

[0138] First, a debonding process is performed, followed by forming a seed layer. In practice, this can be achieved using copper plating or sputtering. Then, the walls of the first, second, and third openings 311, 312, and 313 are electroplated to form conductive blind vias, forming the first, second, and third conductive structures 33, 34, and 35, respectively. Furthermore, the fourth opening 314 is electroplated to form the array of thermally conductive structures 8.

[0139] At the same time, copper is electroplated on the front and back surfaces. The front copper layer is used to form the circuit layer 32 of the front first build-up layer, and the back copper layer is used to form the circuit layer 72 of the back first build-up layer.

[0140] Step S707 , patterning the front copper layer and the back copper layer. Referring to the process diagram of step S307 in FIG3 , corresponding circuit layers are formed, completing the front first build-up layer 3 and the back first build-up layer 7 .

[0141] Step S708 , forming the outer layers of the front build-up layer T and the back build-up layer B, forming the outer solder resist layer 6 at the same time, and processing the surface of the outer metal layer.

[0142] In a specific implementation, the number of layers of each outer layer can be determined according to the overall design requirements of the product, and corresponding process steps can be formulated. This embodiment of the present application is not limited thereto.

[0143] In the embedded substrate architecture described in FIG4 , an array of heat-conducting structures serves as a heat-conducting portion to reduce Z-direction thermal resistance. In other implementations, a heat-conducting portion in the form of a copper block structure can be provided on the back of the chip. See FIG8 for a cross-sectional view of another embedded substrate architecture provided in this embodiment of the present application. To clearly illustrate the differences and connections between this embodiment and the embodiment described in FIG4 , components or structures with the same functions are indicated in the figure with the same reference numerals.

[0144] As shown in Figure 8, the embedded substrate 100b has a chip 2a and electronic components 5 embedded in the core board 1b. The front surface of the chip 2a faces the first surface 1A of the core board 1b, and the PI layer 21 on the front surface is aligned with the first surface 1A of the core board 1b. The first surface 1A of the core board 1b is covered with a front build-up layer T, and the second surface 1B of the core board 1b is covered with a back build-up layer B.

[0145] Similarly, the dielectric layer 31 of the front first build-up layer 3 is made of an exposable and developable material, the dielectric layer 41 of the front second build-up layer 4 can be made of ABF; the dielectric layers of each build-up layer of the back build-up layer B can also be made of ABF.

[0146] The pads 22 of chip 2a are connected to the circuit layer 32 of the front build-up layer T via a first conductive structure 33. The openings used to construct the first conductive structure 33 are first openings 311 in the dielectric layer 31 of the front first build-up layer 3. The second projection of the first opening 311 on the first surface 1A overlaps the first projection of the corresponding window 211 in the PI layer 21 on the first surface 1A. This maximizes the size of the first opening 311 on the chip 2a side to construct the first conductive structure 33. The first conductive structure 33, with its larger flow cross-section, also offers excellent thermal conductivity. Furthermore, it reduces the bonding stress between the circuit layer and the front surface of chip 2a.

[0147] Compared with the embedded substrate described in Figure 4, the difference of this embodiment is that the heat conducting part on the back of the chip 2a is a heat conducting copper block 8c, and the base of the core board 1b includes a multi-layer circuit layer 11b to have large flow capacity and high thermal conductivity.

[0148] As shown in the figure, the back surface of chip 2a abuts against thermally conductive copper block 8c. The inner end of thermally conductive copper block 8c abuts against the back copper layer 23 of chip 2a, while the outer end extends to the surface of back build-up layer B. Thus, heat generated by the chip is quickly conducted away through thermally conductive copper block 8c.

[0149] In this embodiment, the pins of the electronic components 5 embedded in the core board 1b can be connected to the circuit layer 32 of the front build-up layer T through the second conductive structure 34. For the multi-layer circuit layer 11b provided on the substrate of the core board 1b, for example but not limited to, the layers can be connected through copper-filled blind vias 111b and X-shaped vias 112b. On the basis of having large flow and high thermal conductivity, layer-changing routing can be achieved in the substrate of the core board 1b as needed, making the architectural design more flexible.

[0150] The following briefly describes the process of manufacturing the embedded substrate 100 b described in FIG. 8 in conjunction with FIG. 9 .

[0151] Step S901: preparing a core board 1b.

[0152] First, after the core board intermediate layer has been received, an X-shaped hole is machined at the location where the X-shaped hole 112b is formed. This hole is then filled with electroplating and the surface copper is formed. The surface of the intermediate layer is then patterned. For example, lamination, exposure, development, etching, and stripping processes can be performed in sequence to obtain the corresponding circuit layer. Then, based on the core board intermediate layer, the build-up layer is completed and pressed. Blind holes are machined at the location where the blind holes 111b are formed. This hole is then filled with electroplating and the surface copper is formed. This is then patterned. Finally, after all the build-up layers are completed, the surface copper layer is patterned to form the interface pad 111.

[0153] It should be noted that the substrates of the core board 1b can be made of organic materials, such as but not limited to FR4, BT or BT-like materials. The above steps can be implemented using existing technologies and will not be described in detail here.

[0154] Step S902: Preparation for embedding and mounting.

[0155] A groove 1-1 is embedded in the core board 1b and the adhesive is removed. In a specific implementation, the groove can be cut using UV laser, CO2 laser or other mechanical processing. Then, an adhesive film 1-2 is applied to the first surface 1A of the core board 1b.

[0156] Step S903: Mounting chips and electronic components, and pressing and filling.

[0157] The chip 2a and electronic component 5 are placed within the embedding groove 1-1 and mounted on the front side of the adhesive film 1-2, followed by a filling and pressing operation. The embedding filler material 1-3 may be ABF. While filling the gaps between the components and between the components and the embedding groove, the embedding filler material 1-3 also forms the dielectric layer 71 of the back first build-up layer 7 bonded to the second surface 1B of the core board 1b.

[0158] Step S904 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0159] The adhesive film 1 - 2 is removed, and the dielectric layer 31 made of an exposable and developable material is pressed onto the core board 1 b and bonded to the front surface of the chip 2 a and the electronic component 5 .

[0160] Step S905: forming holes on the front side by exposure and development processes.

[0161] Through exposure and development processes, a first opening 311 is formed in the dielectric layer 31 of the front first build-up layer 3, corresponding to the pad 22 of the chip 2a; a second opening 312 is formed corresponding to the pin of the electronic component 5; and a third opening 313 is formed corresponding to the interface pad 111 of the multi-layer circuit layer 11b. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings, thereby forming the corresponding conductive structure.

[0162] Based on the laser hole forming process, a fourth opening 314b is formed on the embedded filling material layers 1-3 on the back side of the chip 2a, corresponding to the thermal conductive copper block 8c, so as to construct the corresponding thermal conductive copper block 8c.

[0163] Step S906 , forming each conductive structure, and the surface copper of the first front build-up layer and the first back build-up layer.

[0164] First, a debonding process is performed to form a seed layer, and then the walls of the first opening 311, the second opening 312, and the third opening 313 are electroplated to form conductive blind vias, forming the first conductive structure 33, the second conductive structure 34, and the third conductive structure 35, respectively.

[0165] At the same time, copper is electroplated on the front and back surfaces. The front copper layer is used to form the circuit layer 32 of the front first build-up layer, and the back copper layer is electroplated on the wall surface of the fourth opening 314b.

[0166] Step S907: filling the fourth opening on the back side by electroplating.

[0167] Based on the blind slot filling electroplating process, a thermal conductive copper block 8c is formed in the fourth opening 314b.

[0168] Step S908 , patterning the front copper layer and the back copper layer.

[0169] After the surface treatment, lamination, exposure, development, etching and stripping processes can be performed in sequence to form the corresponding circuit layer.

[0170] Step S909 , forming the outer build-up layer of the front build-up layer and the back build-up layer, forming the outer solder resist layer, and processing the surface of the outer metal layer.

[0171] The number of layers of each outer layer can be determined according to the overall design requirements of the product and the corresponding process steps can be formulated.

[0172] In the embedded substrate architectures described in Figures 4 and 8 above, the heat conducting portions are in contact with the chip's back copper layer. In other possible implementations, the heat conducting portions may directly contact the chip's back surface. Please refer to Figure 10, which is a cross-sectional view of another embedded substrate architecture provided in an embodiment of the present application. To clearly illustrate the differences and connections between this embodiment and the embodiment described in Figure 8, components or structures with the same functions are indicated in the figure with the same reference numerals.

[0173] As shown in Figure 10 , the embedded substrate 100c has a chip 2 and electronic components 5 embedded within its core 1b. Compared to the embedded substrate described in Figure 8 , this embodiment differs in that the backside of the chip 2 lacks a backing copper layer, and instead, a heat-conducting copper block 8c, acting as a heat conductor, abuts the backside of the chip 2.

[0174] The other structures and connection relationships of the embedded substrate 100c may be the same as those of the embedded substrate shown in FIG8 , and will not be described in detail here.

[0175] The following briefly describes the process of manufacturing the embedded substrate 100 c described in FIG. 10 in conjunction with FIG. 11 .

[0176] Step S1101: preparing a core board.

[0177] Step S1102: Preparation for embedding and mounting.

[0178] For the above steps S1101 to S1102 , please refer to the process diagram of steps S901 to S902 in FIG. 9 .

[0179] Step S1103: Mount the chips and electronic components, and press and fill them.

[0180] The front sides of the chip 2 and electronic components 5 are mounted on the adhesive film 1-2, followed by a filling and lamination operation. The embedded filler material 1-3 may be ABF. While filling the gaps between components and between the components and the embedded slots, the embedded filler material 1-3 also forms a dielectric layer 81 of the backside first build-up layer 7, which is bonded to the second side 1B of the core board 1b. Next, a surface copper layer is electroplated on this dielectric layer 81 to form the circuit layer 82 of the backside first build-up layer 7.

[0181] Step S1104 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0182] The adhesive film 1 - 2 is removed, and the dielectric layer 31 made of an exposable and developable material is pressed onto the core board 1 b and bonded to the front surface of the chip 2 and the electronic component 5 .

[0183] Step S1105: forming holes on the front side by exposure and development processes.

[0184] Through exposure and development processes, a first opening 311 is formed on the dielectric layer 31 of the front first build-up layer 3, corresponding to the pad 22 of the chip 2; a second opening 312 is formed corresponding to the pin of the electronic component 5; and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through-hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings, thereby forming the corresponding conductive structure.

[0185] Step S1106 , forming each conductive structure and the surface copper of the first build-up layer on the front side.

[0186] First, a debonding process is performed to form a seed layer. Then, the walls of the first, second, and third openings 311, 312, and 313 are electroplated to form conductive blind vias, forming the first, second, and third conductive structures 33, 34, and 35, respectively. Simultaneously, copper is electroplated on the front surface, which is used to form the circuit layer 32 of the first front build-up layer.

[0187] Step S1107, forming a hole on the back side.

[0188] Based on the plasma process, holes are formed in the embedded filling material layers 1-3 on the back side and the copper layer on the back side of the core board 1b. In other specific implementations, laser or mechanical hole forming processes can also be used.

[0189] A fourth opening 314b is formed corresponding to the thermally conductive copper block 8c to construct the corresponding thermally conductive copper block 8c; a third opening 313 is formed corresponding to the interface pad 111 of the multi-layer circuit layer 11b to construct the third conductive structure 35.

[0190] Step S1108: Fill the third opening and the fourth opening on the back side by electroplating.

[0191] Based on the electroplating blind slot filling process, a three-conducting structure 35 is formed in the third opening 313, and a heat-conducting copper block 8c is formed in the fourth opening 314b. The blind holes are filled with electroplating, and the blind slots are filled with electroplating.

[0192] Step S1109: patterning the front copper layer and the back copper layer.

[0193] After the surface treatment, lamination, exposure, development, etching and stripping processes can be performed in sequence to form the corresponding circuit layer.

[0194] Step S1110 , forming the outer build-up layer of the front build-up layer and the back build-up layer, forming the outer solder resist layer, and processing the surface of the outer metal layer.

[0195] The number of layers of each outer layer can be determined according to the overall design requirements of the product and the corresponding process steps can be formulated.

[0196] In the embedded substrate architecture described in the aforementioned Figures 1, 4, 8 and 10, the front PI layer 21 of the chip and the pin side of the electronic component 5 are aligned with the first side of the core board. In other specific implementations, the chips and electronic components embedded in the core board can also be arranged in a manner where the back side is aligned with the second side of the core board. Please refer to Figure 12, which is a cross-sectional view of the architecture of another embedded substrate provided in an embodiment of the present application. In order to clearly illustrate the difference and connection between this embodiment and the embodiment described in Figure 8, the components or structures with the same functions are illustrated in the figure with the same mark.

[0197] As shown in Figure 12, the embedded substrate 100d has a core board 1b embedded with a chip 2 and an electronic component 5. Compared to the embedded substrate described in Figure 8, this embodiment differs in that the back surfaces of the chip 2 and the electronic component 5 are aligned with the second surface 1B of the core board 1b.

[0198] The chip 2 is sunken into the heat-conducting copper block 8c, and the back copper layer 23 on the back of the chip 2 serves as a direct support layer for blind vias. In a specific implementation, the gaps between the devices (chip 2 and electronic components 5) and between the devices and the embedded grooves of the core board 1b can be filled with a photosensitive and developable material or an ABF material.

[0199] The other structures and connection relationships of the embedded substrate 100d may be the same as those of the embedded substrate shown in FIG8 , and will not be described in detail here.

[0200] 13 and taking the exposeable and developable material as the embedded filling material 1-3 as an example, the process of the embedded substrate 100d described in FIG. 12 will be briefly described.

[0201] Step S1301: preparing a core board.

[0202] Step S1302: prepare for embedded mounting, and stick the adhesive film on the second side of the core board.

[0203] For the above steps S1301 to S1302 , please refer to the process diagram of steps S901 to S902 in FIG. 9 .

[0204] Step S1303: mounting chips and electronic components.

[0205] The chip 2 and the electronic component 5 are embedded in the embedding groove 1-1 of the core board 1b, and the back side is mounted on the adhesive film 1-2.

[0206] Step S1304: pressing and filling.

[0207] Exposible and developable materials are used as embedded filling materials 1-3 to fill gaps between devices and between devices and embedded grooves, thereby forming a dielectric layer 31 of the front first build-up layer 3.

[0208] Step S1305: forming holes on the front side by exposure and development processes.

[0209] Through exposure and development processes, a first opening 311 is formed on the dielectric layer 31 of the front first build-up layer 3, corresponding to the pad 22 of the chip 2; a second opening 312 is formed corresponding to the pin of the electronic component 5; and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through-hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings, thereby forming the corresponding conductive structure.

[0210] Step S1306 , forming each conductive structure and the surface copper of the first build-up layer on the front side.

[0211] After removing the adhesive films 1-2, a seed layer is first formed. Then, the walls of the first, second, and third openings 311, 312, and 313 are electroplated to form conductive blind vias, forming the first, second, and third conductive structures 33, 34, and 35, respectively. Simultaneously, copper is electroplated on the front surface. This copper layer is used to form the circuit layer 32 of the first front build-up layer.

[0212] Step S1307: forming a back copper layer on the back side of the chip.

[0213] A sputtering process or an electroplating process is used on the back side to form a copper layer on the chip 2 , and then patterning is performed to form a back copper layer 23 .

[0214] Step S1308: forming a hole on the back side.

[0215] Holes are formed on the layers 1-3 of the embedded filling material on the back side and the copper layer on the back side of the core board 1b by laser drilling. In other specific implementations, plasma drilling or mechanical drilling processes can also be used.

[0216] A fourth opening 314b is formed corresponding to the thermally conductive copper block 8c to construct the corresponding thermally conductive copper block 8c; a third opening 313 is formed corresponding to the interface pad 111 of the multi-layer circuit layer 11b to construct the third conductive structure 35.

[0217] Step S1309 , forming a third conductive structure and a thermal conductive copper block on the back side, as well as the surface copper of the first build-up layer on the back side.

[0218] Specifically, a seed layer may be formed first; in a specific implementation, a copper plating or sputtering process may be used to form the seed layer. Then, the walls of the third opening 313 and the fourth opening 314b are electroplated to form the third conductive structure 35 and the thermal conductive copper block 314c.

[0219] At the same time, surface copper is formed by electroplating on the back surface, and the surface copper layer on the back surface is used to form the circuit layer 72 of the first build-up layer on the back surface.

[0220] Step S1310: patterning the front copper layer and the back copper layer.

[0221] After the surface treatment, lamination, exposure, development, etching and stripping processes may be used to form corresponding circuit layers, thereby completing the front first build-up layer 3 and the back first build-up layer 7 .

[0222] Step S1311 , forming the outer build-up layer of the front build-up layer and the back build-up layer, forming the outer solder resist layer, and processing the surface of the outer metal layer.

[0223] The number of layers of each outer layer can be determined according to the overall design requirements of the product and the corresponding process steps can be formulated.

[0224] In the embedded substrate architecture described in FIG12 above, the gaps between the devices and between the devices and the embedded grooves of the core board can be made of an exposeable and developable material as the embedding material. In other possible implementations, the dielectric layer of the first back-side build-up layer on the back side of the core board can also be made of an exposeable and developable material. Please refer to FIG14, which is a cross-sectional view of the architecture of another embedded substrate provided in an embodiment of the present application. In order to clearly illustrate the difference and connection between this embodiment and the embodiment described in FIG12, the components or structures with the same functions are illustrated in the figure with the same mark.

[0225] As shown in FIG14 , the core board 1b of the embedded substrate 100e is embedded with a chip 2 and an electronic component 5. Both sides of the core board 1b include three build-up layers, wherein the front build-up layer T includes three layers stacked in sequence, namely, one first front build-up layer 3 and two second front build-up layers 4. The back build-up layer B includes three layers stacked in sequence, namely, one first back build-up layer 7 and two second back build-up layers 9. Relative to the first back build-up layer 7, the second back build-up layer 9 is located on the outer layer of the back build-up layer B. In a specific implementation, the number of layers of the second back build-up layer 9 can be set as needed, rather than being limited to the two layers shown in the figure.

[0226] Compared with the embedded substrate described in Figure 12, the difference of this embodiment is that the front of the chip 2 and the electronic component 5 are aligned with the first surface 1A of the core board 1b, and at the same time, the dielectric layer 71 of the first build-up layer 7 on the back is made of an exposeable and developable material.

[0227] This chip 2 has no back copper layer. The thermally conductive copper block 8c, which serves as the heat conducting portion, and the third opening 312 on the back of the core board 1b are both formed using an exposure and development process, which improves processability. In a specific implementation, the other layers of the front build-up layer T and the back build-up layer B (the front second build-up layer 4 and the back second build-up layer 9) can be made of ABF material as the dielectric layer.

[0228] The other structures and connection relationships of the embedded substrate 100e may be the same as those of the embedded substrate shown in FIG12 , and will not be described in detail here.

[0229] The following briefly describes the process of the embedded substrate 100e described in FIG. 14 with reference to FIG. 15 .

[0230] Step S1501: prepare a core board.

[0231] Step S1502: Preparation for embedding and mounting.

[0232] For the above steps S1501 to S1502 , please refer to the process diagram of steps S901 to S902 in FIG. 9 .

[0233] Step S1503: Mount the chips and electronic components, and press and fill them.

[0234] Chip 2 and electronic components 5 are embedded in embedding groove 1-1 of core board 1b and mounted on adhesive film 1-2 from the front. Exposible and developable material is used as embedding filler material 1-3, filling the gaps between components and between the components and the embedding grooves while forming dielectric layer 71 of first build-up layer 7 on the back side.

[0235] Step S1504 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0236] The adhesive film 1 - 2 is removed, and the exposable and developable material is pressed onto the core board 1 b to form a dielectric layer 31 , which is then bonded to the front surface of the chip 2 and the electronic component 5 .

[0237] Step S1505: forming holes by exposure and development processes.

[0238] Based on the exposure and development process, a first opening 311 is formed on the dielectric layer 31 of the first build-up layer 3 on the front side, corresponding to the pad 22 of the chip 2, and a second opening 312 is formed corresponding to the pin of the electronic component 5; a third opening 313 is formed corresponding to the interface pad 111 of the multi-layer circuit layer 11b; and a fourth opening 314b is formed on the embedded filling material layers 1-3 on the back side of the chip 2, corresponding to the thermally conductive copper block, and the back side of the chip 2 is exposed in the fourth opening 314b.

[0239] Step S1506 , forming each conductive structure, and the surface copper of the first front build-up layer and the first back build-up layer.

[0240] First, a seed layer is formed. Then, the walls of the first, second, and third openings 311, 312, and 313 are electroplated to form conductive blind vias, forming the first, second, and third conductive structures 33, 34, and 35, respectively. The fourth opening 314 is electroplated to form a thermally conductive copper block 8c. Simultaneously, surface copper is plated on the front and back surfaces. The front surface copper layer is used to form the circuit layer 32 of the first front build-up layer, while the back surface copper layer is used to form the circuit layer 72 of the first back build-up layer.

[0241] Step S1507: patterning the front copper layer and the back copper layer.

[0242] After the surface treatment, lamination, exposure, development, etching and stripping processes may be used to form corresponding circuit layers, thereby completing the front first build-up layer 3 and the back first build-up layer 7 .

[0243] Step S1508 , forming the outer build-up layer of the front build-up layer and the back build-up layer, forming the outer solder resist layer, and processing the surface of the outer metal layer.

[0244] In the embedded substrate architecture described in FIG14 , except for the front first build-up layer 3 and the back first build-up layer 7, all other build-up layers in the front build-up layer T and the back build-up layer B are made of ABF material. In other possible implementations, the dielectric layers in the front build-up layer T and the other build-up layers in the back build-up layer B can also be made of an exposeable and developable material. Please refer to FIG16 , which is a cross-sectional view of another embedded substrate architecture provided in an embodiment of the present application. To clearly illustrate the differences and connections between this embodiment and the embodiment described in FIG14 , components or structures with the same functions are indicated in the figure with the same reference numerals.

[0245] As shown in Figure 16, the embedded substrate 100f has a chip 2 and electronic components 5 embedded within its core 1b. Both sides of the core 1b include three build-up layers. The dielectric layers of the front build-up layers T and back build-up layers B are made of an exposable and developable material. This arrangement allows the outer blind vias and blind slots to be formed through an exposure and development process, resulting in higher efficiency.

[0246] The other structures and connection relationships of the embedded substrate 100f may be the same as those of the embedded substrate shown in FIG14 , and will not be described in detail here.

[0247] The following briefly describes the process of the embedded substrate 100f described in FIG. 16 with reference to FIG. 17 .

[0248] Step S1701: prepare a core board.

[0249] Step S1702: Preparation for embedding and mounting.

[0250] Step S1703: Mount the chips and electronic components, and press and fill them.

[0251] Step S1704 , laminating the dielectric layer of the first front build-up layer.

[0252] Step S1705: forming holes by exposure and development processes.

[0253] Step S1706 , forming each conductive structure, and the surface copper of the first front build-up layer and the first back build-up layer.

[0254] Step S1707: patterning the front copper layer and the back copper layer.

[0255] For the above steps S1701 to S1707 , please refer to the process diagram of steps S1501 to S1507 in FIG9 .

[0256] Step S1708 , laminating to form dielectric layers of the front second build-up layer and the back second build-up layer, and forming holes by exposure and development processes.

[0257] Based on the exposure and development process, corresponding openings are formed on the dielectric layer 41 of the second build-up layer on the front side and the dielectric layer 91 of the second build-up layer on the back side, respectively, to construct the circuit layer and thermal conductive copper block 8c structure of the corresponding build-up layer.

[0258] Step S1709 , forming circuit layers of the front second build-up layer and the back second build-up layer.

[0259] In a specific implementation, an electroplating process can be used to form a copper layer on the front and back sides respectively. After surface treatment, lamination, exposure, development, etching and stripping processes can be used to form the corresponding circuit layers to complete the production of the second build-up layer 4 on the front side and the second build-up layer 9 on the back side.

[0260] Step S1710 , forming other outer build-up layers of the front build-up layer and the back build-up layer, forming an outer solder resist layer, and processing the surface of the outer metal layer.

[0261] The formation of the front build-up layer and the other outer build-up layers of the back build-up layer can be seen in the process diagrams of steps S1708 to S1709, which will not be described in detail here.

[0262] In the embedded substrate architecture described in FIG4 , except for the front first build-up layer 3, all other build-up layers of the front build-up layer T and all back build-up layers B are made of ABF material. In other possible implementations, the dielectric layers of the other build-up layers of the front build-up layer T and all back build-up layers B can also be made of PP material. Please refer to FIG18 , which is a cross-sectional view of another embedded substrate architecture provided in an embodiment of the present application. To clearly illustrate the differences and connections between this embodiment and the embodiment described in FIG4 , components or structures with the same functions are indicated in the figure with the same reference numerals.

[0263] As shown in Figure 18, the core board 1b of the embedded substrate 100g is embedded with a chip 2 and an electronic component 5. The embedding material between each device and between the device and the embedding groove of the core board can be ABF. Both sides of the core board 1b include three build-up layers, among which the outer layer of the front build-up layer T (the second front build-up layer 4) and the dielectric layer of each build-up layer of the back build-up layer B (the first back build-up layer 7 and the second back build-up layer 9) are made of PP material. In this way, compared with ABF material, PP material has good strength and high temperature resistance, and the overall strength of the substrate is enhanced.

[0264] In this embodiment, the backside of chip 2a abuts against the array of thermally conductive structures 8. The heat-conducting portion formed by the array of thermally conductive structures 8 effectively reduces the Z-direction thermal resistance of the backside of chip 2a, rapidly dissipating heat generated by the chip, and exhibiting excellent high thermal conductivity. Simultaneously, the inner end of each thermally conductive structure 8 abuts against the back copper layer 23 of chip 2a, while the outer end of each thermally conductive structure 8 extends to the surface of the backside build-up layer B. The array of thermally conductive structures 8 sequentially penetrates the ABF embedding material and the PP build-up material, creating a pinning effect at the interface between the two, reducing the risk of delamination between the ABF embedding material and the PP build-up material, and resulting in lower PP costs.

[0265] The other structures and connection relationships of the embedded substrate 100g may be the same as those of the embedded substrate shown in FIG14 , and will not be described in detail here.

[0266] The following briefly describes the process of the embedded substrate 100g described in FIG. 18 in conjunction with FIG. 19 .

[0267] Step S1901, preparing a core board.

[0268] Step S1902: Preparation for embedding and mounting.

[0269] Step S1903: Mount the chips and electronic components, and press and fill them.

[0270] ABF is used as the embedding filling material 1-3 to fill the gaps between the components and between the components and the embedding grooves of the core board.

[0271] For the above steps S1901 to S1903 , please refer to the process diagram of steps S301 to S303 in FIG3 .

[0272] Step S1904 , laminating the dielectric layer of the front first build-up layer and laminating the back first build-up layer.

[0273] Remove the adhesive films 1-2, and press the exposable and developable material onto the core board 1 to form the dielectric layer 31 of the front first build-up layer, which is bonded to the front of the chip 2 and the electronic component 5. Simultaneously, PP material and copper foil are pressed onto the core board 1 to form the back first build-up layer 7.

[0274] Step S1905: forming holes on the front side by exposure and development process; and forming holes on the back side.

[0275] Through exposure and development processes, a first opening 311 is formed in the dielectric layer 31 of the first front build-up layer 3, corresponding to the pad 22 of the chip 2a; a second opening 312 is formed corresponding to the pin of the electronic component 5; and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through-hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings, thereby forming the corresponding conductive structure.

[0276] Based on the laser hole forming process, a third opening 313 is formed on the first build-up layer 7 on the back side, corresponding to the interface pad 111 of the PTH through-hole 11, and a fourth opening 314 is formed corresponding to the array thermal conductive structure through the embedded filling material 1-3 layers on the back side of the chip 2a, so as to construct the corresponding thermal conductive structure 8.

[0277] Step S1906 , forming each conductive structure and the thermal conductive structure arranged in an array, as well as the surface copper of the front first build-up layer and the back first build-up layer, and patterning them.

[0278] First, the glue removal process is performed, and then the seed layer can be formed first; then, the walls of the first opening 311, the second opening 312 and the third opening 313 are electroplated to form conductive blind holes, forming the first conductive structure 33, the second conductive structure 34 and the third conductive structure 35 respectively; and the fourth opening 314 is electroplated to form an array-arranged thermal conductive structure 8.

[0279] At the same time, surface copper is electroplated on the front and back sides and patterned. The surface copper layer on the front side is used to form the circuit layer 32 of the first front build-up layer, and the surface copper layer on the back side is used to form the circuit layer 72 of the first back build-up layer, thereby completing the production of the first front build-up layer 3 and the first back build-up layer 7.

[0280] Step S1907: forming a second front-side build-up layer and a second back-side build-up layer.

[0281] In the specific implementation, PP material and copper foil are respectively pressed on the first build-up layer on the front side and the first build-up layer on the back side, and then laser holes are opened. The corresponding surface copper layers are formed on the front side and the back side respectively by electroplating process, and the surface is patterned to form the corresponding circuit layer, and the second build-up layer 4 on the front side and the second build-up layer 9 on the back side are completed.

[0282] Step S1908 , forming other outer layers of the front build-up layer and the back build-up layer, forming an outer solder resist layer, and processing the surface of the outer metal layer.

[0283] In each of the aforementioned embodiments, the substrate of the core plate is made of an organic material. In other specific implementations, the substrate of the core plate can also be made of a glass material. Please refer to Figure 20, which is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application. To clearly illustrate the differences and connections between this embodiment and the embodiment described in Figure 8, components or structures with the same functions are indicated in the figure with the same reference numerals.

[0284] As shown in Figure 20, the embedded substrate 100i has a chip 2a and an electronic component 5 embedded in the core 1c. The front surfaces of the chip 2a and the electronic component 5 are aligned with the first surface 1A of the core 1c. Both sides of the core 1c include three build-up layers: a front build-up layer T and a back build-up layer B.

[0285] Compared to the embedded substrate described in Figure 8, the difference of this embodiment is that the core board 1c is a glass core board, and the base of the core board 1c is provided with TGV through holes 11c formed by the TGV process, which realizes the conduction between the first surface 1A and the second surface 1B of the core board 1c, and has the functions of power supply, signal transmission and heat conduction. In this way, the modulus of the glass substrate frame is relatively high, and the overall strength of the substrate is improved. At the same time, based on the CTE adjustability of the glass material, in the specific implementation, glass with a CTE close to that of the chip substrate can be selected, which can effectively reduce structural stress. In addition, based on the good TGV hole density and hole filling ability, the Z-direction heat transfer conduction and flow capacity can also be improved.

[0286] Chip 2a has a back copper layer 23, and the thermally conductive copper block 8c abutting it effectively reduces the Z-direction thermal resistance of the back side of chip 2a. Similarly, the thermally conductive copper block 8c sequentially penetrates the ABF embedding material and the PP build-up material, creating a pinning effect at the interface between the two, reducing the risk of delamination between the ABF embedding material and the PP build-up material.

[0287] In this embodiment, ABF is used as the embedding material to fill the gaps between components and between the components and the embedding grooves of the core board. The dielectric layer 31 of the front first build-up layer 3 is formed using an exposure and development process. The dielectric layers of the front second build-up layer 4 and the back build-up layer B are all made of PP.

[0288] The other structures and connection relationships of the embedded substrate 100i may be the same as those of the embedded substrate shown in FIG8 , and will not be described in detail here.

[0289] The following briefly describes the process of the embedded substrate 100i described in FIG. 20 in conjunction with FIG. 21.

[0290] Step S2101, preparing a core board 1c.

[0291] First, after the glass core board is received, a laser processing process is used to open holes at the location of the TGV through hole 11c and grooves are cut at the location where the device is embedded. Then, the hole is filled with electroplating based on the TGV process to form the interface pad 111.

[0292] Step S2102: Preparation for embedding and mounting: Apply adhesive film 1-2 to the first surface 1A of the core board 1c.

[0293] Step S2103: Mount the chips and electronic components, and press and fill them.

[0294] Specifically, the chip 2a and the electronic component 5 are embedded in the embedding groove 1-1 and mounted on the adhesive film 1-2. Next, a filling and pressing operation is performed. The embedding filling material 1-3 can be ABF, or can be selected according to actual process conditions.

[0295] Here, while the gaps between the devices and between the devices and the embedded grooves are filled by pressing, the embedded filling material 1-3 also forms the dielectric layer 71 of the back first build-up layer 7 bonded to the second surface 1B side of the core board 1c.

[0296] Step S2104 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0297] The adhesive film 1 - 2 is removed, and the exposable and developable material is pressed onto the core board 1 c to form a dielectric layer 31 , which is then bonded to the front surface of the chip 2 a and the electronic component 5 .

[0298] Step S2105: forming holes on the front side and forming holes on the back side by using exposure and development processes.

[0299] Specifically, on the dielectric layer 31 of the front first build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2a, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the TGV through hole 11c. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to form a conductive structure.

[0300] Based on the laser hole forming process, a third opening 313 is formed on the embedded filling material layers 1-3 on the back side of the chip 2a, corresponding to the interface pad 111 of the TGV through hole 11c, and a fourth opening 314b is formed corresponding to the thermal conductive copper block 8c, so as to construct the corresponding thermal conductive copper block 8c.

[0301] Step S2106 , forming the surface copper of each conductive structure, the front first build-up layer and the back first build-up layer, and performing surface patterning.

[0302] First, the adhesive is removed, and then a seed layer is formed. Then, the walls of the first, second, and third openings 311, 312, and 313 are electroplated to form conductive blind vias, forming the first, second, and third conductive structures 33, 34, and 35, respectively. The fourth opening 314b is electroplated to form a thermally conductive copper block 8c.

[0303] At the same time, copper is electroplated on the front and back surfaces. The front copper layer is patterned to form the circuit layer 32 of the front first build-up layer, and the back copper layer is patterned to form the circuit layer 72 of the back first build-up layer.

[0304] Step S2107 , forming the outer layers of the front build-up layer T and the back build-up layer B, forming the outer solder resist layer 6 at the same time, and processing the surface of the outer metal layer.

[0305] In the aforementioned embodiment, build-up layers are provided on both sides of the core substrate: a front build-up layer T and a back build-up layer B. In a specific implementation, only the front build-up layer T may be provided. Please refer to Figure 22 for a cross-sectional view of the structure of another embedded substrate provided in an embodiment of this application. To clearly illustrate the differences and connections between this embodiment and the embodiment described in Figure 20, components or structures with the same functions are indicated with the same reference numerals in the figure.

[0306] As shown in Figure 22, the embedded substrate 100j has a chip 2 and an electronic component 5 embedded in the core board 1c. Compared to the embedded substrate described in Figure 20, this embodiment differs in that the back surfaces of the chip 2 and the electronic component 5 are aligned with the second surface 1B of the glass core board 1c. The first surface A of the core board 1c is provided with a front build-up layer T, and there is no back build-up layer B. In other words, the build-up layers of this embedded substrate are arranged asymmetrically. This shortens the heat conduction path on the back of the chip, maximizing thermal conductivity and conforming to the product evolution trend of ultra-thin embedded architectures.

[0307] Core plate 1c is a glass core plate, and TGV holes 11c are provided on its base, enabling electrical conductivity between the first surface 1A and the second surface 1B of core plate 1c. This results in a relatively high modulus for the glass substrate frame, improving the overall strength of the substrate. In practice, glass with a CTE close to that of the chip substrate can be selected to effectively reduce structural stress. Furthermore, the high TGV hole density and filling capacity improve Z-direction heat transfer and flow capacity.

[0308] In this embodiment, the dielectric layer 31 of the front first build-up layer 3 and the embedding material filling the gaps between the devices and between the devices and the embedding grooves of the core board are all exposed and developable materials.

[0309] The other structures and connection relationships of the embedded substrate 100j may be the same as those of the embedded substrate shown in FIG20 , and will not be described in detail here.

[0310] The following briefly describes the process of the embedded substrate 100j described in FIG. 22 in conjunction with FIG. 23 .

[0311] Step S2301, preparing a core board 1c.

[0312] Step S2302: Preparation for embedding and mounting: Apply adhesive film 1-2 to the second surface 1B of the core board 1c.

[0313] For the above steps S2301 to S2302, please refer to the process diagram of steps S2101 to S2102 in Figure 21.

[0314] Step S2303: Mount the chips and electronic components, and press and fill them.

[0315] Specifically, the chip 2a and electronic component 5 are placed within the embedding groove 1-1 and mounted on the back surface of the adhesive film 1-2. Next, a filling and laminating operation is performed. The embedding filling material 1-3 can be a light-exposing and developable material. While laminating and filling the gaps between the components and between the components and the embedding groove, the dielectric layer 31 of the front first build-up layer 3 is formed, which is bonded to the first surface 1A of the core board 1c.

[0316] Step S2304: forming holes on the front side by exposure and development processes.

[0317] After removing the adhesive films 1-2, a first opening 311 is formed in the dielectric layer 31 of the first front build-up layer 3, corresponding to the pad 22 of the chip 2a. A second opening 312 is formed corresponding to the pin of the electronic component 5. A third opening 313 is formed corresponding to the interface pad 111 of the TGV via 11c. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings, thereby establishing a conductive structure.

[0318] Step S2305 , forming each conductive structure and the copper of the first front build-up layer, and performing surface patterning.

[0319] First, the adhesive removal process is performed, and then a seed layer can be formed first; then, the walls of the first opening 311, the second opening 312 and the third opening 313 are electroplated to form conductive blind holes, forming the first conductive structure 33, the second conductive structure 34 and the third conductive structure 35 respectively.

[0320] At the same time, copper is formed by electroplating on the front and back surfaces. The copper layer on the front surface is patterned to form the circuit layer 32 of the first build-up layer on the front surface, and the copper layer on the back surface is used to form the back interface of the substrate.

[0321] Step S2306: forming the outer layer of the front build-up layer T.

[0322] Step S2307: patterning the back copper layer.

[0323] In a specific implementation, the thickness of the back copper layer can be increased to form a substrate back interface through patterning.

[0324] Step S2308: forming an outer solder resist layer 6 and processing the surface of the outer metal layer.

[0325] In the aforementioned embodiment with an asymmetrical build-up layer arrangement, the base core plate is a glass core plate. In specific implementations, a core plate made of organic materials can also be used for the embedded substrate with an asymmetrical build-up layer arrangement. Please refer to Figure 24, which is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of this application. To clearly illustrate the differences and connections between this embodiment and the embodiment described in Figure 22, components or structures with the same functions are indicated in the figure with the same reference numerals.

[0326] As shown in Figure 24 , the embedded substrate 100k has a chip 2 and electronic components 5 embedded in its core board 1b. Compared to the embedded substrate described in Figure 22 , this embodiment differs in that the core board 1b is made of an organic material. For example, but not limited to, the base of the core board 1b includes multiple circuit layers 11b, which have high flow capacity and high thermal conductivity. Furthermore, the dielectric layer of the outer build-up layer of the front build-up layer T is made of PP. This combination of an organic core board and PP prevents the build-up board from unidirectional warping, effectively improving its stability and reliability during use.

[0327] The backs of the chip 2 and electronic components 5 are aligned with the second side 1B of the core board 1b. The first side A of the core board 1c is provided with a front build-up layer T, but no back build-up layer B. This shortens the heat conduction path on the back of the chip, maximizing thermal conductivity.

[0328] In this embodiment, the material of the dielectric layer 31 of the first front build-up layer 3 and the embedding material filling the gaps between the devices and between the devices and the embedding grooves of the core board are all materials that can be exposed and developed.

[0329] The other structures and connection relationships of the embedded substrate 100k may be the same as those of the embedded substrate shown in FIG22 and will not be described in detail here.

[0330] The following briefly describes the process of the embedded substrate 100k described in FIG. 24 in conjunction with FIG. 25 .

[0331] Step S2501, preparing a core board 1b.

[0332] Step S2502: prepare for embedded mounting, and stick the adhesive film on the second side of the core board.

[0333] Step S2503: mounting chips and electronic components.

[0334] Step S2504: pressing and filling.

[0335] Exposible and developable materials are used as embedded filling materials 1-3 to fill gaps between devices and between devices and embedded grooves, thereby forming a dielectric layer 31 of the front first build-up layer 3.

[0336] For the above steps S2501 to S2502, please refer to the process diagram of steps S901 to S902 in Figure 9; for the above steps S2501 to S2502, please refer to the process diagram of steps S1303 to S1304 in Figure 13.

[0337] Step S2505: bonding and gluing the carrier board.

[0338] After removing the adhesive film 1-2, the back surface of the carrier 1-4 is bonded. In a specific implementation, thermal adhesive or photo-adhesive can be used to bond the carrier. For example, but not limited to, the carrier can be FR4, BT core, metal plate or glass plate.

[0339] Step S2506: The front side is exposed and developed to form holes, shape various conductive structures, and form a first build-up layer on the front side.

[0340] Through exposure and development processes, corresponding openings are formed in the dielectric layer 31 of the front first build-up layer 3 to construct the corresponding conductive structure. After forming the seed layer, the walls of each opening are electroplated to form conductive blind vias, thus constructing the corresponding conductive structure. Simultaneously, surface copper is electroplated on the front surface, and this surface copper layer is patterned to form the circuit layer 32 of the front first build-up layer 3.

[0341] Step S2507: forming the outer layer of the front build-up layer T.

[0342] Step S2508: forming an outer solder resist layer 6 and processing the surface of the outer metal layer.

[0343] In the aforementioned embodiments, a core plate is used as the core retainer. In other specific implementations, a filler material may also be used to form the core retainer. Please refer to Figure 26, which is a cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application. To clearly illustrate the differences and connections between this embodiment and the embodiments described in Figures 22 and 24, components or structures with the same functions are indicated in the figures with the same reference numerals.

[0344] As shown in Figure 26 , the core retainer 1d of the embedded substrate 100m comprises a dielectric layer formed of a dielectric material, within which the chip 2 and electronic components 5 are embedded. This creates a coreless frame structure, simplifying the process and minimizing manufacturing costs. Copper pillars 11d provide electrical continuity between the first and second surfaces 1A, 1B of the core retainer 1d, providing excellent thermal and electrical conductivity.

[0345] Similar to the embedded substrate described in Figures 22 and 23 , this embodiment also uses a single-sided build-up layer structure. The back surfaces of the chip 2 and electronic component 5 are aligned with the second surface 1B of the core retainer 1d. The first surface A of the core retainer 1d is provided with a front-side build-up layer T, and no back-side build-up layer B. This allows the back copper layer or substrate of the chip 2 to be directly exposed at the bottom, shortening the thermal path on the back of the chip and maximizing thermal conductivity.

[0346] In this embodiment, the material of the dielectric layer 31 of the first build-up layer 3 on the front side, as well as the embedded material filling the gaps between the devices and between the devices and the embedded grooves of the core board, are all exposed and developable materials. In this way, on the one hand, the window size on the chip side can be maximized to form a first conductive structure. The first conductive structure has a larger flow cross-section, which can effectively improve the flow capacity while also having good thermal conductivity. On the other hand, on the basis of meeting the requirements of large flow and high thermal conductivity on the front side of the chip, the dielectric layer of the first build-up layer on the front side and the outer protective layer on the chip side have material thermal expansion coefficients that are close to each other. Both of them have organic materials, which can reduce the bonding stress between the circuit layer and the front side of the chip and reduce the risk of delamination.

[0347] The other structures and connection relationships of the embedded substrate 100m can be the same as those of the embedded substrate shown in FIG22, and will not be described in detail here.

[0348] The following briefly describes the process of the embedded substrate 100m described in FIG. 26 in conjunction with FIG. 27 .

[0349] In step S2701, a detachable copper foil 1-6 is coated on a first carrier board 1-5. For example, but not limited to, the first carrier board 1-5 may be an organic core board.

[0350] Step S2702: Processing copper pillars 11d on the copper foil 1-6, for example but not limited to, using lamination, exposure, development, electroplating and stripping processes; applying temporary bonding glue 1-7 on the copper foil 1-6, and mounting the chip 2 and electronic component 5.

[0351] Step S2703, the filling dielectric material is pressed, for example but not limited to pressing with an exposable and developable material, to form a filling material layer of the core retaining body 1d and a dielectric layer 31 of the front first build-up layer 3, respectively, and forming holes by exposure and development processes.

[0352] Specifically, a first opening 311 is formed corresponding to the pad of chip 2, a second opening 312 is formed corresponding to the pin of electronic component 5, and a third opening 313 is formed corresponding to copper pillar 11d. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to form a conductive structure.

[0353] Step S2704 , forming each conductive structure and the copper surface of the first front build-up layer, and performing surface patterning.

[0354] First, a seed layer is formed, and then the walls of the first opening 311 , the second opening 312 and the third opening 313 are electroplated to form conductive blind vias, thereby forming the first conductive structure 33 , the second conductive structure 34 and the third conductive structure 35 , respectively.

[0355] At the same time, copper is electroplated on the front surface and patterned to form the circuit layer 32 of the first build-up layer on the front surface.

[0356] Step S2705: forming the outer layer of the front build-up layer T.

[0357] Step S2706, front-side bonding of the second carrier 1-8, for example but not limited to, the material of the second carrier 1-8 can be FR4, BT, stainless steel or glass, the second carrier 1-8 and the core retaining body 1d are bonded by a temporary bonding material, the temporary bonding material includes but is not limited to pyrolytic glue, photolytic glue or light-curing glue, etc.; the first carrier is removed, and the removal method includes but is not limited to pyrolysis, photolysis or mechanical stripping; finally, the copper foil 1-6 is etched away and the temporary bonding glue 1-7 is removed.

[0358] Step S2707 , patterning the back interface to form a back solder resist layer 6 .

[0359] Step S2708: remove the second carrier 1-8 by methods including but not limited to thermal decomposition, photolysis, or mechanical stripping; then, form a front solder resist layer 6, such as but not limited to liquid solder resist, dry film solder resist, PID, or PI.

[0360] Finally, the surface is metal treated, including but not limited to ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold), ENIG (Electroless Nickel / Immersion Gold), OSP (Organic solderability preservative) or SOP process.

[0361] The embedded substrate architecture described in the aforementioned embodiments can be widely applied to the packaging structures of various functional modules. In practical applications, the advantages of the above technology are particularly significant in power module architecture scenarios. See Figure 28, which is a schematic diagram of an application scenario for a power supply device provided in an embodiment of the present application.

[0362] As shown in Figure 28, the power supply device 1000 includes a chip 2, an inductor 10, and multiple electronic components. The chip 2 and some of the electronic components form a first package using the embedded substrate 100d architecture described in Figure 12. The inductor 10 and other electronic components form a second package 200, which is stacked with the first package (embedded substrate 100d). The back of the power supply device 1000 is assembled on one side of the system board 2000, and the XPU 3000 is assembled on the other side of the system board 2000. The heat sink 4000 is bonded to the XPU 3000.

[0363] In use, it can achieve high flow and high thermal conductivity. The flow path is shown by thin arrows in the figure, and the heat dissipation path is shown by thick arrows in the figure.

[0364] In other implementations, the first package body may also be formed using the aforementioned other embedded substrate structures.

[0365] The power supply device 1000a shown in Figure 19 comprises a chip 2 and some electronic components, forming a first package using the embedded substrate 100m architecture described in Figure 26. The inductor 10 and other electronic components form a second package 200, which is stacked with the first package (embedded substrate 100m). The front surface of the power supply device 1000a is mounted on one side of the system board 2000, while the XPU 3000 is mounted on the other side of the system board 2000. A first heat sink 4000a is bonded to the XPU 3000, while a second heat sink 4000b is bonded to the back surface of the power supply device 1000a.

[0366] Likewise, the flow path is shown by thin arrows in the figure, and the heat dissipation path is shown by thick arrows in the figure.

[0367] It should be understood that the other functional components of the power supply device are not the core invention of this application, and those skilled in the art can implement them according to the existing technology, so they will not be described in detail herein.

[0368] In addition to the aforementioned embedded substrate, this embodiment also provides an electronic device. Please refer to Figure 30, which is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0369] As shown in Figure 30, the electronic device 10000 includes a housing 301 and a motherboard 302 disposed within the housing 301. The motherboard 302 is provided with an embedded substrate 100 as described in the previous embodiment. Due to the excellent flow rate and high thermal conductivity of the embedded substrate, it can be widely used in various high-density application scenarios.

[0370] In a specific implementation, the electronic device can be a server, a computer or a high-performance computing cluster, which is a high-power, highly integrated, and ultra-large-scale data center server; in addition, the electronic device can also be a switch, a router or an edge device, etc., which is not limited in the embodiments of the present application.

[0371] It should be understood that other functions of the electronic device are not the core invention of this application, and those skilled in the art can implement them according to existing technologies, so they will not be described in detail herein.

[0372] The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An embedded substrate, characterized in that: The embedded substrate comprises a core retainer, a build-up layer and a chip embedded in the core retainer; the core retainer comprises a first surface and a second surface, and the front surface of the chip is arranged toward the first surface of the core retainer; An outer protective layer is arranged outside the pads of the chip, and the outer protective layer has windows arranged corresponding to the pads on the chip; The build-up layer comprises a front build-up layer covering the first surface of the core retainer, the front build-up layer comprises a front first build-up layer, and the front first build-up layer is respectively bonded to the first surface of the core retainer and the front surface of the chip; The first front build-up layer comprises a dielectric layer and a circuit layer which are stacked together, a conductive structure electrically connected to the circuit layer is provided in the dielectric layer of the first front build-up layer, and the conductive structure comprises a first conductive structure electrically connected to a pad on the chip; Among them, the dielectric layer of the first front build-up layer is made of an exposeable and developable material, and an opening for constructing the conductive structure is formed by exposure and development, and the opening for constructing the first conductive structure is a first opening; the window opening of the outer protective layer has a first projection on the first surface, and the first opening corresponding to the window opening has a second projection on the first surface, and the second projection covers the first projection.

2. The embedded substrate according to claim 1, characterized in that: The embedded substrate further includes an electronic component embedded in the core retaining body, the conductive structure further includes a second conductive structure electrically connected to the pins of the electronic component, and the opening for constructing the second conductive structure is a second opening.

3. The embedded substrate according to claim 2, characterized in that: The electronic component is provided in plurality, and at least one of the plurality of electronic components is a capacitor or a resistor.

4. The embedded substrate according to any one of claims 1 to 3, characterized in that: The embedded substrate further includes a flow-through structure built into the core retaining body, the conductive structure further includes a third conductive structure electrically connected to the flow-through structure, and the opening for constructing the third conductive structure is a third opening.

5. The embedded substrate according to any one of claims 1 to 4, characterized in that: The core retainer is a core plate made of organic material.

6. The embedded substrate according to claim 5, characterized in that: The flow-through structure in the core plate is a PTH or a copper column that passes through the core plate substrate, or the flow-through structure in the core plate is a multi-layer hole structure in the core plate substrate.

7. The embedded substrate according to any one of claims 1 to 4, characterized in that: The core retaining body is a core plate made of glass material.

8. The embedded substrate according to claim 7, characterized in that: The flow-through structure in the core plate is a TGV.

9. The embedded substrate according to any one of claims 5 to 8, characterized in that: The chip and the electronic components embedded in the core board are arranged in alignment with the first surface of the core board, or are arranged in alignment with the second surface of the core board.

10. The embedded substrate according to any one of claims 5 to 9, characterized in that: The embedding material around the chip and the electronic components embedded in the core board is ABF, or the embedding material around the chip and the electronic components embedded in the core board is an exposable and developable material.

11. The embedded substrate according to any one of claims 1 to 10, characterized in that: The build-up layer further includes a back surface build-up layer covering the second surface of the core retainer.

12. The embedded substrate according to claim 11, characterized in that: A heat conducting portion is provided in the back surface build-up layer, an inner end side of the heat conducting portion is in contact with the back surface of the chip, and an outer end side of the heat conducting portion extends to the surface layer of the back surface build-up layer.

13. The embedded substrate according to claim 12, characterized in that: The heat conducting part is a copper block, or a blind hole or a copper bar arranged in an array.

14. The embedded substrate according to claim 13, characterized in that: The back surface of the chip has a back copper layer, and the inner end side of the heat conducting portion abuts against the back copper layer.

15. The embedded substrate according to any one of claims 11 to 14, characterized in that: The back side build-up layer includes a first back side build-up layer, which is bonded to the second side of the core retaining body; the first back side build-up layer includes a dielectric layer and a circuit layer which are stacked together, and a conductive structure electrically connected to the circuit layer is provided in the dielectric layer of the first back side build-up layer.

16. The embedded substrate according to claim 15, characterized in that: The dielectric layer of the first back build-up layer is made of an exposable and developable material, and openings for constructing a conductive structure are formed by exposure and development.

17. The embedded substrate according to claim 15, characterized in that: The dielectric layer of the first back build-up layer is made of PP material.

18. The embedded substrate according to any one of claims 15 to 17, characterized in that: The back side build-up layer includes at least one back side second build-up layer, the back side second build-up layer is stacked on the back side first build-up layer, the back side second build-up layer includes a stacked dielectric layer and a circuit layer, and the dielectric layer of the back side second build-up layer is made of ABF, PP or an exposable and developable material.

19. The embedded substrate according to any one of claims 1 to 18, characterized in that: The front build-up layer includes at least one front second build-up layer, which is sequentially stacked on the front first build-up layer. The front second build-up layer includes a stacked dielectric layer and a circuit layer, and the dielectric layer of the front second build-up layer is made of ABF, PP or an exposable and developable material.

20. The embedded substrate according to any one of claims 1 to 4, characterized in that: The core retainer is a filling medium layer made of a filling medium material.

21. The embedded substrate according to claim 20, characterized in that: The filling medium material is an exposed and developable material.

22. The embedded substrate according to claim 20 or 21, characterized in that: The flow-through structure in the filling medium layer is a copper column.

23. The embedded substrate according to any one of claims 20 to 22, characterized in that: The chip and the electronic components embedded in the core board are arranged in alignment with the second surface of the filling medium layer.

24. A power supply device, characterized in that: The invention comprises a chip, an inductor element and a plurality of electronic components, wherein the chip and some of the plurality of electronic components form a first package body by using the embedded substrate described in any one of claims 1 to 23, and the inductor element and another part of the plurality of electronic components form a second package body, and the second package body is overlapped with the first package body.

25. An electronic device, characterized in that: It comprises a system board and a power supply device, wherein the power supply device is arranged on the system board, and the power supply device is the power supply device according to claim 24.

26. An electronic device, characterized in that: It comprises a main board and an embedded component, wherein the embedded component is arranged on the main board, and the embedded component is made of the embedded substrate according to any one of claims 1 to 23.

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