Mosfet device and manufacturing method therefor

Abstract

The present application relates to the field of semiconductors, and in particular to a MOSFET device and a manufacturing method therefor. The MOSFET device comprises a semiconductor material layer, a well region, a gate trench, and an electric field shielding structure; the gate trench extends from an upper surface of the semiconductor material layer to the interior of the semiconductor material layer and comprises a first trench portion and a second trench portion; the bottom wall of the first trench portion is located in the well region; the second trench portion passes through the well region and extends into the semiconductor material layer below the well region; the electric field shielding structure comprises a first structure portion and a second structure portion which are electrically connected to each other; the first structure portion is located below the first trench portion and is in electrical contact with the well region; and the second structure portion is located below the second trench portion. According to the embodiments of the present application, the cell pitch is reduced, the stability of long-term operation of a device is improved, and the manufacturing process is simplified.

Description

MOSFET device and preparation method thereof Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a MOSFET device and a method for preparing the same. Background Art

[0002] The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a crucial electronic component widely used in both analog and digital circuits. Silicon carbide MOSFETs (SiC MOSFETs), with their low on-resistance, fast switching speed, and high-temperature resistance, offer significant advantages in high-voltage frequency conversion, new energy vehicles, rail transit, and other fields.

[0003] The gate electrode of the traditional trench MOSFET device is arranged in the trench, the electric field at the bottom of the trench is concentrated, and the gate oxide electric field is high, which can easily cause gate oxide breakdown, thereby causing device failure. The current common solution is to form an electric field shielding structure at the bottom of the trench. In order to connect the electric field shielding structure to a low potential or ground and play a shielding role, it is usually necessary to set a specific connecting portion (for example, a column area electric field modulation structure) to lead the electric field shielding structure at the bottom of the trench. However, the setting of the connecting portion undoubtedly increases the size of the cell area and increases the complexity of the process.

[0004] Summary of the Invention

[0005] In view of this, embodiments of the present application provide a MOSFET device and a method for manufacturing the same in order to solve at least one problem existing in the background technology.

[0006] In the first aspect, an embodiment of the present application provides a MOSFET device, comprising: a semiconductor material layer, comprising an upper surface and a lower surface opposite to each other; a well region, located in the semiconductor material layer and on a side close to the upper surface; a gate trench, extending from the upper surface of the semiconductor material layer to the interior of the semiconductor material layer; the gate trench comprises a first trench portion and a second trench portion, the bottom wall of the first trench portion is located in the well region, the second trench portion passes through the well region and extends into the semiconductor material layer below the well region; wherein the semiconductor material layer below the well region has a first conductivity type, and the well region has a second conductivity type electrically opposite to the first conductivity type; an electric field shielding structure, located below the gate trench, having a second conductivity type; the electric field shielding structure comprises a first structure portion and a second structure portion electrically connected to each other, the first structure portion is located below the first trench portion and electrically in contact with the well region, and the second structure portion is located below the second trench portion.

[0007] In combination with the first aspect of the present application, in an optional embodiment, the line width of the first groove portion is smaller than the line width of the second groove portion, and the gate trench is formed based on the load effect of etching with different line widths so that the depth of the first groove portion is smaller than the depth of the second groove portion.

[0008] In combination with the first aspect of the present application, in an optional embodiment, it also includes: a source region, located in the well region; a source electrode, located on the well region and the source region; wherein the source region, the well region and the electric field shielding structure are grounded through the source electrode.

[0009] In combination with the first aspect of the present application, in an optional embodiment, for any of the gate trenches, the total extended length of the first trench portion is less than or equal to the total extended length of the second trench portion.

[0010] In combination with the first aspect of the present application, in an optional embodiment, the first groove portion is located in the extension direction of the second groove portion, the first groove portion extends in the same direction as the extension direction of the second groove portion, and the total extension length of the first groove portion is less than the total extension length of the second groove portion; or, the first groove portion is located in the extension direction of the second groove portion, the first groove portion extends in the same direction as the extension direction of the second groove portion, the first groove portion and the second groove portion are alternately arranged in the extension direction, the extension lengths of each second groove portion are equal, and the spacing between two adjacent second groove portions is equal; or, the extension direction of the first groove portion intersects with the extension direction of the second groove portion; or, the number of the second groove portions is multiple, and the multiple second groove portions extend in at least two different directions respectively, the number of the first groove portions is one or more, the extension direction of the first groove portion is the same as the extension direction of at least one second groove portion, and the total extension length of the first groove portion is less than the total extension length of the second groove portion.

[0011] In second aspect, an embodiment of the present application provides a method for preparing a MOSFET device, the method comprising: providing a semiconductor material layer; forming a well region in the semiconductor material layer; forming a gate trench in the semiconductor material layer, the gate trench comprising a first trench portion and a second trench portion, the bottom wall of the first trench portion being located in the well region, the second trench portion passing through the well region and extending into the semiconductor material layer below the well region; wherein the semiconductor material layer below the well region has a first conductivity type, and the well region has a second conductivity type electrically opposite to the first conductivity type; an electric field shielding structure having the second conductivity type is formed below the gate trench, the electric field shielding structure comprising a first structure portion and a second structure portion electrically connected to each other, the first structure portion being located below the first trench portion and electrically contacting the well region, and the second structure portion being located below the second trench portion.

[0012] In combination with the second aspect of the present application, in an optional embodiment, the gate trench is formed in the semiconductor material layer, comprising: forming a patterned mask layer on the semiconductor material layer, the patterned mask layer comprising a first pattern and a second pattern, the line width of the first pattern being smaller than the line width of the second pattern; etching the semiconductor material layer using the patterned mask layer as a mask, and forming the first groove portion having a first depth and the second groove portion having a second depth based on the load effect of etching with different line widths, the first depth being smaller than the second depth.

[0013] In combination with the second aspect of the present application, in an optional embodiment, the forming of the gate trench in the semiconductor material layer includes: forming a first patterned mask layer on the semiconductor material layer, the first patterned mask layer having an opening exposing a preset formation position of the second groove portion; performing a first etching process using the first patterned mask layer as a mask; forming a second patterned mask layer on the semiconductor material layer, the second patterned mask layer having an opening exposing the preset formation position of the first groove portion and the preset formation position of the second groove portion; performing a second etching process using the second patterned mask layer as a mask to form the first groove portion having a first depth and the second groove portion having a second depth, the first depth being less than the second depth.

[0014] In combination with the second aspect of the present application, in an optional embodiment, for any of the gate trenches, the total extended length of the first trench portion is less than or equal to the total extended length of the second trench portion.

[0015] In combination with the second aspect of the present application, in an optional embodiment, the first groove portion is located in the extension direction of the second groove portion, the first groove portion extends in the same direction as the extension direction of the second groove portion, and the total extension length of the first groove portion is less than the total extension length of the second groove portion; or, the first groove portion is located in the extension direction of the second groove portion, the first groove portion extends in the same direction as the extension direction of the second groove portion, the first groove portion and the second groove portion are alternately arranged in the extension direction, the extension lengths of each second groove portion are equal, and the spacing between two adjacent second groove portions is equal; or, the extension direction of the first groove portion intersects with the extension direction of the second groove portion; or, the number of the second groove portions is multiple, and the multiple second groove portions extend in at least two different directions respectively, the number of the first groove portions is one or more, the extension direction of the first groove portion is the same as the extension direction of at least one second groove portion, and the total extension length of the first groove portion is less than the total extension length of the second groove portion.

[0016] The MOSFET device and its preparation method provided in the embodiment of the present application are configured such that the gate trench includes a first trench portion and a second trench portion, and the bottom wall of the first trench portion is located in the well region, and the second trench portion penetrates the well region and extends into the semiconductor material layer below the well region; on this basis, a corresponding electric field shielding structure including a first structure portion and a second structure portion is formed, and the first structure portion is located below the first trench portion and electrically contacts the well region, and the second structure portion is located below the second trench portion; in this way, the second structure portion is electrically connected to the first structure portion, and the first structure portion is electrically contacted with the well region, thereby realizing conductive extraction of the second structure portion through the first structure portion and the well region, and then the electric field shielding structure can be connected to a low potential or ground to play a shielding role; the MOSFET device and its preparation method provided in the embodiment of the present application reduce the size of the cell region, improve the long-term working stability of the device, extend the service life of the device, and make the structure setting more flexible, which is convenient for simplifying the corresponding preparation process.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] FIG1 is a schematic diagram of a three-dimensional structure of an exemplary MOSFET device according to some embodiments of the present application;

[0020] FIG2 is a schematic diagram of the three-dimensional structure of the MOSFET device observed from the position and direction of the arrow in FIG1 ;

[0021] FIG3 is a schematic structural diagram of the CC section in FIG1 ;

[0022] FIG4 is a schematic structural diagram of the AA section in FIG1 ;

[0023] FIG5 is a schematic structural diagram of the BB section in FIG1 ;

[0024] FIG6 is a layout diagram of an exemplary gate trench according to some embodiments of the present application;

[0025] FIG7 is a layout diagram of another exemplary gate trench according to some embodiments of the present application;

[0026] FIG8 is a layout diagram of yet another exemplary gate trench according to some embodiments of the present application;

[0027] FIG9 is a layout diagram of another exemplary gate trench according to some embodiments of the present application;

[0028] FIG10 is a diagram showing the relationship between drain current and drain-source voltage according to some embodiments of the present application;

[0029] FIG11 is a flow chart showing the preparation of a MOSFET device according to some embodiments of the present application;

[0030] 12 to 17 are schematic structural diagrams of MOSFET devices during the manufacturing process according to some embodiments of the present application;

[0031] 18 and 19 are schematic diagrams of preparing exemplary gate trenches according to some embodiments of the present application. DETAILED DESCRIPTION

[0032] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0033] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0034] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0035] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0039] Figure 1 is a schematic diagram of the three-dimensional structure of an exemplary MOSFET device according to some embodiments of the present application. Figure 2 is a schematic diagram of the three-dimensional structure of the MOSFET device viewed from the arrow position and direction in Figure 1. Figure 3 is a schematic diagram of the CC cross-section in Figure 1.

[0040] As shown in FIG. 1 to FIG. 3 , the MOSFET device includes a substrate 105 , a semiconductor material layer 110 , a gate trench 120 , and an electric field shielding structure 130 .

[0041] The substrate 105 can be the base of the MOSFET device and the carrier for adding subsequent material layers. The substrate 105 may include a top surface for forming the MOSFET device and a bottom surface opposite to the top surface. Ignoring the flatness of the top and bottom surfaces, the direction perpendicular to the top and bottom surfaces of the substrate 105 is defined as the thickness direction of the substrate 105. The thickness direction of the substrate 105 is also the stacking direction of the various material layers subsequently deposited on the substrate 105, or the height direction of the device, which is shown as the "third direction" in the figure. The surface where the top and bottom surfaces of the substrate 105 are located, or strictly speaking, the center plane of the substrate 105 in the thickness direction, is determined to be the substrate plane. Two mutually intersecting first and second directions are defined in the direction of the substrate plane; the first and second directions are, for example, two directions perpendicular to each other. The top and bottom surfaces of the substrate 105 may also be referred to as the upper surface and lower surface, respectively.

[0042] A semiconductor material layer 110 is located on a substrate 105. In some embodiments, the semiconductor material layer 110 may be an epitaxial layer grown on the substrate 105. For example, the semiconductor material layer 110 may include a silicon carbide epitaxial layer. In some embodiments, the semiconductor material layer 110 may include one or more regions having the same or different charge types. For example, the semiconductor material layer 110 may include a well region 112 formed on one side near the top surface. The semiconductor material layer 110 itself has a first conductivity type, while the well region 112 may have a second conductivity type. The figure shows a portion 114 of the semiconductor material layer 110 located below the well region 112. It is understood that the portion 114 located below the well region 112 was not ion implanted during the formation of the well region 112 and thus remains the first conductivity type. The first and second conductivity types have opposite electrical properties. For example, the first conductivity type may be N-type and the second conductivity type may be P-type; however, the present application does not exclude the opposite case.

[0043] The gate trench 120 extends from the upper surface of the semiconductor material layer 110 to the interior of the semiconductor material layer 110 . The gate trench 120 may include one or more first trench portions 122 and one or more second trench portions 124 .

[0044] The first trench portion 122 and the second trench portion 124 may have the same or different line widths.

[0045] In some embodiments, the first groove portion 122 and the second groove portion 124 may have different depths. Detailed descriptions of the first groove portion 122 and the second groove portion 124 are provided in FIG. 4 to FIG. 8 and related descriptions.

[0046] The electric field shielding structure 130 is disposed below the gate trench 120. The electric field shielding structure 130 may include a first structure portion 132 and a second structure portion 134. The first structure portion 132 may be disposed below the first trench portion 122, and the second structure portion 134 may be disposed below the second trench portion 124. A being disposed below B specifically means that A is located directly below B, or at least the main portion of A is located directly below B. The first structure portion 132 and the second structure portion 134 are in electrical contact with each other. For example, as shown in FIG3 , a step is formed between the bottom surface of the first structure portion 132 and the bottom surface of the second structure portion 134. In some embodiments, the electric field shielding structure 130 may have a second conductivity type.

[0047] In some embodiments, the MOSFET device may further include, but is not limited to, a source region 140 , a source electrode 150 , a gate electrode 160 , a gate dielectric layer 170 , and the like.

[0048] A gate electrode 160 may be disposed in the gate trench 120. In some embodiments, the material of the gate electrode 160 may include polysilicon. A gate dielectric layer 170 is disposed in the gate trench 120. The gate dielectric layer 170 is disposed between the gate electrode 160 and the inner sidewalls of the gate trench 120, between the gate electrode 160 and the bottom wall of the gate trench 120, and so on.

[0049] The source region 140 can be located in the well region 112. For example, the source region 140 can be located in a surface region near the semiconductor material layer 110. The source electrode 150 can be located on the semiconductor material layer 110, specifically on the source region 140 and the well region 112, and can be conductively connected to at least the source region 140 and the well region 112. The source electrode 150 can be grounded, so that the electric field shielding structure 130 electrically connected thereto is also grounded. In this way, the electric field at the bottom of the gate dielectric layer 170 is effectively shielded, thereby improving the avalanche capability of the device. In some embodiments, the gate oxide electric field at the gate dielectric layer 170 can be reduced to 1.7 MV / cm, thereby improving the reliability of the device.

[0050] FIG4 is a schematic structural diagram of the AA section in FIG1 . As shown in FIG4 , the first trench portion 122 extends from the upper surface of the semiconductor material layer 110 into the semiconductor material layer 110 . Furthermore, the bottom wall of the first trench portion 122 is disposed in the well region 112 .

[0051] In some embodiments, the first structure portion 132 is disposed below the first trench portion 122. For example, the first structure portion 132 may be disposed only in the region of the well region 112 below the first trench portion 122. In another example, a portion of the first structure portion 132 may be disposed in the region of the well region 112 below the first trench portion 122, while a portion of the first structure portion 132 may be disposed in the semiconductor material layer below the well region 112 (in the portion 114). This arrangement allows the first structure portion 132 to be in electrical contact with the well region 112, thereby enabling the first structure portion 132 to be grounded through the well region 112.

[0052] Figure 5 is a schematic diagram of the structure of the cross section BB in Figure 1. As shown in Figure 5, second trench portion 124 extends from the upper surface of semiconductor material layer 110, through well region 112, and into the semiconductor material layer below well region 112 (in portion 114). Second structure portion 134 is disposed below second trench portion 124.

[0053] In this embodiment, the second structure portion 134 is in electrical contact with the first structure portion 132. Therefore, the second structure portion 134 can be connected to the source electrode 150 through the first structure portion 132, through the well region 112 and / or the source region 140, thereby achieving grounding. In this way, the electric field at the gate dielectric layer 170 can be effectively shielded, thereby improving the avalanche capability of the device.

[0054] In some embodiments, the electrical contact between the second structure portion 134 and the first structure portion 132 specifically means that the second structure portion 134 is in direct contact with the first structure portion 132 , and the two are connected as a whole.

[0055] In some embodiments, the doping concentrations of the dopant in the first structure portion 132 and the second structure portion 134 may be the same or different.

[0056] In some embodiments, the second structure portion 134 and the first structure portion 132 can be configured as needed. Since the first structure portion 132 is disposed below the first groove portion 122 and the second structure portion 134 is disposed below the second groove portion 124, the specific configuration of the first structure portion 132 and the second structure portion 134 can refer to the first groove portion 122 and the second groove portion 124 in Figures 6 to 8 and the related descriptions.

[0057] In some embodiments, the line width of the first trench portion 122 is smaller than that of the second trench portion 124 , and the gate trench 120 is formed such that the depth of the first trench portion 122 is smaller than that of the second trench portion 124 based on the loading effect of etching with different line widths.

[0058] In some embodiments, for a gate trench, the total extension length of the first trench portion 122 is less than or equal to the total extension length of the second trench portion 124; in this way, the electric field shielding structure can be connected to a low potential or ground to play a shielding role without wasting too much area of ​​the chip active area, effectively ensuring the length of the device channel region and avoiding the device R on loss.

[0059] In some embodiments, the extension direction of at least one first groove portion 122 intersects with the extension direction of at least one second groove portion 124; thus, by arranging the first groove portion 122 in a direction intersecting with the extension direction of the second groove portion 124, the influence on the extension length of the second groove portion 124 is reduced, thereby further ensuring the length of the device channel region and avoiding the device R on loss.

[0060] Next, the arrangement of the first groove portion 122 and the second groove portion 124 will be further exemplarily described with reference to FIG. 6 to FIG. 8 .

[0061] First, please refer to Figure 6, which shows an exemplary gate trench layout according to some embodiments of the present application. As shown in the figure, the first trench portion 122 is located in the extension direction of the second trench portion 124. The first trench portion 122 extends in the same direction as the second trench portion 124, and the total extension length of the first trench portion 122 is less than the total extension length of the second trench portion 124.

[0062] It is understandable that since channels cannot be formed on both sides of the first groove portion 122, while the electric field shielding structure is connected to a low potential or ground to play a shielding role, the area of ​​the chip active area will be wasted to a certain extent. By setting the extension length of the first groove portion 122 to be smaller than the extension length of the second groove portion 124, the length of the device channel region can be guaranteed as much as possible to avoid the device R on In addition, the first groove portion 122 is located in the extending direction of the second groove portion 124 and the two extend in the same direction. The structure arranged in this way is relatively easy to implement in the manufacturing process.

[0063] As shown in FIG6 , a gate trench 120 may include one or more first trench portions 122 and one or more second trench portions 124. The first trench portion 122 is located at the end of the second trench portion 124 in the extending direction. FIG6 specifically illustrates a gate trench 120 including two first trench portions 122, which are respectively disposed at both ends of the second trench portion 124. Disposing the first trench portion 122 at the end of the second trench portion 124 can reduce the area of ​​the well region 112 occupied by the first trench portion 122, thereby effectively protecting the gate dielectric layer in the second trench portion 124 while not reducing the conductive efficiency of the MOSFET device.

[0064] Furthermore, the number of gate trenches 120 can be one or more. When there is one gate trench 120, the various portions of the gate trench 120 are connected to form a whole; when there are multiple gate trenches 120, the gate trenches 120 are not connected to each other. Figure 6 specifically illustrates the case where there are multiple gate trenches 120; the multiple gate trenches 120 can extend in the same direction (i.e., the extension direction of the aforementioned second trench portion 124). In this embodiment, the first trench portion 122 and the second trench portion 124 in each gate trench 120 can be arranged in the same manner; of course, this application does not exclude the case where the arrangements are different.

[0065] Furthermore, for the case where there is one gate trench 120, the total extension length of the first trench portion 122 is less than the total extension length of the second trench portion 124; for the case where there are multiple gate trenches 120, the total extension length of the first trench portion 122 in the multiple gate trenches 120 is less than the total extension length of the second trench portion 124 in the multiple gate trenches 120.

[0066] Next, please refer to Figure 7, which illustrates another exemplary gate trench layout according to some embodiments of the present application. Unlike the arrangement of the first and second trench portions in Figure 6, the first trench portions 122 and second trench portions 124 in Figure 7 are alternately arranged along the extension direction, with each second trench portion 124 extending to the same length and the spacing between adjacent second trench portions 124 being equal. In Figure 7, the first trench portions 122 are also located in the extension direction of the second trench portions 124, extending in the same direction as the extension direction of the second trench portions 124.

[0067] It can be understood that compared with Figure 6, this arrangement will have a more uniform electric field distribution, but the device R on The loss may be relatively large; in addition, the structure arranged in this way is relatively easy to implement during the preparation process.

[0068] 7 , a gate trench 120 may include a plurality of periodically arranged first trench portions 122 and a plurality of second trench portions 124, with the first trench portions 122 and the second trench portions 124 being alternately arranged. The number of first trench portions 122 and second trench portions 124 and their arrangement may be determined based on actual needs and the size of the MOSFET device cell region.

[0069] Optionally, the extension lengths of the plurality of first groove portions 122 are equal to ensure that the intervals between two adjacent second groove portions 124 are equal.

[0070] Further optionally, the extension length of each first groove portion 122 is equal to the extension length of each second groove portion 124 ; in this way, the first groove portions 122 and the second groove portions 124 are evenly distributed.

[0071] In some embodiments, there are multiple gate trenches 120. For each gate trench 120, the first trench portion 122 is located in the extension direction of the second trench portion 124. The first trench portion 122 extends in the same direction as the extension direction of the second trench portion 124, and the first trench portion 122 and the second trench portion 124 are alternately arranged in the extension direction. Furthermore, the arrangement of the first trench portion 122 and the second trench portion 124 in two adjacent gate trenches 120 is different. Specifically, taking the example of each gate trench 120 extending in the second direction and the gate trenches 120 arranged along the first direction, along the first direction, if one of the two adjacent gate trenches 120 is the first trench portion 122 at a certain position, then the other gate trench 120 is the second trench portion 124 at a corresponding position. In this way, a complementary distribution is formed, which not only makes the electric field distribution more uniform, but also helps to fully utilize the area of ​​the active area.

[0072] Furthermore, when there is only one gate trench 120, the total extended length of the first trench portion 122 is less than or equal to the total extended length of the second trench portion 124. When there are multiple gate trenches 120, the total extended length of the first trench portions 122 in the multiple gate trenches 120 is less than or equal to the total extended length of the second trench portions 124 in the multiple gate trenches 120. In other words, regardless of whether there is one or more gate trenches 120, for any gate trench, the total extended length of the first trench portion 122 is less than or equal to the total extended length of the second trench portion 124.

[0073] 8 is a layout diagram of another exemplary gate trench according to some embodiments of the present application. As shown in the figure, the extension direction of the first trench portion 122 intersects with the extension direction of the second trench portion 124.

[0074] Specifically, the first groove portion 122 extends along a first direction, and the second groove portion 124 extends along a second direction, and the first direction intersects the second direction.

[0075] In some embodiments, the extension directions of the first groove portion 122 and the second groove portion 124 can intersect at any angle, for example, 15°, 30°, 45°, 60°, 75°, 90°, 135°, etc. As an example only, as shown in FIG8 , the extension direction of the first groove portion 122 is perpendicular to the extension direction of the second groove portion 124, that is, the first direction and the second direction are specifically perpendicularly intersected. By intersecting the extension directions of the first groove portion 122 and the second groove portion 124, the length of the device channel region can be effectively guaranteed, thereby effectively protecting the gate dielectric layer 170 in the second groove portion 124 while avoiding the loss of the device R on , to avoid reducing the conduction efficiency of MOSFET devices.

[0076] In some embodiments, there are multiple first groove portions 122 and multiple second groove portions 124. The multiple first groove portions 122 extend along the first direction and intersect at different locations on the same second groove portion 124. The multiple second groove portions 124 extend along the second direction and intersect at different locations on the same first groove portion 122. The multiple first groove portions 122 and the multiple second groove portions 124 form a grid. At least one first groove portion 122 connects the ends of the second groove portions 124; alternatively, the second groove portions 124 intersect with the first groove portions 122 through portions other than the ends.

[0077] In some embodiments, the intervals between the plurality of first groove portions 122 are equal, so that the electric field distribution is more uniform.

[0078] FIG9 is a layout of another exemplary gate trench according to some embodiments of the present application. There are multiple second trench sections, each extending in at least two different directions. There are one or more first trench sections, each extending in the same direction as at least one second trench section, and the total length of each first trench section is less than the total length of each second trench section.

[0079] The plurality of second groove portions extend in at least two different directions, for example, a portion of the plurality of second groove portions extend in a first direction and a portion extend in a second direction, and the first direction intersects the second direction. The extending direction of the first groove portion is the same as the extending direction of at least one second groove portion, for example, one first groove portion or all of the plurality of first groove portions extend in the first direction; or one first groove portion or all of the plurality of first groove portions extend in the second direction; or a portion of the plurality of first groove portions extend in the first direction and a portion extend in the second direction.

[0080] Understandably, this arrangement increases the length of the device channel region, thereby effectively protecting the gate dielectric layer 170 in the second trench portion 124 while improving the conduction efficiency of the MOSFET device. Furthermore, compared to FIG8 , the trench portions still need to be arranged in both the first and second directions, so the process difficulty is not increased.

[0081] In some embodiments, the gate trench 120 includes a plurality of second trench portions extending along the second direction (marked as 124-1 in the figure for ease of distinction), a plurality of second trench portions extending along the first direction (marked as 124-2 in the figure), a first trench portion extending along the second direction (marked as 122-2 in the figure), and a first trench portion extending along the first direction (marked as 122-1 in the figure).

[0082] In some embodiments, the first trench portion can be located at the end of the second trench portion in the extension direction. For example, 122-1 is located at the end of 124-1 and intersects with 124-1, and 122-2 is located at the end of 124-2 and intersects with 124-2. This arrangement not only reduces the space occupied by the first trench portion relative to the second trench portion, but also increases the length of the device channel region, effectively protecting the gate dielectric layer in the second trench portion while ensuring the conductive efficiency of the MOSFET device.

[0083] FIG. 10 is a diagram showing the relationship between drain current and drain-source voltage according to some embodiments of the present application.

[0084] In FIG10 , L1 represents the relationship between the drain current and the drain-source voltage of a conventional MOSFET device with a column region electric field modulation structure, and L2 represents the relationship between the drain current and the drain-source voltage of the MOSFET device shown in the embodiment of the present application; wherein the horizontal axis Vd represents the drain-source voltage, and the vertical axis Id represents the drain current. As can be seen from FIG10 , under the same Vd condition, the drain current Id of the MOSFET device shown in the present application is much greater than the drain current Id of the conventional MOSFET device with a column region electric field modulation structure. Therefore, compared with the conventional MOSFET device with a column region electric field modulation structure, the MOSFET device shown in the embodiment of the present application can effectively reduce the characteristic on-resistance (Rsp) of the device.

[0085] The present application also provides a method for preparing a MOSFET device, which can be used to prepare the MOSFET device provided in the above embodiment. With reference to FIG. 11 to FIG. 17 , the preparation method includes:

[0086] Step S1: providing a semiconductor material layer (please refer to FIG. 12 for understanding);

[0087] Step S2: forming a well region in the semiconductor material layer (please refer to FIG. 13 for understanding);

[0088] Step S3: forming a gate trench in the semiconductor material layer, the gate trench including a first trench portion and a second trench portion, wherein the bottom wall of the first trench portion is located in the well region, and the second trench portion penetrates the well region and extends into the semiconductor material layer below the well region (please refer to FIG. 14 and FIG. 15 for understanding);

[0089] The semiconductor material layer below the well region has a first conductivity type, and the well region has a second conductivity type that is electrically opposite to the first conductivity type.

[0090] Step S4: An electric field shielding structure with a second conductivity type is formed below the gate trench. The electric field shielding structure includes a first structure portion and a second structure portion electrically connected to each other. The first structure portion is located below the first trench portion and is electrically in contact with the well region. The second structure portion is located below the second trench portion (please refer to Figures 16 and 17 for understanding).

[0091] As shown in FIG12 , a semiconductor material layer 110 is provided. Semiconductor material layer 110 is, for example, an epitaxial layer formed by epitaxial growth on substrate 105. As shown in FIG13 , a second conductivity type dopant may be doped from the upper surface of semiconductor material layer 110 to form a well region 112 having the second conductivity type. A portion 114 of semiconductor material layer 110 located below well region 112 is not implanted with ions and maintains the first conductivity type.

[0092] As shown in Figures 14 and 15, a gate trench 120 can be formed in the semiconductor material layer 110. The gate trench 120 includes a first trench portion 122 and a second trench portion 124. The first trench portion 122 extends from the upper surface of the semiconductor material layer 110 to the interior of the semiconductor material layer 110. The bottom wall of the first trench portion 122 is located in the well region 112. The second trench portion 124 penetrates the well region 112 from the upper surface of the semiconductor material layer 110 and extends into the semiconductor material layer below the well region 112 (see 114 in the figure). Figures 14 and 15 are schematic structural diagrams viewed from the side where the first trench portion 122 is formed and from the side where the second trench portion 124 is formed, respectively.

[0093] In some embodiments, the gate trench 120 can be formed based on the load effect of etching with different line widths. Specifically, a patterned mask layer can be formed on the semiconductor material layer 110, and the patterned mask layer includes a first pattern and a second pattern, wherein the first pattern corresponds to the predetermined formation position of the first trench portion 122, and the second pattern corresponds to the predetermined formation position of the second trench portion 124. The line width of the first pattern is smaller than the line width of the second pattern. Using the patterned mask layer as a mask, the semiconductor material layer 110 is etched. Based on the load effect of etching with different line widths (specifically, the load effect related to the etching aspect ratio), a first trench portion 122 corresponding to the first pattern and a second trench portion 124 corresponding to the second pattern can be formed. Since the line width of the first pattern is smaller than the line width of the second pattern, the first width of the formed first trench portion 122 is smaller than the second width of the second trench portion 124, and the first depth of the first trench portion 122 is smaller than the second depth of the second trench portion 124.

[0094] In some embodiments, other processes may also be used to form the first groove portion 122 and the second groove portion 124. For example, multiple photolithography processes may be performed to obtain the first groove portion 122 and the second groove portion 124 having different depths. For details, please refer to Figures 18 and 19 and their related descriptions.

[0095] Referring to Figures 16 and 17 , doping with a second conductive type dopant is performed at the bottom of the first trench portion 122 , for example, by ion implantation of the second conductive type, to form the first structure portion 132 ; and doping with a second conductive type dopant is performed at the bottom of the second trench portion 124 to form the second structure portion 134 . In some embodiments, the dopant doping to form the first structure portion 132 and the dopant doping to form the second structure portion 134 can be performed simultaneously, thereby reducing the process flow and lowering production costs. In some embodiments, the dopant doping to form the first structure portion 132 and the dopant doping to form the second structure portion 134 can be performed separately, which is not limited in this application. It can be understood that Figures 16 and 17 correspond to Figures 14 and 15 , respectively. Figure 16 is a schematic diagram of the structure viewed from the side where the first trench portion 122 is formed, and Figure 17 is a schematic diagram of the structure viewed from the side where the second trench portion 124 is formed.

[0096] The method for manufacturing a MOSFET device further includes sequentially forming a gate dielectric layer 170 and a gate electrode 160 in the gate trench 120. The gate dielectric layer 170 may be disposed between the gate electrode 160 and the inner wall of the gate trench 120, as shown in FIG1 and FIG2.

[0097] Figures 18 and 19 are schematic diagrams illustrating exemplary gate trench fabrication according to some embodiments of the present disclosure. As shown in Figure 18 , a first patterned mask layer 102 is formed on a semiconductor material layer 110. The first patterned mask layer 102 has a first opening 104 that exposes a portion of the semiconductor material layer 110. The first opening 104 corresponds to the predetermined location for forming the second trench portion 124. Using the first patterned mask layer 102 as a mask, a first etching process is performed to form a third trench portion 126 corresponding to the first opening 104.

[0098] As shown in FIG19 , a second patterned mask layer 106 is formed on the semiconductor material layer 110. The second patterned mask layer 106 has a second opening 108 and a third opening 107. The third opening 107 has the same exposed area as the first opening 104, and the second opening 108 exposes the predetermined formation location of the first trench portion 122. Using the second patterned mask layer 106 as a mask, a second etching process is performed to form a first trench portion 122 having a first depth corresponding to the second opening 108. The third trench portion 126 is further etched to form a second trench portion 124 having a second depth corresponding to the third opening 107, wherein the first depth is less than the second depth.

[0099] In some embodiments, the first trench portion 122 and the second trench portion 124 having different depths can be formed by any feasible method. For example, a first etching process can be performed using a patterned mask layer to form the first trench portion 122 having a first depth, and a second etching process can be performed using another patterned mask layer to form the second trench portion 124 having a second depth. In some embodiments, the first patterned mask layer 102 and / or the second patterned mask layer 106 is specifically a hard mask layer.

[0100] It should be noted that the MOSFET device embodiments provided in this application and the MOSFET device preparation method embodiments are based on the same concept; the various technical features in the technical solutions described in the various embodiments can be arbitrarily combined without conflict. However, it should be further noted that the MOSFET device provided in the embodiments of this application, the combination of its various technical features can already solve the technical problem to be solved by this application; therefore, the MOSFET device provided in the embodiments of this application is not limited by the MOSFET device preparation method provided in the embodiments of this application, and any device prepared by the preparation method that can form the MOSFET device structure provided in the embodiments of this application is within the scope of protection of this application.

[0101] In various embodiments of the present application, the MOSFET device is specifically, for example, a SiC MOSFET device.

[0102] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations of the claims. Various modifications and variations may be made to the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form additional embodiments of the present application that may not be explicitly described. Therefore, the above embodiments merely illustrate several implementations of the present application and do not limit the scope of protection of the patent application.

Claims

1. A MOSFET device, characterized in that: include: a semiconductor material layer including an upper surface and a lower surface opposite to each other; A well region, located in the semiconductor material layer and located on a side close to the upper surface; A gate trench extending from the upper surface of the semiconductor material layer to the interior of the semiconductor material layer; The gate trench comprises a first trench portion and a second trench portion, the bottom wall of the first trench portion is located in the well region, and the second trench portion penetrates the well region and extends into the semiconductor material layer below the well region; wherein the semiconductor material layer below the well region has a first conductivity type, and the well region has a second conductivity type that is electrically opposite to the first conductivity type; An electric field shielding structure is located below the gate trench and has a second conductivity type; the electric field shielding structure includes a first structure portion and a second structure portion electrically connected to each other, the first structure portion is located below the first trench portion and is electrically in contact with the well region, and the second structure portion is located below the second trench portion.

2. The MOSFET device according to claim 1, characterized in that The line width of the first trench portion is smaller than that of the second trench portion, and the gate trench is formed such that a depth of the first trench portion is smaller than a depth of the second trench portion based on a load effect of etching with different line widths.

3. The MOSFET device according to claim 1, characterized in that: Also includes: A source region, located in the well region; A source electrode, located on the well region and the source region; Wherein, the source region, the well region and the electric field shielding structure are grounded through the source electrode.

4. The MOSFET device according to claim 1, characterized in that: For any of the gate trenches, a total extending length of the first trench portion is less than or equal to a total extending length of the second trench portion.

5. The MOSFET device according to claim 1, characterized in that: The first groove portion is located in an extending direction of the second groove portion, the first groove portion extends in the same direction as the extending direction of the second groove portion, and a total extending length of the first groove portion is smaller than a total extending length of the second groove portion.

6. The MOSFET device according to claim 1, characterized in that: The first groove portion is located in the extension direction of the second groove portion, the first groove portion extends in the same direction as the extension direction of the second groove portion, the first groove portion and the second groove portion are alternately arranged in the extension direction, the extension lengths of each second groove portion are equal, and the spacing between two adjacent second groove portions is equal.

7. The MOSFET device according to claim 1, characterized in that: An extending direction of the first groove portion intersects with an extending direction of the second groove portion.

8. The MOSFET device according to claim 1, characterized in that: There are multiple second groove portions, each of which extends in at least two different directions. There are one or more first groove portions, and the extending direction of the first groove portion is the same as the extending direction of at least one second groove portion. The total extending direction of the first groove portion is The length is smaller than the total extension length of the second groove portion.

9. A method for preparing a MOSFET device, characterized in that: The method comprises: providing a semiconductor material layer; forming a well region in the semiconductor material layer; A gate trench is formed in the semiconductor material layer, the gate trench includes a first trench portion and a second trench portion, the bottom wall of the first trench portion is located in the well region, and the second trench portion penetrates the well region and extends into the semiconductor material layer below the well region; wherein the semiconductor material layer below the well region has a first conductivity type, and the well region has a second conductivity type that is electrically opposite to the first conductivity type; An electric field shielding structure with a second conductivity type is formed below the gate trench, and the electric field shielding structure includes a first structure portion and a second structure portion electrically connected to each other, the first structure portion is located below the first trench portion and is electrically in contact with the well region, and the second structure portion is located below the second trench portion.

10. The method for preparing a MOSFET device according to claim 9, characterized in that: The forming of a gate trench in the semiconductor material layer comprises: forming a patterned mask layer on the semiconductor material layer, wherein the patterned mask layer comprises a first pattern and a second pattern, and a line width of the first pattern is smaller than a line width of the second pattern; The semiconductor material layer is etched using the patterned mask layer as a mask, and the first groove portion having a first depth and the second groove portion having a second depth are formed based on a load effect of etching with different line widths, wherein the first depth is smaller than the second depth.

11. The method for preparing a MOSFET device according to claim 9, characterized in that: The forming of a gate trench in the semiconductor material layer comprises: forming a first patterned mask layer on the semiconductor material layer, wherein the first patterned mask layer has an opening exposing a predetermined formation position of the second groove portion; Using the first patterned mask layer as a mask, performing a first etching process; forming a second patterned mask layer on the semiconductor material layer, wherein the second patterned mask layer has openings exposing a predetermined formation position of the first groove portion and a predetermined formation position of the second groove portion; A second etching process is performed using the second patterned mask layer as a mask to form the first trench portion having a first depth and the second trench portion having a second depth, wherein the first depth is smaller than the second depth.

12. The method for preparing a MOSFET device according to claim 9, characterized in that: For any of the gate trenches, a total extending length of the first trench portion is less than or equal to a total extending length of the second trench portion.

13. The method for preparing a MOSFET device according to claim 9, characterized in that: The first groove portion is located in the extending direction of the second groove portion, the first groove portion extends in the same direction as the extending direction of the second groove portion, and the total extending length of the first groove portion is less than the total extending length of the second groove portion; or, The first groove portion is located in the extending direction of the second groove portion, the first groove portion extends in the same direction as the extending direction of the second groove portion, the first groove portion and the second groove portion are alternately arranged in the extending direction, and the extending lengths of the second groove portions are equal. The intervals between two adjacent second groove portions are equal.

14. The method for preparing a MOSFET device according to claim 9, characterized in that: An extending direction of the first groove portion intersects with an extending direction of the second groove portion.

15. The method for preparing a MOSFET device according to claim 9, characterized in that: The number of the second groove portions is multiple, and the multiple second groove portions extend in at least two different directions respectively. The number of the first groove portions is one or more, and the extension direction of the first groove portion is the same as the extension direction of at least one of the second groove portions. The total extension length of the first groove portion is less than the total extension length of the second groove portion.

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