Display panel and driving method therefor

Abstract

A display panel (PNL) and a driving method therefor. The display panel (PNL) comprises a plurality of display unit sets (DUS) arranged in sequence along a row direction (DH); and each display unit set (DUS) comprises a plurality of first display units (DU1) located in different display unit columns (VDU) and a plurality of second display units (DU2) located in different display unit columns (VDU). The display panel (PNL) is further provided with a first data line (DL1) and a second data line (DL2) that correspond to the display unit set (DUS); the first display units (DU1) of the display unit set (DUS) each are electrically connected to the first data line (DL1), and the second display units (DU2) of the display unit set (DUS) each are electrically connected to the corresponding second data line (DL2). The display panel (PNL) can reduce power consumption.

Description

Display panel and driving method thereof

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311434410.2, filed on October 31, 2023, entitled “A display panel and its driving method”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the technical field of pixel data line layout, and in particular to a display panel and a driving method thereof. Background Art

[0004] In the Pentile pixel arrangement, the red sub-pixels and the blue sub-pixels share a data line. The voltage on the data line needs to be refreshed once for each odd and even row, and it jumps cyclically between L255 and L0, resulting in additional power consumption.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a driving method thereof to reduce the power consumption of the display panel.

[0008] According to one aspect of the present disclosure, a display panel is provided, comprising a plurality of display unit sets sequentially arranged along a row direction; the display unit sets comprising a plurality of first display units located in different display unit columns and a plurality of second display units located in different display unit columns;

[0009] The display panel is also provided with a first data line and a second data line corresponding to the display unit set; each first display unit of the display unit set is electrically connected to the first data line, and each second display unit of the display unit set is electrically connected to the corresponding second data line.

[0010] According to one embodiment of the present disclosure, the display unit set includes a first display unit column arranged adjacent to the first data line and a second display unit column arranged adjacent to the second data line; the first display unit column includes first display units and second display units arranged alternately in sequence along the column direction; the second display unit column includes second display units and first display units arranged alternately in sequence along the column direction.

[0011] According to an embodiment of the present disclosure, in the same display unit row, the first display units and the second display units are alternately arranged.

[0012] According to one embodiment of the present disclosure, the display unit set includes a first display unit column, a third display unit column, a second display unit column and a fourth display unit column arranged in sequence along the row direction; the third display unit column and the fourth display unit column both include multiple third display units arranged in sequence along the column direction.

[0013] According to an embodiment of the present disclosure, in the same display unit row, each row of sub-pixels includes one first display unit, one second display unit and two third display units.

[0014] According to an embodiment of the present disclosure, the display panel is further provided with a third data trace and a fourth data trace corresponding to the display unit set;

[0015] Each third display unit in the third display unit column is electrically connected to a third data line, and each third display unit in the fourth display unit column is electrically connected to a fourth data line.

[0016] According to an embodiment of the present disclosure, the third data line is disposed adjacent to the first data line and is located between each pixel driving circuit of the first display unit column and each pixel driving circuit of the third display unit column;

[0017] The fourth data line and the second data line are arranged adjacent to each other and are located between each pixel driving circuit of the second display unit column and each pixel driving circuit of the fourth display unit column.

[0018] According to an embodiment of the present disclosure, the display panel is provided with a first adapter cable and a second adapter cable;

[0019] The second display unit located in the first display unit column is electrically connected to the second data line through the second adapter line;

[0020] The first display unit located in the second display unit column is electrically connected to the first data line through the first adapter line.

[0021] According to one embodiment of the present disclosure, the display panel includes a base substrate, a driving circuit layer, and a pixel layer stacked in sequence; the driving circuit layer includes a transistor layer, a first source-drain metal layer, a transfer metal layer, and a second source-drain metal layer stacked in sequence; each transistor of the pixel driving circuit of the display unit is arranged in the transistor layer; and the sub-pixels of the display unit are arranged in the pixel electrode layer;

[0022] The second source / drain metal layer is provided with the first data wiring and the second data wiring;

[0023] The transfer metal layer is provided with a first transfer metal structure, a first transfer wire and a second transfer wire; wherein,

[0024] The data voltage input terminal of the pixel driving circuit of the first display unit adjacent to the first data line is electrically connected to the first transfer metal structure corresponding to the first display unit through a via hole; the first transfer metal structure is electrically connected to the first data line through a via hole;

[0025] The data voltage input terminal of the pixel driving circuit of the second display unit adjacent to the second data line is electrically connected to the first transfer metal structure corresponding to the second display unit through a via hole, and the first transfer metal structure is electrically connected to the second data line through a via hole;

[0026] The data voltage input terminal of the pixel driving circuit of the first display unit adjacent to the second data line is electrically connected to the first end of the first adapter line through a via hole, and the second end of the first adapter line is electrically connected to the first data line through a via hole;

[0027] The data voltage input terminal of the pixel driving circuit of the second display unit adjacent to the first data line is electrically connected to the first end of the second adapter line through a via hole, and the second end of the second adapter line is electrically connected to the second data line through a via hole.

[0028] According to an embodiment of the present disclosure, the shape of the first end of the second patch cord is the same as the shape of the first patch metal structure; the second end of the second patch cord is adjacent to and insulated from the first end of the first patch cord;

[0029] The shape of the first end of the first transition wire is the same as that of the first transition metal structure; the second end of the first transition wire is adjacent to and insulated from the first end of the second transition wire.

[0030] According to an embodiment of the present disclosure, the second source-drain metal layer further includes a driving voltage trace;

[0031] A first avoidance gap is formed on a side of the driving voltage line close to the first data line; the orthographic projection of the second end of the first adapter line on the plane where the display panel is located is located within the orthographic projection of the first avoidance gap on the plane where the display panel is located;

[0032] The driving voltage line has a second avoidance gap on one side close to the second data line; the orthographic projection of the second end of the second adapter line on the plane where the display panel is located is located within the orthographic projection of the second avoidance gap on the plane where the display panel is located.

[0033] According to an embodiment of the present disclosure, the first data line has a first side branch portion extending deep into the first avoidance gap, and the first side branch portion is electrically connected to the second end of the first adapter line through a via;

[0034] The second data wiring has a second side branch portion extending deep into the second avoidance gap, and the second side branch portion is electrically connected to the second end of the second adapter wire through a via.

[0035] According to another aspect of the present disclosure, there is provided a method for driving a display panel, comprising: driving each display unit row by row;

[0036] When driving any display unit row, the driving voltage required by the first display unit of the display unit set is loaded onto the first data line corresponding to the display unit set, and the driving voltage required by the second display unit of the display unit set is loaded onto the second data line corresponding to the display unit set.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0039] FIG1 is a schematic structural diagram of a display panel in the related art.

[0040] FIG2 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0041] FIG3 is a schematic diagram of a cross-sectional structure of a display panel in one embodiment of the present disclosure.

[0042] FIG4 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0043] 5 is a schematic diagram of a stacked structure of a polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer, and a first source-drain metal layer in a circuit layout region according to an embodiment of the present disclosure.

[0044] FIG6 is a schematic diagram of a partial structure of a metal light-shielding layer in one embodiment of the present disclosure.

[0045] FIG7 is a schematic diagram of a partial structure of a polysilicon semiconductor layer in one embodiment of the present disclosure.

[0046] FIG8 is a schematic diagram of a partial structure of a first gate layer in one embodiment of the present disclosure.

[0047] FIG9 is a schematic diagram of a partial structure of a second gate layer in one embodiment of the present disclosure.

[0048] FIG10 is a schematic diagram of a partial structure of a metal oxide semiconductor layer in one embodiment of the present disclosure.

[0049] FIG11 is a schematic diagram of a partial structure of a third gate layer in one embodiment of the present disclosure.

[0050] FIG12 is a schematic diagram of a partial structure of a first source / drain metal layer in one embodiment of the present disclosure.

[0051] FIG13 is a schematic diagram of a stacked structure of a second gate layer, a metal oxide semiconductor layer, a third gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0052] FIG14 is a schematic diagram of a partial structure of a transfer metal layer in one embodiment of the present disclosure.

[0053] FIG15 is a schematic diagram of the stacked structure of the second source-drain metal layer in one embodiment of the present disclosure.

[0054] FIG16 is a schematic diagram of the stacked structure of the transfer metal layer and the second source-drain metal layer in one embodiment of the present disclosure.

[0055] FIG17 is a schematic diagram of the stacked structure of a transfer metal layer, a second source / drain metal layer, and a pixel layer in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed description will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0057] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0058] In the present disclosure, a transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the region where the current mainly flows. In cases where transistors with opposite polarities are used or where the direction of current changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchangeable. Therefore, in this specification, "source" and "drain" are relative concepts that can be interchanged.

[0059] In the present disclosure, when describing the overlapping arrangement of structure A and structure B, it means that structure A and structure B are arranged in different film layers, and the orthographic projection of structure A on the substrate overlaps with the orthographic projection of structure B on the substrate.

[0060] In the present disclosure, the overlapping part of structure C and structure D refers to a specific part C1 in structure C; the orthographic projection of the specific part C1 on the substrate is the overlapping part of the orthographic projection of structure C on the substrate and the orthographic projection of structure D on the substrate.

[0061] In the present disclosure, the structural layer E is located on the side of the structural layer F away from the base substrate. This can be understood as the structural layer E being formed on the side of the structural layer F away from the base substrate. When the structural layer F is a patterned structure, part of the structure layer E may also be located at the same physical height as the structural layer E or lower than the physical height of the structural layer E, where the base substrate serves as a height reference.

[0062] FIG1 is a schematic structural diagram of a display panel in the related art. Referring to FIG1 , in the related art, the display panel has display unit columns and data lines DL corresponding to the display unit columns. Among them, each pixel driving circuit PDC of the display unit column is electrically connected to the data line DL corresponding to the display unit column. Some of the display unit columns have display units DU of different colors, and these display units DU of different colors are driven by the same data line DL. For example, at least one display unit column includes alternating red display units and blue display units; the voltage on the data line is refreshed once for each odd row and even row, and it cyclically jumps between grayscale Lmax and grayscale L0, resulting in additional power consumption. Among them, grayscale Lmax is the maximum value of the grayscale of the display panel, for example, 255 grayscales.

[0063] The present disclosure provides a display panel PNL. Referring to FIG. 2 , the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. Within the display area AA, the display panel PNL is provided with an array of display units DU (e.g., the first display unit DU1, the second display unit DU2, and the third display unit DU3 in FIG. 2 ). The display units DU include sub-pixels PIX (e.g., the first sub-pixel PIX1, the second sub-pixel PIX2, and the third sub-pixel PIX3 in FIG. 2 ) and pixel drive circuits PDC for driving the sub-pixels PIX. The display panel PNL does not have display units DU in the peripheral area BB, or the display units DU provided are not used for displaying images. The display panel PNL is provided with a plurality of scan lines (not shown in FIG. 2 ) extending along the row direction DH within the display area AA. Each scan line corresponds to a display unit row HDU. The pixel drive circuit PDC of each display unit DU within the display unit row is electrically connected to the corresponding scan line. The display panel PNL is also provided with a plurality of data lines DL extending along the column direction DV within the display area AA. Each data line DL is provided in a one-to-one correspondence with each display unit column VDU. The pixel driver circuit PDC of each display unit DU is connected to a scan line and a data line DL. When a scan signal is applied to the scan line, the drive voltage applied to the data line DL can be written into the pixel driver circuit PDC, which can then control the brightness of the sub-pixel PIX based on the written drive voltage.

[0064] The display panel PNL includes a plurality of display unit sets DUS (only one is illustrated in FIG2 ) arranged in sequence along the row direction DH; referring to FIG2 , the display unit set DUS includes a plurality of first display units DU1 located in different display unit columns VDU and a plurality of second display units DU2 located in different display unit columns VDU. The display panel PNL is also provided with a first data line DL1 and a second data line DL2 corresponding to the display unit set DUS. Each first display unit DU1 of the display unit set DUS is electrically connected to the first data line DL1, and each second display unit DU2 of the display unit set DUS is electrically connected to the corresponding second data line DL2. In this way, the first data line DL1 can be used to load the data voltage for controlling each first display unit DU1, and the second data line DL2 can be used to load the data voltage for controlling each second display unit DU2, thereby avoiding the extra power consumption generated by the same data line simultaneously controlling the first display unit DU1 and the second display unit DU2, thereby reducing the power consumption of the display panel.

[0065] It can be understood that the voltage signal on the first data line DL1 is written into the pixel driving circuit PDC of each first display unit DU1 in sequence according to the preset control timing, and the voltage signal on the second data line DL2 is written into the pixel driving circuit PDC of each second display unit DU2 in sequence according to the preset control timing, and the control of the corresponding sub-pixel PIX is realized through the pixel driving circuit PDC.

[0066] In one embodiment of the present disclosure, as shown in FIG2 , the display unit set DUS includes a first display unit column VDU1, a third display unit column VDU3A, a second display unit column VDU2, and a fourth display unit column VDU3B arranged sequentially along the row direction DH. The first display unit column VDU1 is adjacent to the first data line DL1, and the second display unit column VDU2 is adjacent to the second data line DL2. In one example, the first display unit column VDU1 includes first display units DU1 and second display units DU2 arranged alternately along the row direction DV; the second display unit column VDU2 includes second display units DU2 and first display units DU1 arranged alternately along the row direction DV. The second display unit DU2 in the first display unit column VDU1 is electrically connected to the second data line DL2, and the first display unit DU1 in the second display unit column VDU2 is electrically connected to the first data line DL1. In this way, while maintaining the existing pixel arrangement, within a display unit set DUS, the first data line DL1 controls the first display unit DU1, and the second data line DL2 controls the second display unit DU2.

[0067] In one embodiment of the present disclosure, the display panel PNL is further provided with a third data line DL3A and a fourth data line DL3B corresponding to the display unit set DUS. The third display unit column VDU3A is disposed adjacent to the third data line DL3A, and the fourth display unit column VDU3B is disposed adjacent to the fourth data line DL3B. Both the third display unit column VDU3A and the fourth display unit column VDU3B include a plurality of third display units DU3 arranged sequentially along a line DV. Each third display unit DU3 in the third display unit column VDU3A is electrically connected to the third data line DL3A, and each third display unit DU3 in the fourth display unit column VDU3B is electrically connected to the fourth data line DL3B.

[0068] In one embodiment of the present disclosure, in a display unit set DUS, the same display unit row includes one first display unit DU1, one second display unit DU2, and two third display units DU3. In the same display unit row, the first display unit DU1 and the second display unit DU2 are alternately arranged. For example, as shown in FIG2 , the sub-pixels of the first display unit row in the display unit set DUS are the first display unit DU1, the third display unit DU3, the second display unit DU2, and the third display unit DU3, respectively; and the sub-pixels of the adjacent second display unit row are the second display unit DU2, the third display unit DU3, the first display unit DU1, and the third display unit DU3, respectively.

[0069] In one embodiment of the present disclosure, the third data line DL3A and the first data line DL1 are arranged adjacent to each other, and the third data line DL3A and the first data line DL1 are both located between the respective pixel driving circuits PDC of the first display unit column VDU1 and the respective pixel driving circuits PDC of the third display unit column VDU3A; the fourth data line DL3B and the second data line DL2 are arranged adjacent to each other, and the fourth data line DL3B and the second data line DL2 are both located between the respective pixel driving circuits PDC of the second display unit column VDU2 and the respective pixel driving circuits PDC of the fourth display unit column VDU3B.

[0070] In one embodiment of the present disclosure, referring to FIG2 , a display panel PNL is provided with a first adapter line TRL1 and a second adapter line TRL2. The second display unit DU2 located in the first display unit column VDU1 is electrically connected to the second data line DL2 via the second adapter line TRL2. The first display unit DU1 located in the second display unit column VDU2 is electrically connected to the first data line DL1 via the first adapter line TRL1. Thus, by bridging the first adapter line TRL1 and the second adapter line TRL2, the same data line DL only needs to control display units DU of one color, based on the existing pixel arrangement. This reduces the power consumption of the display panel without affecting the existing pixel arrangement.

[0071] In one embodiment of the present disclosure, a first display unit DU1 includes a pixel driving circuit PDC and a first subpixel PIX1 driven by the pixel driving circuit PDC; a second display unit DU2 includes a pixel driving circuit PDC and a second subpixel PIX2 driven by the pixel driving circuit PDC; and a third display unit DU3 includes a pixel driving circuit PDC and a third subpixel PIX3 driven by the pixel driving circuit PDC. The first subpixel PIX1, the second subpixel PIX2, and the third subpixel PIX3 have different colors; furthermore, the first subpixel PIX1, the second subpixel PIX2, and the third subpixel PIX3 have different sizes.

[0072] In one example, the sizes of the first sub-pixel PIX1 , the second sub-pixel PIX2 , and the third sub-pixel PIX3 decrease in sequence.

[0073] In an example, the first sub-pixel PIX1 is a blue sub-pixel; the second sub-pixel PIX2 is a red sub-pixel; and the third sub-pixel PIX3 is a green sub-pixel.

[0074] 3 illustrates a cross-sectional view of a display panel according to an embodiment of the present disclosure. The display panel includes a base substrate BP, a driving circuit layer FA, and a pixel layer FB stacked in sequence.

[0075] The substrate substrate BP may be a substrate substrate BP of an inorganic material, or a substrate substrate BP of an organic material. For example, in one embodiment of the present disclosure, the material of the substrate substrate BP may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or may be a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate substrate BP may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. In another embodiment of the present disclosure, the substrate substrate BP may also be a flexible substrate substrate BP, for example, the material of the substrate substrate BP may be polyimide (PI). The substrate BP can also be a composite of multiple layers of materials. For example, in one embodiment of the present disclosure, the substrate BP can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer stacked in sequence.

[0076] As an example, in Figure 3, the base substrate BP is made of polyimide, enabling the display panel to be flexible. Referring to Figure 3, the display panel can be initially formed on a supporting substrate SBP, which can then be peeled off after fabrication. This allows the supporting substrate SBP to provide support for the display panel during the manufacturing process.

[0077] The driving circuit layer FA is provided with a pixel driving circuit PDC for driving sub-pixels. The driving circuit layer FA includes a transistor layer, and each transistor of the pixel driving circuit PDC of the display unit DU is provided in the transistor layer. In the driving circuit layer FA, any pixel driving circuit PDC may include a transistor and a storage capacitor. In the example of Figure 3, the driving circuit layer may be provided with a polycrystalline silicon semiconductor layer SEMI1 and a metal oxide semiconductor layer SEMI2, so that the transistors in the driving circuit layer may include metal oxide transistors and polycrystalline silicon transistors (such as low-temperature polycrystalline silicon transistors) at the same time. Furthermore, these transistors may be thin film transistors. Of course, in other embodiments of the present disclosure, polycrystalline silicon transistors may also be amorphous silicon transistors; accordingly, the polycrystalline silicon semiconductor layer SEMI1 of the driving circuit layer may be replaced by an amorphous silicon semiconductor layer.

[0078] In one embodiment of the present disclosure, the polysilicon transistor may be a top-gate thin-film transistor, a bottom-gate thin-film transistor, or a dual-gate thin-film transistor, whichever is capable of effectively controlling the transistor. The metal oxide transistor is a dual-gate thin-film transistor, i.e., the channel region of the transistor is sandwiched between a top gate (the gate on the side away from the substrate) and a bottom gate (the gate on the side close to the substrate); thus, the bottom gate can block light from the substrate, preventing light from reaching the channel region of the transistor and causing abnormal operation of the transistor.

[0079] In some embodiments of the present disclosure, the gate of the polysilicon transistor can be disposed in the same layer as a gate of a metal oxide transistor. For example, the gate of the polysilicon transistor and the bottom gate of the metal oxide transistor are disposed in the same gate layer. In other embodiments, the gate of the polysilicon transistor and the top gate and bottom gate of the metal oxide transistor can be disposed in different gate layers, respectively.

[0080] As an example, referring to FIG3 , the driver circuit layer includes a polysilicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer SEMI2, a third gate insulating layer GI3, and a third gate layer GT3, which are sequentially stacked on one side of the substrate BP. The polysilicon semiconductor layer SEMI1 is provided with the active region of the polysilicon transistor, and the first gate layer GT1 is provided with the gate of the polysilicon transistor. The metal oxide semiconductor layer SEMI2 is provided with the active region of the metal oxide transistor; the second gate layer GT2 is provided with the bottom gate of the metal oxide transistor; and the third gate layer GT3 is provided with the top gate of the metal oxide transistor. In the present disclosure, the active region of the transistor includes the channel region of the transistor and the source and drain located on both sides of the channel region; wherein the channel region maintains semiconductor characteristics, and the source and drain are conductive.

[0081] In one example, the display panel further includes control traces for applying control signals to the gates of the transistors. These control traces may extend substantially along a row direction and be electrically connected to the gates of the driven transistors.

[0082] In an embodiment of the present disclosure, the driver circuit layer further comprises a metal layer, which is located on the side of each gate layer and semiconductor layer away from the substrate BP. The metal layer is provided with a data line DL for applying a data voltage Data and a drive voltage line VDDL for applying a drive voltage VDD. The data line DL is used to apply the data voltage Data to the pixel driver circuit PDC, so that the pixel driver circuit PDC controls the brightness of the subpixel based on the voltage value of the data voltage Data. In the example of FIG3 , the metal layer comprises three layers, including a first source / drain metal layer SD1, a transfer metal layer DRL, and a second source / drain metal layer SD2. An interlayer dielectric layer ILD is provided on the surface of the first source / drain metal layer SD1 near the substrate BP. A first planarization layer PLN1 is provided between the first source / drain metal layer SD1 and the transfer metal layer DRL. A second planarization layer PLN2 is provided between the transfer metal layer DRL and the second source / drain metal layer SD2. A third planarization layer PLN3 is provided on the side of the second source / drain metal layer SD2 away from the substrate BP.

[0083] Optionally, the drive circuit layer FA may further include a first buffer layer Buff1 disposed between the base substrate BP and the semiconductor layer, with the semiconductor layer and gate layer located on a side of the first buffer layer Buff1 away from the base substrate BP. The first buffer layer Buff1 may be made of an inorganic insulating material such as silicon oxide or silicon nitride. The first buffer layer Buff1 may be a single inorganic material layer or a plurality of stacked inorganic material layers.

[0084] Optionally, the driving circuit layer FA may further include a metal light-shielding layer LS located between the first buffer layer Buff1 and the base substrate BP, and the metal light-shielding layer LS may shield at least part of the channel region of the transistor. Furthermore, in some embodiments, the metal light-shielding layer LS may be electrically connected to the metal layer through a via, so that the metal light-shielding layer LS may perform signal transmission, signal shielding or other functions as needed. For example, the metal light-shielding layer LS may be loaded with a common electrode voltage so that the metal light-shielding layer LS can achieve the function of signal shielding. For another example, a portion of the metal light-shielding layer LS is patterned into a conductive wire so that the conductive wire located in the metal light-shielding layer LS can be used to transmit signals, such as transmitting touch signals.

[0085] Optionally, an inorganic barrier layer Barr may be further provided between the metal light-shielding layer LS and the first buffer layer Buff1 to prevent the material in the base substrate BP from penetrating into the driving circuit layer.

[0086] The pixel layer FB is provided with light-emitting elements distributed in an array, and each light-emitting element emits light under the control of the pixel driving circuit. These light-emitting elements can serve as sub-pixels in the embodiment of the present disclosure. In the present disclosure, the light-emitting element can be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot-organic light-emitting diode (QD-OLED), a quantum dot light-emitting diode (QLED) or other types of light-emitting elements. For example, as follows, taking the light-emitting element as an organic light-emitting diode as an example, a feasible structure of the pixel layer is exemplarily introduced.

[0087] In this example, the pixel layer FB can be arranged on the side of the driving circuit layer FA away from the base substrate BP, which may include a pixel electrode layer ANL, a pixel definition layer PDL, a support column layer PS, an organic light-emitting functional layer EL and a common electrode layer COML stacked in sequence. The pixel electrode layer ANL has a plurality of pixel electrodes in the display area of ​​the display panel; the pixel definition layer PDL has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes in the display area, and any pixel opening exposes at least a portion of the corresponding pixel electrode. The support column layer PS includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer PDL away from the base substrate BP so as to support the fine metal mask (FMM) during the evaporation process. The organic light-emitting functional layer EL at least covers the pixel electrode exposed by the pixel definition layer PDL. The organic light-emitting functional layer EL may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer. Each film layer of the organic light-emitting functional layer EL can be prepared by an evaporation process, and a fine metal mask or an open mask (Open Mask) can be used to define the pattern of each film layer during evaporation. The common electrode layer COML can cover the organic light-emitting functional layer EL in the display area. In this way, the pixel electrode, the common electrode layer COML and the organic light-emitting functional layer EL located between the pixel electrode and the common electrode layer COML form an organic electroluminescent diode, and any organic electroluminescent diode can be used as a sub-pixel of the display panel. In this embodiment, referring to Figure 17, the sub-pixel PIX may include sub-pixels PIX of multiple different colors, for example, a red sub-pixel R for emitting red light, a blue sub-pixel B for emitting blue light, and a green sub-pixel G for emitting green light.

[0088] In some embodiments, the pixel layer FB may further include a light extraction layer located on a side of the common electrode layer COML away from the base substrate BP to enhance light extraction efficiency of the organic light emitting diode.

[0089] Optionally, the display panel may further include a thin film encapsulation layer TFE. The thin film encapsulation layer TFE is provided on the surface of the pixel layer FB away from the base substrate BP, and may include an inorganic encapsulation layer and an organic encapsulation layer that are alternately stacked. Among them, the inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the organic light-emitting functional layer EL and causing material degradation. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve flattening and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer FB away from the base substrate BP.

[0090] In one embodiment of the present disclosure, the pixel driving circuit PDC includes a storage capacitor Cst and a plurality of transistors, wherein a portion of the transistors may be polysilicon transistors and another portion may be metal oxide transistors.

[0091] FIG4 provides a pixel driving circuit PDC as an example. Referring to FIG4 , the exemplary pixel driving circuit PDC includes transistors such as a storage capacitor Cst, a threshold compensation transistor T2, a driving transistor T3, a capacitor reset transistor T1, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a pixel electrode reset transistor T7. The threshold compensation transistor T2 is a metal oxide transistor, which is used to compensate the threshold voltage of the driving transistor T3 in response to the threshold compensation signal GN1. The driving transistor T3 is a polysilicon transistor, which can generate a driving current under the control of the first node N1. It is understood that in other examples of the present disclosure, the pixel driving circuit PDC may also include other transistors or a storage capacitor Cst, or may have fewer transistors; the electrical connection relationship between the transistors, the loaded signals, and the timing of the loaded signals may also be different from the pixel driving circuit PDC shown in FIG3 .

[0092] As follows, the structure, principle and effect of the display panel according to the embodiment of the present disclosure are further introduced and illustrated by taking the pixel driving circuit PDC shown in FIG. 4 as an example.

[0093] In the pixel driving circuit PDC illustrated in FIG4 , the first electrode plate of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode plate of the storage capacitor Cst is used to load the driving voltage VDD. In this way, the voltage loaded on the second electrode plate of the storage capacitor Cst is stable. In some other embodiments of the present disclosure, the second electrode plate of the storage capacitor Cst can be loaded with other power supply voltages, such as the same common voltage as the common electrode layer. Of course, in other embodiments of the present disclosure, the voltage of the second electrode plate of the storage capacitor may not be constant, for example, the drain of the capacitor reset transistor and the drain of the data write transistor are electrically connected to the second electrode plate of the storage capacitor; the capacitor reset transistor is used to reset the voltage of the second electrode plate of the storage capacitor, and the data write transistor is used to load the data voltage to the second electrode plate of the storage capacitor; through coupling, the voltage of the first node can be adjusted as the voltage of the second electrode plate of the storage capacitor is adjusted.

[0094] In the pixel driving circuit PDC shown in FIG4 , the pixel driving circuit PDC further includes a first emission control transistor T5 and a second emission control transistor T6. The source of the first emission control transistor T5 is configured to apply a driving voltage VDD and is, for example, electrically connected to a data line DL for applying the driving voltage VDD. The drain of the first emission control transistor T5 is electrically connected to a third node N3. The source of the second emission control transistor T6 is electrically connected to a second node N2, and the drain of the second emission control transistor T6 is electrically connected to a fourth node N4, which is also electrically connected to a pixel electrode of the subpixel. The gates of the first emission control transistor T5 and the second emission control transistor T6 are configured to apply an emission control signal EM and are, for example, electrically connected to an emission control line EML for applying the emission control signal EM. When the first emission control transistor T5 and the second emission control transistor T6 are turned on in response to the emission control signal EM, the drive current generated by the driving transistor T3 can flow to the subpixel, thereby driving the subpixel to emit light. Furthermore, the first emission control transistor T5 and the second emission control transistor T6 can be polysilicon transistors. Of course, in other embodiments of the present disclosure, the pixel driving circuit PDC may include only one of the first light emission control transistor T5 and the second light emission control transistor T6.

[0095] In the pixel driving circuit PDC shown in FIG4 , the pixel driving circuit PDC further includes a capacitor reset transistor T1 and a data write transistor T4. The source of the capacitor reset transistor T1 is used to load a first initialization voltage Vinit1, and the drain of the capacitor reset transistor T1 is electrically connected to the first node N1. The capacitor reset transistor T1 is used to load the first initialization voltage Vinit1 to the first node N1 in response to the capacitor reset signal GN2, thereby resetting the first node N1. In this example, the capacitor reset transistor T1 is a metal oxide semiconductor transistor. In other examples of the present disclosure, the capacitor reset transistor T1 may also be a polysilicon transistor. The data write transistor T4 is a polysilicon transistor. The source of the data write transistor T4 is used to load a data voltage Data, for example, electrically connected to a data line DL for loading the data voltage Data. The drain of the data write transistor T4 is electrically connected to the third node N3. The data write transistor T4 is used to load the data voltage Data to the third node N3 in response to the data scan signal GP.

[0096] In the pixel driver circuit PDC shown in FIG4 , the pixel driver circuit PDC further includes a pixel electrode reset transistor T7, which is a polysilicon transistor. The source of the pixel electrode reset transistor T7 is used to apply the second initialization voltage Vinit2, for example, electrically connected to a second initialization voltage trace Vinit2L for applying the second initialization voltage Vinit2. The drain of the pixel electrode reset transistor T7 is electrically connected to a fourth node N4. The pixel electrode reset transistor T7 is used to apply the second initialization voltage Vinit2 to the fourth node N4 in response to a pixel electrode reset signal RP, thereby resetting the pixel electrode of the sub-pixel. Of course, in other embodiments of the present disclosure, the pixel driver circuit PDC may not include the pixel electrode reset transistor T7, or the pixel electrode reset transistor T7 may be a metal oxide thin film transistor.

[0097] In the pixel driving circuit PDC shown in FIG4 , the first initialization voltage Vinit1 applied to the source of the capacitor reset transistor T1 and the second initialization voltage Vinit2 applied to the source of the pixel electrode reset transistor T7 can be different voltage signals, for example, voltage signals from different wirings (the voltages can be the same). In other examples of the present disclosure, the first initialization voltage Vinit1 applied to the source of the capacitor reset transistor T1 and the second initialization voltage Vinit2 applied to the source of the pixel electrode reset transistor T7 can also be the same signal, for example, a signal from the same wiring.

[0098] In the display panel of the present disclosure, the pixel driver circuit PDC shown in FIG4 can operate sequentially according to the following timing sequence. During the capacitor reset phase, the gate of the capacitor reset transistor T1 is applied with the capacitor reset signal GN2 and turned on, causing the first node N1 to be reset to the first initialization voltage Vinit1. At this time, under the control of the first node N1, the drive transistor T3 is turned on. The threshold compensation transistor T2, the first emission control transistor T5, the second emission control transistor T6, the data write transistor T4, and the pixel electrode reset transistor T7 remain off.

[0099] During the data write phase, the data scan signal GP is applied to the gate of the data write transistor T4, turning on the data write transistor T4 and writing the data voltage Data to the third node N3. The threshold compensation signal GN1 is applied to the gate of the threshold compensation transistor T2, turning on the threshold compensation transistor T2. The capacitor reset transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 remain off. In this way, the third node N3 can charge the first node N1, raising the voltage of the first node N1 until the first node N1 is raised to a level that turns off the driving transistor T3. Thus, the data voltage Data and the threshold voltage of the driving transistor T3 are written to the first node N1. The voltage of the first node N1 is VData + Vth3, where Vth3 is the threshold voltage of the driving transistor T3 and VData is the voltage value of the data voltage Data. Thus, during the data write phase, data writing and threshold compensation of the driving transistor T3 are simultaneously achieved.

[0100] In the pixel electrode reset phase, the gate of the pixel electrode reset transistor T7 is loaded with the pixel electrode reset signal RP, causing the pixel electrode reset transistor T7 to be turned on, thereby causing the second initialization voltage Vinit2 to be loaded to the fourth node N4. In some embodiments, the pixel electrode reset signal RP of the pixel driving circuit PDC of the previous row and the data scanning signal GP of the pixel driving circuit PDC of the next row are the same signal, so that when the pixel driving circuit PDC of the previous row is in the pixel electrode reset phase, the pixel driving circuit PDC of the next row is in the data writing phase. Of course, in other examples of the present disclosure, the pixel electrode reset signal RP and the data scanning signal GP of the pixel driving circuit PDC of the same row can be the same signal, and the pixel electrode reset phase and the data writing phase of the pixel driving circuit PDC of this row are the same phase, that is, the data writing transistor T4 and the pixel electrode reset transistor T7 are synchronously turned on or off.

[0101] During the light-emitting phase, the gates of the first and second light-emitting control transistors T5 and T6 are loaded with the light-emitting control signal EM, turning on the first and second light-emitting control transistors T5 and T6. As a result, the drive voltage VDD is applied to the third node N3, and the second node N2 is electrically connected to the sub-pixel. Under the control of the first node N1, the drive transistor T3 outputs a drive current, thereby driving the sub-pixel to emit light.

[0102] It is understandable that the pixel driving circuit PDC of the 7T1C (7 transistors and 1 storage capacitor) exemplified in the present disclosure is merely one of the exemplary pixel driving circuits PDC of the display panel of the present disclosure, and is not a specific limitation of the pixel driving circuit PDC used in the display panel of the present disclosure. In other embodiments of the present disclosure, the pixel driving circuit PDC may include more or fewer transistors, for example, 8 transistors, 9 transistors, etc., and one or more of the transistors exemplified in the above 7T1C may also be configured as a plurality of sub-transistors connected in series. In other embodiments of the present disclosure, the pixel driving circuit PDC may include more storage capacitors Cst, for example, two or three storage capacitors.

[0103] In the display panel disclosed herein, the pixel driving circuit PDC can reduce the leakage of the first node N1 by setting the threshold compensation transistor T2 to a metal oxide transistor, thereby improving the voltage holding capability of the pixel driving circuit PDC, reducing the flicker risk of the display panel under low-frequency driving and reducing the power consumption of the display panel.

[0104] The following describes and illustrates the specific layout of the 7T1C pixel driver circuit PDC in the display panel, using the accompanying drawings. It is understood that the 7T1C illustrated in the embodiments of the present disclosure may also be presented in other layouts, and the display panel of the present disclosure may also employ other pixel driver circuit PDCs. When other pixel driver circuit PDC structures are employed, the layout of the pixel driver circuit PDC in the display panel of the present disclosure may be adjusted accordingly.

[0105] 3 , in the display panel of this example, the driving circuit layer FA includes a metal light-shielding layer LS, an inorganic barrier layer Barr, a first buffer layer Buff1, a polycrystalline silicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer SEMI2, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source-drain metal layer SD1, a first planarization layer PLN1, a transfer metal layer DRL, a second planarization layer PLN2, a second source-drain metal layer SD2, and a third planarization layer PLN3, which are sequentially stacked on one side of the substrate BP. It will be understood that in some other embodiments of the display panel of the present disclosure, the metal light-shielding layer LS may not be provided.

[0106] In the display area AA, the primary area where the pixel driver circuit PDC is located can be defined as the circuit layout area PDCA corresponding to the pixel driver circuit PDC. Thus, the primary or majority transistors and storage capacitor Cst of the pixel driver circuit PDC are located within the corresponding circuit layout area PDCA. Referring to FIG5 , the circuit layout area PDCA can be rectangular. In two adjacent rows of pixel driver circuits PDC, the pixel electrode reset transistor T7 of the pixel driver circuit PDC in the previous row can be located within the circuit layout area PDCA corresponding to the pixel driver circuit PDC in the next row. In other words, the capacitor reset transistor T1 to the second light-emitting control transistor T6 and the storage capacitor Cst of the pixel driver circuit PDC are located within the circuit layout area PDCA corresponding to the pixel driver circuit PDC, while the pixel electrode reset transistor T7 of the pixel driver circuit PDC is located within the circuit layout area PDCA in the next row. In the example of the present disclosure, the layouts of two adjacent pixel driver circuits PDC can be mirrored. Of course, in other embodiments of the present disclosure, the layouts of two adjacent pixel driver circuits PDC can also be identical rather than mirrored.

[0107] FIG6 shows a schematic diagram of the partial structure of the metal light-shielding layer LS of the display panel of the example disclosed herein. Referring to FIG6 , in the circuit layout area PDCA, the metal light-shielding layer LS has a metal light-shielding portion LSP and a connecting trace LSL; adjacent metal light-shielding portions LSP in the same row and in the same column are connected by connecting traces LSL. In this way, the metal light-shielding layer LS is in a grid shape, which can shield external signals and prevent signals outside the display panel from affecting the normal display of the display panel. The metal light-shielding portion LSP needs to have a large size to shield the light irradiating the channel region of the driving transistor T3 to ensure the stability of the characteristics of the driving transistor T3.

[0108] FIG7 shows a partial structural diagram of a polysilicon semiconductor layer SEMI1 of a display panel according to an example of the present disclosure. FIG8 shows a partial structural diagram of a first gate layer GT1 of a display panel according to an example of the present disclosure. Referring to FIG7 , the polysilicon semiconductor layer SEMI1 has a polysilicon pattern corresponding to each pixel drive circuit PDC. The polysilicon pattern forms a channel region T3Act of a drive transistor T3 having semiconductor characteristics, a channel region T4Act of a data write transistor T4, a channel region T5Act of a first emission control transistor T5, a channel region T6Act of a second emission control transistor T6, and a channel region T7Act of a pixel electrode reset transistor T7, as well as conductive first polysilicon strips PL1, second polysilicon strips PL2, third polysilicon strips PL3, fourth polysilicon strips PL4, fifth polysilicon strips PL5, and sixth polysilicon strips PL6. The first, second, third, fourth, fifth, and sixth polysilicon strips PL1, PL2, PL3, PL4, PL5, and PL6 may be conductively formed after the first gate layer GT1 is patterned. Referring to FIG7 , the first polysilicon strip PL1 is electrically connected to one end of the channel region T4Act of the data write transistor T4, serving as the source of the data write transistor T4. The second polysilicon strip PL2 is electrically connected to the other end of the channel region T4Act of the data write transistor T4, one end of the channel region T3Act of the drive transistor T3, and one end of the channel region T5Act of the first emission control transistor T5, serving as part of the third node N3 and simultaneously serving as the drain of the data write transistor T4, the source of the drive transistor T3, and the drain of the first emission control transistor T5. The third polysilicon strip PL3 is electrically connected to the other end of the channel region T5Act of the first emission control transistor T5, serving as the source of the first emission control transistor T5. The fourth polysilicon strip PL4 is electrically connected to the other end of the channel region T3Act of the drive transistor T3 and one end of the channel region T6Act of the second emission control transistor T6, serving as part of the second node N2 and simultaneously serving as the drain of the drive transistor T3 and the source of the second emission control transistor T6. The fifth polysilicon strip PL5 is electrically connected to the other end of the channel region T6Act of the second emission control transistor T6 and one end of the channel region T7Act of the pixel electrode reset transistor T7, serving as part of the fourth node N4 and simultaneously serving as the drain of the second emission control transistor T6 and the drain of the pixel electrode reset transistor T7. The sixth polysilicon strip PL6 is electrically connected to the other end of the channel region T7Act of the pixel electrode reset transistor T7 and serves as the source of the pixel electrode reset transistor T7.Referring to Figure 7, the channel region T7Act of the pixel electrode reset transistor T7 of the polysilicon pattern corresponding to the pixel driving circuit PDC, a portion of the sixth polysilicon strip PL6 and the fifth polysilicon strip PL5 can be arranged in the circuit layout area PDCA corresponding to the next row of pixel driving circuits PDC; correspondingly, the channel region T7Act of the pixel electrode reset transistor T7, the sixth polysilicon strip PL6 and a portion of the fifth polysilicon strip PL5 of the previous row of pixel driving circuits PDC are arranged in the circuit layout area PDCA corresponding to the pixel driving circuit PDC.

[0109] Referring to FIG7 , the channel region T3Act of the driving transistor T3 is bent so that the channel region T3Act of the driving transistor T3 has a longer length, for example, a length of 15 to 25 microns. Furthermore, the area where the channel region T3Act of the driving transistor T3 is distributed can be completely located within the metal light shielding portion LSP on the orthographic projection of the metal light shielding layer LS. In this way, the metal light shielding portion LSP can shield the channel region T3Act of the driving transistor T3 from light. Referring to FIG5 and FIG8 , the first gate layer GT1 is provided with a first electrode plate CP1 of the storage capacitor Cst, and the first electrode plate CP1 of the storage capacitor Cst completely covers the channel region T3Act of the driving transistor T3; that is, the orthographic projection of the channel region T3Act of the driving transistor T3 on the first gate layer GT1 is located within the range of the first electrode plate CP1 of the storage capacitor Cst. In this way, the first electrode plate CP1 of the storage capacitor Cst can serve as the gate of the driving transistor T3.

[0110] Referring to FIG7 , the channel region T4Act of the data write transistor T4 in the pixel drive circuit PDC of the next row is adjacent to the channel region T7Act of the pixel electrode reset transistor T7 in the pixel drive circuit PDC of the previous row. Thus, referring to FIG5 and FIG8 , the first gate layer GT1 is provided with a data scan line GPL for carrying a data scan signal GP and extending substantially along the row direction. The data scan line GPL is arranged to overlap with the channel region T4Act of the data write transistor T4. The portion where the data scan line GPL overlaps with the channel region T4Act of the data write transistor T4 can be reused as the gate T4G of the data write transistor T4. The data scanning line GPL is also arranged to overlap with the channel area T7Act of the pixel electrode reset transistor T7, so that the part where the data scanning line GPL overlaps with the channel area T7Act of the pixel electrode reset transistor T7 can be reused as the gate of the pixel electrode reset transistor T7; the data scanning signal GP loaded on the data scanning line GPL can also be used as the pixel electrode reset signal RP, so that the data scanning line GPL can be multiplexed as the pixel electrode reset line RPL.

[0111] Referring to Figures 5, 7, and 8, the channel region T5Act of the first emission control transistor T5 and the channel region T6Act of the second emission control transistor T6 are arranged in the same row or substantially the same row. The first gate layer GT1 is provided with an emission control trace EML for carrying an emission control signal EM and extending substantially in the row direction. The emission control trace EML overlaps the channel region T5Act of the first emission control transistor T5 and the channel region T6Act of the second emission control transistor T6. The portion where the emission control trace EML overlaps with the channel region T5Act of the first emission control transistor T5 serves as the gate of the first emission control transistor T5, and the portion where the emission control trace EML overlaps with the channel region T6Act of the second emission control transistor T6 serves as the gate of the second emission control transistor T6.

[0112] Figure 9 shows a partial structural diagram of the second gate layer GT2 of the display panel of the present disclosure. Figure 10 shows a partial structural diagram of the metal oxide semiconductor layer SEMI2 of the display panel of the present disclosure. Figure 11 shows a partial structural diagram of the third gate layer GT3 of the display panel of the present disclosure.

[0113] Referring to FIG10 , the metal oxide semiconductor layer SEMI2 includes a metal oxide pattern corresponding one-to-one to each pixel driver circuit PDC. The metal oxide pattern of each pixel driver circuit PDC is completely located within the circuit layout area PDCA corresponding to the pixel driver circuit PDC. The orthographic projections of the metal oxide pattern of the pixel driver circuit PDC and the polysilicon pattern on the substrate BP do not overlap. The metal oxide pattern of the pixel driver circuit PDC includes a channel region T1Act of the capacitor reset transistor T1 and a channel region T2Act of the threshold compensation transistor T2, both of which maintain semiconductor characteristics, and a first metal oxide portion OL1, a second metal oxide portion OL2, and a third metal oxide portion OL3 that are conductive. The first metal oxide portion OL1, the second metal oxide portion OL2, and the third metal oxide portion OL3 can be conductive after the third gate layer GT3 is patterned. The second metal oxide portion OL2 is electrically connected to one end of the channel region T1Act of the capacitor reset transistor T1 and one end of the channel region T2Act of the threshold compensation transistor T2, serving as a portion of the first node N1 and simultaneously serving as the drain of the capacitor reset transistor T1 and the drain of the threshold compensation transistor T2. The first metal oxide portion OL1 is electrically connected to the other end of the channel region T1Act of the capacitor reset transistor T1 and serves as the source of the capacitor reset transistor T1. The third metal oxide portion OL3 is electrically connected to the other end of the channel region T2Act of the threshold compensation transistor T2 and serves as the source of the threshold compensation transistor T2.

[0114] 5 and 11 , the third gate layer GT3 is provided with a capacitor reset top trace GN2UL and a threshold compensation top trace GN1UL extending substantially along the row direction. The capacitor reset top trace GN2UL is used to carry the capacitor reset signal GN2 and includes a channel defining portion GN2ULP of the capacitor reset top trace GN2UL that overlaps with the channel region T1Act of the capacitor reset transistor T1. The portion of the channel defining portion GN2ULP of the capacitor reset top trace GN2UL that overlaps with the channel region T1Act of the capacitor reset transistor T1 is reused as the top gate T1GU of the capacitor reset transistor T1 and is used to define the boundary of the channel region T1Act of the capacitor reset transistor T1 along its length. The threshold compensation top routing GN1UL is used to load the threshold compensation signal GN1, and has a channel defining portion GN1ULP of the threshold compensation top routing GN1UL that overlaps with the channel region T2Act of the threshold compensation transistor T2. The portion of the channel defining portion GN1ULP of the threshold compensation top routing GN1UL that overlaps with the channel region T2Act of the threshold compensation transistor T2 is reused as the top gate T2GU of the threshold compensation transistor T2, and is used to define the boundary of the channel region T2Act of the threshold compensation transistor T2 in the length direction.

[0115] 5 and 9 , the second gate layer GT2 is provided with a capacitor reset bottom trace GN2DL and a threshold compensation bottom trace GN1DL extending substantially along the row direction, and a second electrode plate CP2 provided with storage capacitors Cst corresponding one-to-one to each pixel driver circuit PDC. The capacitor reset bottom trace GN2DL is used to apply the capacitor reset signal GN2 and has an enlarged portion GN2DLP of the capacitor reset bottom trace GN2DL that overlaps with the channel region T1Act of the capacitor reset transistor T1. The orthographic projection of the channel defining portion GN2ULP of the capacitor reset top trace GN2UL on the second gate layer GT2 is completely located within the enlarged portion GN2DLP of the capacitor reset bottom trace GN2DL. This ensures that the orthographic projection of the channel region T1Act of the capacitor reset transistor T1 on the second gate layer GT2 is completely located within the enlarged portion GN2DLP of the capacitor reset bottom trace GN2DL. In this way, the expanded portion GN2DLP of the capacitor reset bottom trace GN2DL can both apply the capacitor reset signal GN2 to the channel region T1Act of the capacitor reset transistor T1 to eliminate the floating body effect of the capacitor reset transistor T1 and shield light from the substrate BP side, thereby maintaining stable performance of the channel region T1Act of the capacitor reset transistor T1. The threshold compensation bottom trace GN1DL is used to apply the threshold compensation signal GN1 and has an expanded portion GN1DLP of the threshold compensation bottom trace GN1DL that overlaps with the channel region T2Act of the threshold compensation transistor T2. The orthographic projection of the channel defining portion GN1ULP of the threshold compensation top trace GN1UL on the second gate layer GT2 is completely located within the expanded portion GN1DLP of the threshold compensation bottom trace GN1DL. This ensures that the orthographic projection of the channel region T2Act of the threshold compensation transistor T2 on the second gate layer GT2 is completely located within the expanded portion GN1DLP of the threshold compensation bottom trace GN1DL. In this way, the expanded portion GN1DLP of the threshold compensation bottom trace GN1DL can both load the threshold compensation signal GN1 to the channel region T2Act of the threshold compensation transistor T2 to eliminate the floating body effect of the threshold compensation transistor T2, and shield the light on the side of the substrate BP so that the channel region T2Act of the threshold compensation transistor T2 maintains stable performance.

[0116] Referring to Figures 5, 8 and 9, the second electrode plate CP2 of the storage capacitor Cst is overlapped with the first electrode plate CP1 of the storage capacitor Cst to form the storage capacitor Cst. The second electrode plate CP2 of the storage capacitor Cst has a notch CP2G, which exposes a portion of the first electrode plate CP1 of the storage capacitor Cst, so that the first electrode plate CP1 of the storage capacitor Cst can be connected to the first source-drain metal layer SD1 through a via located in the notch CP2G. Referring to Figure 9, the second gate layer GT2 may also be provided with a first initialization voltage trace Vinit1L for loading the first initialization voltage Vinit1, and the first initialization voltage trace Vinit1L extends substantially in the row direction. Furthermore, the capacitor reset bottom trace GN2DL is located between the threshold compensation bottom trace GN1DL and the first initialization voltage trace Vinit1L.

[0117] Figure 12 shows a schematic diagram of the partial structure of the first source / drain metal layer SD1 of a display panel according to an example of the present disclosure. Figure 13 shows a schematic diagram of the partial structure of the second gate layer GT2, the metal oxide semiconductor layer SEMI2, the third gate layer GT3, and the first source / drain metal layer SD1 of a display panel according to an example of the present disclosure. Figure 14 shows a schematic diagram of the partial structure of the transfer metal layer DRL of a display panel according to an example of the present disclosure.

[0118] Referring to Figures 5, 12, and 13, in the circuit layout area PDCA, the first source / drain metal layer SD1 is provided with first through sixth conductive structures ML1 through ML6, as well as a second initialization voltage trace Vinit2L extending substantially along the row direction and configured to apply a second initialization voltage Vinit2. The second initialization voltage trace Vinit2L can be bent within the circuit layout area PDCA to avoid other conductive structures.

[0119] Figure 14 shows a schematic structural diagram of the transfer metal layer DRL of the circuit layout area corresponding to the eight local sub-pixels of the display panel of the example disclosed in the present invention; Figure 15 shows a schematic structural diagram of the second source-drain metal layer SD2 of the circuit layout area corresponding to the eight local sub-pixels of the display panel of the example disclosed in the present invention; Figure 16 shows a schematic structural coordination diagram of the transfer metal layer DRL and the second source-drain metal layer SD2 of the circuit layout area corresponding to the eight local sub-pixels of the display panel of the example disclosed in the present invention.

[0120] As shown in Figures 14 to 16, the second source-drain metal layer SD2 includes data lines DL and drive voltage lines VDDL, as well as a pixel transfer structure PA; the data lines DL include the first data lines DL1, the second data lines DL2, the third data lines DL3A, and the fourth data lines DL3B. In the circuit layout diagram of each display unit DU, the transfer metal layer DRL is provided with a second transfer metal structure TRP2 and a third transfer metal structure TRP3. The second transfer metal structure TRP2 is electrically connected to the pixel transfer structure PA through a via, and is also electrically connected to the output end of the pixel driving circuit through a via, for example, through a via to the sixth conductive structure ML6 located in the first source-drain metal layer. The pixel transfer structure PA is electrically connected to the pixel electrode of the sub-pixel through the via. In this way, the driving current of the pixel driving circuit can be loaded to the sub-pixel through the sixth conductive structure ML6, the second transfer metal structure TRP2, and the pixel transfer structure PA. The third transfer metal structure TRP3 is electrically connected to the drive voltage line VDDL through a via, and provides a drive voltage to the pixel driver circuit through the via. For example, the third transfer metal structure TRP3 is electrically connected to the second conductive structure ML2 located on the first source / drain metal layer SD1 through a via. In this way, the drive voltage from the drive voltage line VDDL is applied to the pixel driver circuit via the third transfer metal structure TRP3 and the second conductive structure ML2.

[0121] For a display unit directly connected to an adjacent data line, a first transfer metal structure TRP1 is further provided in the transfer metal layer DRL in the circuit layout area of ​​the display unit. The first transfer metal structure TRP1 is electrically connected to the data line through a via, and a data voltage is loaded to the pixel driving circuit through the via, for example, it is electrically connected to the first conductive structure ML1 of the pixel driving circuit through the via.

[0122] The transfer metal layer DRL is also provided with a first transfer wire TRL1 and a second transfer wire TRL2. The second display unit DU2 located in the first display unit column VDU1 is electrically connected to the second data line DL2 via the second transfer wire TRL2. For example, the first conductive structure ML1 of the second display unit DU2 located in the first display unit column VDU1 is electrically connected to the first end TRL21 of the second transfer wire TRL2 via a via, and the second end TRL22 of the second transfer wire TRL2 is electrically connected to the second data line DL2 via a via. The first display unit DU1 located in the second display unit column VDU2 is electrically connected to the first data line DL1 via the first transfer wire TRL1. For example, the first conductive structure ML1 of the first display unit DU1 located in the second display unit column VDU2 is electrically connected to the first end TRL11 of the first transfer wire TRL1 via a via, and the second end TRL12 of the first transfer wire TRL1 is electrically connected to the first data line DL1 via a via.

[0123] For example, as shown in FIG14 , the transfer metal layer DRL in the circuit layout area PDCA of the first display unit DU1 of the first display unit column VDU1, the circuit layout area PDCA of the second display unit DU2 of the second display unit column VDU2, and the circuit layout areas PDCA of the third display unit DU3 of the third display unit column VDU3A and the fourth display unit column VDU3B all include a first transfer metal structure TRP1, a second transfer metal structure TRP2, and a third transfer metal structure TRP3. In the circuit layout area PDCA corresponding to the pixel driving circuit PDC of the second display unit DU2 of the first display unit column VDU1, the transfer metal layer DRL includes a first end TRL21 of the second transfer line, a second end TRL12 of the first transfer line, a second transfer metal structure TRP2, and a third transfer metal structure TRP3. In the circuit layout area PDCA corresponding to the pixel driving circuit PDC of the first display unit DU1 of the second display unit column VDU2, the transfer metal layer DRL includes the second end TRL22 of the second transfer line, the first end TRL11 of the first transfer line, the second transfer metal structure TRP2 and the third transfer metal structure TRP3; wherein, the second end TRL12 of the first transfer line is electrically connected to the first end TRL11 of the first transfer line through TRL1; the second end TRL22 of the second transfer line is electrically connected to the first end TRL21 of the second transfer line through TRL2.

[0124] In one example, the shape of the first end TRL21 of the second transfer line is the same as the shape of the first transfer metal structure TRP1; the second end TRL22 of the second transfer line is adjacent to and insulated from the first end TRL11 of the first transfer line; the shape of the first end TRL11 of the first transfer line is the same as the shape of the second transfer metal structure TRP2; the second end TRL12 of the first transfer line is adjacent to and insulated from the first end TRL21 of the second transfer line.

[0125] As shown in Figures 7, 12, 13, 14, and 15, the electrical connection relationship between the data voltage and the drive voltage in the drive circuit layer FA in the first display unit DU1 adjacent to the first data line DL1, the second display unit DU2 adjacent to the second data line DL2, and the third display unit DU3 is described in detail below. The third display unit DU3 in the third display unit column VDU3A is used as an example.

[0126] The first conductive structure ML1 overlaps with the first polysilicon strip PL1 and is electrically connected to it through a via. The first conductive structure ML1 also overlaps with the first transfer metal structure TRP1 and is electrically connected to it through a via. The first transfer metal structure TRP1 overlaps with the third data line DL3A and is electrically connected to it through a via. In this way, the data voltage Data applied to the data line DL can be applied to the first polysilicon strip PL1, which serves as the source of the data write transistor T4, via the first transfer metal structure TRP1 and the first conductive structure ML1.

[0127] The second conductive structure ML2 overlaps with the third polysilicon strip PL3 and is electrically connected via a via. It also overlaps with the second electrode plate CP2 of the storage capacitor Cst and is electrically connected via a via. It also overlaps with the third transfer metal structure TRP3 and is electrically connected via a via. The third transfer metal structure TRP3 overlaps with the drive voltage line VDDL and is electrically connected via a via. In this way, the drive voltage VDD applied to the drive voltage line VDDL can be applied to the second electrode plate CP2 of the storage capacitor Cst and the third polysilicon strip PL3, which serves as the source of the first light-emitting control transistor T5, via the third transfer metal structure TRP3 and the second conductive structure ML2.

[0128] In one embodiment of the present disclosure, referring to FIG12 , two adjacent second conductive structures ML2 are connected, such that two adjacent drive voltage traces VDDL are electrically connected via the second conductive structures ML2. In this way, the drive voltage VDD of the display panel in the display area AA is distributed in a grid-like manner, which can improve the signal uniformity of the drive voltage VDD and thereby prevent uneven display on the display panel due to voltage drop or current unevenness of the drive voltage VDD.

[0129] 5 , 10 , and 12 , the third conductive structure ML3 overlaps with the second metal oxide portion OL2 and is electrically connected via a via. It also overlaps with the first electrode plate CP1 of the storage capacitor Cst and is electrically connected via a via. The via between the third conductive structure ML3 and the first electrode plate CP1 of the storage capacitor Cst can pass through the gap CP2G. Thus, the second metal oxide portion OL2, which serves as the drain of the threshold compensation transistor T2, the drain of the capacitor reset transistor T1, and a portion of the first node N1, is electrically connected to the second electrode plate CP2 of the storage capacitor Cst via the third conductive structure ML3.

[0130] The fourth conductive structure ML4 overlaps with the first initialization voltage trace Vinit1L and is electrically connected to it through a via, and also overlaps with the first metal oxide portion OL1 and is electrically connected to it through a via. Thus, the first metal oxide portion OL1, serving as the source of the capacitor reset transistor T1, is electrically connected to the first initialization voltage trace Vinit1L via the fourth conductive structure ML4. The first initialization voltage Vinit1 applied to the first initialization voltage trace Vinit1L can be applied to the source of the capacitor reset transistor T1.

[0131] The fifth conductive structure ML5 overlaps and is electrically connected to the third metal oxide portion OL3, and also overlaps and is electrically connected to the fourth polysilicon strip PL4. Thus, the third metal oxide portion OL3, which serves as the source of the threshold compensation transistor T2, is electrically connected to the fourth polysilicon strip PL4, which serves as the drain of the drive transistor T3, the source of the second emission control transistor T6, and a portion of the second node N2, via the fifth conductive structure ML5.

[0132] The sixth conductive structure ML6 overlaps with the fifth polysilicon strip PL5 and is electrically connected via a via. It also overlaps with the second transfer metal structure TRP2 and is electrically connected via a via. The second transfer metal structure TRP2 overlaps with the pixel transfer structure PA and is electrically connected via a via. Thus, the fifth polysilicon strip PL5, which serves as the drain of the second light-emission control transistor T6, the drain of the pixel electrode reset transistor T7, and a portion of the fourth node N4, is electrically connected to the pixel transfer structure PA via the sixth conductive structure ML6 and the third transfer metal structure TRP3. The pixel transfer structure PA is used to electrically connect to the pixel electrode of the sub-pixel, as shown in Figures 15 and 16.

[0133] In one embodiment of the present disclosure, referring to Figures 14 to 16 , the drive voltage line VDDL has a first runout notch on a side proximate to the first data line DL1; the orthographic projection of the second end TRL12 of the first adapter line TRL1 on the plane of the display panel PNL is located within the orthographic projection of the first runout notch on the plane of the display panel PNL. The drive voltage line VDDL has a second runout notch on a side proximate to the second data line DL2; the orthographic projection of the second end TRL22 of the second adapter line on the plane of the display panel PNL is located within the orthographic projection of the second runout notch on the plane of the display panel PNL. The first data line DL1 has a first side branch portion LBP1 extending into the first runout notch, and the first side branch portion LBP1 is electrically connected to the second end TRL12 of the first adapter line TRL1 via a via. The second data line DL2 has a second side branch portion LBP2 extending into the second runout notch, and the second side branch portion LBP2 is electrically connected to the second end TRL22 of the second adapter line via a via. In this way, the first conductive structure ML1 corresponding to the first display unit DU1 adjacent to the second data line DL2 is electrically connected to the first end TRL11 of the first transfer line TRL1 through a via, the second end TRL12 of the first transfer line TRL1 is electrically connected to the first side branch LBP1 through a via, and the first side branch LBP1 is electrically connected to the first data line DL1.

[0134] In this way, the data voltage applied to the first data line DL1 can be applied to the first polysilicon strip PL1 at the source of the data write transistor T4 corresponding to the first display unit DU1 adjacent to the second data line DL2 via the first side branch portion LBP1, the second end TRL12 of the first transfer line TRL1, the first transfer line TRL1, the first end TRL11 of the first transfer line TRL1, and the first conductive structure ML1. Similarly, the first conductive structure ML1 corresponding to the second display unit DU2 adjacent to the first data line DL1 is electrically connected to the first end TRL21 of the second transfer line TRL2 via a via, the second end TRL22 of the second transfer line is electrically connected to the second side branch portion LBP2 via a via, and the second side branch portion LBP2 is electrically connected to the second data line DL2. In this way, the data voltage applied to the second data line DL2 can be applied to the first polysilicon strip PL1 at the source of the data write transistor T4 corresponding to the second display unit DU2 adjacent to the first data line DL1 via the second side branch portion LBP2, the second end TRL22 of the second transfer line, the second transfer line TRL2, the first end TRL21 of the second transfer line TRL2, and the first conductive structure ML1. This achieves a cross-bridge connection between the second display unit DU2 adjacent to the first data line DL1 and the second data line DL2, and a cross-bridge connection between the first display unit DU1 adjacent to the second data line DL2 and the first data line DL1.

[0135] The embodiment of the present disclosure also provides a method for driving a display panel PNL, the method comprising: driving each DU row by row; when driving any HDU, loading the driving voltage required by the first display unit DU1 of the display unit set DUS onto the first data line DL1 corresponding to the display unit set DUS, and loading the driving voltage required by the second display unit DU2 of the display unit set DUS onto the second data line DL2 corresponding to the display unit set DUS. This ensures that the data voltage loaded on the first data line DL1 can be written into the pixel driving circuit PDC of the first display unit DU1 of the display unit set DUS, and the data voltage loaded on the second data line DL2 can be written into the pixel driving circuit PDC of the second display unit DU2 of the display unit set DUS, thereby avoiding additional energy consumption caused by the alternating control of the first display unit DU1 and the second display unit DU2 by the first data line DL1 and the second data line DL2.

[0136] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, wherein, It includes a plurality of sets of display units arranged in sequence along the row direction; each set of display units includes a plurality of first display units located in different display unit columns and a plurality of second display units located in different display unit columns; The display panel is further provided with a first data trace and a second data trace corresponding to the set of display units; each first display unit of the set of display units is electrically connected to the first data trace, and each second display unit of the set of display units is electrically connected to the corresponding second data trace.

2. The display panel according to claim 1, wherein, The set of display units includes a first display unit column adjacent to the first data trace and a second display unit column adjacent to the second data trace; the first display unit column includes first display units and second display units alternately arranged in sequence along the column direction; the second display unit column includes second display units and first display units alternately arranged in sequence along the column direction.

3. The display panel according to claim 1, wherein, In the same row of display units, the first display unit and the second display unit are alternately arranged.

4. The display panel according to any one of claims 1-3, wherein, The set of display units includes a first display unit column, a third display unit column, a second display unit column, and a fourth display unit column arranged in sequence along the row direction; both the third display unit column and the fourth display unit column include a plurality of third display units arranged in sequence along the column direction.

5. The display panel according to claim 4, wherein, In the same row of display units, each row of sub-pixels includes one first display unit, one second display unit, and two third display units.

6. The display panel according to claim 4, wherein, The display panel is further provided with a third data trace and a fourth data trace corresponding to the set of display units; Each third display unit of the third display unit column is electrically connected to the third data trace, and each third display unit of the fourth display unit column is electrically connected to the fourth data trace.

7. The display panel according to claim 6, wherein, The third data trace and the first data trace are adjacent to each other and are located between the pixel driving circuits of each pixel in the first display unit column and the pixel driving circuits of each pixel in the third display unit column; The fourth data trace and the second data trace are adjacent to each other and are located between the pixel driving circuits of each pixel in the second display unit column and the pixel driving circuits of each pixel in the fourth display unit column.

8. The display panel according to claim 7, wherein, The display panel is provided with a first jumper wire and a second jumper wire; The second display unit located in the first display unit column is electrically connected to the second data trace through the second jumper wire; The first display unit located in the second display unit column is electrically connected to the first data trace through the first jumper wire.

9. The display panel according to claim 1, wherein, The display panel includes a substrate substrate, a driving circuit layer, and a pixel layer stacked in sequence; the driving circuit layer includes a transistor layer, a first source-drain metal layer, a transfer metal layer, and a second source-drain metal layer stacked in sequence; each transistor of the pixel driving circuit of the display unit is disposed on the transistor layer; the sub-pixels of the display unit are disposed on the pixel electrode layer; The first data trace and the second data trace are disposed on the second source-drain metal layer; The transfer metal layer is provided with a first transfer metal structure, a first jumper wire, and a second jumper wire; among them, The data voltage input terminal of the pixel driving circuit of the first display unit adjacent to the first data wiring is electrically connected to the first transfer metal structure corresponding to the first display unit through a via hole; the first transfer metal structure is electrically connected to the first data wiring through a via hole; The data voltage input terminal of the pixel driving circuit of the second display unit adjacent to the second data wiring is electrically connected to the first transfer metal structure corresponding to the second display unit through a via hole, and the first transfer metal structure is electrically connected to the second data wiring through a via hole; The number of pixel driving circuits of the first display unit adjacent to the second data wiring The voltage input terminal is electrically connected to the first end of the first adapter wire through a via hole, and the second end of the first adapter wire is electrically connected to the first data wiring through a via hole; The data voltage input terminal of the pixel driving circuit of the second display unit adjacent to the first data wiring is electrically connected to the first end of the second adapter wire through a via hole, and the second end of the second adapter wire is electrically connected to the second data wiring through a via hole.

10. The display panel according to claim 9, wherein, The shape of the first end of the second patch cord is the same as that of the first patch metal structure; the second end of the second patch cord is adjacent to and insulated from the first end of the first patch cord; The shape of the first end of the first transition wire is the same as that of the first transition metal structure; the second end of the first transition wire is adjacent to and insulated from the first end of the second transition wire.

11. The display panel according to claim 9, wherein, The second source-drain metal layer also includes a driving voltage wiring; A first avoidance gap is formed on a side of the driving voltage wiring close to the first data wiring; the orthographic projection of the second end of the first adapter wire on the plane where the display panel is located is located within the orthographic projection of the first avoidance gap on the plane where the display panel is located; A second avoidance gap is formed on one side of the driving voltage wiring close to the second data wiring; the orthographic projection of the second end of the second adapter wire on the plane where the display panel is located is located within the orthographic projection of the second avoidance gap on the plane where the display panel is located.

12. The display panel according to claim 11, wherein, The first data wiring has a first side branch portion extending deep into the first avoidance gap, and the first side branch portion is electrically connected to the second end of the first adapter wire through a via hole; The second data wiring has a second side branch portion extending deep into the second avoidance gap, and the second side branch portion is electrically connected to the second end of the second adapter wire through a via.

13. A driving method for a display panel according to any one of claims 1 to 12, wherein, include: Driving each display unit line by line; When driving any display unit row, the first display unit of the display unit set is The required driving voltage is loaded onto the first data wiring corresponding to the display unit set, and the required driving voltage of the second display unit of the display unit set is loaded onto the second data wiring corresponding to the display unit set.

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