Semiconductor device

Abstract

Provided is a semiconductor device that occupies little area. The semiconductor device has a horizontal transistor and a vertical transistor combined therein. A CMOS semiconductor device is achieved as a result of a p-channel transistor being constituted by the horizontal transistor and an n-channel transistor being constituted by the vertical transistor. An insulating layer is provided on a gate electrode of the horizontal transistor, and a lower electrode of the vertical transistor is provided on the insulating layer. Silicon is used for a semiconductor layer of the horizontal transistor, and a metal oxide is used for a semiconductor layer of the vertical transistor.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a semiconductor device and a method for manufacturing a display device.

[0002] One embodiment of the present invention is not limited to the above technical field, but examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In display devices, which are a type of semiconductor device, it is known that one way to achieve weight reduction and narrower frame widths is to fabricate at least a part of a driver circuit together with a pixel circuit on the same substrate. Furthermore, in order to achieve even narrower frame widths, it is necessary to further reduce the size of the driver circuit.

[0005] The drive circuit is generally configured with a CMOS (Complementary Metal Oxide Semiconductor) circuit, which is configured by combining n-channel transistors and p-channel transistors, and has a high degree of design freedom.

[0006] On the other hand, in order to achieve a narrower frame, driver circuits configured with only n-channel transistors or only p-channel transistors are also being considered. Circuits with such configurations are also called "unipolar circuits." For example, Patent Document 1 discloses a technology for configuring a shift register with unipolar circuits.

[0007] Japanese Patent Application Laid-Open No. 2002-049333

[0008] When semiconductor devices such as driver circuits are configured with unipolar circuits, the degree of design freedom is lower than when they are configured with CMOS circuits. On the other hand, when both n-channel and p-channel transistors are, for example, transistors using silicon (Si) in the semiconductor layer, the difference in electrical characteristics between the n-channel and p-channel transistors is large. Specifically, when the channel lengths and channel widths of the n-channel and p-channel transistors are equal, the on-current of the n-channel transistor is larger than that of the p-channel transistor. On the other hand, if the difference between the on-current of the n-channel transistor and the on-current of the p-channel transistor constituting the CMOS circuit is large, the CMOS circuit may not operate normally. For this reason, for example, the channel width of the p-channel transistor must be larger than that of the n-channel transistor. Therefore, the area occupied by the CMOS circuit is larger than when the channel width of the p-channel transistor is equal to that of the n-channel transistor.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area, or that consumes low power, or that has high reliability, or that has a novel semiconductor device.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0011] One embodiment of the present invention includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor is a vertical transistor. The first transistor includes a lower electrode serving as one of a source electrode and a drain electrode of the first transistor, and an upper electrode located over the lower electrode and serving as the other of the source electrode and drain electrode of the first transistor. A gate insulating layer of the second transistor is provided to cover a top surface and a side surface of a semiconductor layer of the second transistor. A gate electrode of the second transistor is provided over the gate insulating layer of the second transistor. The first insulating layer is , on a gate electrode of the second transistor and on a gate insulating layer of the second transistor, the second insulating layer having a region located between the lower electrode and the upper electrode and a region located on the first insulating layer, the source electrode of the second transistor having a region in contact with a top surface of the semiconductor layer of the second transistor and a region in contact with a top surface of the second insulating layer, the drain electrode of the second transistor having a region in contact with a top surface of the semiconductor layer of the second transistor and a region in contact with a top surface of the second insulating layer, the lower electrode having a region in contact with a top surface of the first insulating layer, and the upper electrode having a region in contact with a top surface of the second insulating layer.

[0012] Alternatively, in the above aspect, the gate insulating layer, the first insulating layer, and the second insulating layer of the second transistor may have a first opening reaching the semiconductor layer of the second transistor, the gate insulating layer, the first insulating layer, and the second insulating layer of the second transistor may have a second opening reaching the semiconductor layer of the second transistor, the source electrode of the second transistor may have a region located inside the first opening, and the drain electrode of the second transistor may have a region located inside the second opening.

[0013] Alternatively, in the above aspect, the semiconductor device may have a conductive layer, and the first insulating layer and the second insulating layer may have a third opening that reaches the gate electrode of the second transistor, and the conductive layer may have a region located inside the third opening, and may have a region in contact with the upper surface of the gate electrode of the second transistor and a region in contact with the upper surface of the second insulating layer.

[0014] Alternatively, one embodiment of the present invention includes a first transistor, a second transistor, a capacitor, a base insulating layer, and a first insulating layer. The first transistor includes a first semiconductor layer, a first conductive layer, and a second insulating layer. The second transistor includes a second semiconductor layer. The second transistor is a vertical transistor. The capacitor includes a second conductive layer, a second insulating layer, and a third conductive layer. The first semiconductor layer and the second conductive layer have regions in contact with a top surface of the base insulating layer. The second insulating layer includes a first insulating layer. The semiconductor device is provided so as to cover an upper surface of the semiconductor layer, a side surface of the first semiconductor layer, an upper surface of the second conductive layer, and a side surface of the second conductive layer, the first conductive layer is provided so as to overlap with the first semiconductor layer and have a region in contact with the upper surface of the second insulating layer, the third conductive layer is provided so as to overlap with the second conductive layer and have a region in contact with the upper surface of the second insulating layer, the first insulating layer is provided on the first conductive layer, the third conductive layer, and the second insulating layer, and the second transistor is provided on the first insulating layer.

[0015] Alternatively, in the above aspect, the second transistor has a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and a third insulating layer, the second transistor has an eighth conductive layer and a ninth conductive layer, the eighth conductive layer has a region in contact with an upper surface of the first insulating layer, the third insulating layer is provided on the eighth conductive layer and on the first insulating layer, and the first insulating layer, the second insulating layer, and the third insulating layer have a first opening reaching the first semiconductor layer. the first insulating layer, the second insulating layer, and the third insulating layer have a second opening that reaches the first semiconductor layer and faces the first opening with the first conductive layer interposed therebetween; the first insulating layer, the second insulating layer, and the third insulating layer have a third opening that reaches the second conductive layer; the first insulating layer and the third insulating layer have a fourth opening that reaches the third conductive layer; the fourth conductive layer has a region located inside the first opening; and the fifth conductive layer has a region located inside the second opening and has a region located inside the second opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening and has a region located inside the third opening

[0016] Alternatively, in the above aspect, the second transistor may have a fourth insulating layer and a tenth conductive layer, the fourth insulating layer being provided on the second semiconductor layer so as to have a region located inside the fifth opening, the tenth conductive layer having a region located inside the fifth opening, and the second semiconductor layer and the tenth conductive layer being provided so as to have regions facing each other across the fourth insulating layer.

[0017] Alternatively, in the above aspect, there may be an eleventh conductive layer, and the first insulating layer and the third insulating layer may have a sixth opening reaching the first conductive layer, and the eleventh conductive layer may have a region located inside the sixth opening, and may have a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the third insulating layer.

[0018] Alternatively, in the above embodiment, the first semiconductor layer may include silicon, and the second semiconductor layer may include a metal oxide.

[0019] Alternatively, in the above embodiment, the first transistor may be a p-channel transistor, and the second transistor may be an n-channel transistor.

[0020] Alternatively, one embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first insulating layer. The first transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer, and a second insulating layer. The second transistor includes the first semiconductor layer, a third conductive layer, a fourth conductive layer, and a second insulating layer. The third transistor includes the second semiconductor layer, a third conductive layer, a fifth conductive layer, a sixth conductive layer, and a third insulating layer. The fourth transistor includes the second semiconductor layer, the fifth conductive layer, and a seventh conductive layer, an eighth conductive layer, and a third insulating layer, the second insulating layer being provided so as to cover an upper surface and a side surface of the first semiconductor layer, the second insulating layer having a first opening reaching the first semiconductor layer, the second insulating layer having a second opening reaching the first semiconductor layer and facing the first opening across the second conductive layer and the fourth conductive layer in a plan view, the first conductive layer having a region located inside the first opening and a region in contact with the first semiconductor layer, the second conductive layer being provided on the second insulating layer so as to have a region overlapping with the first semiconductor layer; The third conductive layer has a region located inside the second opening and a region in contact with the first semiconductor layer, the fourth conductive layer is provided on the second insulating layer to have a region overlapping with the first semiconductor layer and is located between the second conductive layer and the third conductive layer, the seventh conductive layer is provided on the second insulating layer, the first insulating layer is provided on the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the seventh conductive layer, the fifth conductive layer is provided on the first insulating layer, and the first insulating layer and the fifth conductive layer have a third opening reaching the third conductive layer and a seventh opening. the second semiconductor layer has a region in contact with the third conductive layer, a region in contact with the fifth conductive layer, and a region in contact with the seventh conductive layer, and also has a region located inside the third opening and a region located inside the fourth opening; the third insulating layer is provided on the second semiconductor layer so as to have a region located inside the third opening and a region located inside the fourth opening; the sixth conductive layer has a region located inside the third opening and is connected to the fourth conductive layer; the eighth conductive layer has a region located inside the fourth opening;The second semiconductor layer and the sixth conductive layer are provided so as to have an area where they face each other with the third insulating layer sandwiched therebetween, and the second semiconductor layer and the eighth conductive layer are provided so as to have an area where they face each other with the third insulating layer sandwiched therebetween.

[0021] Alternatively, in the above embodiment, the first transistor and the second transistor may be p-channel transistors, and the third transistor and the fourth transistor may be n-channel transistors.

[0022] Alternatively, in the above embodiment, the first semiconductor layer may include silicon, and the second semiconductor layer may include a metal oxide.

[0023] Alternatively, in the above embodiment, a ninth conductive layer may be provided, and the ninth conductive layer may have a region in contact with the fourth conductive layer and a region in contact with the sixth conductive layer.

[0024] Alternatively, in the above aspect, there may be a fourth insulating layer, the fourth insulating layer being provided between the first insulating layer and the second insulating layer, the fourth insulating layer having a first opening and a second opening, the fourth insulating layer having a fifth opening reaching the fourth conductive layer, and the ninth conductive layer having a region located inside the fifth opening.

[0025] According to one embodiment of the present invention, a semiconductor device with a small occupation area, low power consumption, high reliability, or a novel semiconductor device can be provided.

[0026] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0027] FIG. 1A is a plan view showing a configuration example of a semiconductor device. FIGS. 1B to 1D are cross-sectional views showing a configuration example of a semiconductor device. FIG. 2A is a plan view showing a configuration example of a transistor. FIG. 2B is a cross-sectional view showing a configuration example of a transistor. FIG. 3 is a cross-sectional view showing a configuration example of a semiconductor device. FIGS. 4A to 4C are cross-sectional views showing a configuration example of a semiconductor device. FIG. 5A is a plan view showing a configuration example of a semiconductor device. FIG. 5B is a cross-sectional view showing a configuration example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 7A and 7B are plan views showing a configuration example of a semiconductor device. FIG. 7C is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 8A is a plan view showing a configuration example of a semiconductor device. FIG. 8B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 9A is a plan view showing a configuration example of a semiconductor device. FIG. 9B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 10A is a plan view showing a configuration example of a semiconductor device. FIG. 10B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 11A is a plan view showing a configuration example of a semiconductor device. FIG. 11B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 12A is a plan view showing a configuration example of a semiconductor device. FIG. 12B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 13A is a plan view showing a configuration example of a semiconductor device. FIGS. 13B and 13C are cross-sectional views showing a configuration example of a semiconductor device. FIG. 14A is a plan view showing a configuration example of a semiconductor device. FIGS. 14B and 14C are cross-sectional views showing a configuration example of a semiconductor device. FIG. 15A is a plan view showing a configuration example of a semiconductor device. FIGS. 15B and 15C are cross-sectional views showing a configuration example of a semiconductor device. FIG. 16A is a plan view showing a configuration example of a semiconductor device. FIGS. 16B and 16C are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 18A is a plan view showing a configuration example of a semiconductor device. FIGS. 18B and 18C are cross-sectional views showing a configuration example of a semiconductor device. FIG. 19A is a plan view showing a configuration example of a semiconductor device. FIGS. 19B and 19C are cross-sectional views showing a configuration example of a semiconductor device. FIG. 20A is a plan view showing a configuration example of a semiconductor device. FIG. 20B is a cross-sectional view showing a configuration example of a semiconductor device.FIG. 21 is a plan view showing a configuration example of a semiconductor device. FIG. 22A is a plan view showing a configuration example of a semiconductor device. FIG. 22B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 23A is a plan view showing a configuration example of a semiconductor device. FIG. 23B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 24A is a plan view showing a configuration example of a semiconductor device. FIG. 24B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 25A is a plan view showing a configuration example of a semiconductor device. FIG. 25B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 26A is a plan view showing a configuration example of a semiconductor device. FIG. 26B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 27A is a plan view showing a configuration example of a semiconductor device. FIG. 27B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 28A is a plan view showing a configuration example of a semiconductor device. FIG. 28B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 29A is a plan view showing a configuration example of a semiconductor device. FIG. 29B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 30A is a plan view showing a configuration example of a semiconductor device. FIG. 30B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 31A is a plan view showing a configuration example of a semiconductor device. FIG. 31B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 32A is a plan view showing a configuration example of a semiconductor device. FIG. 32B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 33A is a plan view showing a configuration example of a semiconductor device. FIG. 33B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 34A is a plan view showing a configuration example of a semiconductor device. FIG. 34B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 35A is a plan view showing a configuration example of a semiconductor device. FIG. 35B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 36A is a plan view showing a configuration example of a semiconductor device. FIG. 36B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 37A is a plan view showing a configuration example of a semiconductor device. FIG. 37B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 38A is a plan view showing a configuration example of a semiconductor device. FIG. 38B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 39A is a plan view showing a configuration example of a semiconductor device. FIG. 39B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 40A is a plan view showing a configuration example of a semiconductor device. FIG. 40B is a cross-sectional view showing a configuration example of a semiconductor device.FIG. 41A is a plan view showing a configuration example of a semiconductor device. FIG. 41B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 42A is a plan view showing a configuration example of a semiconductor device. FIG. 42B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 43A is a block diagram showing a configuration example of a display device. FIG. 43B is a plan view showing a configuration example of a pixel. FIGS. 43C to 43E are circuit diagrams showing configuration examples of sub-pixels. FIGS. 44A and 44B are block diagrams showing a configuration example of a semiconductor device. FIG. 44C is a circuit diagram showing a configuration example of a semiconductor device. FIGS. 45A to 45G are circuit diagrams showing a configuration example of a semiconductor device. FIGS. 46A1 to 46A7 and 46B1 to 46B6 are circuit diagrams for explaining electrical connections. FIG. 47A is a plan view showing a configuration example of a semiconductor device. FIG. 47B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 48A is a plan view showing a configuration example of a semiconductor device. FIGS. 48B and 48C are cross-sectional views showing configuration examples of a semiconductor device. 49A and 49B are plan views showing a configuration example of a semiconductor device. FIG. 50A is a plan view showing a configuration example of a semiconductor device. FIG. 50B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 51 is a plan view showing a configuration example of a semiconductor device. FIG. 52A is a plan view showing a configuration example of a semiconductor device. FIG. 52B is a cross-sectional view showing a configuration example of a semiconductor device. FIGS. 53A and 53B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 54 is a plan view showing a configuration example of a semiconductor device. FIG. 55A is a plan view showing a configuration example of a semiconductor device. FIG. 55B is a cross-sectional view showing a configuration example of a semiconductor device. FIGS. 56A and 56B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 57 is a plan view showing a configuration example of a semiconductor device. FIG. 58A is a plan view showing a configuration example of a semiconductor device. FIG. 58B is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 59 is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 60 is a plan view showing a configuration example of a semiconductor device. FIG. 61A is a plan view showing a configuration example of a semiconductor device. FIG. 61B is a cross-sectional view showing a configuration example of a semiconductor device. Fig. 62 is a cross-sectional view showing a configuration example of a semiconductor device, Fig. 63 is a plan view showing a configuration example of a semiconductor device, and Fig. 64A is a plan view showing a configuration example of a semiconductor device.FIG. 64B is a cross-sectional view showing a structural example of a semiconductor device. FIG. 65 is a plan view showing a structural example of a semiconductor device. FIG. 66A is a plan view showing a structural example of a semiconductor device. FIG. 66B is a cross-sectional view showing a structural example of a semiconductor device. FIG. 67 is a plan view showing a structural example of a semiconductor device. FIGS. 68A and 68B are circuit diagrams showing structural examples of subpixels. FIGS. 69A and 69B are circuit diagrams showing structural examples of subpixels. FIGS. 70A and 70B are circuit diagrams showing structural examples of subpixels. FIG. 71 is a circuit diagram showing a structural example of a subpixel. FIGS. 72A to 72F are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 73A to 73D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 74A to 74C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 75A to 75C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 76A to 76C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 77 is a perspective view showing a structural example of a display device. Fig. 78A is a cross-sectional view showing an example of the configuration of a pixel circuit. Figs. 78B and 78C are cross-sectional views showing an example of the configuration of a display device. Fig. 79 is a cross-sectional view showing an example of the configuration of a display device. Fig. 80 is a cross-sectional view showing an example of the configuration of a display device. Figs. 81A to 81D are cross-sectional views showing an example of the configuration of an LED package. Figs. 82A to 82G are plan views showing an example of the configuration of a pixel. Figs. 83A to 83K are plan views showing an example of the configuration of a pixel. Figs. 84A to 84D are diagrams showing an example of an electronic device. Figs. 85A to 85F are diagrams showing an example of an electronic device. Figs. 86A to 86G are diagrams showing an example of an electronic device.

[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations are omitted. Also, when similar functions are indicated, the same hatching pattern may be used and no particular reference numeral may be used. Furthermore, multiple layers that can be formed in the same process may be denoted by the same hatching pattern.

[0030] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0031] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0032] It should be noted that the terms "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0033] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0034] In this specification and the like, a structure in which at least light-emitting layers are separately formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0035] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0036] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). Note that the carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes, characteristics, etc. In addition, one layer may have two or three functions of the carrier injection layer, carrier transport layer, and carrier block layer.

[0037] In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0038] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also referred to as the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0039] In this specification, when the side surface of a layer has a tapered shape, the outermost part of the side surface of the layer is referred to as the edge of the layer unless otherwise specified. For example, when the bottom surface edge of a layer is located outward from the top surface edge, the bottom surface edge of the layer is simply referred to as the edge unless otherwise specified.

[0040] Furthermore, in this specification, terms indicating positions such as "upper," "lower," "left," and "right" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0041] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0042] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention, a manufacturing method thereof, and the like will be described with reference to drawings.

[0043] One embodiment of the present invention is a CMOS semiconductor device including a p-channel transistor and an n-channel transistor. In one embodiment of the present invention, the p-channel transistor is a lateral transistor using silicon for a semiconductor layer (also referred to as a lateral Si transistor). The n-channel transistor is a vertical transistor using metal oxide for a semiconductor layer (also referred to as a vertical OS transistor).

[0044] In this specification, a lateral transistor refers to a transistor in which a drain current flows in a direction parallel or approximately parallel to the top surface of a substrate or a base insulating layer, i.e., in a horizontal direction. In a lateral transistor, the source electrode and the drain electrode can be provided so as not to overlap each other. In a lateral transistor, the source electrode and the drain electrode can be provided so as to face each other across a gate electrode in a plan view. Furthermore, in a lateral transistor, the source electrode and the drain electrode can be provided on the same formation surface. Note that a lateral transistor is also called a lateral channel transistor or a lateral channel transistor.

[0045] In this specification and the like, a vertical transistor refers to a transistor in which the lower surface of a source electrode and the lower surface of a drain electrode are provided at different heights. Here, of the source electrode and the drain electrode, the electrode that is lower in height from a reference plane such as the upper surface of a substrate or the upper surface of a base insulating layer is referred to as a lower electrode, and the electrode that is higher in height is referred to as an upper electrode. An insulating layer that functions as a spacer is provided between the lower electrode and the upper electrode. In the following description, the insulating layer that functions as a spacer may be simply referred to as a spacer, but the term "spacer" may also be interpreted as an insulating layer.

[0046] In a vertical transistor, a drain current flows in a direction perpendicular or substantially perpendicular to the upper surface of a substrate or an insulating base layer. That is, the drain current flows vertically. Note that a vertical transistor is also called a vertical channel transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).

[0047] When both p-channel and n-channel transistors are, for example, lateral Si transistors, the difference in electrical characteristics between the p-channel and n-channel transistors is large. Specifically, when the channel lengths and channel widths of the n-channel and p-channel transistors are equal, the on-current of the n-channel transistor is larger than that of the p-channel transistor. On the other hand, if the difference between the on-current of the n-channel transistor and the on-current of the p-channel transistor constituting a CMOS circuit is large, the CMOS circuit may not operate normally. For this reason, for example, the channel width of the p-channel transistor must be larger than that of the n-channel transistor. Therefore, the area occupied by the CMOS circuit is larger than when the channel width of the p-channel transistor is equal to that of the n-channel transistor.

[0048] In a semiconductor device according to one embodiment of the present invention, a vertical OS transistor is used as an n-channel transistor. The field-effect mobility of an OS transistor may be lower than that of a Si transistor. Therefore, when an OS transistor and a Si transistor have the same channel length, channel width, polarity, and the like, the on-state current of the OS transistor can be smaller than that of a Si transistor. Furthermore, the channel length of a vertical OS transistor is not affected by the performance of an exposure tool used to manufacture the transistor, so the channel length can be smaller than the resolution limit of the exposure tool. Therefore, the channel length of a vertical OS transistor can be shorter than that of a lateral transistor (also referred to as a lateral OS transistor) using a metal oxide for the semiconductor layer. Therefore, the on-state current of a vertical OS transistor can be larger than that of a lateral OS transistor. Therefore, the difference in electrical characteristics between a p-channel transistor and an n-channel transistor can be smaller than when, for example, a p-channel transistor is used as a lateral Si transistor and an n-channel transistor is used as a lateral OS transistor. Specifically, the difference in on-state current can be smaller.

[0049] As described above, by using a horizontal Si transistor as a p-channel transistor and a vertical OS transistor as an n-channel transistor, the difference in electrical characteristics between the p-channel transistor and the n-channel transistor can be reduced without increasing the channel width of the p-channel transistor, compared to when both the p-channel transistor and the n-channel transistor are horizontal Si transistors. Specifically, the difference in on-state current can be reduced. Therefore, a semiconductor device with a small occupation area can be provided.

[0050] Furthermore, since a vertical transistor can have a region where the source electrode and the drain electrode overlap, the area occupied by the vertical transistor can be smaller than that of a horizontal transistor. Therefore, by using an n-channel transistor as a vertical transistor, the area occupied by the semiconductor device can be made smaller than that of a horizontal transistor.

[0051] <Configuration Example 1 of Semiconductor Device> Fig. 1A is a plan view showing a configuration example of a semiconductor device 10 according to one embodiment of the present invention. Fig. 1B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 1A. Fig. 1C is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 1A. Fig. 1D is a cross-sectional view taken along dashed dotted line B3-B4 in Fig. 1A. Note that in Fig. 1A, some components such as insulating layers are omitted to make the configuration of the semiconductor device easier to understand. Some components will also be omitted in the subsequent plan views.

[0052] The semiconductor device 10 includes a substrate 101, an insulating layer 102 functioning as a base insulating layer over the substrate 101, transistors 100 and 200 over the insulating layer 102, and insulating layers 207 over the transistors 100 and 200. The transistor 100 is a p-channel transistor, and the transistor 200 is an n-channel transistor. Note that a conductive layer functioning as, for example, a wiring may be provided between the substrate 101 and the insulating layer 102.

[0053] The dashed-dotted line A1-A2 includes cross sections of the transistor 100 and the transistor 200. The dashed-dotted line B1-B2 includes cross sections of the transistor 100. The dashed-dotted line B3-B4 includes cross sections of the transistor 200.

[0054] 1A to 1D, the direction parallel to the dashed-dotted line A1-A2 is the X direction, and the direction parallel to the dashed-dotted line B1-B2 and the dashed-dotted line B3-B4 is the Y direction. The direction perpendicular to both the X direction and the Y direction is the Z direction. The X direction and the Y direction can be parallel to the top surface of the substrate 101 (also referred to as the surface of the substrate 101). The Z direction can be perpendicular to the top surface of the substrate 101.

[0055] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0056] The transistor 100 includes a semiconductor layer 113, an insulating layer 105, a conductive layer 115, a conductive layer 111a, and a conductive layer 111b. The transistor 200 includes a conductive layer 211, a conductive layer 212, a semiconductor layer 213, an insulating layer 205, and a conductive layer 215.

[0057] The conductive layer 111a functions as one of a source electrode and a drain electrode of the transistor 100. The conductive layer 111b functions as the other of the source electrode and the drain electrode of the transistor 100. The insulating layer 105 functions as a gate insulating layer of the transistor 100. The conductive layer 115 functions as a gate electrode of the transistor 100.

[0058] The conductive layer 211 functions as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 212 functions as the other of the source electrode and the drain electrode of the transistor 200. The insulating layer 205 functions as a gate insulating layer of the transistor 200. The conductive layer 215 functions as a gate electrode of the transistor 200.

[0059] The semiconductor layer 113 is provided over the insulating layer 102. The semiconductor layer 113 may have a region in contact with the top surface of the insulating layer 102.

[0060] The insulating layer 105 is provided over the semiconductor layer 113 and the insulating layer 102. The insulating layer 105 can be provided over the insulating layer 102 so as to cover the top surface and side surfaces of the semiconductor layer 113. The conductive layer 115 is provided over the insulating layer 105 so as to have a region overlapping with the semiconductor layer 113. The conductive layer 115 can have a region in contact with the top surface of the insulating layer 105.

[0061] The semiconductor device 10 includes an insulating layer 107, an insulating layer 203, and a conductive layer 116. The insulating layer 107 is provided over the conductive layer 115 and the insulating layer 105 and can function as an interlayer insulating layer. The insulating layer 107 can be provided over the insulating layer 105 so as to cover the top surface and side surfaces of the conductive layer 115. The transistor 200 is provided over the insulating layer 107. The insulating layer 203 is provided over the insulating layer 107.

[0062] The insulating layer 105, the insulating layer 107, and the insulating layer 203 have an opening 121a and an opening 121b that reach the semiconductor layer 113. The opening 121a and the opening 121b can face each other with the conductive layer 115 interposed therebetween. The insulating layer 107 and the insulating layer 203 also have an opening 122 that reaches the conductive layer 115.

[0063] The opening 121a and the opening 121b each include an opening in the insulating layer 105, an opening in the insulating layer 107, and an opening in the insulating layer 203. The opening 122 includes an opening in the insulating layer 107 and an opening in the insulating layer 203.

[0064] The conductive layer 111a has a region located inside the opening 121a. The conductive layer 111b has a region located inside the opening 121b. The conductive layer 111a has a region in contact with the top surface of the semiconductor layer 113 and a region in contact with the top surface of the insulating layer 203. Similarly, the conductive layer 111b also has a region in contact with the top surface of the semiconductor layer 113 and a region in contact with the top surface of the insulating layer 203.

[0065] The conductive layer 116 has a region located inside the opening 122. The conductive layer 116 has a region in contact with the top surface of the conductive layer 115 and a region in contact with the top surface of the insulating layer 203. The conductive layer 111a and the conductive layer 111b can face each other with the conductive layer 115 and the conductive layer 116 sandwiched therebetween. Note that the conductive layer 116 may or may not be included in the gate electrode of the transistor 100. The conductive layer 111a and the conductive layer 111b may not be included in the transistor 100.

[0066] The conductive layer 111a can have, inside the opening 121a, a region in contact with the side surface of the insulating layer 105, a region in contact with the side surface of the insulating layer 107, and a region in contact with the side surface of the insulating layer 203. The conductive layer 111b can have, inside the opening 121b, a region in contact with the side surface of the insulating layer 105, a region in contact with the side surface of the insulating layer 107, and a region in contact with the side surface of the insulating layer 203. The conductive layer 116 can have, inside the opening 122, a region in contact with the side surface of the insulating layer 107 and a region in contact with the side surface of the insulating layer 203.

[0067] The semiconductor layer 113 has a region 113i, a region 113na, and a region 113nb. The region 113i overlaps with the conductive layer 115 that functions as the gate electrode of the transistor 100 and functions as a channel formation region of the transistor 100. The region 113na includes a portion in contact with the conductive layer 111a and functions as one of the source region and drain region of the transistor 100. The region 113nb includes a portion in contact with the conductive layer 111b and functions as the other of the source region and drain region of the transistor 100. By using p-type semiconductors for the regions 113na and 113nb, the transistor 100 can be a p-channel transistor.

[0068] The regions 113na and 113nb have lower electrical resistivity than the region 113i. Therefore, the regions 113na and 113nb can be referred to as low-resistance regions. Introducing an impurity element into the semiconductor layer 113 can form a low-resistance region in the semiconductor layer 113. For example, the regions 113na and 113nb can be formed in the semiconductor layer 113 by introducing an impurity element into the semiconductor layer 113 using the conductive layer 115 as a mask. Here, the transistor 100 can be a p-channel transistor by using one or more elements selected from Group 13 elements such as boron (B), aluminum (Al), and gallium (Ga) as the impurity element.

[0069] In the transistor 100 shown in FIG. 1B , drain current flows laterally (in the X direction) from one of the regions 113na and 113nb through the region 113i toward the other of the regions 113na and 113nb. Therefore, the transistor 100 is a horizontal transistor. In the example shown in FIG. 1B , the channel length L100 of the transistor 100 can be the length in the X direction of the region 113i, which is the channel formation region of the transistor 100 (the distance from the region 113na to the region 113nb). The length in the Y direction of the region 113i can be the channel width W100 of the transistor 100. In FIG. 1B , the channel length L100 is indicated by a dashed double-headed arrow. In FIG. 1C , the channel width W100 is indicated by a solid double-headed arrow.

[0070] The semiconductor layer 113 including the channel formation region of the transistor 100 can be made of, for example, silicon. As described above, the transistor 100 is a lateral transistor. As described above, the transistor 100 is a lateral Si transistor. Specifically, the transistor 100 is a p-channel lateral Si transistor.

[0071] Examples of silicon used for the semiconductor layer 113 include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using polycrystalline silicon for its semiconductor layer has high field-effect mobility and can operate at high speed.

[0072] Note that the semiconductor layer 113 may be made of a material other than silicon. For example, germanium may be used as the semiconductor layer 113, or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor may be used as the semiconductor layer 113. An organic material having semiconductor properties may be used as the compound semiconductor. Alternatively, a layered material that functions as a semiconductor may be used as the semiconductor layer 113.

[0073] A conductive layer 211 is provided between the insulating layer 107 and the insulating layer 203. The conductive layer 211 may have a region in contact with the top surface of the insulating layer 107. The insulating layer 203 is provided over the conductive layer 211 and may have a region in contact with the top surface of the conductive layer 211, a region in contact with the side surface of the conductive layer 211, and a region in contact with the top surface of the insulating layer 107.

[0074] By providing the insulating layer 107 over the conductive layer 115 and the insulating layer 105 and providing the conductive layer 211 over the insulating layer 107, the distance between the semiconductor layer 113 (region 113nb in FIG. 1B ) and the conductive layer 211 can be increased compared to, for example, a case where the insulating layer 107 is not provided and the conductive layer 211 is provided so as to have a region in contact with the top surface of the insulating layer 105. Therefore, by providing the insulating layer 107, the parasitic capacitance between the semiconductor layer 113 (region 113nb in FIG. 1B ) and the conductive layer 211 can be reduced compared to a case where the insulating layer 107 is not provided. This allows the semiconductor device 10 to operate at high speed. Note that the insulating layer 107 can function as a protective layer for the transistor 100. The insulating layer 107 can also function as a protective layer for the transistor 200. Furthermore, the insulating layer 107 may have a function of supplying hydrogen to the semiconductor layer 113.

[0075] It is preferable to use a material with a low dielectric constant for the insulating layer 107. This can further reduce the parasitic capacitance between the semiconductor layer 113 and the conductive layer 211. It is also preferable to use a material with a low dielectric constant for the insulating layer 102, which functions as a base insulating layer. This can reduce the parasitic capacitance generated between wirings. For example, it can reduce the parasitic capacitance between a conductive layer provided between the substrate 101 and the insulating layer 102 and a conductive layer provided on the insulating layer 102.

[0076] Examples of insulating layers with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0077] The conductive layer 212 has a region in contact with the top surface of the insulating layer 203. Here, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, and the conductive layer 212 all have a region in contact with the top surface of the insulating layer 203. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, and the conductive layer 212 are provided on the same surface where they are to be formed. The conductive layer 111a, the conductive layer 111b, the conductive layer 116, and the conductive layer 212 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, and the conductive layer 212 can have the same material.

[0078] When the conductive layer 116 is formed on the same surface as the conductive layers 111a and 111b, the opening 122 in which the conductive layer 116 is provided can be formed in the same process as the opening 121a in which the conductive layer 111a is provided and the opening 121b in which the conductive layer 111b is provided. Therefore, the number of manufacturing steps for the semiconductor device 10 can be reduced. Therefore, the manufacturing cost of the semiconductor device 10 can be reduced. As described above, the semiconductor device 10 can be a low-cost semiconductor device.

[0079] The insulating layer 203 and the conductive layer 212 have an opening 221 that reaches the conductive layer 211. The opening 221 includes an opening in the insulating layer 203 and an opening in the conductive layer 212. In other words, the opening in the region where the insulating layer 203 overlaps with the conductive layer 211 is part of the opening 221. The opening in the region where the conductive layer 212 overlaps with the conductive layer 211 is another part of the opening 221.

[0080] 1A shows an example in which the shape of the opening 221 is circular in a plan view. By making the shape of the opening 221 in a plan view (also referred to as the planar shape) circular, the processing accuracy when forming the opening 221 can be improved, and the opening 221 can be formed with a fine size. Note that in this specification, a circle is not limited to a perfect circle. Furthermore, the planar shape of the opening 221 may be, for example, an ellipse.

[0081] FIG. 1A also shows an example in which the shapes of openings 121a, 121b, and 122 are rectangular with rounded corners in a plan view. The planar shape of opening 221 may be rectangular with rounded corners. Furthermore, the planar shape of at least one of openings 121a, 121b, and 122 may be circular or elliptical. Furthermore, in a planar view, the corners of at least one of openings 221, 121a, 121b, and 122 do not have to be rounded, and the planar shape may be, for example, rectangular, rhombic, or square. Furthermore, the planar shape of at least one of openings 221, 121a, 121b, and 122 may be triangular, polygonal with pentagons or more, or any of these shapes with rounded corners.

[0082] 1B and 1D show an example in which the end of the conductive layer 212 on the opening 221 side coincides with or roughly coincides with the end of the insulating layer 203 on the opening 221 side. In this specification and the like, the end of the conductive layer 212 on the opening 221 side refers to the end of the lower surface of the conductive layer 212 on the opening 221 side. The lower surface of the conductive layer 212 refers to the surface on the insulating layer 203 side. The end of the insulating layer 203 on the opening 221 side refers to the end of the upper surface of the insulating layer 203 on the opening 221 side. The upper surface of the insulating layer 203 refers to the surface on the conductive layer 212 side.

[0083] Incidentally, "the edges coincide or approximately coincide" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, and when the planar shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. Examples of such cases include when the upper and lower layers are processed using the same mask pattern or a mask pattern that is partially identical. However, strictly speaking, the contours may not overlap, and a portion of the upper layer may be located inside the lower layer, or a portion of the upper layer may be located outside the lower layer. In these cases, the edges are also said to be approximately aligned or the planar shapes are approximately aligned.

[0084] The semiconductor layer 213 is provided to cover the opening 221. The semiconductor layer 213 is provided to have a region located inside the opening 221. The semiconductor layer 213 has a shape that follows the shapes of the top surface and side surface of the conductive layer 212, the side surface of the insulating layer 203, and the top surface of the conductive layer 211. The semiconductor layer 213 has a region in contact with the conductive layer 211 and a region in contact with the conductive layer 212. Specifically, the semiconductor layer 213 can have a region in contact with the top surface of the conductive layer 211 and a region in contact with the top surface of the conductive layer 212, and can also have a region in contact with the side surface of the conductive layer 212 inside the opening 221. The semiconductor layer 213 can also have a region in contact with the side surface of the insulating layer 203 inside the opening 221.

[0085] 1B and 1D, the semiconductor layer 213 has a single-layer structure, but one embodiment of the present invention is not limited to this. The semiconductor layer 213 may have a stacked structure of two or more layers.

[0086] The semiconductor layer 213 including the channel formation region of the transistor 200 can be formed using, for example, a metal oxide. As described above, the transistor 200 is a vertical transistor. As described above, the transistor 200 is a vertical OS transistor. Specifically, the transistor 200 is an n-channel vertical OS transistor.

[0087] Examples of metal oxides used for the semiconductor layer 213 include indium oxide, gallium oxide, and zinc oxide. Examples of metal oxides used for the semiconductor layer 213 include indium zinc oxide and indium gallium zinc oxide.

[0088] Metal oxides can increase the band gap, for example, to 2.0 eV or more. Therefore, the off-state current of an OS transistor can be significantly reduced. Therefore, the semiconductor device 10 using an OS transistor as the transistor 200 can be a semiconductor device with low power consumption. Furthermore, the OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range from room temperature to 200° C. or less. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device using an OS transistor operates stably even in a high-temperature environment and has high reliability.

[0089] The insulating layer 205, which functions as a gate insulating layer of the transistor 200, is provided to cover the opening 221. The insulating layer 205 has a region located inside the opening 221. The insulating layer 205 is provided over the semiconductor layer 213, the conductive layer 212, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, and the insulating layer 203. The insulating layer 205 can have a region in contact with the top surface of the semiconductor layer 213, a region in contact with the side surface of the semiconductor layer 213, a region in contact with the top surface of the conductive layer 212, a region in contact with the side surface of the conductive layer 212, a region in contact with the top surface of the conductive layer 111a, a region in contact with the side surface of the conductive layer 111a, a region in contact with the top surface of the conductive layer 111b, a region in contact with the side surface of the conductive layer 111b, a region in contact with the top surface of the conductive layer 116, a region in contact with the side surface of the conductive layer 116, and a region in contact with the top surface of the insulating layer 203. The insulating layer 205 has a shape that follows the shapes of the top and side surfaces of the semiconductor layer 213, the top and side surfaces of the conductive layer 212, the top and side surfaces of the conductive layer 111a, the top and side surfaces of the conductive layer 111b, the top and side surfaces of the conductive layer 116, and the top surface of the insulating layer 203.

[0090] The conductive layer 215 functioning as a gate electrode of the transistor 200 is provided over the insulating layer 205 and can have a region in contact with a top surface of the insulating layer 205. The conductive layer 215 has a region overlapping with the semiconductor layer 213 with the insulating layer 205 interposed therebetween.

[0091] 1B and 1D , the conductive layer 215 is provided to have a region located inside the opening 221. The semiconductor layer 213 and the conductive layer 215 are provided to have a region facing each other with the insulating layer 205 sandwiched therebetween. Specifically, the semiconductor layer 213 and the conductive layer 215 are provided to have a region facing each other with the insulating layer 205 sandwiched therebetween inside the opening 221. The conductive layer 215 has a region overlapping with the conductive layer 211 with the insulating layer 205 and the semiconductor layer 213 interposed therebetween, and a region overlapping with the conductive layer 212 with the insulating layer 205 and the semiconductor layer 213 interposed therebetween.

[0092] The insulating layer 207 can be provided over the insulating layer 205 so as to cover the top surface and side surfaces of the conductive layer 215. The insulating layer 207 can function as a protective layer for the transistor 200. The insulating layer 207 can also function as a protective layer for the transistor 100.

[0093] As shown in FIGS. 1B and 1D , the insulating layer 203 has a region located between the conductive layer 211 and the conductive layer 212 and a region located on the insulating layer 107. Therefore, the conductive layer 211 and the conductive layer 212 have a region where they overlap with each other through the insulating layer 203. Therefore, the lower surface of the conductive layer 211, which functions as one of the source electrode and drain electrode of the transistor 200, and the lower surface of the conductive layer 212, which functions as the other of the source electrode and drain electrode of the transistor 200, are located at different heights. As described above, the transistor 200 is a vertical transistor. In the transistor 200, a drain current flows in the vertical direction (Z direction) from one of the conductive layer 211 and the conductive layer 212 through the semiconductor layer 113 toward the other of the conductive layer 211 and the conductive layer 212. Specifically, the drain current flows along the side surface of the insulating layer 203 on the opening 221 side.

[0094] In the transistor 200, the conductive layer 212 is provided over the conductive layer 211. That is, for example, the height of the bottom surface of the conductive layer 212 from the top surface of the substrate 101 and the top surface of the insulating layer 102 is higher than the height of the bottom surface of the conductive layer 211. Therefore, the conductive layer 211 is referred to as a lower electrode, and the conductive layer 212 is referred to as an upper electrode.

[0095] The transistor 200 has a region where the conductive layer 211 and the conductive layer 212 overlap. Therefore, the transistor 200 can occupy a smaller area than, for example, a lateral transistor, specifically, a lateral OS transistor. Therefore, the semiconductor device 10 can be a semiconductor device with a small area.

[0096] Here, the channel length and channel width of the transistor 200 will be described with reference to FIGS. 2A and 2B. FIG. 2A is an enlarged plan view illustrating an example of the configuration of the transistor 200 and its periphery shown in FIG. 1A. FIG. 2B is a cross-sectional view taken along dashed dotted line A3-A4 shown in FIG. 2A. In FIG. 2B, of the openings 221, the openings in the insulating layer 203 are referred to as openings 221a, and the openings in the conductive layer 212 are referred to as openings 221b.

[0097] In the semiconductor layer 213, a region in contact with the conductive layer 211 functions as one of a source region and a drain region, a region in contact with the conductive layer 212 functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0098] The channel length of the transistor 200 is the distance between the source region and the drain region. In Figure 2B, the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L200 is the distance between the edge of the region where the semiconductor layer 213 and the conductive layer 211 contact each other and the edge of the region where the semiconductor layer 213 and the conductive layer 212 contact each other.

[0099] Here, the channel length L200 of the vertical transistor 200 corresponds to the length of the side surface of the insulating layer 203 on the opening 221a side when viewed from the XZ plane. In other words, the channel length L200 is determined by the film thickness T203 of the insulating layer 203 and the angle θ203 between the side surface of the insulating layer 203 on the opening 221a side and the surface on which the insulating layer 203 is to be formed (here, the top surface of the conductive layer 211), and is not affected by the performance of the exposure equipment used to fabricate the transistor. Therefore, the channel length L200 can be made smaller than the resolution limit of the exposure equipment, allowing for the realization of a fine-sized transistor. Specifically, a transistor with a channel length shorter than that of a lateral transistor can be realized. Therefore, the channel length L200 can be made shorter than the channel length L100 of the lateral transistor 100, for example.

[0100] For example, the channel length L200 can be set to 0.01 μm or more and less than 3.0 μm, preferably 0.05 μm or more and less than 3.0 μm, more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.5 μm. 2B , the thickness T203 of the insulating layer 203 is preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.2 μm, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less.

[0101] The on-state current of the transistor 200 can be increased by shortening the channel length L200. Therefore, by using the transistor 200 as a vertical OS transistor, the semiconductor device 10 can be driven at higher speed than when the transistor 200 is, for example, a horizontal OS transistor. Furthermore, by shortening the channel length L200, the driving voltage of the transistor 200 can be reduced. Therefore, by using the transistor 200 as a vertical OS transistor, the power consumption of the semiconductor device 10 can be reduced compared to when the transistor 200 is, for example, a horizontal OS transistor.

[0102] The channel length L200 can be controlled by adjusting the thickness T203 and angle θ203 of the insulating layer 203. Thus, the insulating layer 203 functions as a spacer for controlling the channel length L200.

[0103] The thickness T203 of the insulating layer 203 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, even more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.5 μm. It is preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.2 μm, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, even more preferably 0.50 μm or more and 1.0 μm or less.

[0104] The side surface of the insulating layer 203 on the opening 221a side is preferably tapered. The angle θ203 formed between the side surface of the insulating layer 203 on the opening 221a side and the surface on which the insulating layer 203 is to be formed (here, the top surface of the conductive layer 211) is preferably less than 90 degrees. By reducing the angle θ203, it is possible to improve the coverage of a layer (e.g., the semiconductor layer 213) provided on the insulating layer 203. However, reducing the angle θ203 reduces the contact area between the semiconductor layer 213 and the conductive layer 211, which may increase the contact resistance between the semiconductor layer 213 and the conductive layer 211. The angle θ203 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and less than 90 degrees, even more preferably 55 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 80 degrees, and even more preferably 70 degrees or more and less than 80 degrees. By setting the angle θ203 within the above range, the channel length of the transistor 200 can be shortened while improving the coverage of the conductive layer 211 and the layer (e.g., the semiconductor layer 213) formed on the insulating layer 203, and defects such as discontinuities or voids in the layer can be suppressed. Furthermore, the contact resistance between the semiconductor layer 213 and the conductive layer 211 can be reduced.

[0105] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0106] 2B shows a cross-sectional view in which the side surface of the insulating layer 203 on the opening 221a side is linear, but one embodiment of the present invention is not limited to this. In the cross-sectional view, the side surface of the insulating layer 203 on the opening 221a side may be curved, or the side surface may have both linear and curved regions.

[0107] The channel width of the transistor 200 is the width of the source region or the width of the drain region in a direction perpendicular to the channel length direction. That is, the channel width is the width of the region where the semiconductor layer 213 and the conductive layer 211 contact each other or the width of the region where the semiconductor layer 213 and the conductive layer 212 contact each other in a direction perpendicular to the channel length direction. Here, the channel width of the transistor 200 is described as the width of the region where the semiconductor layer 213 and the conductive layer 212 contact each other in a direction perpendicular to the channel length direction. In Figures 2A and 2B, the channel width W200 of the transistor 200 is indicated by a solid double-headed arrow. The channel width W200 is the length of the bottom end of the conductive layer 212 on the opening 123 side in a plan view.

[0108] The channel width W200 is determined by the planar shape of the opening 221b. In Figures 2A and 2B, the width D221 of the opening 221b is indicated by a two-dot chain line with a double arrow. The width D221 indicates the short side of the smallest rectangle circumscribing the opening 221b in plan view.

[0109] When the opening 221 is formed by photolithography and etching, the width D221 is equal to or greater than the limit resolution of the exposure device. The width D221 is, for example, preferably 0.20 μm or more and less than 5.0 μm, more preferably 0.20 μm or more and less than 4.5 μm, even more preferably 0.20 μm or more and less than 4.0 μm, even more preferably 0.20 μm or more and less than 3.5 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.5 μm. Preferably, the width is less than 2.0 μm, more preferably 0.20 μm or more but less than 1.5 μm, even more preferably 0.30 μm or more but less than 1.5 μm, even more preferably 0.30 μm or more but less than 1.2 μm, even more preferably 0.40 μm or more but less than 1.2 μm, even more preferably 0.40 μm or more but less than 1.0 μm, even more preferably 0.50 μm or more but less than 1.0 μm. When the planar shape of the opening 221 is circular, the width D221 corresponds to the diameter of the opening 221b, and the channel width W200 can correspond to the periphery length "D221 × π" of the opening 221b in plan view. For example, "D221 × π" can be regarded as the channel width W200.

[0110] As described above, the semiconductor device 10 is a CMOS semiconductor device including the transistor 100 which is a p-channel lateral Si transistor and the transistor 200 which is an n-channel vertical OS transistor.

[0111] When both p-channel and n-channel transistors are, for example, lateral Si transistors, the difference in electrical characteristics between the p-channel and n-channel transistors is large. Specifically, when the channel lengths and channel widths of the n-channel and p-channel transistors are equal, the on-current of the n-channel transistor is larger than that of the p-channel transistor. On the other hand, if the difference between the on-current of the n-channel transistor and the on-current of the p-channel transistor constituting a CMOS circuit is large, the CMOS circuit may not operate normally. For this reason, for example, the channel width of the p-channel transistor must be larger than that of the n-channel transistor. Therefore, the area occupied by the CMOS circuit is larger than when the channel width of the p-channel transistor is equal to that of the n-channel transistor.

[0112] In the semiconductor device of one embodiment of the present invention, a vertical OS transistor is used as an n-channel transistor. The field-effect mobility of an OS transistor may be lower than that of a Si transistor. Therefore, when an OS transistor and a Si transistor have the same channel length, channel width, polarity, and the like, the on-state current of the OS transistor can be smaller than that of a Si transistor. As described above, the channel length of a vertical transistor can be shorter than that of a horizontal transistor. Therefore, the on-state current of a vertical transistor can be larger than that of a horizontal transistor. As described above, in the semiconductor device of one embodiment of the present invention, the difference in electrical characteristics between a p-channel transistor and an n-channel transistor can be smaller than when, for example, a p-channel transistor is replaced with a horizontal Si transistor and an n-channel transistor is replaced with a horizontal OS transistor. Specifically, the difference in on-state current can be reduced.

[0113] As described above, by using a horizontal Si transistor as a p-channel transistor and a vertical OS transistor as an n-channel transistor, the difference in electrical characteristics between the p-channel transistor and the n-channel transistor can be reduced without increasing the channel width of the p-channel transistor, compared to when both the p-channel transistor and the n-channel transistor are horizontal Si transistors. Specifically, the difference in on-state current can be reduced. Therefore, a semiconductor device with a small occupation area can be provided.

[0114] Furthermore, since a vertical transistor can have a region where the source electrode and the drain electrode overlap, the area occupied by the vertical transistor can be smaller than that of a horizontal transistor. Therefore, by using an n-channel transistor as a vertical transistor, the area occupied by the semiconductor device can be made smaller than that of a horizontal transistor.

[0115] 1A to 2B , an insulating layer 107 is provided on the conductive layer 115 and under the conductive layer 211. This allows the distance between the semiconductor layer 113 (region 113nb in FIG. 1B ) and the conductive layer 211 to be longer than when the semiconductor device 10 does not include the insulating layer 107 and the conductive layer 211 is provided on the same formation surface as the conductive layer 115. Therefore, by providing the insulating layer 107 in the semiconductor device 10 as described above, the parasitic capacitance between the semiconductor layer 113 (region 113nb in FIG. 1B ) and the conductive layer 211 can be reduced compared to when the semiconductor device 10 does not include the insulating layer 107. This allows the semiconductor device 10 to operate at high speed.

[0116] 3 is a cross-sectional view illustrating the transistor 200 illustrated in FIG. 1B and a conductive layer provided on the same formation surface as the conductive layer included in the transistor 200. The conductive layer 231 illustrated in FIG. 3 can be the conductive layer 211. The conductive layer 231 can be a conductive layer different from the conductive layer 211 and provided on the same formation surface as the conductive layer 211.

[0117] The insulating layer 203 has an opening 241 that reaches the conductive layer 231. The conductive layer 232 is provided so as to have a region located inside the opening 241. The conductive layer 232 has a region in contact with the top surface of the conductive layer 231 and a region in contact with the top surface of the insulating layer 203. Thus, the conductive layer 231 and the conductive layer 232 can be connected. Note that the opening 241 can be formed in the same process as the openings 121a, 121b, and 122 shown in FIG. 1B.

[0118] The conductive layer 232 can be the conductive layer 212. Alternatively, the conductive layer 232 can be a conductive layer different from the conductive layer 212 and provided on the same surface where the conductive layer 212 is to be formed.

[0119] The conductive layer 233 can be the conductive layer 212. The conductive layer 233 can be a conductive layer different from the conductive layer 212 and provided on the same surface where the conductive layer 212 is formed.

[0120] The insulating layer 205 has an opening 243 that reaches the conductive layer 233. The conductive layer 234 is provided so as to have a region located inside the opening 243. The conductive layer 234 has a region in contact with the top surface of the conductive layer 233 and a region in contact with the top surface of the insulating layer 205. Thus, the conductive layer 233 and the conductive layer 234 can be connected to each other.

[0121] The conductive layer 234 can be the conductive layer 215. Alternatively, the conductive layer 234 can be a conductive layer different from the conductive layer 215 and provided on the same surface where the conductive layer 215 is formed.

[0122] The conductive layer 235 can be the conductive layer 211. Alternatively, the conductive layer 235 can be a conductive layer different from the conductive layer 211 and provided on the same surface where the conductive layer 211 is formed.

[0123] The insulating layer 203 and the insulating layer 205 have openings 245 that reach the conductive layer 235. The openings 245 include an opening in the insulating layer 203 and an opening in the insulating layer 205. In other words, the openings in the regions where the insulating layer 203 overlaps with the conductive layer 235 are part of the openings 245. The openings in the regions where the insulating layer 205 overlaps with the conductive layer 235 are another part of the openings 245.

[0124] The conductive layer 236 is provided to have a region located inside the opening 245. The conductive layer 236 has a region in contact with the top surface of the conductive layer 235 and a region in contact with the top surface of the insulating layer 205. Thus, the conductive layer 235 and the conductive layer 236 can be connected to each other.

[0125] The conductive layer 236 can be the conductive layer 215. Alternatively, the conductive layer 236 can be a conductive layer different from the conductive layer 215 and provided on the same surface where the conductive layer 215 is to be formed.

[0126] 4A, 4B, and 4C show examples in which the insulating layer 203 shown in FIGS. 1B, 1C, and 1D, respectively, has an insulating layer 203a, an insulating layer 203b on the insulating layer 203a, and an insulating layer 203c on the insulating layer 203b.

[0127] Here, the insulating layer 203b is preferably an insulating layer containing oxygen. Furthermore, the insulating layer 203b is preferably an insulating layer that releases oxygen by heating. Thus, for example, when a metal oxide is used for the semiconductor layer 213, oxygen contained in the insulating layer 203b can be supplied to the metal oxide. Thus, oxygen vacancies in the metal oxide can be repaired, thereby improving the electrical characteristics and reliability of the transistor 200 shown in FIGS. 4A to 4C.

[0128] On the other hand, the insulating layers 203a and 203c are preferably insulating layers that have a blocking property against oxygen, hydrogen, and the like. This can prevent oxygen contained in the insulating layer 203b from being released to the outside through the insulating layer 203a or 203c. Furthermore, when the insulating layer 203a has a blocking property against hydrogen, even when the insulating layer 107 has a function of supplying hydrogen to the semiconductor layer 113, for example, the hydrogen contained in the insulating layer 107 can be prevented from diffusing to the semiconductor layer 213. Furthermore, when the insulating layer 203a has a blocking property against hydrogen, the hydrogen contained in the semiconductor layer 113 can be prevented from diffusing to the semiconductor layer 213. As described above, hydrogen can be contained in the semiconductor layer 113 while preventing the hydrogen from diffusing to the semiconductor layer 213. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. The insulating layer 203 may have a two-layer stacked structure or a four-layer or more stacked structure. When the insulating layer 203 has a two-layer stacked structure, the insulating layer 203 can have, for example, an insulating layer 203a and an insulating layer 203b on the insulating layer 203a.

[0129] 5A and 5B are diagrams showing an example in which the other of the source electrode and the drain electrode of the transistor 100 shown in Figures 1A and 1B and the other of the source electrode and the drain electrode of the transistor 200 are both formed as the conductive layer 112. Note that examples of cross-sectional structures taken along dashed dotted lines B1-B2 and B3-B4 shown in Figure 5A can be seen in Figures 1C and 1D, respectively.

[0130] 5B , the conductive layer 112 has a region in contact with the top surface of the insulating layer 203 and is provided on the same surface as the conductive layers 111a and 116. The conductive layers 111a, 112, and 116 can be formed by processing the same conductive film, for example. Therefore, the conductive layers 111a, 112, and 116 can have the same material.

[0131] For example, FIG. 1B shows an example in which the insulating layer 105 functioning as the gate insulating layer of the transistor 100 and the insulating layer 105 functioning as the gate insulating layer of the transistor 200 are not patterned. However, one or both of the insulating layer 105 and the insulating layer 205 may be patterned for processing. FIGS. 6A and 6B show an example in which the insulating layer 105 and the insulating layer 205 are patterned for processing. FIG. 6A shows an example in which the top surface end of the insulating layer 105 coincides or approximately coincides with the bottom surface end of the conductive layer 115, and the top surface end of the insulating layer 205 coincides or approximately coincides with the bottom surface end of the conductive layer 215. FIG. 6B shows an example in which the bottom surface end of the conductive layer 115 is located inside the top surface end of the insulating layer 105, i.e., on the conductive layer 116 side, and the bottom surface end of the conductive layer 215 is located inside the top surface end of the insulating layer 205, i.e., on the opening 221 side.

[0132] The structures of the insulating layer 105 and the insulating layer 205 shown in Figures 1B, 6A, and 6B can be combined as appropriate. Specifically, the insulating layer 105 can have the structure shown in any one of Figures 1B, 6A, and 6B, and the insulating layer 205 can have the structure shown in another one of them. For example, one of the insulating layer 105 and the insulating layer 205 can have the structure shown in Figure 1B, and the other of the insulating layer 105 and the insulating layer 205 can have the structure shown in Figure 6A or 6B.

[0133] <Configuration Example 2 of Semiconductor Device> Hereinafter, a configuration example of a semiconductor device that is partially different from that of Figures 1A to 6B will be described. Note that, below, descriptions of parts that overlap with Figures 1A to 6B will be omitted as appropriate.

[0134] [Configuration Example 2-1] FIGS. 7A and 7B are plan views illustrating a configuration example of a semiconductor device 10. FIG. 7C is a cross-sectional view along dashed dotted line A1-A2 in FIG. 7A. FIGS. 7A and 7C illustrate an example in which a conductive layer 211 functioning as a lower electrode of a transistor 200 is provided on the same formation surface as a conductive layer 115 functioning as a gate electrode of a transistor 100. In the semiconductor device 10 illustrated in FIGS. 7A and 7C, for example, the insulating layer 107 illustrated in FIG. 1B is not provided. The conductive layer 211 has a region in contact with the top surface of the insulating layer 105. Furthermore, the openings 121a and 121b are provided in the insulating layer 105 and the insulating layer 203, respectively, and the opening 122 is provided in the insulating layer 203. The semiconductor device 10 illustrated in FIGS. 7A and 7C may also include the insulating layer 107. Specifically, the insulating layer 107 may be provided between the insulating layer 105 and the insulating layer 203 , the conductive layer 115 , and the conductive layer 211 .

[0135] 7A and 7C, the conductive layer 115 and the conductive layer 211 can be formed by processing the same conductive film, for example, and therefore can have the same material.

[0136] 7B illustrates an example in which the gate electrode of the transistor 100 and one of the source electrode and drain electrode of the transistor 200 illustrated in FIG. 7A are both formed as the conductive layer 117. Here, for an example of a cross-sectional structure taken along the dashed dotted line A1-A2 illustrated in FIG. 7B, the conductive layer 115 and the conductive layer 211 are both replaced with the conductive layer 117, and FIG. 7C can be referred to. For the conductive layer 117, the same material as that which can be used for the conductive layer 115 and the conductive layer 211 can be used.

[0137] 8A and 8B are diagrams illustrating an example in which the conductive layer 111a, the conductive layer 111b, and the conductive layer 116 illustrated in FIGS. 1A and 1B are provided on the same formation surface as the conductive layer 215. As illustrated in FIG. 8B, the conductive layer 111a, the conductive layer 111b, and the conductive layer 116 have regions in contact with the top surface of the insulating layer 205. Furthermore, the opening 121a and the opening 121b are both provided in the insulating layer 205 in addition to the insulating layer 105, the insulating layer 107, and the insulating layer 203. Furthermore, the opening 122 is provided in the insulating layer 205 in addition to the insulating layer 107 and the insulating layer 203.

[0138] 8A and 8B , the openings 121a and 121b each include an opening in the insulating layer 105, an opening in the insulating layer 107, an opening in the insulating layer 203, and an opening in the insulating layer 205. In other words, the opening in the region where the insulating layer 205 overlaps with the region 113na is part of the opening 121a, and the opening in the region where the insulating layer 205 overlaps with the region 113nb is part of the opening 121b. Furthermore, the opening 122 includes an opening in the insulating layer 205, in addition to the openings in the insulating layer 107 and the insulating layer 203. In other words, the opening in the region where the insulating layer 205 overlaps with the conductive layer 115 is part of the opening 122.

[0139] The conductive layer 111a, the conductive layer 111b, the conductive layer 116, and the conductive layer 215 can be formed by processing the same conductive film, for example. Thus, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, and the conductive layer 215 can have the same material.

[0140] 9A and 9B show an example in which the conductive layer 211 shown in FIGS. 8A and 8B is provided on the same formation surface as the conductive layer 115. In the semiconductor device 10 shown in FIGS. 9A and 9B, for example, the insulating layer 107 shown in FIG. 8B is not provided. FIG. 9A can be said to be a combination of the configuration shown in FIG. 7A and the configuration shown in FIG. 8A. FIG. 9B can be said to be a combination of the configuration shown in FIG. 7C and the configuration shown in FIG. 8B. Note that the insulating layer 107 may also be provided in the semiconductor device 10 shown in FIGS. 9A and 9B.

[0141] 10A and 10B illustrate an example in which the gate electrode of the transistor 100 and the lower electrode of the transistor 200 shown in FIGS. 8A and 8B are both formed as the conductive layer 118. In the example illustrated in FIGS. 10A and 10B , an opening 221 reaching the conductive layer 118 is provided in the insulating layer 107, the insulating layer 203, and the conductive layer 212. The opening 221 includes an opening in the insulating layer 107, an opening in the insulating layer 203, and an opening in the conductive layer 212. In other words, the opening in the region where the insulating layer 107 overlaps with the conductive layer 118 is part of the opening 221. The opening in the region where the insulating layer 203 overlaps with the conductive layer 118 is another part of the opening 221. The opening in the region where the conductive layer 212 overlaps with the conductive layer 118 is another part of the opening 221.

[0142] 10B , the semiconductor layer 213 has a region in contact with the conductive layer 118, specifically a region in contact with the top surface of the conductive layer 118. The semiconductor layer 213 can also have a region in contact with the side surface of the insulating layer 107 inside the opening 221.

[0143] 10A and 10B , the semiconductor layer 113 can overlap with the opening 221, specifically, the region 113i can overlap with the opening 221. Therefore, at least a part of the semiconductor layer 213, the insulating layer 205, and the conductive layer 215, each of which has a region located inside the opening 221, can overlap with the semiconductor layer 113, specifically, the region 113i.

[0144] 8A and 8B can be used for the conductive layer 118. Alternatively, the conductive layer 118 can be used for the conductive layer 211 shown in FIGS.

[0145] 11A and 11B are diagrams showing an example in which the other of the source electrode and the drain electrode of the transistor 100 shown in FIGS. 10A and 10B and the gate electrode of the transistor 200 are both formed of a conductive layer 119. As shown in FIG. 11B, the conductive layer 119 has a region located inside the opening 121b and a region located inside the opening 221. The conductive layer 119 is provided on the same formation surface as the conductive layer 111a. For example, the conductive layer 119 can be formed using a material that can be used for the conductive layer 215 shown in FIGS. 10A and 10B.

[0146] 12A and 12B are diagrams illustrating an example in which the conductive layer 111a, the conductive layer 111b, and the conductive layer 116 illustrated in FIGS. 1A and 1B are provided on the same formation surface as the conductive layer 211. As illustrated in FIG. 12B, the conductive layer 111a, the conductive layer 111b, and the conductive layer 116 have regions in contact with the top surface of the insulating layer 107. The openings 121a and 121b are provided in the insulating layer 105 and the insulating layer 107, respectively, and the opening 122 is provided in the insulating layer 107.

[0147] The conductive layer 111a, the conductive layer 111b, the conductive layer 116, and the conductive layer 211 can be formed by processing the same conductive film, for example. Thus, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, and the conductive layer 211 can have the same material.

[0148] 13A, 13B, and 13C illustrate an example in which the structure of a transistor 200 is different from that of the transistor 200 illustrated in FIGS. 1A, 1B, and 1D, respectively. The transistor 200 illustrated in FIGS. 13A, 13B, and 13C does not include the conductive layer 211 and the conductive layer 212 illustrated in FIGS. 1A, 1B, and 1D, but includes a conductive layer 212a and a conductive layer 212b.

[0149] The conductive layer 212a functions as one of the source electrode and the drain electrode of the transistor 200. The conductive layer 212b functions as the other of the source electrode and the drain electrode of the transistor 200. The conductive layer 212a and the conductive layer 212b have a region in contact with the top surface of the insulating layer 203. The conductive layer 212a and the conductive layer 212b are provided on the same formation surface as the conductive layer 111a, the conductive layer 111b, and the conductive layer 116. The conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212a, and the conductive layer 212b can be formed by processing the same conductive film, for example. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212a, and the conductive layer 212b can have the same material.

[0150] 13A, 13B, and 13C, the opening 221 is provided in the insulating layer 203 so as to reach the insulating layer 107. The conductive layer 212a and the conductive layer 212b can be provided so as to face each other with the opening 221 interposed therebetween in a plan view.

[0151] The semiconductor layer 213 has a shape along the top surface and side surfaces of the conductive layer 212a, the top surface and side surfaces of the conductive layer 212b, the side surfaces of the insulating layer 203, and the top surface of the insulating layer 107. The semiconductor layer 213 has a region in contact with the conductive layer 212a and a region in contact with the conductive layer 212b. Specifically, the semiconductor layer 213 can have a region in contact with the top surface of the conductive layer 212a, a region in contact with the side surface of the conductive layer 212a, a region in contact with the top surface of the conductive layer 212b, and a region in contact with the side surface of the conductive layer 212b. The semiconductor layer 213 can also have a region in contact with the top surface of the insulating layer 107 inside the opening 221 and a region in contact with the side surface of the insulating layer 203.

[0152] 13B shows an example of a cross-sectional configuration of the transistor 200 in the channel width direction, and Fig. 13C shows an example of a cross-sectional configuration of the transistor 200 in the channel length direction. In Fig. 13C, the channel length L200a of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L200a is the distance between the end of the region where the semiconductor layer 213 and the conductive layer 212a contact each other and the end of the region where the semiconductor layer 213 and the conductive layer 212b contact each other in a cross-sectional view.

[0153] The channel length L200a has not only a component along the side surface of the insulating layer 203 on the opening 221 side (vertical direction) but also a component along the top surface of the insulating layer 107 (horizontal direction). Therefore, the channel length L200a can be made longer than the channel length L200 shown in FIG. 2B. Therefore, the transistor 200 shown in FIGS. 13A to 13C can have higher saturation than, for example, the transistor 200 shown in FIG. 2B. Note that the transistor 200 shown in FIGS. 13A to 13C can be called a VLFET (Vertical Lateral Field Effect Transistor) because it has a configuration in which current flows both vertically and horizontally.

[0154] In this specification and the like, a small change in current (small gradient) in the saturation region in the Id-Vd characteristics of a transistor is referred to as "high saturation."

[0155] 14A, 14B, and 14C illustrate examples of the transistor 200 illustrated in FIGS. 13A, 13B, and 13C, respectively, including a conductive layer 216. The conductive layer 216 is provided between the insulating layer 105 and the insulating layer 107. The conductive layer 216 has a region in contact with the top surface of the insulating layer 105. The insulating layer 107 can be provided to cover the top surface and side surfaces of the conductive layer 216.

[0156] The conductive layer 216 has a region overlapping with the opening 221. Specifically, the conductive layer 216 has a region overlapping with a region of the semiconductor layer 213, the insulating layer 205, and the conductive layer 215 that is located inside the opening 221.

[0157] 14A to 14C , not only the conductive layer 215 but also the conductive layer 216 can function as the gate electrode of the transistor 200. Furthermore, not only the insulating layer 205 but also the insulating layer 107 can function as the gate insulating layer of the transistor 200. Therefore, the transistor 200 shown in FIGS. 14A to 14C can be referred to as a dual-gate transistor in which gate electrodes are provided on both sides of a channel formation region. On the other hand, the transistor 200 shown in FIGS. 13A to 13C , which does not include the conductive layer 216, can be referred to as a single-gate transistor. Here, since not only the insulating layer 205 but also the insulating layer 107 can function as the gate insulating layer of the transistor 200, the insulating layer 107 included in the semiconductor device 10 shown in FIGS. 14A to 14C can be formed using a material that can be used for the insulating layer 205. Furthermore, the insulating layer 107 included in the semiconductor device 10 shown in FIGS. 14A to 14C can be formed using a material that can be used for the insulating layer 105.

[0158] 14A to 14C , for example, the conductive layer 215 can be referred to as a first gate electrode, a front gate electrode, or simply as a gate electrode. The conductive layer 216 can be referred to as a second gate electrode, a back gate electrode, or simply as a gate electrode. The insulating layer 205 can be referred to as a first gate insulating layer, and the insulating layer 107 can be referred to as a second gate insulating layer. Note that the names of the conductive layer 215 and the conductive layer 216 may be interchanged, and the names of the insulating layer 205 and the insulating layer 107 may be interchanged.

[0159] The conductive layer 216 in the transistor 200 can fix the potential on the back gate electrode side (also referred to as the back channel side) of the semiconductor layer 213, thereby suppressing a shift in the threshold voltage. Here, if the threshold voltage of the transistor 200 shifts in the negative direction, the drain current (also referred to as the cutoff current) that flows when the gate voltage is 0 V may become large. By suppressing the shift in the threshold voltage of the transistor 200 in the negative direction, the transistor can have a small cutoff current. Note that a small cutoff current is sometimes referred to as a normally-off transistor.

[0160] 14A to 14C , the transistor 200 is a dual-gate transistor, which can provide a transistor 200 that exhibits better electrical characteristics than a single-gate transistor. Meanwhile, as shown in, for example, FIGS. 13A to 13C , the transistor 200 is a single-gate transistor, which can reduce the number of manufacturing steps of the semiconductor device 10 compared to a dual-gate transistor. This reduces the manufacturing cost of the semiconductor device 10. Therefore, the semiconductor device 10 can be a low-cost semiconductor device.

[0161] The conductive layer 216 can be provided on the same surface as the conductive layer 115. The conductive layer 115 and the conductive layer 216 can be formed by processing the same conductive film, for example. Thus, the conductive layer 115 and the conductive layer 216 can have the same material.

[0162] [Configuration Example 2-5] Figures 15A, 15B, and 15C show examples in which the configuration of the transistor 200 is different from that of the transistor 200 shown in Figures 1A, 1B, and 1D, respectively, and specifically show examples in which the transistor 200 is a lateral transistor.

[0163] 1A, 1B, and 1D, the transistor 200 includes a conductive layer 211a and a conductive layer 211b. The semiconductor device 10 shown in FIGS. 15A to 15C does not include the insulating layer 203 shown in FIG. 1B, for example. FIGS. 15A and 15B illustrate an example in which the conductive layer 215 has a region overlapping with the conductive layer 211a and a region overlapping with the conductive layer 211b. FIGS. 15A to 15C illustrate an example in which the conductive layer 215 extends in the X direction.

[0164] The conductive layer 211a functions as one of the source electrode and the drain electrode of the transistor 200. The conductive layer 211b functions as the other of the source electrode and the drain electrode of the transistor 200. The conductive layer 211a and the conductive layer 211b have regions in contact with the top surface of the insulating layer 107. In the example shown in FIGS. 15A to 15C , the conductive layer 111a, the conductive layer 111b, and the conductive layer 116 have regions in contact with the top surface of the insulating layer 107. As described above, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 211a, and the conductive layer 211b are provided on the same formation surface. The conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 211a, and the conductive layer 211b can be formed, for example, by processing the same conductive film. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 211a, and the conductive layer 211b can have the same material.

[0165] 15A to 15C , a semiconductor layer 213 is provided between the conductive layer 211a and the conductive layer 211b. The semiconductor layer 213 has a region in contact with the conductive layer 211a and a region in contact with the conductive layer 211b. Specifically, the semiconductor layer 213 can have a region in contact with the top surface of the conductive layer 211a, a region in contact with the side surface of the conductive layer 211a, a region in contact with the top surface of the conductive layer 211b, and a region in contact with the side surface of the conductive layer 211b. The semiconductor layer 213 can also have a region in contact with the top surface of the insulating layer 107.

[0166] 15B shows an example of a cross-sectional configuration in the channel length direction of the transistor 200 shown in FIG. 15A. 15C shows an example of a cross-sectional configuration in the channel width direction of the transistor 200 shown in FIG. 15B. In FIG. 15B, the channel length L100 of the transistor 100 and the channel length L200b of the transistor 200 are indicated by dashed double-headed arrows. The channel length L200b is the distance between the end of the region where the semiconductor layer 213 and the conductive layer 211a contact each other and the end of the region where the semiconductor layer 213 and the conductive layer 211b contact each other in a cross-sectional view.

[0167] In a horizontal transistor such as the transistor 200 shown in Figures 15A to 15C, the channel formation region overlaps with the gate electrode but not with either the source or drain electrode. On the other hand, in a vertical transistor such as the transistor 200 shown in Figures 1A, 1B, and 1D, the channel formation region overlaps not only with the gate electrode but also with, for example, the bottom electrode. Therefore, by configuring the transistor 200 as a horizontal transistor, the area where the source electrode and gate electrode overlap, and the area where the drain electrode and gate electrode overlap, can be made smaller than in the case of a vertical transistor. Therefore, by configuring the transistor 200 as a horizontal transistor, the parasitic capacitance between the source electrode and gate electrode and the parasitic capacitance between the drain electrode and gate electrode can be made smaller than in the case of a vertical transistor.

[0168] The semiconductor device 10 shown in FIGS. 15A to 15C does not require the formation of the insulating layer 203 shown in FIG. 1B, nor does it require the formation of the opening 221. Therefore, the semiconductor device 10 shown in FIGS. 15A to 15C can be manufactured using fewer manufacturing steps than the semiconductor device 10 shown in FIGS. 1A to 1D, for example. Therefore, the semiconductor device 10 shown in FIGS. 15A to 15C can be manufactured at lower cost than the semiconductor device 10 shown in FIGS. 1A to 1D, for example. Therefore, the semiconductor device 10 shown in FIGS. 15A to 15C can be manufactured at lower cost. Furthermore, the channel length L200b of the transistor 200 shown in FIG. 15B can be longer than the channel length L200 of the transistor 200 shown in FIG. 2B. Therefore, the transistor 200 shown in FIGS. 15A to 15C can have higher saturation than the transistor 200 shown in FIG. 2B, for example.

[0169] Here, for example, the distance in the X direction between the conductive layer 211a and the conductive layer 211b is set to be shorter than at least the distance in the X direction between the region 113na and the region 113nb of the semiconductor layer 113. For example, it is preferable that the distance in the X direction between the conductive layer 211a and the conductive layer 211b be as short as possible. For example, by shortening the distance in the X direction between the conductive layer 211a and the conductive layer 211b, the channel length L200b of the transistor 200 shown in FIGS. 15A to 15C can be shortened. Specifically, the channel length L200b can be made shorter than the channel length L100 of the transistor 100. This can reduce the difference in on-current between the transistor 100, which is a p-channel transistor, and the transistor 200, which is an n-channel transistor.

[0170] 16A, 16B, and 16C show examples in which the conductive layer 215 shown in Fig. 15A, 15B, and 15C does not overlap with the conductive layer 211 a and the conductive layer 211 b, respectively. Note that Fig. 16A to 16C show examples in which the conductive layer 215 extends in the Y direction.

[0171] 15A to 15C , the transistor 200 shown in FIGS. 16A to 16C can reduce the parasitic capacitance between the conductive layer 211a and the conductive layer 215 and the parasitic capacitance between the conductive layer 211b and the conductive layer 215, as compared with the transistor 200 shown in FIGS. 15A to 15C . Meanwhile, the transistor 200 shown in FIGS. 15A to 15C can have a structure in which the entire semiconductor layer 213 overlaps with at least one of the conductive layer 211a, the conductive layer 211b, and the conductive layer 215. Therefore, the transistor 200 shown in FIGS. 15A to 15C can prevent a high-resistance region (offset region) from being formed in the semiconductor layer 213 due to the difficulty of the gate electric field reaching the semiconductor layer 213. Therefore, the transistor 200 shown in FIGS. 15A to 15C can have a larger on-state current than the transistor 200 shown in FIGS. 16A to 16C .

[0172] 17A shows an example in which the end of the upper surface of the insulating layer 205 shown in Fig. 16B coincides or approximately coincides with the end of the lower surface of the conductive layer 215. For example, when the conductive layer 215 is formed by photolithography and etching, if the etching selectivity between the conductive layer 215 and the insulating layer 205 is low, the structure shown in Fig. 17A may be formed.

[0173] 17B shows an example in which the bottom end of the conductive layer 215 shown in FIG. 16B is located inside the top end of the insulating layer 205, i.e., on the opposite side from the conductive layers 211a and 211b. For example, when the etching rate of the conductive layer 215 in the X and Y directions is faster than the etching rate of the insulating layer 205 in the X and Y directions, the structure shown in FIG. 17B may be formed. Alternatively, an insulating film to be the insulating layer 205 and a conductive film to be the conductive layer 215 are formed, and the conductive film and the insulating film are processed by, for example, photolithography and etching. Thereafter, the conductive layer 215 is isotropically etched, and the resist mask is then removed, whereby the transistor 200 having the structure shown in FIG. 17B can be formed.

[0174] 17B , an LDD (Lightly Doped Drain) region can be formed in the semiconductor layer 213. Specifically, the LDD region can be formed in a region of the semiconductor layer 213 that overlaps with the insulating layer 205 but does not overlap with the conductive layer 215. Specifically, after forming the insulating layer 205 and the conductive layer 215 over the semiconductor layer 213, an impurity element is introduced into the semiconductor layer 213 using the conductive layer 215 as a mask, thereby forming a low-resistance region and an LDD region having a higher resistance than the low-resistance region in the semiconductor layer 213. As described above, the transistor 200 can be a highly reliable transistor.

[0175] 18A, 18B, and 18C illustrate an example in which the transistor 200 illustrated in FIGS. 1A, 1B, and 1D includes a conductive layer 223 and an insulating layer 227. In addition, FIGS. 18B and 18C illustrate an example in which the insulating layer 203 includes an insulating layer 203a, an insulating layer 203b over the insulating layer 203a, and an insulating layer 203c over the insulating layer 203b.

[0176] 18A to 18C includes a conductive layer 223 and a layer 225 between the insulating layer 203a and the insulating layer 203b. The insulating layer 203a is provided over the conductive layer 211 and the insulating layer 107. The insulating layer 203a can be provided over the insulating layer 107 so as to cover the top surface and side surfaces of the conductive layer 211. The conductive layer 223 is provided over the insulating layer 203a so as to have a region overlapping with the conductive layer 211. The layer 225 is provided on the top surface and side surfaces of the conductive layer 223. Here, the boundary between the conductive layer 223 and the layer 225 may be unclear, and therefore the boundary is indicated by a dashed line in FIGS. 18B and 18C . Note that the layer 225 does not necessarily have to be provided on the top surface and side surfaces of the conductive layer 223.

[0177] The insulating layer 203b is provided over the conductive layer 223, the layer 225, and the insulating layer 203a. The insulating layer 203c is provided over the insulating layer 203b. As described above, the insulating layer 203c is provided over the conductive layer 223, the layer 225, and the insulating layer 203a.

[0178] The insulating layer 203a, the layer 225, the conductive layer 223, the insulating layer 203b, the insulating layer 203c, and the conductive layer 212 have an opening 221 that reaches the conductive layer 211. The insulating layer 227 is provided inside the opening 221. The insulating layer 227 has a region in contact with the side surface of the insulating layer 203 on the opening 221 side and a region in contact with the side surface of the layer 225 on the opening 221 side. The insulating layer 227 is provided along the side surface of the insulating layer 203 inside the opening 221, and therefore can be referred to as a sidewall or sidewall insulating layer. Furthermore, the insulating layer 227 has a region in contact with the top surface of the conductive layer 211 inside the opening 221. The semiconductor layer 213 has a region in contact with the top surface of the conductive layer 211 inside the opening 221 and a region in contact with the side surface of the insulating layer 227. The insulating layer 227 is located between the conductive layer 223 and the layer 225 and the semiconducting layer 213 , and the conductive layer 223 and the semiconducting layer 213 are electrically insulated from each other by the insulating layer 227 .

[0179] 18A to 18C , the semiconductor layer 213 and the conductive layer 223 are provided to have regions that face each other with the insulating layer 227 sandwiched therebetween. Similarly to the transistor 200 illustrated in, for example, FIGS. 1A , 1B , and 1D , the semiconductor layer 213 and the conductive layer 215 are provided to have regions that face each other with the insulating layer 205 sandwiched therebetween. Furthermore, in the transistor 200 illustrated in FIGS. 18A to 18C , the conductive layer 215 and the conductive layer 223 are provided inside the opening 221 to have regions that face each other with the insulating layer 205, the semiconductor layer 213, and the insulating layer 227 sandwiched therebetween, in this order from the side closest to the conductive layer 215.

[0180] 18A to 18C , the conductive layer 215 functions as a gate electrode (also referred to as a first gate electrode). The insulating layer 205 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 223 functions as a back gate electrode (also referred to as a second gate electrode). The insulating layer 227 functions as a back gate insulating layer (also referred to as a second gate insulating layer). Note that the names of the conductive layer 215 and the conductive layer 223 may be interchanged, and the names of the insulating layer 205 and the insulating layer 227 may be interchanged.

[0181] The conductive layer 223 in the transistor 200 can fix the potential on the back channel side of the semiconductor layer 213, thereby preventing a shift in the threshold voltage. As described above, a negative shift in the threshold voltage of the transistor 200 can increase the cutoff current. By preventing a negative shift in the threshold voltage of the transistor 200, the transistor can have a small cutoff current.

[0182] The conductive layer 223 can be connected to the conductive layer 211. For example, an opening can be provided in a region of the insulating layer 203a that overlaps with the conductive layer 211, and the conductive layer 223 can be provided to cover the opening, thereby making the conductive layer 223 and the conductive layer 211 in contact with each other. The conductive layer 211 that functions as a source or drain electrode and the conductive layer 223 that functions as a back gate electrode are connected, so that the source or drain electrode and the back gate electrode can have the same potential. For example, when the conductive layer 211 functions as a source electrode, a shift in the threshold voltage of the transistor 200 shown in FIGS. 18A to 18C can be suppressed. Furthermore, the reliability of the transistor 200 shown in FIGS. 18A to 18C can be improved. Note that the conductive layer 223 can also be formed in contact with the top surface of the conductive layer 211 without providing the insulating layer 203a.

[0183] The conductive layer 223 can be connected to the conductive layer 215. For example, openings can be provided in regions of the insulating layer 203b, the insulating layer 203c, and the insulating layer 205 that overlap with the conductive layer 223, and the conductive layer 215 can be provided to cover the openings, thereby making it possible to have a structure in which the conductive layer 223 and the conductive layer 215 are in contact with each other. The conductive layer 215 that functions as a gate electrode and the conductive layer 223 that functions as a back gate electrode are connected to each other, so that the back gate electrode and the gate electrode can have the same potential. Therefore, the on-state current of the transistor 200 shown in FIGS. 18A to 18C can be increased.

[0184] 18A to 18C may not include the insulating layer 205 and the conductive layer 215. That is, the transistor 200 may be a single-gate transistor using the conductive layer 223 as a gate electrode and the insulating layer 227 as a gate insulating layer.

[0185] Here, the insulating layer 203b and the insulating layer 227 are preferably insulating layers containing oxygen. Furthermore, they are preferably insulating layers that release oxygen by heating. As a result, for example, when a metal oxide is used for the semiconductor layer 213, oxygen contained in the insulating layer 227 can be supplied to the metal oxide. Alternatively, oxygen contained in the insulating layer 203b can be supplied to the metal oxide through the insulating layer 227. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistor 200 shown in FIGS. 18A to 18C . That is, in the transistor 200 shown in FIGS. 18A to 18C , the insulating layer 227 functions as a second gate insulating layer and also has a function of supplying oxygen to the semiconductor layer 213 (mainly the channel formation region). On the other hand, the insulating layer 203a and the insulating layer 203c are preferably insulating layers that have a blocking property against oxygen, hydrogen, and the like, as described above.

[0186] The layer 225 is preferably an insulating layer made of an oxide of an element contained in the conductive layer 223. The material of the conductive layer 223 is preferably a conductive material that is easily oxidized. Thus, for example, the layer 225 can be formed in contact with the side and top surfaces of the conductive layer 223 by performing plasma treatment or the like on the surface of the conductive layer 223 in an oxygen atmosphere. Note that the layer 225 may also be an insulating layer made of a nitride of an element contained in the conductive layer 223.

[0187] The layer 225 is preferably an insulating layer having blocking properties against oxygen, hydrogen, and the like, similar to the insulating layers 203a and 203c. This can prevent oxygen released from the insulating layers 227 and 203b from diffusing to the conductive layer 223 side through the layer 225. Therefore, it is possible to prevent the conductive layer 223 from being oxidized by oxygen released from the insulating layers 227 and 203b, and to prevent the electrical resistance of the conductive layer 223 from increasing. Furthermore, by increasing the amount of oxygen supplied from the insulating layer 203b to the insulating layer 227, it is possible to increase the amount of oxygen supplied to the channel formation region of the semiconductor layer 213. Therefore, oxygen vacancies (V Ｏ : Oxygen Vacancy) and defects in which hydrogen enters an oxygen vacancy (hereinafter referred to as V Ｏ Furthermore, by providing the above-described configuration, an insulating layer having the same function as the insulating layer 203a and the insulating layer 203c can be formed without using a film formation method such as plasma enhanced chemical vapor deposition (PECVD) or a sputtering method, which may reduce the number of times the above-described film formation method is applied and increase productivity.

[0188] The treatment for oxidizing the conductive layer 223 (hereinafter also referred to as oxidation treatment) or nitriding the conductive layer 223 (hereinafter also referred to as nitriding treatment) can be, for example, plasma treatment. The atmosphere during the oxidation treatment preferably contains oxygen. For example, the atmosphere may contain oxygen (O ２ ), nitrous oxide (N ２ O), nitrogen dioxide (NO ２ An atmosphere containing one or more of nitrogen (N), carbon monoxide, and carbon dioxide can be suitably used. The atmosphere used in the nitriding treatment preferably contains nitrogen. ２ ) can be suitably used.

[0189] For example, after forming the layer that will become the conductive layer 223 and before forming the film that will become the insulating layer 203b, the conductive layer 223 is subjected to oxidation treatment or nitriding treatment to form an oxide or nitride on the surface of the layer that will become the conductive layer 223. Furthermore, after forming the opening 221 and before forming the insulating layer 227, the conductive layer 223 is subjected to oxidation treatment or nitriding treatment to form an oxide or nitride on the surface of the conductive layer 223 that faces the opening 221. As a result, a layer 225 can be formed on the top surface and side surface of the conductive layer 223.

[0190] 18A to 18C can be applied to, for example, the transistor 200 shown in any of the transistors other than those shown in FIGS. 1A, 1B, and 1D. For example, the transistor 200 shown in FIGS. 5A to 12B may include the conductive layer 223, the layer 225, and the insulating layer 227.

[0191] 1A, 1B, and 1C each illustrate an example in which the transistor 100 includes a conductive layer 114 and an insulating layer 104. The transistor 100 illustrated in FIGS. 1A to 19C includes the conductive layer 114 between the insulating layer 102 and the semiconductor layer 113 and the insulating layer 104 over the conductive layer 114.

[0192] 19A to 19C , the conductive layer 115 functions as a gate electrode (also referred to as a first gate electrode). The insulating layer 105 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 114 functions as a back gate electrode (also referred to as a second gate electrode). The insulating layer 104 functions as a back gate insulating layer (also referred to as a second gate insulating layer). Note that the names of the conductive layer 115 and the conductive layer 114 may be interchanged, and the names of the insulating layer 105 and the insulating layer 104 may be interchanged.

[0193] Since the transistor 100 includes the conductive layer 114, the region 113i functioning as a channel formation region of the transistor 100 can be sandwiched between the gate electrode and the back gate electrode of the transistor 100. The threshold voltage of the transistor 100 can be changed by changing the potential of the back gate electrode. The potential of the back gate electrode may be ground potential or any other potential.

[0194] The back gate electrode can function similarly to the gate electrode. Here, for example, the conductive layer 114 may have the same potential as the conductive layer 115. For example, the conductive layer 114 may be connected to the conductive layer 115. In this manner, the on-state current of the transistor 100 shown in FIGS. 19A to 19C can be increased.

[0195] The conductive layers 114 and 115 have a function of preventing an electric field generated outside the transistor 100 from acting on the region 113i, which is a channel formation region (particularly, a function of shielding an electric field against static electricity). That is, the electrical characteristics of the transistor 100 can be prevented from fluctuating due to the influence of an external electric field such as static electricity. Furthermore, by providing a backgate electrode in the transistor 100, the amount of change in the threshold voltage of the transistor 100 before and after a bias temperature (BT) stress test can be reduced. By providing a backgate electrode in the transistor 100, variation in the electrical characteristics of the transistor 100 can be reduced, and the reliability of the semiconductor device can be improved.

[0196] The conductive layer 114 can be formed using, for example, a material that can be used for the conductive layer 115. The insulating layer 104 can be formed using, for example, a material that can be used for the insulating layer 105.

[0197] 19A to 19C can be applied to, for example, the transistor 100 shown in any of the transistors other than those shown in FIGS. 1A, 1B, and 1C. For example, the transistor 100 shown in FIGS. 5A to 18B may include the conductive layer 114 and the insulating layer 104.

[0198] <Configuration Example 3 of Semiconductor Device> A semiconductor device having a different configuration from the above-described semiconductor device 10 will be described below. Specifically, a configuration example of a semiconductor device having a capacitance in addition to the transistor 100 and the transistor 200 will be described. This semiconductor device is referred to as semiconductor device 10A.

[0199] [Configuration Example 3-1] Fig. 20A is a plan view showing a configuration example of a semiconductor device 10A. Fig. 20B is a cross-sectional view taken along dashed dotted line A5-A6 shown in Fig. 20A. The semiconductor device 10A shown in Fig. 20A and Fig. 20B has a capacitor 130A in addition to the transistor 100 and transistor 200 shown in Fig. 1A and Fig. 1B. The cross section taken along dashed dotted line A5-A6 includes a cross section of the transistor 100, a cross section of the transistor 200, and a cross section of the capacitor 130A.

[0200] The capacitor 130A has a conductive layer 133, an insulating layer 105 on the conductive layer 133, and a conductive layer 135 on the insulating layer 105. The conductive layer 133 functions as one electrode of the capacitor 130A. The conductive layer 135 functions as the other electrode of the capacitor 130A. The insulating layer 105 functions as a dielectric of the capacitor 130A.

[0201] The conductive layer 133 is provided over the insulating layer 102. The conductive layer 133 may have a region in contact with the top surface of the insulating layer 102. Here, the semiconductor layer 113 and the conductive layer 133 may both have a region in contact with the top surface of the insulating layer 102. Therefore, the semiconductor layer 113 and the conductive layer 133 are provided on the same formation surface. The semiconductor layer 113 and the conductive layer 133 can be formed by processing the same semiconductor film, for example. Therefore, the conductive layer 133 can have the same material as the semiconductor layer 113.

[0202] The insulating layer 105 is provided over the semiconductor layer 113, the insulating layer 102, and the conductive layer 133. The insulating layer 105 can be provided over the insulating layer 102 so as to cover the top and side surfaces of the semiconductor layer 113 and the conductive layer 133. Note that the insulating layer provided over the conductive layer 133 may be different from the insulating layer provided over the semiconductor layer 113. That is, the insulating layer that functions as the gate insulating layer of the transistor 100 and the insulating layer that functions as the dielectric of the capacitor 130A may be different. For example, when the insulating layer 105 is processed as shown in FIGS. 6A and 6B , the insulating layer that functions as the gate insulating layer of the transistor 100 and the insulating layer that functions as the dielectric of the capacitor 130A can be different.

[0203] The conductive layer 135 is provided over the insulating layer 105 to have a region overlapping with the conductive layer 133. The conductive layer 135 can have a region in contact with the top surface of the insulating layer 105. Here, the conductive layer 115 and the conductive layer 135 both have a region in contact with the top surface of the insulating layer 105. Therefore, the conductive layer 115 and the conductive layer 135 are provided on the same surface where they are to be formed. The conductive layer 115 and the conductive layer 135 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 135 can have the same material as the conductive layer 115.

[0204] The insulating layer 107 is provided over the conductive layer 115, the insulating layer 105, and also over the conductive layer 135. The insulating layer 107 can be provided over the insulating layer 105 so as to cover the top surface and side surface of the conductive layer 115 and the top surface and side surface of the conductive layer 135.

[0205] The insulating layer 105, the insulating layer 107, and the insulating layer 203 have openings 121a and 121b that reach the semiconductor layer 113, as well as an opening 141 that reaches the conductive layer 133. The insulating layer 107 and the insulating layer 203 have openings 122 that reach the conductive layer 115, as well as an opening 142 that reaches the conductive layer 135.

[0206] The opening 141 includes an opening in the insulating layer 105, an opening in the insulating layer 107, and an opening in the insulating layer 203. The opening 142 includes an opening in the insulating layer 107 and an opening in the insulating layer 203.

[0207] The semiconductor device 10A shown in FIGS. 20A and 20B includes a conductive layer 131 and a conductive layer 136. The conductive layer 131 has a region located inside an opening 141. The conductive layer 131 has a region in contact with the top surface of the conductive layer 133 and a region in contact with the top surface of the insulating layer 203. The conductive layer 136 has a region located inside an opening 142. The conductive layer 136 has a region in contact with the top surface of the conductive layer 135 and a region in contact with the top surface of the insulating layer 203. The conductive layer 131 may or may not be included in one electrode of the capacitor 130A. The conductive layer 136 may or may not be included in the other electrode of the capacitor 130A.

[0208] 20A and 20B , the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 131, and the conductive layer 136 all have a region in contact with the top surface of the insulating layer 203. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 131, and the conductive layer 136 are provided on the same formation surface. The conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 131, and the conductive layer 136 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 131, and the conductive layer 136 can have the same material as the conductive layer 212.

[0209] By providing the conductive layers 111a, 111b, 116, 212, 131, and 136 on the same formation surface, the number of manufacturing steps for the semiconductor device 10A can be reduced compared to when at least one of these conductive layers is provided on a different formation surface from the other conductive layers. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be a low-cost semiconductor device. Note that at least one of the conductive layers 111a, 111b, 116, 131, and 136 may be provided on a different formation surface from the other conductive layers. In this case, the degree of freedom in the layout of the semiconductor device 10A can be increased and the area occupied by the semiconductor device 10A can be reduced compared to when all of these conductive layers are provided on the same formation surface.

[0210] The conductive layer 131 can have a region in contact with a side surface of the insulating layer 105, a region in contact with a side surface of the insulating layer 107, and a region in contact with a side surface of the insulating layer 203 inside the opening 141. The conductive layer 136 can have a region in contact with a side surface of the insulating layer 107 and a region in contact with a side surface of the insulating layer 203 inside the opening 142.

[0211] The electrical resistivity of the conductive layer 133 can be lower than that of the region 113i of the semiconductor layer 113 and can be approximately the same as that of the regions 113na and 113nb. That is, the conductive layer 133 can be a semiconductor layer with reduced resistance, similar to the regions 113na and 113nb. As described above, the region 113i overlaps with the conductive layer 115 that functions as the gate electrode of the transistor 100. Therefore, the electrical resistivity of the conductive layer 133 is lower than that of at least a part of the region of the semiconductor layer 113 that overlaps with the conductive layer 115.

[0212] The resistance of the semiconductor layer that becomes the conductive layer 133 can be reduced in the same process as that for forming the regions 113na and 113nb. For example, impurity elements can be introduced into the semiconductor layer that becomes the conductive layer 133 in the same process as that for introducing impurity elements into the semiconductor layer 113. In this case, the conductive layer 133 contains the same impurities as those contained in the regions 113na and 113nb of the semiconductor layer 113.

[0213] For example, a resist mask is formed by photolithography after the semiconductor layer 113 and the semiconductor layer that will become the conductive layer 133 are formed and before the conductive layer 115 and the conductive layer 135 are formed. Specifically, the resist mask can be formed after the insulating layer 105 is formed and before the conductive layer 115 and the conductive layer 135 are formed. Then, an impurity element is introduced into the semiconductor layer 113 and the semiconductor layer that will become the conductive layer 133. This allows the formation of the regions 113na and 113nb in the semiconductor layer 113 and the formation of the conductive layer 133 to be performed in the same process. Note that a region of the semiconductor layer 113 into which the impurity element is not introduced can be the region 113i. Then, the resist mask is removed.

[0214] The resistance of the semiconductor layer that becomes the conductive layer 133 may be reduced in a process different from that for forming the regions 113na and 113nb. For example, after the semiconductor layer 113 and the semiconductor layer that becomes the conductive layer 133 are formed and before the conductive layers 115 and 135 are formed, an impurity element is introduced into the semiconductor layer that becomes the conductive layer 133. In this manner, the conductive layer 133 is formed. Subsequently, the conductive layer 115 and the conductive layer 135 are formed. After that, the impurity element is introduced into the semiconductor layer 113 using the conductive layer 115 as a mask, thereby forming the regions 113na and 113nb in the semiconductor layer 113.

[0215] As described above, the conductive layer 133 is provided on the same surface as the semiconductor layer 113. The semiconductor layer 113 can be made of, for example, silicon. Thus, the conductive layer 133 can also be made of, for example, silicon.

[0216] 20A shows an example in which the shapes of openings 141 and 142 are rectangular with rounded corners in a plan view. Note that the shapes of openings 141 and 142 in a plan view are not limited to the shapes shown in FIG. 20A and can be any shape that at least one of openings 121a, 121b, and 122 can have. Note that, in the plan views showing configuration examples of semiconductor device 10A shown below, an example is shown in which the shape of an opening in a plan view, in which a conductive layer connected to an electrode of capacitor 130A is provided, is rectangular with rounded corners in a plan view, but this is not limiting and the shape can be any shape that at least one of openings 121a, 121b, and 122 can have.

[0217] [Configuration Example 3-2] FIG. 21 is a diagram illustrating an example in which a conductive layer 115 is used as the other electrode of the capacitor 130A illustrated in FIG. 20A instead of the conductive layer 135. That is, in the semiconductor device 10A illustrated in FIG. 21 , the gate electrode of the transistor 100 and the other electrode of the capacitor 130A are formed in the same conductive layer. Here, for a cross-sectional configuration example taken along the dashed dotted line A5-A6 illustrated in FIG. 21 , the conductive layer 135 is replaced with the conductive layer 115, and FIG. 20B can be referred to. In the semiconductor device 10A illustrated in FIG. 21 , the other electrode of the capacitor 130A is connected to the gate electrode of the transistor 100. Note that in the semiconductor device 10A described below, by replacing the conductive layer 135 of the capacitor with the conductive layer 115, one or the other of the pair of electrodes of the capacitor can be connected to the gate electrode of the transistor 100.

[0218] 22A and 22B illustrate an example in which the conductive layer 211 functioning as the lower electrode of the transistor 200 in the semiconductor device 10A illustrated in FIGS. 20A and 20B is provided on the same formation surface as the conductive layer 115 functioning as the gate electrode of the transistor 100 and the conductive layer 135 functioning as the other electrode of the capacitor 130A. The description of the semiconductor device 10 illustrated in FIGS. 7A and 7C can be referred to for the description of the semiconductor device 10A illustrated in FIGS. 22A and 22B.

[0219] [Configuration Example 3-4] Fig. 23A is a plan view showing a configuration example of a semiconductor device 10A. Fig. 23B is a cross-sectional view taken along dashed dotted line A5-A6 shown in Fig. 23A. The semiconductor device 10A shown in Fig. 23A and Fig. 23B has a capacitor 130B in addition to the transistor 100 and transistor 200 shown in Fig. 1A and Fig. 1B. The cross section taken along dashed dotted line A5-A6 includes a cross section of the transistor 100, a cross section of the transistor 200, and a cross section of the capacitor 130B.

[0220] The capacitor 130B includes a conductive layer 135, an insulating layer 107 on the conductive layer 135, and a conductive layer 181 on the insulating layer 107. The conductive layer 135 functions as one electrode of the capacitor 130B. The conductive layer 181 functions as the other electrode of the capacitor 130B. The insulating layer 107 functions as a dielectric of the capacitor 130B. In the capacitor 130B, the insulating layer 107 can be made of a material that can be used for the insulating layer 105 because the insulating layer 107 functions as a dielectric of the capacitor 130B. In addition, the insulating layer 107 can be made of a material that can be used for the insulating layer 205.

[0221] In the capacitor 130B, the conductive layer 135 is provided over the insulating layer 105. The conductive layer 181 is provided over the insulating layer 107 so as to have a region overlapping with the conductive layer 135. The conductive layer 181 can have a region in contact with the top surface of the insulating layer 107. Here, the conductive layer 211 and the conductive layer 181 both have a region in contact with the top surface of the insulating layer 107. Therefore, the conductive layer 211 and the conductive layer 181 are provided on the same formation surface. The conductive layer 211 and the conductive layer 181 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 181 can have the same material as the conductive layer 211.

[0222] The insulating layer 203 is provided over the conductive layer 211, the insulating layer 107, and the conductive layer 181. The insulating layer 203 can have a region in contact with the top surface of the conductive layer 211, a region in contact with the side surface of the conductive layer 211, a region in contact with the top surface of the insulating layer 107, a region in contact with the top surface of the conductive layer 181, and a region in contact with the side surface of the conductive layer 181.

[0223] The insulating layer 107 and the insulating layer 203 have an opening 142 that reaches the conductive layer 135. The insulating layer 203 has an opening 143 that reaches the conductive layer 181. The semiconductor device 10A shown in FIGS.

[0224] As described above, the conductive layer 136 has a region located inside the opening 142, a region in contact with the top surface of the conductive layer 135, and a region in contact with the top surface of the insulating layer 203. The conductive layer 137 has a region located inside the opening 143. The conductive layer 137 has a region in contact with the top surface of the conductive layer 181 and a region in contact with the top surface of the insulating layer 203. The conductive layer 136 may or may not be included in one electrode of the capacitor 130B. The conductive layer 137 may or may not be included in the other electrode of the capacitor 130B.

[0225] 23A and 23B , the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 136, and the conductive layer 137 all have a region in contact with the top surface of the insulating layer 203. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 136, and the conductive layer 137 are provided on the same formation surface. The conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 136, and the conductive layer 137 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 136, and the conductive layer 137 can have the same material as the conductive layer 212.

[0226] By providing the conductive layers 111a, 111b, 116, 212, 136, and 137 on the same formation surface, the number of manufacturing steps for the semiconductor device 10A can be reduced compared to when at least one of these conductive layers is provided on a different formation surface from the other conductive layers. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be a low-cost semiconductor device. Note that at least one of the conductive layers 111a, 111b, 116, 136, and 137 may be provided on a different formation surface from the other conductive layers. In this case, the degree of freedom in the layout of the semiconductor device 10A can be increased and the area occupied by the semiconductor device 10A can be reduced compared to when all of these conductive layers are provided on the same formation surface.

[0227] The conductive layer 137 may have a region in contact with the side surface of the insulating layer 203 inside the opening 143 .

[0228] [Configuration Example 3-5] Fig. 24A is a plan view showing a configuration example of a semiconductor device 10A. Fig. 24B is a cross-sectional view taken along dashed dotted line A5-A6 shown in Fig. 24A. The semiconductor device 10A shown in Fig. 24A and Fig. 24B has a capacitor 130C in addition to the transistor 100 and transistor 200 shown in Fig. 1A and Fig. 1B. The cross section taken along dashed dotted line A5-A6 includes a cross section of the transistor 100, a cross section of the transistor 200, and a cross section of the capacitor 130C.

[0229] The capacitor 130C has a conductive layer 135, an insulating layer 106 on the conductive layer 135, and a conductive layer 191 on the insulating layer 106. The conductive layer 135 functions as one electrode of the capacitor 130C. The conductive layer 191 functions as the other electrode of the capacitor 130C. The insulating layer 106 functions as a dielectric of the capacitor 130C.

[0230] The insulating layer 106 is provided over the conductive layer 115, the conductive layer 135, and the insulating layer 105. The insulating layer 106 can be provided over the insulating layer 105 so as to cover the top surface of the conductive layer 115, the side surfaces of the conductive layer 115, the top surface of the conductive layer 135, and the side surfaces of the conductive layer 135.

[0231] The conductive layer 191 is provided over the insulating layer 106 to have a region overlapping with the conductive layer 135. The conductive layer 191 can have a region in contact with the top surface of the insulating layer 106.

[0232] The insulating layer 107 is provided over the conductive layer 191 and the insulating layer 106. The insulating layer 107 can be provided over the insulating layer 106 so as to cover the top surface and side surfaces of the conductive layer 191.

[0233] The insulating layer 105, the insulating layer 106, the insulating layer 107, and the insulating layer 203 have openings 121a and 121b that reach the semiconductor layer 113. The insulating layer 106, the insulating layer 107, and the insulating layer 203 have openings 122 that reach the conductive layer 115 and openings 142 that reach the conductive layer 135. The insulating layer 107 and the insulating layer 203 have openings 145 that reach the conductive layer 191.

[0234] Opening 121a includes an opening in insulating layer 105, an opening in insulating layer 106, an opening in insulating layer 107, and an opening in insulating layer 203. Similarly, opening 121b includes an opening in insulating layer 105, an opening in insulating layer 106, an opening in insulating layer 107, and an opening in insulating layer 203. Opening 122 includes an opening in insulating layer 106, an opening in insulating layer 107, and an opening in insulating layer 203. Similarly, opening 142 includes an opening in insulating layer 106, an opening in insulating layer 107, and an opening in insulating layer 203. Opening 145 includes an opening in insulating layer 107 and an opening in insulating layer 203.

[0235] 24A and 24B includes a conductive layer 136 and a conductive layer 192. As described above, the conductive layer 136 has a region located inside the opening 142, a region in contact with the upper surface of the conductive layer 135, and a region in contact with the upper surface of the insulating layer 203. The conductive layer 192 has a region located inside the opening 145. The conductive layer 192 has a region in contact with the upper surface of the conductive layer 191 and a region in contact with the upper surface of the insulating layer 203. The conductive layer 136 may or may not be included in one electrode of the capacitor 130C. The conductive layer 192 may or may not be included in the other electrode of the capacitor 130C.

[0236] 24A and 24B , the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 136, and the conductive layer 192 all have a region in contact with the top surface of the insulating layer 203. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 136, and the conductive layer 192 are provided on the same formation surface. The conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 136, and the conductive layer 192 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 136, and the conductive layer 192 can have the same material as the conductive layer 212.

[0237] By providing the conductive layers 111a, 111b, 116, 212, 136, and 192 on the same formation surface, the number of manufacturing steps for the semiconductor device 10A can be reduced compared to when at least one of these conductive layers is provided on a different formation surface from the other conductive layers. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be a low-cost semiconductor device. Note that at least one of the conductive layers 111a, 111b, 116, 136, and 192 may be provided on a different formation surface from the other conductive layers. In this case, the degree of freedom in the layout of the semiconductor device 10A can be increased and the area occupied by the semiconductor device 10A can be reduced compared to when all of these conductive layers are provided on the same formation surface.

[0238] The conductive layer 192 can have a region in contact with the side surface of the insulating layer 107 and a region in contact with the side surface of the insulating layer 203 inside the opening 145 .

[0239] The conductive layer 191 can be formed using a material that can be used for at least one of the conductive layers 115, 211, 212, and 215. The insulating layer 106 can be formed using a material that can be used for the insulating layer 105.

[0240] [Configuration Example 3-6] Fig. 25A is a plan view showing a configuration example of a semiconductor device 10A. Fig. 25B is a cross-sectional view taken along dashed dotted line A5-A6 shown in Fig. 25A. The semiconductor device 10A shown in Fig. 25A and Fig. 25B has a capacitor 130D in addition to the transistor 100 and transistor 200 shown in Fig. 1A and Fig. 1B. The cross section taken along dashed dotted line A5-A6 includes a cross section of the transistor 100, a cross section of the transistor 200, and a cross section of the capacitor 130D.

[0241] The capacitor 130D has a conductive layer 133, an insulating layer 105 on the conductive layer 133, a conductive layer 135 on the insulating layer 105, an insulating layer 106 on the conductive layer 135, and a conductive layer 191 on the insulating layer 106. The conductive layer 133 and the conductive layer 191 function as one electrode of the capacitor 130D. The conductive layer 135 functions as the other electrode of the capacitor 130D. The insulating layer 105 and the insulating layer 106 function as a dielectric of the capacitor 130D.

[0242] 24B , the capacitor 130D has a configuration in which the conductive layer 133 of the capacitor 130A is provided below the insulating layer 105. The conductive layer 133, the insulating layer 105, the conductive layer 135, the insulating layer 106, and the conductive layer 191 have overlapping regions.

[0243] The insulating layers 105, 106, 107, and 203 have openings 141 that reach the conductive layer 133. The insulating layers 107 and 203 have openings 145 that reach the conductive layer 191. The openings 141 include an opening in the insulating layer 105, an opening in the insulating layer 106, an opening in the insulating layer 107, and an opening in the insulating layer 203. The openings 145 include an opening in the insulating layer 107 and an opening in the insulating layer 203.

[0244] The semiconductor device 10A shown in FIGS. 25A and 25B includes a conductive layer 193. The conductive layer 193 has a region located inside the opening 141 and a region located inside the opening 145. The conductive layer 193 has a region in contact with the upper surface of the conductive layer 133, a region in contact with the upper surface of the conductive layer 191, and a region in contact with the upper surface of the insulating layer 203. This allows the conductive layer 133 and the conductive layer 191 to be connected via the conductive layer 193. Therefore, both the conductive layer 133 and the conductive layer 191 can function as one electrode of the capacitor 130D. Note that the conductive layer 193 may or may not be included in one electrode of the capacitor 130D.

[0245] In the capacitor 130D, both the upper and lower surfaces of the other electrode of the capacitor 130D face one of the electrodes of the capacitor 130D. Therefore, the capacitance value of the capacitor 130D can be made larger than, for example, the capacitors 130A, 130B, and 130C. On the other hand, the number of manufacturing steps for the capacitors 130A, 130B, and 130C can be made smaller than that for the capacitor 130D. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be made into a low-cost semiconductor device.

[0246] 25A and 25B , the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 136, and the conductive layer 193 all have a region in contact with the top surface of the insulating layer 203. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 136, and the conductive layer 193 are provided on the same formation surface. The conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 136, and the conductive layer 193 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 136, and the conductive layer 193 can have the same material as the conductive layer 212.

[0247] By providing the conductive layers 111a, 111b, 116, 212, 136, and 193 on the same formation surface, the number of manufacturing steps for the semiconductor device 10A can be reduced compared to when at least one of these conductive layers is provided on a different formation surface from the other conductive layers. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be a low-cost semiconductor device. Note that at least one of the conductive layers 111a, 111b, 116, 136, and 193 may be provided on a different formation surface from the other conductive layers. In this case, the layout flexibility of the semiconductor device 10A can be increased and the area occupied by the semiconductor device 10A can be reduced compared to when all of these conductive layers are provided on the same formation surface.

[0248] The conductive layer 193 can have, inside the opening 141, a region in contact with the side surface of the insulating layer 105, a region in contact with the side surface of the insulating layer 106, a region in contact with the side surface of the insulating layer 107, and a region in contact with the side surface of the insulating layer 203. Furthermore, the conductive layer 193 can have, inside the opening 145, a region in contact with the side surface of the insulating layer 107 and a region in contact with the side surface of the insulating layer 203.

[0249] [Configuration Example 3-7] Fig. 26A is a plan view showing a configuration example of a semiconductor device 10A. Fig. 26B is a cross-sectional view taken along dashed dotted line A5-A6 shown in Fig. 26A. The semiconductor device 10A shown in Fig. 26A and Fig. 26B has a capacitor 130E in addition to the transistor 100 and transistor 200 shown in Fig. 1A and Fig. 1B. The cross section taken along dashed dotted line A5-A6 includes a cross section of the transistor 100, a cross section of the transistor 200, and a cross section of the capacitor 130E.

[0250] The capacitor 130E has a conductive layer 191, an insulating layer 106 on the conductive layer 191, and a conductive layer 181 on the insulating layer 106. The conductive layer 191 functions as one electrode of the capacitor 130E. The conductive layer 181 functions as the other electrode of the capacitor 130E. The insulating layer 106 functions as a dielectric of the capacitor 130E.

[0251] 26A and 26B , a conductive layer 191 is provided on an insulating layer 107. An insulating layer 106 is provided on the conductive layer 191 and the insulating layer 107. The insulating layer 106 can be provided on the insulating layer 107 so as to cover the top surface and side surfaces of the conductive layer 191.

[0252] The conductive layer 181 is provided on the insulating layer 106 so as to have a region overlapping with the conductive layer 191. The conductive layer 181 can have a region in contact with the top surface of the insulating layer 106. Here, in the semiconductor device 10A shown in FIGS. 26A and 26B , the conductive layer 211 can be provided so as to have a region in contact with the top surface of the insulating layer 106.

[0253] The insulating layer 106 and the insulating layer 203 have openings 145 that reach the conductive layer 191. The openings 145 include an opening in the insulating layer 106 and an opening in the insulating layer 203. The insulating layer 203 has openings 143 that reach the conductive layer 181.

[0254] 26A and 26B includes a conductive layer 192 and a conductive layer 137. As described above, the conductive layer 192 has a region located inside the opening 145, a region in contact with the upper surface of the conductive layer 191, and a region in contact with the upper surface of the insulating layer 203. As described above, the conductive layer 137 has a region located inside the opening 143, a region in contact with the upper surface of the conductive layer 181, and a region in contact with the upper surface of the insulating layer 203. The conductive layer 192 may or may not be included in one electrode of the capacitor 130E. The conductive layer 137 may or may not be included in the other electrode of the capacitor 130E.

[0255] 26A and 26B , the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 137, and the conductive layer 192 all have a region in contact with the top surface of the insulating layer 203. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 137, and the conductive layer 192 are provided on the same formation surface. The conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 137, and the conductive layer 192 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 137, and the conductive layer 192 can have the same material as the conductive layer 212.

[0256] By providing the conductive layers 111a, 111b, 116, 212, 137, and 192 on the same formation surface, the number of manufacturing steps for the semiconductor device 10A can be reduced compared to when at least one of these conductive layers is provided on a different formation surface from the other conductive layers. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be a low-cost semiconductor device. Note that at least one of the conductive layers 111a, 111b, 116, 137, and 192 may be provided on a different formation surface from the other conductive layers. In this case, the degree of freedom in the layout of the semiconductor device 10A can be increased and the area occupied by the semiconductor device 10A can be reduced compared to when all of these conductive layers are provided on the same formation surface.

[0257] The conductive layer 192 can have a region in contact with the side surface of the insulating layer 106 and a region in contact with the side surface of the insulating layer 203 inside the opening 145 .

[0258] 27A and 27B, 28A and 28B, 29A and 29B, 30A and 30B, 31A and 31B, and 32A and 32B are modified examples of the structures shown in FIGS. 20A and 20B, 22A and 22B, 23A and 23B, 24A and 24B, 25A and 25B, and 26A and 26B, respectively, and illustrate an example in which the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 131, the conductive layer 136, the conductive layer 137, the conductive layer 192, and the conductive layer 193 are provided on the same formation surface as the conductive layer 215 that functions as the gate electrode of the transistor 200. 27A to 32B , the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 131, the conductive layer 136, the conductive layer 137, the conductive layer 192, the conductive layer 193, and the conductive layer 215 all have a region in contact with the top surface of the insulating layer 205. These conductive layers can be formed by processing the same conductive film, for example. Therefore, these conductive layers can have the same material.

[0259] 33A and 33B, 34A and 34B, 35A and 35B, 36A and 36B, and 37A and 37B are modified examples of the structures shown in FIGS. 20A and 20B, 23A and 23B, 24A and 24B, 25A and 25B, and 26A and 26B, respectively, and illustrate an example in which the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 131, the conductive layer 136, the conductive layer 192, and the conductive layer 193 are provided on the same formation surface as the conductive layer 211 that functions as one of the source electrode and the drain electrode of the transistor 200. 33A to 36B , the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 131, the conductive layer 136, the conductive layer 181, the conductive layer 192, the conductive layer 193, and the conductive layer 211 all have a region in contact with the top surface of the insulating layer 107. In the example shown in Figures 37A and 37B , the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 181, the conductive layer 192, and the conductive layer 211 all have a region in contact with the top surface of the insulating layer 107.

[0260] 33A to 37B , in the semiconductor device 10A in which a pair of electrodes of a capacitor includes a conductive layer 181 provided on the same formation surface as the conductive layer 211, an opening 143 reaching the conductive layer 181 is not provided in, for example, the insulating layer 203. Also, the semiconductor device 10A does not include a conductive layer 137 having a region in contact with the upper surface of the conductive layer 181. Specifically, in the semiconductor device 10A having the capacitor 130B and the semiconductor device 10A having the capacitor 130E, for example, the opening 143 is not provided in the insulating layer 203, and the conductive layer 137 is not provided in the semiconductor device 10A.

[0261] The conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 131, the conductive layer 136, the conductive layer 181, the conductive layer 192, the conductive layer 193, and the conductive layer 211 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 131, the conductive layer 136, the conductive layer 181, the conductive layer 192, and the conductive layer 193 can have the same material as the conductive layer 211.

[0262] [Configuration Example 3-10] Fig. 38A is a plan view showing a configuration example of a semiconductor device 10A. Fig. 38B is a cross-sectional view taken along dashed dotted line A5-A6 shown in Fig. 38A. The semiconductor device 10A shown in Fig. 38A and Fig. 38B has a capacitor 130F in addition to the transistor 100 and transistor 200 shown in Fig. 18A and Fig. 18B. The cross section taken along dashed dotted line A5-A6 includes a cross section of the transistor 100, a cross section of the transistor 200, and a cross section of the capacitor 130F.

[0263] 38A and 38B includes a conductive layer 223 that functions as a back gate electrode of the transistor 200 and an insulating layer 227 that functions as a back gate insulating layer of the transistor 200. In addition, in an example shown in Figures 38A and 38B, the insulating layer 203 has a three-layer stacked structure of an insulating layer 203a, an insulating layer 203b over the insulating layer 203a, and an insulating layer 203c over the insulating layer 203b.

[0264] The capacitor 130F has a conductive layer 181, an insulating layer 203a on the conductive layer 181, and a conductive layer 183 on the insulating layer 203a. The conductive layer 181 functions as one electrode of the capacitor 130F. The conductive layer 183 functions as the other electrode of the capacitor 130F. The insulating layer 203a functions as a dielectric of the capacitor 130F.

[0265] The conductive layer 181 is provided on the insulating layer 107. The conductive layer 181 has a region in contact with the upper surface of the insulating layer 107. Here, the conductive layer 211 and the conductive layer 181 both have a region in contact with the upper surface of the insulating layer 107. Therefore, similar to the semiconductor device 10A described above, the conductive layer 181 is provided on the same formation surface as the conductive layer 211.

[0266] The insulating layer 203a is provided over the conductive layer 211, the insulating layer 107, and also over the conductive layer 181. The insulating layer 203a can be provided over the insulating layer 107 so as to cover the top surface and side surface of the conductive layer 211 and the top surface and side surface of the conductive layer 181.

[0267] The conductive layer 183 is provided over the insulating layer 203a so as to have a region overlapping with the conductive layer 181. The conductive layer 183 can have a region in contact with the top surface of the insulating layer 203a. Here, the conductive layer 223 and the conductive layer 183 both have a region in contact with the top surface of the insulating layer 203a. Therefore, the conductive layer 223 and the conductive layer 183 are provided on the same formation surface. The conductive layer 223 and the conductive layer 183 can be formed, for example, by processing the same conductive film. Therefore, the conductive layer 183 can be made of the same material as the conductive layer 223. Figure 38B shows an example in which a layer 185 is provided on the top surface and side surface of the conductive layer 183. The layer 185 can be formed in the same process as the layer 225. Note that the layer 185 does not necessarily have to be provided on the top surface and side surface of the conductive layer 183. For example, when the layer 225 is not provided on the top surface and side surface of the conductive layer 223 , the layer 185 may not be provided on the top surface and side surface of the conductive layer 183 .

[0268] The insulating layer 203b is provided over the conductive layer 223, the layer 225, and the insulating layer 203a, as well as over the conductive layer 183 and the layer 185. The insulating layer 203c is provided over the insulating layer 203b. As described above, the insulating layer 203c is provided over the conductive layer 223, the layer 225, and the insulating layer 203a, as well as over the conductive layer 183 and the layer 185.

[0269] The insulating layers 203a, 203b, and 203c have openings 143 that reach the conductive layer 181. The layer 185, the insulating layers 203b, and 203c have openings 144 that reach the conductive layer 183.

[0270] The opening 143 includes an opening in the insulating layer 203 a, an opening in the insulating layer 203 b, and an opening in the insulating layer 203 c. The opening 144 includes an opening in the layer 185, an opening in the insulating layer 203 b, and an opening in the insulating layer 203 c.

[0271] The semiconductor device 10A shown in Figures 38A and 38B has a conductive layer 137 and a conductive layer 138. As described above, the conductive layer 137 has a region located inside the opening 143. The conductive layer 137 has a region in contact with the top surface of the conductive layer 181 and a region in contact with the top surface of the insulating layer 203c. The conductive layer 138 has a region in contact with the top surface of the conductive layer 183 and a region in contact with the top surface of the insulating layer 203c. The conductive layer 137 may or may not be included in one electrode of the capacitor 130F. The conductive layer 138 may or may not be included in the other electrode of the capacitor 130F.

[0272] 38B shows an example in which opening 144 reaches conductive layer 183, but opening 144 does not have to reach conductive layer 183 as long as electrical continuity between conductive layer 183 and conductive layer 138 can be ensured. For example, opening 144 may reach layer 185. Alternatively, layer 185 may have a recess in the region overlapping opening 144. In the above cases, conductive layer 138 may be configured to be in contact with layer 185 but not with conductive layer 183. In semiconductor device 10A described below, opening 144 may also be configured not to reach conductive layer 183.

[0273] 38A and 38B , the conductive layers 111a, 111b, 116, 212, 137, and 138 all have regions in contact with the top surface of the insulating layer 203c. Therefore, the conductive layers 111a, 111b, 116, 212, 137, and 138 are provided on the same surface where they are to be formed. The conductive layers 111a, 111b, 116, 212, 137, and 138 can be formed by processing the same conductive film, for example. Therefore, the conductive layers 111a, 111b, 116, 137, and 138 can be made of the same material as the conductive layer 212.

[0274] By providing the conductive layers 111a, 111b, 116, 212, 137, and 138 on the same formation surface, the number of manufacturing steps for the semiconductor device 10A can be reduced compared to when at least one of these conductive layers is provided on a different formation surface from the other conductive layers. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be a low-cost semiconductor device. Note that at least one of the conductive layers 111a, 111b, 116, 137, and 138 may be provided on a different formation surface from the other conductive layers. In this case, the layout flexibility of the semiconductor device 10A can be increased and the area occupied by the semiconductor device 10A can be reduced compared to when all of these conductive layers are provided on the same formation surface.

[0275] The conductive layer 137 can have a region in contact with the side surface of the insulating layer 203a, a region in contact with the side surface of the insulating layer 203b, and a region in contact with the side surface of the insulating layer 203c inside the opening 143. The conductive layer 138 can have a region in contact with the side surface of the layer 185, a region in contact with the side surface of the insulating layer 203b, and a region in contact with the side surface of the insulating layer 203c inside the opening 144.

[0276] [Configuration Example 3-11] Fig. 39A is a plan view showing a configuration example of a semiconductor device 10A. Fig. 39B is a cross-sectional view taken along dashed dotted line A5-A6 shown in Fig. 39A. The semiconductor device 10A shown in Fig. 39A and Fig. 39B has a capacitor 130G in addition to the transistor 100 and transistor 200 shown in Fig. 18A and Fig. 18B. The cross section taken along dashed dotted line A5-A6 includes a cross section of the transistor 100, a cross section of the transistor 200, and a cross section of the capacitor 130G.

[0277] The capacitor 130G includes a conductive layer 133, an insulating layer 105 on the conductive layer 133, a conductive layer 181 on the insulating layer 105, an insulating layer 203a on the conductive layer 181, and a conductive layer 183 on the insulating layer 203a. The conductive layer 133 and the conductive layer 183 function as one electrode of the capacitor 130G. The conductive layer 181 functions as the other electrode of the capacitor 130G. The insulating layer 105 and the insulating layer 203a function as a dielectric of the capacitor 130G.

[0278] 28A and 28B, the semiconductor device 10A shown in Figures 39A and 39B does not include the insulating layer 107. Furthermore, the capacitor 130G can be said to have a configuration in which the conductive layer 133 of the capacitor 130A is provided below the insulating layer 105 shown in Figure 38B, for example. The conductive layer 133, the insulating layer 105, the conductive layer 181, the insulating layer 203a, and the conductive layer 183 have overlapping regions.

[0279] The insulating layer 105, the insulating layer 203a, the insulating layer 203b, and the insulating layer 203c have openings 141 that reach the conductive layer 133. The layer 185, the insulating layer 203b, and the insulating layer 203c have openings 144 that reach the conductive layer 183. The insulating layers 203a, 203b, and 203c have openings 143 that reach the conductive layer 181. The openings 141 include the openings in the insulating layer 105, the openings in the insulating layer 203a, the openings in the insulating layer 203b, and the openings in the insulating layer 203c. The openings 144 include the openings in the layer 185, the openings in the insulating layer 203b, and the openings in the insulating layer 203c. The opening 143 includes an opening in the insulating layer 203a, an opening in the insulating layer 203b, and an opening in the insulating layer 203c.

[0280] The semiconductor device 10A shown in FIGS. 39A and 39B includes a conductive layer 139 and a conductive layer 137. The conductive layer 139 has a region located inside the opening 141 and a region located inside the opening 144. The conductive layer 139 has a region in contact with the top surface of the conductive layer 133, a region in contact with the top surface of the conductive layer 183, and a region in contact with the top surface of the insulating layer 203c. This allows the conductive layer 133 and the conductive layer 183 to be connected via the conductive layer 139. Therefore, both the conductive layer 133 and the conductive layer 183 can function as one electrode of the capacitor 130G. Note that the conductive layer 139 may or may not be included in one electrode of the capacitor 130G.

[0281] In the capacitor 130G, both the upper and lower surfaces of the other electrode of the capacitor 130G face one of the electrodes of the capacitor 130G. Therefore, the capacitance value of the capacitor 130G can be made larger than that of the capacitor 130F, for example. On the other hand, the number of manufacturing steps for the capacitor 130F can be made smaller than that of the capacitor 130G. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be made into a low-cost semiconductor device.

[0282] 39A and 39B , the conductive layers 111a, 111b, 116, 212, 137, and 139 all have regions in contact with the top surface of the insulating layer 203c. Therefore, the conductive layers 111a, 111b, 116, 212, 137, and 139 are provided on the same surface. The conductive layers 111a, 111b, 116, 212, 137, and 139 can be formed by processing the same conductive film, for example. Therefore, the conductive layers 111a, 111b, 116, 137, and 139 can be made of the same material as the conductive layer 212.

[0283] By providing the conductive layers 111a, 111b, 116, 212, 137, and 139 on the same formation surface, the number of manufacturing steps for the semiconductor device 10A can be reduced compared to when at least one of these conductive layers is provided on a different formation surface from the other conductive layers. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be a low-cost semiconductor device. Note that at least one of the conductive layers 111a, 111b, 116, 137, and 139 may be provided on a different formation surface from the other conductive layers. In this case, the layout flexibility of the semiconductor device 10A can be increased and the area occupied by the semiconductor device 10A can be reduced compared to when all of these conductive layers are provided on the same formation surface.

[0284] The conductive layer 139 can have a region in contact with the side surface of the insulating layer 105, a region in contact with the side surface of the insulating layer 203a, a region in contact with the side surface of the insulating layer 203b, and a region in contact with the side surface of the insulating layer 203c inside the opening 141. The conductive layer 139 can have a region in contact with the side surface of the layer 185, a region in contact with the side surface of the insulating layer 203b, and a region in contact with the side surface of the insulating layer 203c inside the opening 144. The conductive layer 137 can have a region in contact with the side surface of the insulating layer 203a, a region in contact with the side surface of the insulating layer 203b, and a region in contact with the side surface of the insulating layer 203c inside the opening 143.

[0285] 40A and 40B and 41A and 41B are modifications of the structures shown in FIGS. 38A and 38B and 39A and 39B, respectively, and illustrate an example in which the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 137, the conductive layer 138, and the conductive layer 139 are provided on the same formation surface as the conductive layer 215 that functions as the gate electrode of the transistor 200. In the examples shown in FIGS. 40A to 41B, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 137, the conductive layer 138, the conductive layer 139, and the conductive layer 215 all have a region in contact with the top surface of the insulating layer 205. These conductive layers can be formed by processing the same conductive film, for example. Therefore, these conductive layers can have the same material.

[0286] [Configuration Example 3-13] Fig. 42A is a plan view showing a configuration example of a semiconductor device 10A. Fig. 42B is a cross-sectional view taken along dashed dotted line A5-A6 shown in Fig. 42A. The semiconductor device 10A shown in Fig. 42A and Fig. 42B includes a capacitor 130H in addition to a transistor 100 and a transistor 200. The cross section taken along dashed dotted line A5-A6 includes a cross section of the transistor 100, a cross section of the transistor 200, and a cross section of the capacitor 130H. The transistor 200 shown in Fig. 42A and Fig. 42B includes a conductive layer 223 functioning as a back gate electrode of the transistor 200 and an insulating layer 227 functioning as a back gate insulating layer of the transistor 200.

[0287] In the semiconductor device 10A shown in Figures 42A and 42B, an insulating layer 203d is provided between insulating layer 203b and insulating layer 203c. That is, Figures 42A and 42B show an example in which insulating layer 203 has a four-layer laminated structure including insulating layer 203a, insulating layer 203b on insulating layer 203a, insulating layer 203d on insulating layer 203b, and insulating layer 203c on insulating layer 203d.

[0288] The conductive layer 223 and the conductive layer 183 are provided between the insulating layer 203d and the insulating layer 203c. A layer 225 is provided on the top surface and side surface of the conductive layer 223, and a layer 185 is provided on the top surface and side surface of the conductive layer 183.

[0289] The insulating layer 203d can be formed using a material that can be used for the insulating layer 203a. By providing the insulating layer 203d between the insulating layer 203b and the conductive layer 183, oxidation of the lower surfaces of the conductive layer 223 and the conductive layer 183 can be prevented, even when the insulating layer 203b contains oxygen, for example. In other words, formation of the layer 225 on the lower surface of the conductive layer 223 and formation of the layer 185 on the lower surface of the conductive layer 183 can be prevented. As a result, an increase in the electrical resistance of the conductive layer 183 can be prevented.

[0290] The capacitor 130H includes a conductive layer 183, an insulating layer 203c on the conductive layer 183, and a conductive layer 187 on the insulating layer 203c. The conductive layer 183 functions as one electrode of the capacitor 130H. The conductive layer 187 functions as the other electrode of the capacitor 130H. The insulating layer 203c functions as a dielectric of the capacitor 130H.

[0291] The conductive layer 223 and the conductive layer 183 are provided on the insulating layer 203d. The upper surfaces of the conductive layer 223 and the conductive layer 183 have regions that are in contact with the upper surface of the insulating layer 203d. Therefore, similar to the semiconductor device 10A shown in FIGS. 38A to 39B , the conductive layer 223 and the conductive layer 183 are provided on the same formation surface.

[0292] The insulating layer 203c is provided over the conductive layer 223, the layer 225, the conductive layer 183, the layer 185, and the insulating layer 203d. The insulating layer 203c can be provided over the insulating layer 203d so as to cover top surfaces of the conductive layer 223 and the layer 225, side surfaces of the conductive layer 223 and the layer 225, top surfaces of the conductive layer 183 and the layer 185, and side surfaces of the conductive layer 183 and the layer 185.

[0293] The layer 185 and the insulating layer 203c have an opening 144 that reaches the conductive layer 183. The semiconductor device 10A shown in FIGS. 42A and 42B also has a conductive layer 138 and a conductive layer 187. As described above, the conductive layer 138 has a region located inside the opening 144. The conductive layer 138 has a region in contact with the top surface of the conductive layer 183 and a region in contact with the top surface of the insulating layer 203c. The conductive layer 138 can also have a region in contact with the side surface of the layer 185 and a region in contact with the side surface of the insulating layer 203c inside the opening 144. The conductive layer 138 may or may not be included in one of the electrodes of the capacitor 130H.

[0294] 42A and 42B , the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 138, and the conductive layer 187 all have regions in contact with the top surface of the insulating layer 203c. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 138, and the conductive layer 187 are provided on the same formation surface. The conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 212, the conductive layer 138, and the conductive layer 187 can be formed by processing the same conductive film, for example. Therefore, the conductive layer 111a, the conductive layer 111b, the conductive layer 116, the conductive layer 138, and the conductive layer 187 can have the same material as the conductive layer 212.

[0295] By providing the conductive layers 111a, 111b, 116, 212, 138, and 187 on the same formation surface, the number of manufacturing steps for the semiconductor device 10A can be reduced compared to when at least one of these conductive layers is provided on a different formation surface from the other conductive layers. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced. As a result, the semiconductor device 10A can be a low-cost semiconductor device. Note that at least one of the conductive layers 111a, 111b, 116, 138, and 187 may be provided on a different formation surface from the other conductive layers. In this case, the degree of freedom in the layout of the semiconductor device 10A can be increased and the area occupied by the semiconductor device 10A can be reduced compared to when all of these conductive layers are provided on the same formation surface.

[0296] The above is a description of the configuration example of the semiconductor device 10A.

[0297] <Components of Semiconductor Device> Components included in the semiconductor device of this embodiment will be described below.

[0298] [Semiconductor Layer 213] As described above, the semiconductor layer 213 includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 213 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. Gallium is more preferred as the element M.

[0299] The semiconductor layer 213 can be formed using, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO), or the like. Alternatively, indium tin oxide containing silicon can be used.

[0300] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0301] As a specific example of forming the semiconductor layer 213 by the ALD method, it is preferable to use a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it not only exhibits high step coverage but also allows low-temperature film formation.

[0302] The composition of the metal oxide in the semiconductor layer 213 greatly affects the electrical characteristics and reliability of the transistor 200 .

[0303] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized. Furthermore, by using a metal oxide that does not contain gallium or has a low content of gallium in the semiconductor layer 213, a transistor with high reliability against application of a positive bias can be realized. Furthermore, by using a metal oxide with a low content of element M in the semiconductor layer 213, a transistor with high reliability against application of a positive bias can be realized. Furthermore, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be realized.

[0304] The composition of the metal oxide contained in the semiconductor layer 213 will be described in detail later.

[0305] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 213. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 213, the defect level density in the semiconductor layer 213 can be reduced, and a highly reliable transistor can be realized. Note that the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have a c-axis orientation and are connected without being oriented in the a-b plane. The CAAC structure allows crystal grain boundaries (grains) to be less clearly visible in the a-b plane than the polycrystalline structure, and therefore a highly reliable transistor can be realized.

[0306] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 213, the more the density of defect states in the semiconductor layer 213 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0307] The semiconductor layer 213 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer 213 may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 213 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the two or more metal oxide layers included in the semiconductor layer 213 may have different compositions.

[0308] The thickness of the semiconductor layer 213 (film thickness relative to the surface on which it is formed) is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, even more preferably 10 nm or more and 100 nm or less, even more preferably 10 nm or more and 70 nm or less, even more preferably 15 nm or more and 70 nm or less, even more preferably 15 nm or more and 50 nm or less, even more preferably 20 nm or more and 50 nm or less, even more preferably 20 nm or more and 40 nm or less, even more preferably 25 nm or more and 40 nm or less.

[0309] Here, oxygen vacancies that can be formed in the semiconductor layer 213 will be described.

[0310] When an oxide semiconductor is used for the semiconductor layer 213, hydrogen contained in the oxide semiconductor reacts with oxygen that is bonded to a metal atom to form water, and oxygen vacancies (V Ｏ Furthermore, defects where hydrogen is introduced into oxygen vacancies (V ＯHydrogen atoms (H) may function as donors and generate electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0311] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0312] From the above, when an oxide semiconductor is used for the semiconductor layer 213, V in the semiconductor layer 213 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen are removed from the oxide semiconductor (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the Ｏ By using an oxide semiconductor in which defects such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0313] When an oxide semiconductor is used for the semiconductor layer 213, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm−３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0314] An OS transistor has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor in a semiconductor device can reduce the power consumption of the semiconductor device.

[0315] The semiconductor layer 213 may include a layered material that functions as a semiconductor. In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0316] In this specification and the like, the layered material may be referred to as a two-dimensional material. Examples of two-dimensional materials that can be used in one embodiment of the present invention include graphene, silicene (a material in which carbon atoms in graphene are replaced with silicon atoms), germanene (a material in which carbon atoms in graphene are replaced with germanium atoms), transition metal chalcogenides (TMDs), boron nitride (BN), and black phosphorus. Use of the two-dimensional material can enhance one or more physical properties, such as electron mobility, mechanical strength, and thermal conductivity, compared to semiconductors made of single elements such as silicon and germanium. Furthermore, the two-dimensional material has superior physical properties compared to semiconductors made of single elements such as silicon, and may therefore be referred to as a new materials channel (NMC).

[0317] The layered material may be a chalcogenide. A chalcogenide is a compound containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0318] Furthermore, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer 213. Specifically, molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0319] [Semiconductor Layer 113] As described above, a semiconductor of a single element such as silicon or germanium, a compound semiconductor such as gallium arsenide, or a layered substance functioning as a semiconductor can be used for the semiconductor layer 113. In particular, the use of the above-described layered substance is preferable.

[0320] Furthermore, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer 113. Specifically, molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ) etc.

[0321] In addition to the two-dimensional materials described above, the semiconductor layer 113 may include Group III-V compound semiconductors (typically, gallium arsenide compound semiconductors, indium phosphide compound semiconductors, indium gallium arsenide compound semiconductors, indium arsenide compound semiconductors, etc.), carbon nanotubes (CNTs), tin sulfide (typically, SnS), tin selenide (typically, SnSe), etc.

[0322] Note that as long as the transistor 100 including the semiconductor layer 113 can have a higher field-effect mobility than the transistor 200 including the semiconductor layer 213, a material that can be used for the semiconductor layer 213 may be used for the semiconductor layer 113. For example, a metal oxide may be used for the semiconductor layer 113. Furthermore, as long as the transistor 100 including the semiconductor layer 113 can have a higher field-effect mobility than the transistor 200 including the semiconductor layer 213, a material that can be used for the semiconductor layer 113 may be used for the semiconductor layer 213. For example, silicon may be used for the semiconductor layer 213.

[0323] In the transistor of one embodiment of the present invention and the semiconductor device including the transistor of one embodiment of the present invention, an inorganic insulating material or an organic insulating material can be used for the insulating layers (the insulating layer 102, the insulating layer 105, the insulating layer 107, the insulating layer 203, the insulating layer 205, the insulating layer 207, and the insulating layer 227). Alternatively, the insulating layer may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0324] As the inorganic insulating material, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used.

[0325] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0326] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS) can be used to analyze the oxygen and nitrogen contents. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic % or more, or 1 atomic % or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic % or less than 1 atomic %). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0327] Furthermore, for evaluating the film density of an insulating layer or the like, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR) can be used. Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a pale (bright) transmission electron (TE) image. Even when the same material is used for the insulating layer, if the film densities are different, the boundary between these may be observed as a difference in contrast in a cross-sectional TEM image.

[0328] The nitrogen content of the insulating layer can be confirmed, for example, by energy dispersive X-ray spectrometry (EDX). For example, when silicon nitride, silicon oxynitride, or the like is used for the insulating layer, the nitrogen content can be evaluated using the ratio of the nitrogen peak height to the silicon peak height. In EDX, the peak of a certain element refers to the point at which the count number of the element reaches a maximum in a spectrum where the horizontal axis shows the energy of characteristic X-rays and the vertical axis shows the count number (detection value) of characteristic X-rays. Alternatively, the count number at the energy of characteristic X-rays specific to the element may be used to confirm the difference in nitrogen content by the ratio of the nitrogen count number to the silicon count number. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0329] The hydrogen concentration of the insulating layer can be evaluated by, for example, SIMS.

[0330] When hydrogen diffuses into the semiconductor layer 213, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed in the semiconductor layer 213. ＯH may be formed, which may increase the carrier concentration in the semiconductor layer 213. By using a blocking film that suppresses hydrogen diffusion as an insulating layer in contact with the semiconductor layer 213 or an insulating layer located around the semiconductor layer 213, oxygen deficiency (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0331] Oxygen vacancies in the channel formation region of the transistor 200 (V Ｏ ) and V Ｏ In particular, when the channel length L200 is short, oxygen vacancies (V Ｏ ) and V Ｏ H has a large effect on the electrical characteristics and reliability of the transistor 200. For example, when V Ｏ The diffusion of H increases the carrier concentration in the channel formation region, which may cause a change in the threshold voltage of the transistor 200 or a decrease in reliability. Ｏ The influence of the diffusion of H on the electrical characteristics and reliability of the transistor 200 increases as the channel length L200 of the transistor 200 decreases. Ｏ ) and V Ｏ By reducing H, it is possible to realize a transistor with a short channel length, which has good electrical characteristics and high reliability.

[0332] By using an insulating layer that releases oxygen as an insulating layer in contact with the semiconductor layer 213 (for example, the insulating layer 205 and the insulating layer 227) or an insulating layer located around the semiconductor layer 213 (for example, the insulating layer 203), oxygen can be supplied from the insulating layer to the semiconductor layer 213. By supplying oxygen to the channel formation region of the semiconductor layer 213, oxygen vacancies (V Ｏ ) and V ＯThe amount of H can be reduced, and a highly reliable transistor can be obtained, which has favorable electrical characteristics. Note that other treatments for supplying oxygen to the semiconductor layer 213 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0333] It is preferable that the insulating layer in contact with the semiconductor layer 213 or the insulating layer located around the semiconductor layer 213 emits less impurities (for example, water and hydrogen) from itself. Note that the impurities referred to here are impurities that diffuse into the semiconductor layer 213 and cause oxygen deficiency (V Ｏ ) and V Ｏ Impurities refer to substances that can adversely affect the electrical characteristics of a transistor by, for example, generating H. Reducing the release of impurities can suppress the diffusion of the impurities into the semiconductor layer 213, thereby enabling a transistor to exhibit favorable electrical characteristics and high reliability.

[0334] Oxygen may be desorbed from the semiconductor layer 213 due to heat applied in a process after the formation of the semiconductor layer 213. However, oxygen may be supplied to the semiconductor layer 213 from an insulating layer in contact with the semiconductor layer 213 or an insulating layer located around the semiconductor layer 213, causing oxygen vacancies (V Ｏ ) and V Ｏ An increase in H can be suppressed. Furthermore, the degree of freedom in the process temperature can be increased in the processes after the formation of the semiconductor layer 213. Specifically, the process temperature can be increased in the processes after the formation of the semiconductor layer 213. Therefore, the transistor 200 exhibiting favorable electrical characteristics and high reliability can be formed.

[0335] [Insulating Layer 203] An inorganic insulating material or an organic insulating material can be used for the insulating layer 203 (insulating layer 203a, insulating layer 203b, and insulating layer 203c). The insulating layer 203 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0336] An inorganic insulating material can be suitably used for the insulating layer 203. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. Examples of the insulating layer 203 that can be used include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0337] The insulating layer 203 may have a stacked structure of two or more layers. For example, Figures 4A to 4C show a configuration in which the insulating layer 203 has a stacked structure of an insulating layer 203a, an insulating layer 203b over the insulating layer 203a, and an insulating layer 203c over the insulating layer 203b. Note that the insulating layer 203a, the insulating layer 203b, and the insulating layer 203c may be made of the same material or different materials.

[0338] It is preferable that the insulating layer 203 releases little impurities (for example, water and hydrogen) from itself.

[0339] The insulating layer 203b can be thicker than the insulating layer 203a and the insulating layer 203c. As described above, the insulating layer 203b is an insulating layer containing oxygen to be supplied to the semiconductor layer 213. Therefore, by making the insulating layer 203b the thickest among the three insulating layers (insulating layer 203a, insulating layer 203b, and insulating layer 203c) that constitute the insulating layer 203, the amount of oxygen that can be contained in the insulating layer 203 as a whole can be increased. The deposition rate of the insulating layer 203b is preferably faster than the deposition rate of the insulating layer 203a and the deposition rate of the insulating layer 203c. By increasing the deposition rate of a thick film, productivity can be improved.

[0340] The insulating layer 203a and the insulating layer 203c each function as a blocking film that suppresses gas desorption from the insulating layer 203b. It is preferable to use a material that is difficult for gas to diffuse into the insulating layer 203a and the insulating layer 203c. It is preferable that the insulating layer 203a and the insulating layer 203c each have a region with a higher film density than the insulating layer 203b. Increasing the film density of the insulating layer can improve, for example, the blocking ability against gas. Slowing the film formation rate of the insulating layer increases the film density, which can improve, for example, the blocking ability against gas.

[0341] The insulating layer 203b is preferably formed using an oxide or an oxynitride. The insulating layer 203b is preferably formed using a film that releases oxygen when heated. For example, silicon oxide or silicon oxynitride can be suitably used for the insulating layer 203b.

[0342] When the insulating layer 203b releases oxygen, oxygen can be supplied from the insulating layer 203b to the semiconductor layer 213 through the insulating layer 227. The insulating layer 203b preferably has a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient, oxygen can be easily diffused in the insulating layer 203b, and oxygen can be efficiently supplied to the semiconductor layer 213. Furthermore, as described above, by making the insulating layer 203b thicker than the insulating layer 203a and the insulating layer 203c, more oxygen can be supplied to the semiconductor layer 213.

[0343] The insulating layer 203 is preferably formed by a film formation method such as a sputtering method, an ALD method, or a PECVD method.

[0344] In particular, by using a sputtering method without using a gas containing hydrogen in the deposition gas, a film with an extremely low hydrogen content can be obtained. Therefore, hydrogen supply to the semiconductor layer 213 can be suppressed, and the electrical characteristics of the transistor 200 can be stabilized. When silicon oxide is deposited by a sputtering method, for example, it can be deposited using a silicon target in an atmosphere containing an oxygen gas. When silicon nitride is deposited by a sputtering method, for example, it can be deposited using a silicon target in an atmosphere containing nitrogen gas. When aluminum oxide is deposited by a sputtering method, for example, it can be deposited using an aluminum target in an atmosphere containing an oxidizing gas.

[0345] Silicon oxide and silicon nitride can be formed by, for example, the PEALD method. Aluminum oxide and hafnium oxide can be formed by, for example, the thermal ALD method. By forming an insulating layer by the PEALD method and the thermal ALD method, a dense insulating film can be formed, and thus the blocking property against oxygen and hydrogen can be improved.

[0346] The insulating layer 203a and the insulating layer 203c can be formed using a material that contains more nitrogen than the insulating layer 203b. By increasing the nitrogen content of the insulating layer, the blocking property against oxygen and hydrogen can be improved.

[0347] The insulating layer 203a and the insulating layer 203c may have a region where the hydrogen concentration is lower than that of the insulating layer 203b.

[0348] The insulating layers 203a and 203c are preferably impermeable to oxygen. Furthermore, the insulating layers 203a and 203c are preferably impermeable to hydrogen. The insulating layers 203a and 203c function as blocking films that prevent hydrogen from diffusing from the outside of the transistor to the semiconductor layer 213 through the insulating layers 203a and 203c. The film density of the insulating layers 203a and 203c is preferably higher than that of the insulating layer 203b. Increasing the film density of the insulating layer can improve the blocking properties of oxygen and hydrogen. When silicon oxide or silicon oxynitride is used for the insulating layer 203b, silicon nitride or silicon nitride oxide can be used for the insulating layers 203a and 203c, respectively. Furthermore, hafnium oxide or aluminum oxide can be suitably used for the insulating layers 203a and 203c.

[0349] The insulating layer 203a and the insulating layer 203c can each have a stacked structure of two or more materials selected from silicon nitride, silicon nitride oxide, hafnium oxide, and aluminum oxide.

[0350] When oxygen contained in the insulating layer 203b diffuses downward (toward the substrate 101) from the insulating layer 203b, the amount of oxygen supplied from the insulating layer 203b to the semiconductor layer 213 may decrease. By providing the insulating layer 203a below the insulating layer 203b, the oxygen contained in the insulating layer 203b can be prevented from diffusing downward. Furthermore, by providing the insulating layer 203c on the insulating layer 203b, the oxygen contained in the insulating layer 203b can be prevented from diffusing upward. Therefore, the amount of oxygen supplied from the insulating layer 203b to the semiconductor layer 213 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0351] Furthermore, by providing the insulating layer 203a and the insulating layer 203c, the diffusion of hydrogen into the semiconductor layer 213 is suppressed, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0352] The insulating layers 203a and 203c preferably have a thickness that functions as a blocking film for oxygen and hydrogen. If the insulating layers 203a and 203c are too thin, their blocking function may be reduced. On the other hand, if the insulating layers 203a and 203c are too thick, the region of the semiconductor layer 213 facing the insulating layer 203b may be narrowed, and the amount of oxygen supplied to the semiconductor layer 213 may be reduced. The thicknesses of the insulating layers 203a and 203c (with respect to the surface on which they are formed) are preferably 1 nm to 200 nm, 1 nm to 100 nm, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 2 nm to 5 nm, respectively.

[0353] [Insulating Layer 105, Insulating Layer 205, and Insulating Layer 227] The insulating layers 105, 205, and 227, which function as gate insulating layers, preferably have a low defect density. A low defect density in the insulating layer 105 enables the transistor 100 to have favorable electrical characteristics. A low defect density in the insulating layer 205 enables the transistor 200 to have favorable electrical characteristics. A low defect density in the insulating layer 227 enables the transistor 200 shown in FIGS. 18B and 18C to have favorable electrical characteristics, for example. Furthermore, the insulating layers 105, 205, and 227 preferably have a high withstand voltage. A high withstand voltage of the insulating layer 105 enables the transistor 100 to have high reliability. A high withstand voltage of the insulating layer 205 enables the transistor 200 to have high reliability. The high withstand voltage of the insulating layer 227 enables the transistor 200 illustrated in FIGS. 18B and 18C to be a highly reliable transistor, for example.

[0354] The insulating layer 205 is preferably an insulating layer containing oxygen. Furthermore, it is preferably an insulating layer that releases oxygen when heated. For example, when a metal oxide is used for the semiconductor layer 213, oxygen contained in the insulating layer 205 can be supplied to the metal oxide. This allows oxygen vacancies in the metal oxide to be repaired, thereby improving the electrical characteristics and reliability of the transistor 200. Similarly, the insulating layer 227 is preferably an insulating layer containing oxygen. Furthermore, it is preferably an insulating layer that releases oxygen when heated. For example, it is possible to improve the electrical characteristics and reliability of the transistor 200 shown in FIGS. 18A to 18C.

[0355] The insulating layer 105, the insulating layer 205, and the insulating layer 227 can each use, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layer 105, the insulating layer 205, and the insulating layer 227 can each use one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layer 105, the insulating layer 205, and the insulating layer 227 can each be a single layer or a stacked layer. The insulating layer 105, the insulating layer 205, and the insulating layer 227 can each have, for example, a stacked structure of an oxide and a nitride.

[0356] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0357] The insulating layer 205 preferably releases little impurities (for example, water and hydrogen) from itself. The small amount of impurity release from the insulating layer 205 suppresses diffusion of the impurities into the semiconductor layer 213. Therefore, the transistor 200 manufactured by this manufacturing method can be a highly reliable transistor with good electrical characteristics. Similarly, the insulating layer 227 preferably releases little impurities (for example, water and hydrogen) from itself. Therefore, the transistor 200 shown in FIGS. 18A to 18C can be a highly reliable transistor with good electrical characteristics.

[0358] Since the insulating layer 205 is formed over the semiconductor layer 213, it is preferable that the insulating layer 205 be formed under conditions that cause little damage to the semiconductor layer 213. For example, it is preferable that the insulating layer 205 be formed under conditions that cause a sufficiently slow film formation rate. For example, when the insulating layer 205 is formed by a PECVD method, damage to the semiconductor layer 213 can be reduced by forming the insulating layer 205 under low power conditions.

[0359] Here, the insulating layer 205 and the insulating layer 227 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 213.

[0360] In order to improve the interface characteristics with the semiconductor layer 213, it is preferable to use one or more of oxide and oxynitride at least on the side of the insulating layer 205 and the insulating layer 227 that is in contact with the semiconductor layer 213. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 205 and the insulating layer 227. It is more preferable to use a film that releases oxygen by heating for the insulating layer 205.

[0361] Note that the insulating layer 205 and the insulating layer 227 may have a stacked structure. The insulating layer 205 can have a stacked structure of an oxide film or oxynitride film in contact with the semiconductor layer 213 and a nitride film in contact with the conductive layer 215. Similarly, the insulating layer 227 can have a stacked structure of an oxide film or oxynitride film in contact with the semiconductor layer 213 and a nitride film facing the conductive layer 223. As the oxide film or oxynitride film, for example, one or more of silicon oxide and silicon oxynitride can be preferably used. As the nitride film, silicon nitride can be preferably used.

[0362] The insulating layer 105, the insulating layer 205, and the insulating layer 227 preferably have a thickness (film thickness relative to the surface where the insulating layer 105, the insulating layer 205, and the insulating layer 227) of 1 nm to 100 nm. At least a part of the insulating layer 105, the insulating layer 205, and the insulating layer 227 preferably has a region with the above thickness.

[0363] [Conductive Layer 211 and Conductive Layer 212] The conductive layer 211, which functions as one of the source and drain electrodes of the transistor 200, and the conductive layer 212, which functions as the other of the source and drain electrodes of the transistor 200, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. For the conductive layer 211 and the conductive layer 212, a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum can be preferably used. Copper or aluminum is particularly preferable because of its excellent mass productivity.

[0364] A metal oxide film (also referred to as an oxide conductor) can be used for each of the conductive layers 211 and 212. Examples of oxide conductors (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0365] Here, oxide conductors (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0366] The conductive layers 211 and 212 may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0367] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to each of the conductive layers 211 and 212. By using a Cu-X alloy film, it is possible to process it by a wet etching method, which makes it possible to reduce manufacturing costs.

[0368] Note that the conductive layer 211 and the conductive layer 212 may be formed using the same material or different materials.

[0369] Here, the conductive layers 211 and 212 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 213 .

[0370] When an oxide semiconductor is used for the semiconductor layer 213, the conductive layer 211 and the conductive layer 212 are oxidized by oxygen contained in at least one of the semiconductor layer 213, the insulating layer 203, and the insulating layer 227, which may increase the electrical resistance. In addition, the conductive layer 211 and the conductive layer 212 are oxidized by oxygen contained in the semiconductor layer 213, which may cause oxygen deficiency (V Ｏ ) may increase. When the conductive layers 211 and 212 are oxidized by oxygen contained in the insulating layer 203, the amount of oxygen supplied from the insulating layer 203 to the semiconductor layer 213 may decrease. Similarly, when the conductive layers 211 and 212 are oxidized by oxygen contained in the insulating layer 227, the amount of oxygen supplied from the insulating layer 227 to the semiconductor layer 213 may decrease.

[0371] The conductive layers 211 and 212 are preferably made of a material that is resistant to oxidation. The conductive layers 211 and 212 are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layers 211 and 212 may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 211 and 212 may each have a stacked structure of the above-mentioned materials.

[0372] By using a material that is difficult to oxidize for the conductive layer 211 and the conductive layer 212, it is possible to prevent oxidation by at least one of oxygen contained in the semiconductor layer 213, oxygen contained in the insulating layer 203, and oxygen contained in the insulating layer 227, which can prevent an increase in electrical resistance. Ｏ ) can be suppressed, and the amount of oxygen supplied to the semiconductor layer 213 from one or both of the insulating layer 203 and the insulating layer 227 can be increased.

[0373] [Conductive Layer 115, Conductive Layer 215, and Conductive Layer 223] The conductive layer 115, which functions as the gate electrode of the transistor 100, the conductive layer 215, which functions as the gate electrode of the transistor 200, and the conductive layer 223, which functions as the back gate electrode of the transistor 200, can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals. The conductive layer 115, the conductive layer 215, and the conductive layer 223 may be formed using the materials that can be used for the conductive layer 211 and the conductive layer 212. As described above, the conductive layer 223 is preferably formed of a conductive material that is easily oxidized because the layer 225, which can be formed by plasma treatment or the like in an oxygen atmosphere, is provided on the side and top surfaces of the conductive layer 223. For example, aluminum is preferably used for the conductive layer 223.

[0374] Although the conductive layer 215 has a single-layer structure in this embodiment, this is not limiting. For example, the conductive layer 215 may have a stacked structure of two or more layers. For example, when the conductive layer 215 has a two-layer stacked structure, a nitride or an oxide can be used as the first conductive layer (the conductive layer on the insulating layer 205 side), and one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals can be used as the second conductive layer. Furthermore, for example, when the conductive layer 215 has a three-layer stacked structure, the first conductive layer (the conductive layer on the insulating layer 205 side) can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy; the second conductive layer can be an alloy containing one or more of the above-mentioned metals as components; and the third conductive layer can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy.

[0375] [Layer 225] The layer 225 is an oxide containing the elements contained in the conductive layer 223. Examples of the layer 225 include oxides of the conductive layer 223, specifically metal oxides such as aluminum oxide and tantalum oxide. For example, when aluminum is used for the conductive layer 223, the layer 225 becomes aluminum oxide. The layer 225 is preferably an insulating layer that can be formed by subjecting the conductive layer 223 to plasma treatment in an oxygen atmosphere or the like.

[0376] The layer 225 is preferably an insulating layer having blocking properties against oxygen, similar to the insulating layers 203a and 203c. This can prevent oxygen released from the insulating layers 227 and 203b from diffusing toward the conductive layer 223 through the layer 225. Furthermore, an insulating layer having the same function as the insulating layers 203a and 203c can be formed without using a film formation method such as a PECVD method or a sputtering method, which can reduce the number of times the above film formation method is used, thereby increasing productivity in some cases. An example of the layer 225 that satisfies the above properties is aluminum oxide.

[0377] [Insulating Layer 207] For example, the insulating layer 207, which functions as a protective layer for the transistor 200, is preferably made of a material that is less susceptible to impurity diffusion. Providing the insulating layer 207 can effectively prevent external impurities from diffusing into the transistor, thereby improving the reliability of the transistor. Examples of impurities include water and hydrogen. The insulating layer 207 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 207. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of an acrylic resin and a polyimide resin can be used as the organic material. A photosensitive material may be used as the organic material. Two or more of the above insulating films may be stacked. The insulating layer 207 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material. Note that the insulating layer 107, which can function as a protective layer for the transistors 100 and 200, can also be formed using the above-described material that can be used for the insulating layer 207.

[0378] [Substrate 101] There are no significant limitations on the material of the substrate 101, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 101. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 101. The shape of the semiconductor substrate and insulating substrate may be circular or rectangular.

[0379] A flexible substrate, a laminated film, a base film, or the like may be used as the substrate 101. Examples of materials that can be used for the flexible substrate, the laminated film, the base film, or the like include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamides (nylon, aramid, or the like), polysiloxane, cycloolefin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofiber, and the like.

[0380] [Composition of Metal Oxide in Semiconductor Layer 213] The composition of the metal oxide in the semiconductor layer 213 will be described below.

[0381] The composition of the metal oxide in the semiconductor layer 213 greatly affects the electrical characteristics and reliability of the transistor 200 .

[0382] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0383] When an In—Zn oxide is used for the semiconductor layer 213, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a ratio close to these can be used.

[0384] When an In—Sn oxide is used for the semiconductor layer 213, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these values, can be used.

[0385] When an In-M-Zn oxide is used for the semiconductor layer 213, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 213 may have atomic ratios of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1. :6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides thereof having a similar structure can be used.

[0386] In addition, when the element M has a plurality of metal elements, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as the element M, the sum of the atomic ratio of gallium and the atomic ratio of tin can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range.

[0387] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 213, it is preferable that the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms be in the above-mentioned range.

[0388] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0389] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that requires a large on-state current, a semiconductor device with excellent electrical characteristics can be obtained.

[0390] The composition of a metal oxide can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, or quantification may be difficult, or element M may not be detected.

[0391] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0392] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which a transistor is held at a high temperature while an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and the drain potential while the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate while the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0393] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of change in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0394] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 213, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of fluctuation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This makes it possible to realize a highly reliable transistor.

[0395] One factor that causes the threshold voltage to fluctuate in the PBTS test is carrier trapping into defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the greater the number of carriers trapped into the defect levels, resulting in significant degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0396] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0397] More specifically, when an In—Ga—Zn oxide is used for the semiconductor layer 213, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer 213. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 213.

[0398] For the semiconductor layer 213, a metal oxide is preferably used in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V) in the metal oxide can be prevented. Ｏ ) is less likely to occur.

[0399] A metal oxide that does not contain gallium may be used for the semiconductor layer 213. For example, In—Zn oxide may be used for the semiconductor layer 213. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide results in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Alternatively, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 213. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0400] For example, an oxide containing indium and zinc can be used for the semiconductor layer 213. In this case, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3 or a ratio close thereto can be used.

[0401] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layer 213, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M.

[0402] A transistor having high reliability when a positive bias is applied can be obtained by using a metal oxide having a low content of the element M for the semiconductor layer 213. When the transistor is used as a transistor that is required to have high reliability when a positive bias is applied, a highly reliable semiconductor device can be obtained.

[0403] Next, the reliability of the transistor against light will be described.

[0404] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0405] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide in the semiconductor layer 213 is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0406] For example, the semiconductor layer 213 can be made of metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or similar ratios.

[0407] For the semiconductor layer 213, a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0408] When an In—Ga—Zn oxide is used for the semiconductor layer 213, a metal oxide in which the atomic ratio of indium to the atomic number of the metal element is equal to or less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a ratio close to these can be used.

[0409] For the semiconductor layer 213, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is 20 atomic % or more and 60 atomic % or less, preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0410] A transistor with high reliability against light can be obtained by using a metal oxide with a high content of element M for the semiconductor layer 213. By using the transistor as a transistor that is required to have high reliability against light, a highly reliable semiconductor device can be obtained.

[0411] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 213. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0412] The semiconductor layer 213 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 213 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0413] The two or more metal oxide layers included in the semiconductor layer 213 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto provided on the first metal oxide layer can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0414] The above is a description of the components.

[0415] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0416] Embodiment Mode 2 In this embodiment mode, an example in which the semiconductor device shown in the above embodiment mode is applied to a display device will be described with reference to the drawings.

[0417] 43A is a block diagram illustrating a configuration example of a display device 11 according to one embodiment of the present invention. The display device 11 includes a display portion 20, a scanning line driver circuit 12, a signal line driver circuit 13, and a protection circuit 14. The display portion 20 includes a plurality of pixels 21 arranged in a matrix.

[0418] The scanning line driving circuit 12 is connected to the pixels 21 via wiring 31. The wiring 31 extends, for example, in the row direction of the matrix.

[0419] The signal line driving circuit 13 is connected to the pixels 21 via wiring 33. The wiring 33 extends, for example, in the column direction of the matrix.

[0420] 43A, the wiring 31 and the wiring 33 are shown as straight lines, but one straight line does not necessarily mean one wiring, and multiple wirings may be represented by one straight line. In the block diagrams and circuit diagrams that follow, multiple wirings may also be represented by one straight line. Furthermore, multiple wirings other than the wiring 31 and the wiring 33 may also be represented by one straight line.

[0421] The pixel 21 has a display element, and can display an image on the display unit 20 using the display element. For example, a light-emitting element, specifically an organic EL element, can be used as the display element. Alternatively, a liquid crystal element (also called a liquid crystal device) can be used as the display element. Furthermore, a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type, or the like, can also be used as the display element. Alternatively, a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials can be used.

[0422] The scanning line driver circuit 12 has a function of selecting, for example, the pixels 21 to which image data is written, row by row. Specifically, the scanning line driver circuit 12 can select the pixels 21 to which image data is written by outputting a signal to a wiring 31. Here, the scanning line driver circuit 12 can select all the pixels 21 by outputting the signal to the wiring 31 in the first row, for example, and then to the wiring 31 in the second row, and so on, sequentially up to the wiring 31 in the final row. Therefore, the signal output by the scanning line driver circuit 12 to the wiring 31 is a scanning signal, and the wiring 31 can be referred to as a scanning line. The scanning line driver circuit 12 can have a configuration including, for example, a shift register circuit, a level shift circuit, and an analog amplifier circuit.

[0423] The signal line driver circuit 13 has a function of generating image data. The image data is supplied to the pixels 21 via wirings 33. For example, the image data can be written to all the pixels 21 included in the row selected by the scanning line driver circuit 12. Here, the image data can be expressed as a signal (image signal). Therefore, the wirings 33 can be called signal lines.

[0424] The protection circuit 14 has a function of preventing damage to transistors and the like of the pixels 21 when a surge voltage caused by, for example, static electricity is applied to various wirings of the display device 11, such as scanning lines and signal lines. For example, the protection circuit 14 can be configured to release electric charge to a common wiring or the like when a surge voltage is applied. The protection circuit 14 can be configured with nonlinear elements arranged in parallel across the target wiring. The nonlinear elements are configured with two-terminal elements such as diodes or three-terminal elements such as transistors. For example, by connecting the gate terminal and drain terminal of a transistor (also called diode connection), it is possible to give the transistor characteristics similar to those of a diode.

[0425] The scan line driver circuit 12, the signal line driver circuit 13, and the protection circuit 14 can include the semiconductor device 10 or the semiconductor device 10A described in the above embodiment. The diode-connected transistor included in the protection circuit 14 can be, for example, the transistor 100 described in the above embodiment. That is, the diode-connected transistor can be, for example, a p-channel transistor.

[0426] FIG. 43B is a plan view showing an example of the configuration of a pixel 21. The pixel 21 can have multiple sub-pixels 23. FIG. 43B illustrates an example in which the pixel 21 has sub-pixels 23R, 23G, and 23B. Here, if the pixel 21 has a light-emitting element as a display element, for example, the planar shape of the sub-pixels shown in FIG. 43B corresponds to the planar shape of the light-emitting region of the light-emitting element. Note that FIG. 43B illustrates the sub-pixels 23R, 23G, and 23B as having equal or approximately equal aperture ratios (which may also be referred to as sizes or sizes of light-emitting regions), but this is not a limitation of one embodiment of the present invention. The aperture ratios of the sub-pixels 23R, 23G, and 23B can be determined as appropriate. The aperture ratios of the sub-pixels 23R, 23G, and 23B may be different from one another, or two or more of them may be equal or approximately equal.

[0427] In this specification and the like, when describing matters common to, for example, the subpixels 23R, 23G, and 23B, the alphabets that distinguish them may be omitted and they may be referred to as subpixels 23. When describing matters common to other elements that are distinguished by alphabets, they may also be described using symbols without the alphabets.

[0428] 43B, a stripe arrangement is applied as an arrangement method of the sub-pixels 23. Note that an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like may also be applied as an arrangement method of the sub-pixels 23. For an example of the planar shape of the sub-pixels, the arrangement of the sub-pixels, and the like, refer to the fifth embodiment.

[0429] The sub-pixels 23R, 23G, and 23B each emit light of a different color. Examples of the sub-pixels 23R, 23G, and 23B include sub-pixels of three colors: red (R), green (G), and blue (B), and sub-pixels of three colors: yellow (Y), cyan (C), and magenta (M). The pixel 21 may also include four or more sub-pixels 23. For example, the pixel 21 may include sub-pixels of four colors: R, G, B, and white (W). As described above, the display device 11 can display a full-color image on the display unit 20 by including a plurality of sub-pixels 23 that emit light of different colors in the pixel 21. The pixel 21 may also include sub-pixels of R, G, B, and infrared (IR) light, for example.

[0430] The display unit 20 may be provided with a sensor, for example, a sensor may be provided in the pixel 21. For example, the display unit 20 may have a function as a fingerprint sensor. For example, the display unit 20 may have a function as an optical or ultrasonic fingerprint sensor.

[0431] 43C is a circuit diagram showing an example of the configuration of the sub-pixel 23. The sub-pixel 23 shown in FIG. 43C includes a pixel circuit 40A and a light-emitting element 48.

[0432] In this specification and the like, a display device using a light-emitting element as a display element is referred to as a light-emitting display device. The light-emitting display device of one embodiment of the present invention may be any of a top-emission type in which light is emitted in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type in which light is emitted toward a substrate on which a light-emitting element is formed, and a dual-emission type in which light is emitted to both sides.

[0433] The pixel circuit 40A includes a transistor 41, a transistor 43, and a capacitor 45. That is, the pixel circuit 40A is a 2Tr (transistor) 1C (capacitor) type pixel circuit.

[0434] In the pixel circuit 40A, one of the source and the drain of the transistor 41 is connected to the wiring 33. The other of the source and the drain of the transistor 41 is connected to the gate of the transistor 43. The gate of the transistor 43 is connected to one electrode of the capacitor 45. The gate of the transistor 41 is connected to the wiring 31.

[0435] One of the source and drain of the transistor 43 is connected to the wiring 35. The other of the source and drain of the transistor 43 is connected to the other electrode of the capacitor 45. The other electrode of the capacitor 45 is connected to one electrode of the light-emitting element 48. The other electrode of the light-emitting element 48 is connected to the wiring 37. Here, the one electrode of the light-emitting element 48 is also referred to as a pixel electrode. Furthermore, the wiring 37 can be shared by, for example, all the sub-pixels 23. Therefore, the other electrode of the light-emitting element 48 can also be referred to as a common electrode. Here, one of the pixel electrode and the common electrode functions as an anode, and the other of the pixel electrode and the common electrode functions as a cathode.

[0436] As described above, the wiring 31 functions as a scan line, and the wiring 33 functions as a signal line. The wirings 35 and 37 function as power supply lines. For example, a high power supply potential (hereinafter simply referred to as "high potential" or "VDD") can be supplied to the wiring 35. In this case, a low power supply potential (hereinafter simply referred to as "low potential" or "VSS") can be supplied to the wiring 37.

[0437] The transistor 41 functions as a switch and is also referred to as a selection transistor. The transistor 41 controls whether the wiring 33 and the gate of the transistor 43 are electrically connected (allowing current to flow) or disconnected, based on the potential of the wiring 31. Image data is written to the pixel circuit 40A by turning on the transistor 41, and the written image data is held by turning off the transistor 41.

[0438] The transistor 43, which is also referred to as a driving transistor, has a function of controlling the amount of current flowing through the light-emitting element 48. The capacitor 45 has a function of holding the gate potential of the transistor 43. The light emission luminance of the light-emitting element 48 is controlled in accordance with a potential corresponding to image data that is supplied to the gate of the transistor 43. Specifically, when a high potential is supplied to the wiring 35 and a low potential is supplied to the wiring 37, the amount of current flowing from the wiring 35 to the wiring 37 is controlled in accordance with the gate potential of the transistor 43. This controls the light emission luminance of the light-emitting element 48.

[0439] An OS transistor is preferably used as the transistor 41. An OS transistor has an extremely small source-drain leakage current (also referred to as off-state current) in an off state. Therefore, by using an OS transistor as the transistor 41, charge stored in the capacitor 45 can be held for a long period of time. This allows image data written to the subpixel 23 to be held for a long period of time, thereby reducing the frequency of refresh operations (rewriting image data to the subpixel 23). This reduces the power consumption of the display device 11.

[0440] Here, to increase the emission luminance of the light-emitting element 48, it is necessary to increase the amount of current flowing through the light-emitting element 48. To achieve this, it is necessary to increase the source-drain voltage of the transistor 43, which is a driving transistor. Because an OS transistor has a higher withstand voltage between the source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the transistor 43, it is possible to increase the amount of current flowing through the light-emitting element 48 and increase the emission luminance of the light-emitting element 48.

[0441] An OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage (potential difference between the gate and the source) compared to a Si transistor. Therefore, by using an OS transistor as the transistor 43, the current flowing between the source and the drain can be precisely controlled by changing the gate-source voltage. This allows for precise control of the amount of current flowing through the light-emitting element 48. This allows for precise control of the luminance of light emitted by the subpixel 23. This increases the number of gray levels that can be expressed by the subpixel 23.

[0442] Here, if the parasitic capacitance between the gate electrode and source electrode of the transistor 41 and the parasitic capacitance between the gate electrode and drain electrode of the transistor 41 are large, the potential of the gate of the transistor 43, which is a driving transistor, may fluctuate, causing noise. This may change the luminance of the light-emitting element 48, and the quality of an image displayed on the display unit 20 may be degraded. Therefore, the transistor 41 is preferably a transistor with small parasitic capacitance. The transistor 41 is preferably a lateral transistor described in the above embodiment, for example, a lateral OS transistor.

[0443] In this specification and the like, the parasitic capacitance between the gate electrode and source electrode of a transistor and the parasitic capacitance between the gate electrode and drain electrode of a transistor are collectively referred to as the parasitic capacitance between the gate electrode and SD electrode of a transistor.

[0444] Furthermore, if the drain current of the transistor 43, which is a driving transistor, does not change even when the source-drain voltage of the transistor 43 changes, the light emission luminance of the light-emitting element 48 can be stabilized. That is, the transistor 43 preferably has high saturation. Therefore, the transistor 43 is preferably the VLFET or a lateral transistor described in the above embodiment. When the transistor 43 is a lateral transistor, for example, it is preferably a lateral OS transistor.

[0445] Furthermore, when a high potential is supplied to the wiring 35 and a low potential is supplied to the wiring 37, the transistor 43 is preferably a p-channel transistor. This allows the source potential of the transistor 43 to be fixed to the potential of the wiring 35. Therefore, fluctuations in the gate-source voltage of the transistor 43 due to fluctuations in the source potential can be prevented. Therefore, the light-emitting luminance of the light-emitting element 48 can be stabilized. For these reasons, the transistor 100 described in the above embodiment is preferably used as the transistor 43. Note that one or both of the transistors 41 and 43 may be the vertical transistors described in the above embodiment, such as vertical OS transistors.

[0446] As described above, by using an OS transistor for the transistor 43, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," and "suppression of variation in light emission luminance of each light-emitting element 48," etc.

[0447] Examples of the light-emitting element 48 include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. Examples of the LEDs that can be used include mini LEDs and micro LEDs.

[0448] Examples of the light-emitting material contained in the light-emitting element 48 include a material that emits fluorescence (fluorescent material), a material that emits phosphorescence (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material), and an inorganic compound (such as a quantum dot material).

[0449] The light emitting element 48 may emit light of any color, such as infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by providing the light emitting element 48 with a microcavity structure.

[0450] Fig. 43D is a circuit diagram showing an example configuration of the sub-pixel 23. The sub-pixel 23 shown in Fig. 43D includes a pixel circuit 40B and a light-emitting element 48. The pixel circuit 40B has a configuration in which a transistor 44 is added to the pixel circuit 40A. The pixel circuit 40B is a 3Tr1C type pixel circuit.

[0451] The pixel circuit 40B is connected to wirings 31a and 31b as wirings 31. In the pixel circuit 40B, the gate of the transistor 41 is connected to the wiring 31a. One of the source and drain of the transistor 44 is connected to the other of the source and drain of the transistor 43, the other electrode of the capacitor 45, and one electrode of the light-emitting element 48. The other of the source and drain of the transistor 44 is connected to the wiring 38. The gate of the transistor 44 is connected to the wiring 31b.

[0452] The transistor 44 functions as a switch and controls the conductive state or non-conductive state between the wiring 38 and one electrode of the light-emitting element 48 based on the potential of the wiring 31b. A reference potential, for example, is supplied to the wiring 38. The reference potential of the wiring 38 supplied via the transistor 44 can suppress variations in the gate-source voltage of each transistor 43. Note that when the reference potential is supplied to the wiring 38, the wiring 38 can be shared by, for example, all of the sub-pixels 23.

[0453] Furthermore, a current value that can be used to set pixel parameters can be obtained based on the current value of the wiring 38. More specifically, the wiring 38 can function as a monitor line for outputting the current flowing through the transistor 43 or the current flowing through the light-emitting element 48 to the outside of the pixel 21. The current output to the wiring 38 can be converted into a potential by, for example, a source follower circuit, or into a digital signal by, for example, an analog-to-digital (A-D) converter circuit. When the wiring 38 functions as a monitor line, the pixels 21 can be connected to different wirings 38 for each column.

[0454] The transistor 44 preferably has a large on-state current because it can perform a switching operation at high speed. Therefore, the channel length of the transistor 44 is preferably as short as possible. Therefore, the transistor 44 is preferably the vertical transistor described in the above embodiment. Alternatively, since a transistor with a large on-state current is preferably used as the transistor 44, the transistor 100 described in the above embodiment is preferably used.

[0455] 43E is a circuit diagram showing an example of the configuration of the sub-pixel 23. The sub-pixel 23 shown in FIG.

[0456] In this specification and the like, a display device using a liquid crystal element as a display element is referred to as a liquid crystal display device. Examples of liquid crystal display devices include a transmissive liquid crystal display device, a reflective liquid crystal display device, and a semi-transmissive liquid crystal display device.

[0457] The pixel circuit 42 includes a transistor 41 and a capacitor 46. That is, the pixel circuit 42 is a 1Tr1C type pixel circuit.

[0458] In the pixel circuit 42, one of the source and drain of the transistor 41 is connected to the wiring 33. The other of the source and drain of the transistor 41 is connected to one electrode of a capacitor 46. One electrode of the capacitor 46 is connected to one electrode of a liquid crystal element 49. The gate of the transistor 41 is connected to the wiring 31. The other electrode of the capacitor 46 and the other electrode of the liquid crystal element 49 are connected to the wiring 37. Here, the one electrode of the liquid crystal element 49 is also referred to as a pixel electrode. The other electrode of the liquid crystal element 49 may also be referred to as a common electrode. In the pixel circuit 42, for example, a ground potential can be supplied to the wiring 37.

[0459] In the pixel circuit 42, the transistor 41 functions as a switch and controls electrical continuity or non-conduction between the wiring 33 and one electrode of the liquid crystal element 49 based on the potential of the wiring 31. Image data is written to the pixel circuit 42 by turning on the transistor 41, and the written image data is held by turning off the transistor 41.

[0460] The capacitor 46 has a function of holding the potential of one electrode of the liquid crystal element 49. The alignment state of the liquid crystal molecules of the liquid crystal element 49 is controlled in accordance with the potential corresponding to image data that is supplied to one electrode of the liquid crystal element 49.

[0461] The liquid crystal element 49 may be in any of the following modes: TN (Twisted Nematic) mode, STN (Super-Twisted Nematic) mode, VA (Vertical Alignment) mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Opticaly Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, MVA (Multidomain Vertical Alignment) mode, and PVA (Patterned Vertical Alignment mode, In Plane Switching (IPS) mode, Fringe Field Switching (FFS) mode, or Transverse Bend Alignment (TBA) mode may be used. Other examples include Electrically Controlled Birefringence (ECB) mode, Polymer Dispersed Liquid Crystal (PDLC) mode, Polymer Network Liquid Crystal (PNLC) mode, and Guest-Host mode. However, the present invention is not limited to these, and various other modes may be used.

[0462] Examples of liquid crystal materials that can be used for the liquid crystal element 49 include thermotropic liquid crystal, low-molecular-weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, and antiferroelectric liquid crystal. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, blue phase, etc., depending on the conditions. Furthermore, either positive-type or negative-type liquid crystal may be used as the liquid crystal material, and the liquid crystal material can be selected depending on the mode or design to be applied.

[0463] <Configuration Example of Signal Line Driver Circuit> Fig. 44A is a block diagram showing a configuration example of the signal line driver circuit 13 shown in Fig. 43A. As shown in Fig. 44A, the signal line driver circuit 13 has a shift register circuit 15, a latch circuit 16, a level shift circuit 17, a digital-analog (DA) conversion circuit 18, and a sampling switch circuit 19.

[0464] The output terminal of the shift register circuit 15 is connected to the input terminal of the latch circuit 16. The output terminal of the latch circuit 16 is connected to the input terminal of the level shift circuit 17. The output terminal of the level shift circuit 17 is connected to the input terminal of the D-A conversion circuit 18. The output terminal of the D-A conversion circuit 18 is connected to the input terminal of the sampling switch circuit 19. The output terminal of the sampling switch circuit 19 is connected to a wiring 33 that functions as a signal line. Here, the wiring that connects the output terminal of the shift register circuit 15 and the input terminal of the latch circuit 16 is referred to as a wiring 39.

[0465] The shift register circuit 15 has a function of generating a signal for controlling the driving of the latch circuit 16. For example, when a start pulse signal is supplied to the shift register circuit 15, a signal for controlling the driving of the latch circuit 16 is output to the wiring 39.

[0466] The latch circuit 16 has a function of holding or outputting digital image data. Whether the latch circuit 16 holds or outputs image data is determined based on a signal supplied from the shift register circuit 15 to the latch circuit 16.

[0467] The level shift circuit 17 has a function of changing the potential level of the signal representing the image data output from the latch circuit 16. Specifically, the level shift circuit 17 has a function of changing the potential level of the signal representing the image data output from the latch circuit 16 to a potential level that can be processed by the D-A conversion circuit 18.

[0468] The D-A conversion circuit 18 has a function of converting the digital image data output by the level shift circuit 17 into analog image data and outputting it to the sampling switch circuit 19. For example, the larger the digital value of the image data output by the level shift circuit 17, the larger the potential that can be output to the sampling switch circuit 19.

[0469] The sampling switch circuit 19 has a function of controlling the output of analog image data to the wiring 33. A pulse signal (a signal whose potential changes over time) is supplied to the sampling switch circuit 19, and this controls the output of analog image data to the wiring 33.

[0470] 44B is a block diagram showing an example configuration of the signal line driving circuit 13 when the sampling switch circuit 19 shown in FIG. 44A is replaced with a selection circuit 25. The selection circuit 25 has a demultiplexer circuit 26. The demultiplexer circuit 26 has one input terminal and two or more output terminals. Different wirings 33 are connected to the two or more output terminals of the demultiplexer circuit 26, respectively.

[0471] The demultiplexer circuit 26 has a function of outputting, from one of its output terminals, the analog image data input from the D-A conversion circuit 18. The output terminal from which the image data is output is selected by a selection signal input to the demultiplexer circuit 26. For example, if the demultiplexer circuit 26 has a first output terminal and a second output terminal, it is determined from either the first output terminal or the second output terminal that the image data supplied to the input terminal of the demultiplexer circuit 26 will be output, depending on the potential of the selection signal.

[0472] By including the selection circuit 25 in the signal line driver circuit 13, the circuit scale of the signal line driver circuit 13 can be reduced. Specifically, for example, the number of transistors included in the signal line driver circuit 13 can be reduced. Here, when n wires 33 (n is an integer equal to or greater than 2) are connected to the signal line driver circuit 13, the number of wires 39 can be made less than n. For example, when the demultiplexer circuit 26 has two output terminals, the number of wires 39 can be made n / 2. Note that the demultiplexer circuit 26 may have three or more output terminals.

[0473] As described above, since the signal line driver circuit 13 has the selection circuit 25, it is possible to reduce the area occupied by the signal line driver circuit 13. Therefore, since the signal line driver circuit 13 can be made smaller, the display device 11 can be made a small display device, and the display device 11 can be made a display device with a narrow frame.

[0474] 44C is a circuit diagram showing an example configuration of the shift register circuit 15. The shift register circuit 15 can be configured with multiple register circuits 50 connected in series. In FIG. 44C, four stages of register circuits 50 are shown as register circuit 50[1], register circuit 50[2], register circuit 50[3], and register circuit 50[4]. Note that a shift register circuit having a configuration similar to that shown in FIG. 44C can also be provided in the scanning line driving circuit 12.

[0475] The register circuit 50 has a clocked inverter circuit 51, an inverter circuit 53, a clocked inverter circuit 55, and a NAND circuit 57. A signal output from the preceding register circuit 50, specifically the signal output from the inverter circuit 53, is input to the input terminal of the clocked inverter circuit 51 and the first input terminal of the NAND circuit 57. The signal output from the clocked inverter circuit 51 or the signal output from the clocked inverter circuit 55 is input to the input terminal of the clocked inverter circuit 51 in the next register circuit 50, as well as to the input terminal of the clocked inverter circuit 55 and the second input terminal of the NAND circuit 57. An output terminal of the NAND circuit 57 is connected to the wiring 39.

[0476] A clocked inverter circuit is a circuit in which whether or not to output an inverted signal of an input signal is controlled by a clock signal. Clocked inverter circuits 51 and 55 are controlled by clock signals CLK1 and CLKB1. Here, clock signal CLKB1 is an inverted signal of clock signal CLK1. That is, when clock signal CLK1 is at a high potential, clock signal CLKB1 is at a low potential, and when clock signal CLK1 is at a low potential, clock signal CLKB1 is at a high potential.

[0477] The clocked inverter circuit 51 has a function of outputting an inverted signal of an input signal when, for example, the clock signal CLK1 is at a high potential and the clock signal CLKB1 is at a low potential. The clocked inverter circuit 55 has a function of outputting an inverted signal of an input signal when, for example, the clock signal CLK1 is at a low potential and the clock signal CLKB1 is at a high potential. Here, since the clock signal CLKB1 is an inverted signal of the clock signal CLK1, a signal is output from either the clocked inverter circuit 51 or the clocked inverter circuit 55.

[0478] A start pulse signal is input to the first-stage register circuit 50. As a result, the register circuits 50 sequentially output signals to the wiring 39. In the example shown in FIG. 44C , the register circuits 50[1], 50[2], 50[3], and 50[4] output signals to the wiring 39 in this order. In this way, image data is sequentially supplied to the pixels 21 in each column shown in FIG. 43A , for example.

[0479] 45A, 45B, 45C, 45D, 45E, 45F, and 45G are circuit diagrams showing examples of the configuration of circuits, specifically CMOS circuits, included in the signal line driving circuit 13. Note that at least some of these circuits can also be provided in the scanning line driving circuit 12.

[0480] 45A illustrates a configuration example of a clocked inverter circuit 60. The clocked inverter circuit 60 includes a p-channel transistor 61, a p-channel transistor 62, an n-channel transistor 63, and an n-channel transistor 64. The transistor 100 described in the above embodiment can be used as the transistors 61 and 62. The transistor 200 described in the above embodiment can be used as the transistors 63 and 64.

[0481] An input signal IN is input to the gate of the transistor 62 and the gate of the transistor 63. A clock signal CLK2 is input to the gate of the transistor 64. A clock signal CLKB2 is input to the gate of the transistor 61. The clock signal CLKB2 is an inverted signal of the clock signal CLK2.

[0482] A high potential is supplied to one of the source and drain of the transistor 61. The other of the source and drain of the transistor 61 is connected to one of the source and drain of the transistor 62. An output signal OUT is output from the other of the source and drain of the transistor 62 and one of the source and drain of the transistor 63. The other of the source and drain of the transistor 63 is connected to one of the source and drain of the transistor 64. A low potential is supplied to one of the source and drain of the transistor 64.

[0483] Clocked inverter circuit 60 can be applied to clocked inverter circuit 51 shown in Fig. 44C by replacing clock signal CLK2 with clock signal CLK1 and clock signal CLKB2 with clock signal CLKB1. Clocked inverter circuit 60 can be applied to clocked inverter circuit 55 shown in Fig. 44C by replacing clock signal CLK2 with clock signal CLKB1 and clock signal CLKB2 with clock signal CLK1.

[0484] 45B illustrates a configuration example of a NAND circuit 70. The NAND circuit 70 includes a p-channel transistor 71, a p-channel transistor 72, an n-channel transistor 73, and an n-channel transistor 74. The transistor 100 described in the above embodiment can be used as the transistors 71 and 72. The transistor 200 described in the above embodiment can be used as the transistors 73 and 74.

[0485] An input signal IN1 is input to the gate of the transistor 72 and the gate of the transistor 73. An input signal IN2 is input to the gate of the transistor 71 and the gate of the transistor 74.

[0486] A high potential is supplied to one of the source and drain of the transistor 71 and one of the source and drain of the transistor 72. An output signal OUT is output from the other of the source and drain of the transistor 71, the other of the source and drain of the transistor 72, and one of the source and drain of the transistor 73. The other of the source and drain of the transistor 73 is connected to one of the source and drain of the transistor 74. A low potential is supplied to the other of the source and drain of the transistor 74.

[0487] 44C . In this case, a signal input to a first input terminal of the NAND circuit 57 can be one of the input signals IN1 and IN2, and a signal input to a second input terminal of the NAND circuit 57 can be the other of the input signals IN1 and IN2. In addition, an output signal OUT can be output to the wiring 39.

[0488] 45C illustrates a configuration example of a NOR circuit 80. The NOR circuit 80 includes a p-channel transistor 81, a p-channel transistor 82, an n-channel transistor 83, and an n-channel transistor 84. The transistor 100 described in the above embodiment can be used as the transistors 81 and 82. The transistor 200 described in the above embodiment can be used as the transistors 83 and 84.

[0489] An input signal IN1 is input to the gate of the transistor 82 and the gate of the transistor 83. An input signal IN2 is input to the gate of the transistor 81 and the gate of the transistor 84.

[0490] A high potential is supplied to one of the source and drain of the transistor 81. The other of the source and drain of the transistor 81 is connected to one of the source and drain of the transistor 82. An output signal OUT is output from the other of the source and drain of the transistor 82, one of the source and drain of the transistor 83, and one of the source and drain of the transistor 84. A low potential is supplied to the other of the source and drain of the transistor 83 and the other of the source and drain of the transistor 84.

[0491] 45D illustrates a configuration example of an analog switch circuit 90. The analog switch circuit 90 includes a p-channel transistor 91 and an n-channel transistor 93. The transistor 100 described in the above embodiment can be used as the transistor 91. The transistor 200 described in the above embodiment can be used as the transistor 93.

[0492] An input signal IN is input to one of the source and drain of the transistor 91 and one of the source and drain of the transistor 93. An output signal OUT is output from the other of the source and drain of the transistor 91 and the other of the source and drain of the transistor 93.

[0493] A pulse signal P is input to the gate of the transistor 93. A pulse signal PB is input to the gate of the transistor 91. The pulse signal PB is an inverted signal of the pulse signal P. When the pulse signal P is at a high potential, the pulse signal PB is at a low potential, and the transistors 91 and 93 are turned on. Therefore, the analog switch circuit 90 outputs the input signal IN as the output signal OUT. On the other hand, when the pulse signal P is at a low potential, the pulse signal PB is at a high potential, and the transistors 91 and 93 are turned off. Therefore, the analog switch circuit 90 does not output the output signal OUT.

[0494] The analog switch circuit 90 can be provided in, for example, the sampling switch circuit 19 shown in Fig. 44A. In this case, the analog image data output by the D-A conversion circuit 18 can be used as the input signal IN, and the image signal output to the wiring 33 can be used as the output signal OUT. The sampling switch circuit 19 can have the same number of analog switch circuits 90 as the number of wirings 33, for example.

[0495] 45E shows an example configuration of the demultiplexer circuit 26. The demultiplexer circuit 26 has an analog switch circuit 90a and an analog switch circuit 90b. The analog switch circuit 90a and the analog switch circuit 90b can each have the same configuration as the analog switch circuit 90 shown in FIG. 45D. In other words, the demultiplexer circuit 26 can be said to have a configuration including two analog switch circuits 90. Note that the demultiplexer circuit 26 may have three or more analog switch circuits 90. In this case, the demultiplexer circuit 26 has three or more output terminals.

[0496] The analog switch circuit 90a includes a p-channel transistor 91a and an n-channel transistor 93a. The analog switch circuit 90b includes a p-channel transistor 91b and an n-channel transistor 93b. The transistor 100 described in the above embodiment can be used as the transistor 91a and the transistor 91b, similar to the transistor 91 shown in FIG. 45D . The transistor 200 described in the above embodiment can be used as the transistor 93a and the transistor 93b, similar to the transistor 93 shown in FIG. 45D .

[0497] An input signal IN is input to one of the source and drain of transistor 91a, one of the source and drain of transistor 91b, one of the source and drain of transistor 93a, and one of the source and drain of transistor 93b. An output signal OUT1 is output from the other of the source and drain of transistor 91a and the other of the source and drain of transistor 93a. An output signal OUT2 is output from the other of the source and drain of transistor 91b and the other of the source and drain of transistor 93b.

[0498] A selection signal SEL is input to the gates of the transistors 91b and 93a. A selection signal SELB is input to the gates of the transistors 91a and 93b. The selection signal SELB is an inverted signal of the selection signal SEL. When the selection signal SEL is high and the selection signal SELB is low, the transistors 91a and 93a are turned on, and the transistors 91b and 93b are turned off. Therefore, the demultiplexer circuit 26 outputs the input signal IN as the output signal OUT1. On the other hand, when the selection signal SEL is low and the selection signal SELB is high, the transistors 91b and 93b are turned on, and the transistors 91a and 93a are turned off. Therefore, the demultiplexer circuit 26 outputs the input signal IN as the output signal OUT2.

[0499] In the example shown in Fig. 45E, the input signal IN can be analog image data output by the D-A conversion circuit 18 shown in Fig. 44B. The output signals OUT1 and OUT2 can be image signals output by the demultiplexer circuit 26 to the wiring 33. Note that a demultiplexer circuit having a configuration similar to that shown in Fig. 45E can also be provided in a circuit other than the selection circuit 25 of the display device 11.

[0500] 45F illustrates a configuration example of a circuit 160A. The circuit 160A includes a p-channel transistor 161, a p-channel transistor 162, an n-channel transistor 163, and an n-channel transistor 164. The transistor 100 described in the above embodiment can be used as the transistors 161 and 162. The transistor 200 described in the above embodiment can be used as the transistors 163 and 164.

[0501] An input signal IN is input to the gate of the transistor 163. An input signal INB is input to the gate of the transistor 164. The input signal INB is an inverted signal of the input signal IN.

[0502] A high potential is supplied to one of the source and drain of the transistor 161 and one of the source and drain of the transistor 162. The other of the source and drain of the transistor 161 is connected to the gate of the transistor 162. The gate of the transistor 162 is connected to one of the source and drain of the transistor 163.

[0503] An output signal OUT is output from the gate of the transistor 161, the other of the source and drain of the transistor 162, and one of the source and drain of the transistor 164. A low potential is supplied to the other of the source and drain of the transistor 163 and the other of the source and drain of the transistor 164.

[0504] 45G illustrates a configuration example of a circuit 160B. The circuit 160B has a configuration in which a p-channel transistor 165 and a p-channel transistor 166 are added to the circuit 160A. The transistor 100 described in the above embodiment can be used as the transistor 165 and the transistor 166.

[0505] An input signal IN is input to the gate of the transistor 163 and the gate of the transistor 165. An input signal INB is input to the gate of the transistor 164 and the gate of the transistor 166.

[0506] The other of the source and drain of the transistor 161 is connected to one of the source and drain of the transistor 165. The other of the source and drain of the transistor 162 is connected to one of the source and drain of the transistor 166. The other of the source and drain of the transistor 165 is connected to the gate of the transistor 162. The gate of the transistor 162 is connected...

Claims

a first transistor, a second transistor, a first insulating layer, and a second insulating layer; the first transistor is a vertical transistor, the first transistor has a lower electrode functioning as one of a source electrode and a drain electrode of the first transistor, and an upper electrode located on the lower electrode and functioning as the other of the source electrode and drain electrode of the first transistor; a gate insulating layer of the second transistor is provided so as to cover an upper surface and a side surface of the semiconductor layer of the second transistor; a gate electrode of the second transistor is provided on a gate insulating layer of the second transistor; the first insulating layer is provided on a gate electrode of the second transistor and on a gate insulating layer of the second transistor; the second insulating layer has a region located between the lower electrode and the upper electrode and a region located on the first insulating layer; a source electrode of the second transistor has a region in contact with a top surface of the semiconductor layer of the second transistor and a region in contact with a top surface of the second insulating layer; a drain electrode of the second transistor having a region in contact with an upper surface of the semiconductor layer of the second transistor and a region in contact with an upper surface of the second insulating layer; the lower electrode has a region in contact with an upper surface of the first insulating layer, The upper electrode has a region in contact with an upper surface of the second insulating layer. 　 In claim 1, a gate insulating layer of the second transistor, the first insulating layer, and the second insulating layer each have a first opening that reaches a semiconductor layer of the second transistor; a gate insulating layer of the second transistor, the first insulating layer, and the second insulating layer have a second opening reaching a semiconductor layer of the second transistor; a source electrode of the second transistor having a region located within the first opening; The semiconductor device includes a drain electrode of the second transistor having a region located inside the second opening. 　 In claim 2, A conductive layer is provided. the first insulating layer and the second insulating layer have a third opening reaching a gate electrode of the second transistor; The conductive layer has a region located inside the third opening, and has a region in contact with an upper surface of a gate electrode of the second transistor and a region in contact with an upper surface of the second insulating layer. 　 a first transistor, a second transistor, a capacitor, a base insulating layer, and a first insulating layer; the first transistor has a first semiconductor layer, a first conductive layer, and a second insulating layer; the second transistor has a second semiconductor layer; the second transistor is a vertical transistor, the capacitor includes a second conductive layer, the second insulating layer, and a third conductive layer; the first semiconductor layer and the second conductive layer have a region in contact with an upper surface of the base insulating layer; the second insulating layer is provided to cover an upper surface of the first semiconductor layer, a side surface of the first semiconductor layer, an upper surface of the second conductive layer, and a side surface of the second conductive layer; the first conductive layer is provided to have a region overlapping the first semiconductor layer and in contact with an upper surface of the second insulating layer; the third conductive layer is provided to have a region overlapping the second conductive layer and in contact with an upper surface of the second insulating layer; the first insulating layer is provided on the first conductive layer, on the third conductive layer, and on the second insulating layer; The second transistor is provided on the first insulating layer. 　 In claim 4, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and a third insulating layer; the second transistor has an eighth conductive layer and a ninth conductive layer; the eighth conductive layer has a region in contact with an upper surface of the first insulating layer; the third insulating layer is provided on the eighth conductive layer and on the first insulating layer; the first insulating layer, the second insulating layer, and the third insulating layer have a first opening reaching the first semiconductor layer; the first insulating layer, the second insulating layer, and the third insulating layer each have a second opening that reaches the first semiconductor layer and faces the first opening with the first conductive layer interposed therebetween; the first insulating layer, the second insulating layer, and the third insulating layer have a third opening reaching the second conductive layer; the first insulating layer and the third insulating layer have a fourth opening reaching the third conductive layer; the fourth conductive layer has a region located inside the first opening, and has a region in contact with an upper surface of the first semiconductor layer and a region in contact with an upper surface of the third insulating layer; the fifth conductive layer has a region located inside the second opening, and has a region in contact with an upper surface of the first semiconductor layer and a region in contact with an upper surface of the third insulating layer; the sixth conductive layer has a region located inside the third opening, and has a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third insulating layer; the seventh conductive layer has a region located inside the fourth opening, and has a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the third insulating layer; the ninth conductive layer has a region in contact with an upper surface of the third insulating layer; the third insulating layer and the ninth conductive layer have a fifth opening reaching the eighth conductive layer; The second semiconductor layer has a region in contact with the eighth conductive layer and a region in contact with the ninth conductive layer, and has a region located inside the fifth opening. 　 In claim 5, the second transistor has a fourth insulating layer and a tenth conductive layer; the fourth insulating layer is provided on the second semiconductor layer so as to have a region located inside the fifth opening; the tenth conductive layer has a region located within the fifth opening, The second semiconductor layer and the tenth conductive layer are provided to have regions that face each other with the fourth insulating layer interposed therebetween. 　 In claim 6, an eleventh conductive layer; the first insulating layer and the third insulating layer have a sixth opening reaching the first conductive layer; The eleventh conductive layer has a region located inside the sixth opening, and has a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the third insulating layer. 　 In any one of claims 4 to 7, the first semiconductor layer comprises silicon; The second semiconductor layer comprises a metal oxide. 　 In claim 8, the first transistor is a p-channel transistor, The second transistor is an n-channel transistor. 　 a first transistor, a second transistor, a third transistor, a fourth transistor, and a first insulating layer; the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, and a second insulating layer; the second transistor includes the first semiconductor layer, a third conductive layer, a fourth conductive layer, and the second insulating layer; the third transistor includes a second semiconductor layer, the third conductive layer, a fifth conductive layer, a sixth conductive layer, and a third insulating layer; the fourth transistor includes the second semiconductor layer, the fifth conductive layer, a seventh conductive layer, an eighth conductive layer, and the third insulating layer; the second insulating layer is provided so as to cover an upper surface and a side surface of the first semiconductor layer; the second insulating layer has a first opening reaching the first semiconductor layer; the second insulating layer has a second opening that reaches the first semiconductor layer and faces the first opening with the second conductive layer and the fourth conductive layer interposed therebetween in a plan view; the first conductive layer has a region located inside the first opening and a region in contact with the first semiconductor layer; the second conductive layer is provided on the second insulating layer so as to have a region overlapping with the first semiconductor layer; the third conductive layer has a region located inside the second opening and a region in contact with the first semiconductor layer; the fourth conductive layer is provided on the second insulating layer to have a region overlapping with the first semiconductor layer, and is located between the second conductive layer and the third conductive layer; the seventh conductive layer is provided on the second insulating layer; the first insulating layer is provided on the first conductive layer, on the second conductive layer, on the third conductive layer, on the fourth conductive layer, and on the seventh conductive layer; the fifth conductive layer is provided on the first insulating layer; the first insulating layer and the fifth conductive layer have a third opening reaching the third conductive layer and a fourth opening reaching the seventh conductive layer; the second semiconductor layer has a region in contact with the third conductive layer, a region in contact with the fifth conductive layer, and a region in contact with the seventh conductive layer, and also has a region located inside the third opening, and a region located inside the fourth opening; the third insulating layer is provided on the second semiconductor layer to have a region located inside the third opening and a region located inside the fourth opening; the sixth conductive layer has a region located inside the third opening and is connected to the fourth conductive layer; the eighth conductive layer has a region located within the fourth opening, the second semiconductor layer and the sixth conductive layer are provided to have regions that face each other with the third insulating layer interposed therebetween, The second semiconductor layer and the eighth conductive layer are provided to have regions that face each other with the third insulating layer interposed therebetween. 　 In claim 10, the first transistor and the second transistor are p-channel transistors, The semiconductor device, wherein the third transistor and the fourth transistor are n-channel transistors. 　 In claim 11, the first semiconductor layer comprises silicon; The second semiconductor layer comprises a metal oxide. 　 In any one of claims 10 to 12, a ninth conductive layer; The ninth conductive layer has a region in contact with the fourth conductive layer and a region in contact with the sixth conductive layer. 　 In claim 13, A fourth insulating layer is provided. the fourth insulating layer is provided between the first insulating layer and the second insulating layer, the fourth insulating layer has the first opening and the second opening, the fourth insulating layer has a fifth opening reaching the fourth conductive layer; The ninth conductive layer has a region located inside the fifth opening.

Images