Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device having a transistor of very small size. The present invention has a transistor, a first insulation layer, and a second insulation layer. The transistor has a semiconductor layer, a first electroconductive layer, and a second electroconductive layer. The first electroconductive layer and the first insulation layer are provided such that the heights of the respective upper surfaces thereof are substantially the same. The second insulation layer is provided on the first electroconductive layer and the first insulation layer. The second electroconductive layer is provided on the second insulation layer. The second electroconductive layer and the second insulation layer each have an opening reaching the first electroconductive layer. The semiconductor layer is provided in contact with the upper surface of the first electroconductive layer, the side surface of the second insulation layer, and the side surface of the second electroconductive layer within each of the openings.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of these devices, a driving method thereof, or a manufacturing method thereof.

[0003] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for semiconductor devices with higher integration and faster speeds. For example, when semiconductor devices are applied to high-resolution display devices, semiconductor devices with higher integration levels are required. As one means for increasing the integration level of transistors, development of fine-sized transistors is underway.

[0004] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) devices, and light-emitting devices including light-emitting devices (also referred to as light-emitting elements) such as light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a display device for VR that uses an organic EL device (also called an organic EL element).

[0006] International Publication No. 2018 / 087625

[0007] To further increase the integration density of semiconductor devices, it is effective to miniaturize the transistors included in the semiconductor device and to devise a layout for the transistors. For example, it is effective to stack multiple transistors included in a semiconductor device vertically relative to the substrate surface rather than arranging them on the same plane. This allows for increased integration of semiconductor devices without increasing the area occupied by the transistors within the substrate surface. On the other hand, when transistors are stacked, if the top surface of a lower-layer transistor has large unevenness, the surface on which the transistor to be formed thereon is formed also has unevenness, making it difficult to form fine transistors by stacking them. For example, the electrodes (source electrode, drain electrode, and gate electrode) of a transistor and the wiring connected to the electrodes each have a step with respect to the substrate surface. However, stacking the transistors and wiring accumulates these step differences. Therefore, the higher the transistor and wiring are provided in the layer, the greater the unevenness with respect to the substrate surface, making it more difficult to fabricate structures formed thereon. Furthermore, if residues generated during processing remain on steps or the like of the electrodes or wirings of the transistors, the residues may come into contact with the electrodes or wirings of the transistors stacked on top of them, causing problems such as electrical conduction, etc. Therefore, it is preferable that the surfaces on which the transistors and wirings are formed are as flat as possible.

[0008] In view of the above, an object of one embodiment of the present invention is to provide a semiconductor device including a transistor whose top surface is planarized with an insulating layer, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a small-sized semiconductor device, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device, and a manufacturing method thereof.

[0009] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0010] One embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer, and a second insulating layer. The transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer. The first conductive layer and the first insulating layer have top surfaces that are approximately the same height. The second insulating layer is provided on the first conductive layer and the first insulating layer. The second conductive layer is provided on the second insulating layer. The second conductive layer and the second insulating layer each have openings that reach the first conductive layer. In the openings, the semiconductor layer is provided in contact with the top surface of the first conductive layer, a side surface of the second insulating layer, and a side surface of the second conductive layer.

[0011] In the above, it is preferable that a third insulating layer is provided on the second insulating layer, and that the second conductive layer and the third insulating layer are at approximately the same height on their upper surfaces.

[0012] In the above, it is preferable that the transistor has a fourth insulating layer, a fifth insulating layer, and a third conductive layer, the fourth insulating layer is provided in contact with an upper surface of the semiconductor layer and an upper surface of the second conductive layer, the third conductive layer is provided in contact with an upper surface of the fourth insulating layer so as to have a region overlapping with the opening, and the fifth insulating layer is provided on the third conductive layer so as to fill the opening.

[0013] In the above, it is preferable that the semiconductor layer contains a metal oxide, and the metal oxide contains two or three selected from indium, an element M, and zinc, and the element M contains one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and the second insulating layer contains silicon oxide or silicon oxynitride.

[0014] In the above, it is preferable that the second insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, and that the sixth insulating layer and the eighth insulating layer each have silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and that the seventh insulating layer has silicon oxide or silicon oxynitride.

[0015] Another embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer, and a second insulating layer. The transistor includes a semiconductor layer and a first conductive layer. The first conductive layer and the first insulating layer have top surfaces that are approximately the same height. The second insulating layer is provided over the first conductive layer and the first insulating layer and has an opening that reaches the first conductive layer. The semiconductor layer is provided in contact with a top surface of the first conductive layer in the opening, a side surface of the second insulating layer in the opening, and a top surface of the second insulating layer.

[0016] In the above, it is preferable that the transistor has a third insulating layer, a fourth insulating layer, and a second conductive layer, the third insulating layer being provided in contact with an upper surface of the semiconductor layer, the second conductive layer being provided in contact with an upper surface of the third insulating layer so as to have a region overlapping with the opening, and the fourth insulating layer being provided on the second conductive layer so as to fill the opening.

[0017] In the above, it is preferable that the semiconductor layer contains a metal oxide, and the metal oxide contains two or three selected from indium, an element M, and zinc, and the element M contains one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and the second insulating layer contains silicon oxide or silicon oxynitride.

[0018] In the above, it is preferable that the second insulating layer has a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer, and that the fifth insulating layer and the seventh insulating layer each have silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and that the sixth insulating layer has silicon oxide or silicon oxynitride.

[0019] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming a first conductive layer and a first insulating layer whose top surface is at approximately the same height as that of the first conductive layer; forming a first insulating film over the first conductive layer and the first insulating layer; forming a second conductive layer over the first insulating film to have a region overlapping with the first conductive layer; removing parts of the second conductive layer and the first insulating film to form openings reaching the first conductive layer; and forming a third conductive layer and a second insulating layer; and forming semiconductor layers in contact with side surfaces of the third conductive layer, side surfaces of the second insulating layer, and a top surface of the first conductive layer in the openings.

[0020] In the above, after forming the second conductive layer and before forming the opening, it is preferable to form a third insulating layer on the second conductive layer and the first insulating film, the third insulating layer having an upper surface roughly equal in height to that of the second conductive layer.

[0021] In the above, after forming the semiconductor layer, it is preferable to form a fourth insulating layer in contact with the upper surface and side surfaces of the semiconductor layer and the upper surface of the third conductive layer, form a fourth conductive layer in contact with the upper surface of the fourth insulating layer so as to have a region overlapping with the semiconductor layer, form a second insulating film on the fourth conductive layer and the fourth insulating layer so as to fill the opening, and process the second insulating film to form a fifth insulating layer having a flat upper surface and filled in the opening.

[0022] In the above, after forming the first conductive layer, it is preferable to form a third insulating film and a first photoresist in this order on the first conductive layer, and then etch the first photoresist and the third insulating film to form the first insulating layer.

[0023] In the above, after forming the second conductive layer and before forming the opening, it is preferable to form a fourth insulating film and a second photoresist in this order on the second conductive layer and the first insulating film, and then etch the second photoresist and the fourth insulating film to form a sixth insulating layer whose upper surface is approximately the same height as the second conductive layer.

[0024] Furthermore, in the above, after forming the semiconductor layer, it is preferable to form a seventh insulating layer in contact with the upper surface and side surfaces of the semiconductor layer and the upper surface of the third conductive layer, form a fifth conductive layer in contact with the upper surface of the seventh insulating layer so as to have an area overlapping with the semiconductor layer, form a fifth insulating film and a third photoresist in this order on the fifth conductive layer and the seventh insulating layer so as to fill the openings, and etch the third photoresist and the fifth insulating film to form an eighth insulating layer having a flat upper surface and filled in the openings.

[0025] According to one embodiment of the present invention, a semiconductor device including a transistor whose top surface is flat and has little unevenness, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a small-sized semiconductor device, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a manufacturing method of a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a novel semiconductor device, and a manufacturing method thereof can be provided.

[0026] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0027] FIG. 1A is a plan view showing an example of a semiconductor device. FIG. 1B is a cross-sectional view showing an example of a semiconductor device. FIG. 2 is a cross-sectional view showing an example of a semiconductor device. FIG. 3 is a cross-sectional view showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIG. 8 is a cross-sectional view showing an example of a semiconductor device. FIGS. 9A to 9D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 11A to 11C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 15 is a perspective view showing an example of a display device. FIG. 16 is a cross-sectional view showing an example of a display device. FIG. 17 is a cross-sectional view showing an example of a display device. FIG. 18 is a cross-sectional view showing an example of a display device. FIG. 19 is a cross-sectional view showing an example of a display device. FIG. 20 is a cross-sectional view showing an example of a display device. FIGS. 21A and 21B are diagrams showing an example of a configuration of a display device. FIG. 22 is a diagram showing an example of a configuration of a display device. FIG. 23 is a diagram showing an example of a configuration of a display device. FIG. 24 is a diagram showing an example of a configuration of a display device. FIG. 25 is a block diagram of a display device. FIGS. 26A and 26B are circuit diagrams of pixel circuits. FIGS. 27A to 27C are circuit diagrams of pixel circuits. FIGS. 28A to 28D are diagrams showing an example of an electronic device. FIGS. 29A to 29F are diagrams showing an example of an electronic device. FIGS. 30A to 30G are diagrams showing an example of an electronic device.

[0028] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0030] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0031] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0032] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0033] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. Note that the names of the source and drain of a transistor may be appropriately changed to the source terminal and drain terminal, or the source electrode and drain electrode, etc., depending on the situation.

[0034] The terms "gate" and "back gate" can be interchanged. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0035] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0036] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0037] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0038] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0039] In this specification and the like, a structure in which at least light-emitting layers are separately fabricated for light-emitting devices with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting device, increasing the degree of freedom in the selection of materials and configurations, and facilitating improvements in brightness and reliability.

[0040] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other in terms of cross-sectional shape, characteristics, or the like. Furthermore, one layer may have two or three functions of the carrier injection layer, carrier transport layer, and carrier block layer.

[0041] In this specification and the like, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).

[0042] In this specification and the like, a light-receiving device (also referred to as a light-receiving element) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0043] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it refers to a shape having a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface on which the structure is to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface on which the structure is to be formed do not necessarily have to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0044] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0045] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0046] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. Furthermore, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0047] Furthermore, in this specification and the like, "approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are approximately the same in a cross-sectional view. For example, when a planarization process (typically, a chemical mechanical polishing (CMP) process) is performed, the heights of the processed surfaces are approximately the same. However, even when a planarization process is performed, the heights may not strictly match depending on the film material, etc., but in this specification and the like, this case is also considered to be "approximately the same height."

[0048] Embodiment 1 In this embodiment, a transistor of one embodiment of the present invention and a manufacturing method thereof will be described.

[0049] One embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.

[0050] The transistor is a vertical transistor in which a source electrode and a drain electrode are provided at different heights above a substrate surface, overlapping each other, and a drain current flows in the vertical direction (vertical direction). Therefore, the transistor can be miniaturized and occupies a smaller area than a planar transistor in which the source electrode and the drain electrode are provided on the same plane. The transistor has the above-described structure, which allows miniaturization and high integration of semiconductor devices.

[0051] A vertical transistor has a structure in which the source electrode, the channel formation region, and the drain electrode are provided at different heights, and therefore, steps or unevenness occurring in the height direction are likely to be larger than those occurring in a planar transistor. In contrast, in a vertical transistor according to one embodiment of the present invention, some components (such as a source electrode and a drain electrode) are embedded in an insulating layer, which allows the formation surface of a structure formed thereon to be planarized. Therefore, steps or unevenness occurring on the transistor can be made smaller than those occurring in a conventional vertical transistor. Furthermore, wirings connected to the respective electrodes (the source electrode, the drain electrode, and the gate electrode) of the transistor are also embedded in the insulating layer as described above. Therefore, for example, when wirings are stacked, the formation surface of the upper wiring can be planarized. The transistor according to one embodiment of the present invention has the above structure, which reduces steps or unevenness occurring in the stacked structure, even when transistors are stacked, thereby allowing the number of stacked transistors to be increased. Therefore, the occupied area can be reduced compared to when multiple transistors are arranged on the same plane, thereby enabling the miniaturization of a semiconductor device. Furthermore, the semiconductor device can be highly integrated.

[0052] The first insulating layer is provided so as to bury one of the source electrode and the drain electrode of the transistor, and the top surface of the first insulating layer and the top surface of the one of the source electrode and the drain electrode of the transistor are substantially flush with each other.

[0053] The second insulating layer is provided over one of a source electrode or a drain electrode of the transistor and the first insulating layer. The other of the source electrode or the drain electrode of the transistor is provided over the second insulating layer. The one of the source electrode or the drain electrode of the transistor, the second insulating layer, and the other of the source electrode or the drain electrode of the transistor have overlapping regions.

[0054] The third insulating layer is provided so as to bury the other of the source electrode or the drain electrode of the transistor, and the top surface of the third insulating layer and the top surface of the other of the source electrode or the drain electrode of the transistor are approximately flush with each other.

[0055] The second insulating layer and the other of the source and drain electrodes of the transistor each have an opening that reaches one of the source and drain electrodes of the transistor.

[0056] The semiconductor layer of the transistor is provided in contact with an upper surface of one of the source electrode or drain electrode of the transistor in the opening, a side surface of the second insulating layer in the opening, a side surface of the other of the source electrode or drain electrode of the transistor in the opening, and an upper surface of the other of the source electrode or drain electrode of the transistor.

[0057] The gate insulating layer of the transistor is provided in contact with the top surface and side surface of the semiconductor layer, the top surface of the other of the source electrode and the drain electrode, and the top surface of the third insulating layer. The gate electrode of the transistor is provided on the gate insulating layer so as to have a region overlapping with the opening.

[0058] The fourth insulating layer is provided so as to fill the opening and the gate electrode of the transistor. The fourth insulating layer preferably has a planarized upper surface, which can reduce steps or irregularities that the opening and the like have in the transistor.

[0059] As described above, the semiconductor device of one embodiment of the present invention has a structure with reduced steps or unevenness. Therefore, for example, transistors included in the semiconductor device can be stacked over multiple layers with high yield, and the semiconductor device can be miniaturized and highly integrated without increasing the area occupied by the transistors, as compared to when the transistors are arranged on the same plane.

[0060] Below, specific structural examples of a transistor of one embodiment of the present invention will be described with reference to drawings.

[0061] <Configuration Example 1> FIG. 1A shows a plan view (also referred to as a top view) of a transistor 100. FIG. 1B shows a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 2 shows a cross-sectional view taken along dashed dotted line B1-B2 in FIG. 1A. Note that FIG. 1A omits some of the components of the transistor 100 (such as an insulating layer). As with FIG. 1A , some of the components are also omitted in the plan views of the transistor and the like in the following drawings.

[0062] The transistor 100 is provided over a substrate 102. The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode. The conductive layer 112b functions as the other of the source electrode and the drain electrode. An entire region of the semiconductor layer 108 that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0063] The detailed configuration of the transistor 100 will be described.

[0064] A conductive layer 112a is provided on the substrate 102. An insulating layer 197 is also provided on the substrate 102. The insulating layer 197 is provided so as to bury the conductive layer 112a provided on the substrate 102. The height of the top surface of the conductive layer 112a and the top surface of the insulating layer 197 are approximately the same. The insulating layer 197 has a function of planarizing a step on the substrate 102 caused by the formation of the conductive layer 112a. This can improve the coverage of a film on the top surfaces of the conductive layer 112a and the insulating layer 197, which are formation surfaces, and thus makes it easy to stack multiple layers on the formation surfaces.

[0065] 1A , the conductive layer 112a extends to the A1 side and can also function as a wiring. Therefore, by planarizing the step formed on the substrate 102 by the side end of the conductive layer 112a with the insulating layer 197, not only the portion where the transistor 100 is formed but also the top surfaces of the conductive layer 112a and the insulating layer 197 at a portion away from the transistor 100 can have a flat shape with approximately the same height. Therefore, structures such as transistors and wiring can be formed at the portion without being affected by the step of the conductive layer 112a, which is preferable from the viewpoint of manufacturing yield. Furthermore, for example, even if residues generated during processing of the conductive layer 112a remain in the step of the conductive layer 112a, by burying the periphery of the conductive layer 112a with the insulating layer 197, problems such as the aforementioned residues coming into contact with wiring stacked on the upper layer and causing electrical conduction can be suppressed.

[0066] An insulating layer 110a is provided over the conductive layer 112a and the insulating layer 197. An insulating layer 110b is provided over the insulating layer 110a. An insulating layer 110c is provided over the insulating layer 110b. A conductive layer 112b is provided over the insulating layer 110c. Note that the insulating layers 110a, 110b, and 110c may be collectively referred to as the insulating layer 110.

[0067] Furthermore, an insulating layer 198 is provided on the insulating layer 110c. The insulating layer 198 is provided so as to bury the conductive layer 112b provided on the insulating layer 110c. The height of the top surface of the conductive layer 112b and the top surface of the insulating layer 198 are approximately the same. The insulating layer 198 has the function of planarizing a step on the insulating layer 110c that is generated by the formation of the conductive layer 112b. This can improve the coverage of a film on the top surfaces of the conductive layer 112b and the insulating layer 198, which are the formation surfaces, and thus makes it easier to stack multiple layers on the formation surfaces.

[0068] 1A , the conductive layer 112b extends toward the A2 side and can also function as a wiring. Therefore, by planarizing the step on the insulating layer 110 caused by the side end of the conductive layer 112b with the insulating layer 198, not only the portion where the transistor 100 is formed but also the top surfaces of the conductive layer 112b and the insulating layer 198 at a location away from the transistor 100 can have flat shapes with approximately the same height. Therefore, structures such as transistors and wiring can be formed at the location without being affected by the step of the conductive layer 112b, which is preferable from the viewpoint of manufacturing yield. Furthermore, for example, even if residues generated during processing of the conductive layer 112b remain in the step of the conductive layer 112b, by burying the periphery of the conductive layer 112b with the insulating layer 198, problems such as the aforementioned residues coming into contact with wiring stacked on the upper layer and causing electrical conduction can be suppressed.

[0069] The conductive layer 112a, the insulating layer 110, and the conductive layer 112b have a region where they overlap with each other. In this region, the insulating layer 110 is sandwiched between the conductive layer 112a and the conductive layer 112b.

[0070] The insulating layer 110 and the conductive layer 112b each have an opening 143 that reaches the conductive layer 112a.

[0071] 1B and 2 show a configuration in which the thickness of the conductive layer 112a in the region overlapping with the opening 143 is approximately equal to the thickness of the region not overlapping with the opening 143, but this is not limited thereto. The thickness of the conductive layer 112a in the region overlapping with the opening 143 may be thinner than the thickness of the region not overlapping with the opening 143. In this case, the electric field from the conductive layer 104 (i.e., the gate electric field of the transistor 100) can be applied up to the channel formation region near the conductive layer 112a. Therefore, the effect of the gate electric field on carriers in the channel formation region can be strengthened in some cases compared to when the conductive layer 112a has a uniform thickness.

[0072] The semiconductor layer 108 is provided in contact with the top surface of the conductive layer 112a in the opening 143, the side surface of the insulating layer 110 in the opening 143, the side surface of the conductive layer 112b in the opening 143, and the top surface of the conductive layer 112b.

[0073] 1B and 2 show a configuration in which the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112b, but this is not limiting. The semiconductor layer 108 only needs to have a region in contact with the side surface of the conductive layer 112b in at least the opening 143.

[0074] For example, by configuring the entire region of the semiconductor layer 108 to be located within the opening 143 and the end of the semiconductor layer 108 to be in contact only with the side surface of the conductive layer 112b within the opening 143, it is possible to prevent the end of the semiconductor layer 108 from causing a step on the conductive layer 112b. This can improve the coverage of a film on the top surface of the conductive layer 112b as a formation surface.

[0075] 1B and 2 , by configuring the end of the semiconductor layer 108 to extend to the outside of the opening 143 and the semiconductor layer 108 to be in contact with not only the side surface of the conductive layer 112b in the opening 143 but also the top surface of the conductive layer 112b, the contact area between the semiconductor layer 108 and the conductive layer 112b can be increased. This can prevent the semiconductor layer 108 from peeling off. Furthermore, the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced, which may increase the on-state current of the transistor 100.

[0076] Here, the insulating layer 110b of the insulating layer 110 is preferably an insulating layer containing oxygen. Furthermore, the insulating layer 110b is preferably an insulating layer that releases oxygen by heating. Thus, for example, when a metal oxide is used for the semiconductor layer 108, oxygen contained in the insulating layer 110b can be supplied to the metal oxide. Thus, oxygen vacancies in the metal oxide can be repaired, thereby improving the electrical characteristics and reliability of the transistor 100.

[0077] On the other hand, the insulating layer 110a and the insulating layer 110c of the insulating layer 110 preferably have a blocking property against gases such as oxygen and hydrogen. This can prevent oxygen contained in the insulating layer 110b from being released to the outside through the insulating layer 110a or the insulating layer 110c. Furthermore, it can prevent hydrogen from diffusing from the outside of the insulating layer 110 into the insulating layer 110b through the insulating layer 110a or the insulating layer 110c and then diffusing into the semiconductor layer 108. For example, when a metal oxide is used for the semiconductor layer 108, hydrogen in the semiconductor layer 108 can cause deterioration of the electrical characteristics and reliability of the transistor 100.

[0078] The insulating layer 106 is provided over the semiconductor layer 108. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface of the conductive layer 112b, and the top surface of the insulating layer 198.

[0079] The conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 is provided to have a region that overlaps with the opening 143 in a plan view. The conductive layer 104 has a region in the opening 143 that faces the semiconductor layer 108 with the insulating layer 106 interposed therebetween.

[0080] In the transistor 100, a source electrode and a drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor 100 is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows in the vertical direction or approximately vertically in the transistor 100. Therefore, the transistor of one embodiment of the present invention can be called a vertical transistor, a vertical channel transistor, or a vertical field effect transistor (VFET).

[0081] Since the source electrode and the drain electrode of the transistor 100 can be provided overlapping with each other, the transistor can be made smaller than a so-called planar transistor in which the source electrode and the drain electrode are arranged on a plane, and the area occupied by the transistor within the substrate surface can be significantly reduced.

[0082] An insulating layer 195 is provided to cover the conductive layer 112a, the semiconductor layer 108, the conductive layer 112b, the insulating layer 106, the conductive layer 104, and the like included in the transistor 100. The insulating layer 195 functions as a protective layer for the transistor 100.

[0083] The insulating layer 195 is preferably provided over the conductive layer 104 so as to fill the opening 143. The insulating layer 195 preferably has a planarized top surface. This can reduce steps or unevenness in the transistor 100 due to the opening 143. Therefore, the insulating layer 195 also functions as a planarization layer for the transistor 100. Providing the insulating layer 195 is preferable because it makes it easier to stack structures such as transistors over the transistor 100.

[0084] 1A , the conductive layer 104 extends to the B2 side and can also function as a wiring. Therefore, by planarizing steps and the like on the insulating layer 106 caused by the opening 143 and the side edges of the conductive layer 104 with the insulating layer 195, not only the area where the transistor 100 is formed but also the area on the conductive layer 104 away from the transistor 100 can be made substantially flat by the insulating layer 195. Therefore, structures such as transistors and wiring can be formed on the area without being affected by the steps of the conductive layer 104, which is preferable from the viewpoint of manufacturing yield. Furthermore, even if residues or the like generated during processing of the conductive layer 104 remain in the steps or the like of the conductive layer 104, by burying the conductive layer 104 with the insulating layer 195, problems such as the aforementioned residues coming into contact with wiring or the like stacked on the upper layer and causing electrical conduction can be suppressed.

[0085] Since the insulating layer 195 has both a function as a protective layer for the transistor 100 and a function as a planarization layer for the transistor 100, it is preferable that the insulating layer 195 cover the entire transistor 100 so that the conductive layer 104 and the like are not exposed.

[0086] The top surface shape of the opening 143 can be, for example, circular or elliptical. The top surface shape of the opening 143 may be a polygon such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), or a pentagon, or a polygon with rounded corners. As shown in FIG. 1A , the top surface shape of the opening 143 is preferably circular. By making the top surface shape of the opening 143 circular, the processing accuracy when forming the opening 143 can be improved, and the opening 143 can be formed with a fine size. Note that in this specification and the like, a circle is not limited to a perfect circle.

[0087] The channel length and channel width of the transistor 100 will be described.

[0088] In the semiconductor layer 108, a region in contact with the conductive layer 112a functions as one of a source region and a drain region, a region in contact with the conductive layer 112b functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0089] The channel length of the transistor 100 is the distance between the source region and the drain region. In Figures 1B and 2, the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. In Figures 1B and 2, the distance along the semiconductor layer 108 in the region between the conductive layer 112a and the conductive layer 112b is indicated as the channel length L100 of the transistor 100.

[0090] Note that the channel length L100 of the transistor 100 may be represented by a thickness T110 (in FIGS. 1B and 2, the thickness T110 is indicated by a double-headed dashed arrow) that corresponds to the thickness of the insulating layer 110 in a region sandwiched between the top surface of the conductive layer 112a and the bottom surface of the conductive layer 112b. Alternatively, the channel length L100 of the transistor 100 may be represented by the thickness of the insulating layer 110b. Alternatively, the channel length L100 of the transistor 100 may be represented by the sum of the thickness T110 and the thickness of the conductive layer 112b.

[0091] Here, the channel length L100 of the transistor 100 is determined by the thickness of the insulating layer 110, the thickness of the conductive layer 112b, the angle θ110 between the surface on which the semiconductor layer 108 is to be formed within the opening 143 (here, the side surface of the insulating layer 110 and the side surface of the conductive layer 112b) and the surface on which the insulating layer 110 is to be formed (here, the top surface of the conductive layer 112a), and the like, and is not affected by the performance of the exposure apparatus used to fabricate the transistor. Therefore, the channel length L100 can be set to a value smaller than the limit resolution of the exposure apparatus, and a transistor with a fine size can be realized.

[0092] The channel length L100 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 200 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L100 can be 100 nm or more and 1 μm or less.

[0093] The thickness T110 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 200 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0094] The angle θ110 can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and less than 85 degrees, 40 degrees or more and less than 80 degrees, 45 degrees or more and less than 80 degrees, 50 degrees or more and less than 80 degrees, 55 degrees or more and less than 80 degrees, 60 degrees or more and less than 80 degrees, 65 degrees or more and less than 80 degrees, or 70 degrees or more and less than 80 degrees. The angle θ110 can also be 90 degrees. A smaller angle θ110 is preferable because it can improve the coverage of the layer (such as the semiconductor layer 108) formed along the sidewall of the opening 143. On the other hand, a smaller angle θ110 is preferable because it can reduce the area occupied by the transistor on the substrate surface.

[0095] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, when the transistor of one embodiment of the present invention is applied to a semiconductor device, the semiconductor device can be miniaturized.

[0096] For example, when the transistor of one embodiment of the present invention is applied to a display device, the frame of the display device can be narrowed.Furthermore, for example, when the transistor of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed.

[0097] The channel width of the transistor 100 is the length of the source region or the length of the drain region in a plan view ( FIG. 1A ). That is, the channel width of the transistor 100 is the length of the region where the semiconductor layer 108 and the conductive layer 112 a contact each other in a plan view, or the length of the region where the semiconductor layer 108 and the conductive layer 112 b contact each other in a plan view. Alternatively, the channel width of the transistor 100 may be an intermediate value between the length of the region where the semiconductor layer 108 and the conductive layer 112 a contact each other in a plan view and the length of the region where the semiconductor layer 108 and the conductive layer 112 b contact each other in a plan view.

[0098] Here, the channel width of the transistor 100 is described as the perimeter of a region where the semiconductor layer 108 is in contact with the side surface of the conductive layer 112b on the opening 143 side. In Figures 1A, 1B, and 2, the channel width W100 of the transistor 100 is indicated by a solid double-headed arrow. The channel width W100 can also be referred to as the perimeter of the opening 143 in a plan view.

[0099] The channel width W100 is determined by the top surface shape of the opening 143, etc. In Figures 1A, 1B, and 2, the width D143 of the opening 143 is indicated by a two-dot chain line with a double arrow. The width D143 refers to the short side of the smallest rectangle circumscribing the opening 143 in a plan view. When the opening 143 is formed using photolithography, the width D143 of the opening 143 is equal to or greater than the resolution limit of the exposure device. The width D143 is, for example, equal to or greater than 0.20 μm and less than 5.0 μm. When the top surface shape of the opening 143 is circular, the width D143 corresponds to the diameter of the opening 143, and the channel width W100 can be calculated as "D143 x π".

[0100] [Semiconductor Layer 108] The semiconductor material that can be used for the semiconductor layer 108 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. As the elemental semiconductor, for example, silicon or germanium can be used. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide (also referred to as an oxide semiconductor) having semiconductor properties can be used. Note that these semiconductor materials may contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron).

[0101] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0102] Silicon can be used for the semiconductor layer 108. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0103] A transistor using amorphous silicon for the semiconductor layer 108 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 108 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 108 has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0104] The semiconductor layer 108 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 108 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. The element M is more preferably gallium.

[0105] The semiconductor layer 108 can be formed using, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO), or the like. Alternatively, indium tin oxide containing silicon can be used.

[0106] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0107] When the semiconductor layer 108 is formed by the ALD method, it is preferable to use a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it not only exhibits high step coverage but also allows low-temperature film formation.

[0108] The composition of the metal oxide in the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 100 .

[0109] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized. Furthermore, by using a metal oxide that does not contain gallium or has a low content of gallium in the semiconductor layer 108, a transistor with high reliability against application of a positive bias can be realized. Furthermore, by using a metal oxide with a low content of element M in the semiconductor layer 108, a transistor with high reliability against application of a positive bias can be realized. Furthermore, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be realized.

[0110] The composition of the metal oxide contained in the semiconductor layer 108 will be described in detail later.

[0111] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 108. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 108, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized. Note that the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have a c-axis orientation and are connected without being oriented in the a-b plane. In the CAAC structure, crystal grain boundaries (grains) are less clearly visible in the a-b plane than in the polycrystalline structure, and therefore a highly reliable transistor can be realized.

[0112] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 108, the more the density of defect states in the semiconductor layer 108 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0113] The semiconductor layer 108 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer 108 may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 108 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the two or more metal oxide layers included in the semiconductor layer 108 may have different compositions.

[0114] The thickness of the semiconductor layer 108 (film thickness relative to the surface on which it is formed) is preferably 3 nm to 100 nm, more preferably 5 nm to 100 nm, even more preferably 10 nm to 100 nm, even more preferably 10 nm to 70 nm, even more preferably 15 nm to 70 nm, even more preferably 15 nm to 50 nm, even more preferably 20 nm to 50 nm, even more preferably 20 nm to 40 nm, even more preferably 25 nm to 40 nm.

[0115] Here, oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

[0116] When an oxide semiconductor is used for the semiconductor layer 108, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, and oxygen vacancies (V Ｏ Furthermore, defects in which hydrogen is introduced into oxygen vacancies (hereinafter referred to as V ＯH.) functions as a donor and generates electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0117] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0118] From the above, when an oxide semiconductor is used for the semiconductor layer 108, V in the semiconductor layer 108 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen are removed from the oxide semiconductor (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the Ｏ By using an oxide semiconductor in which defects such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0119] In the case where an oxide semiconductor is used for the semiconductor layer 108, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less.１７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0120] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, by using an OS transistor in a semiconductor device, the power consumption of the semiconductor device can be reduced.

[0121] OS transistors can be applied to display devices. To increase the light-emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since OS transistors have a higher source-drain breakdown voltage than transistors using silicon (hereinafter referred to as Si transistors), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as a driving transistor in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light-emission luminance of the light-emitting device.

[0122] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a greater number of gray levels to be displayed in the pixel circuit.

[0123] In terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed through a light-emitting device, even when the current-voltage characteristics of the light-emitting device vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting device.

[0124] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of variations in light-emitting devices," and the like.

[0125] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0126] In the transistor of one embodiment of the present invention, and in a semiconductor device, a display device, or the like to which the transistor of one embodiment of the present invention is applied, an inorganic insulating material or an organic insulating material can be used for an insulating layer (the insulating layer 110, the insulating layer 106, the insulating layer 195, the insulating layer 197, and the insulating layer 198). Alternatively, a stacked structure of an inorganic insulating material and an organic insulating material may be used for the insulating layer.

[0127] As the inorganic insulating material, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used.

[0128] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0129] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS) can be used to analyze the oxygen and nitrogen contents. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0130] Furthermore, for evaluating the film density of an insulating layer or the like, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR) can be used. Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a pale (bright) transmission electron (TE) image. Even when the same material is used for the insulating layer, if the film densities are different, the boundary between these may be observed as a difference in contrast in a cross-sectional TEM image.

[0131] The nitrogen content of the insulating layer can be confirmed, for example, by energy dispersive X-ray spectrometry (EDX). For example, when silicon nitride, silicon oxynitride, or the like is used for the insulating layer, the nitrogen content can be evaluated using the ratio of the nitrogen peak height to the silicon peak height. In EDX, the peak of a certain element refers to the point at which the count number of the element reaches a maximum in a spectrum where the horizontal axis shows the energy of characteristic X-rays and the vertical axis shows the count number (detection value) of characteristic X-rays. Alternatively, the count number at the energy of characteristic X-rays specific to the element may be used to confirm the difference in nitrogen content by the ratio of the nitrogen count number to the silicon count number. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0132] The hydrogen concentration of the insulating layer can be evaluated by, for example, SIMS.

[0133] When hydrogen diffuses into the semiconductor layer 108, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed in the semiconductor layer 108. ＯH may be formed, which may increase the carrier concentration in the semiconductor layer 108. By using a blocking film that suppresses hydrogen diffusion as an insulating layer in contact with the semiconductor layer 108 or an insulating layer located around the semiconductor layer 108, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0134] Oxygen vacancies in the channel formation region of the transistor 100 (V Ｏ ) and V Ｏ In particular, when the channel length L100 is short, oxygen vacancies (V Ｏ ) and V Ｏ H has a large effect on the electrical characteristics and reliability of the transistor 100. For example, when V Ｏ The diffusion of H increases the carrier concentration in the channel formation region, which may cause a change in the threshold voltage of the transistor 100 or a decrease in reliability. Ｏ The influence of the diffusion of H on the electrical characteristics and reliability of the transistor 100 increases as the channel length L100 of the transistor 100 decreases. Ｏ ) and V Ｏ By reducing H, it is possible to realize a transistor with a short channel length, which has good electrical characteristics and high reliability.

[0135] By using an insulating layer that releases oxygen as an insulating layer in contact with the semiconductor layer 108 (for example, the insulating layer 106 or the insulating layer 110b), oxygen can be supplied from the insulating layer to the semiconductor layer 108. By supplying oxygen to the channel formation region of the semiconductor layer 108, oxygen vacancies (V Ｏ ) and V ＯThe amount of H can be reduced, and a highly reliable transistor can be obtained, which has favorable electrical characteristics. Note that other treatments for supplying oxygen to the semiconductor layer 108 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0136] It is preferable that the insulating layer in contact with the semiconductor layer 108 or the insulating layer located around the semiconductor layer 108 emits less impurities (for example, water and hydrogen) from itself. Note that the impurities referred to here are impurities that diffuse into the semiconductor layer 108 and cause oxygen deficiency (V Ｏ ) and V Ｏ Impurities refer to substances that can adversely affect the electrical characteristics of a transistor by, for example, generating H. Reducing the release of impurities can suppress the diffusion of the impurities into the semiconductor layer 108, thereby enabling a transistor to exhibit favorable electrical characteristics and high reliability.

[0137] Oxygen may be desorbed from the semiconductor layer 108 due to heat applied in a process after the formation of the semiconductor layer 108. However, oxygen is supplied to the semiconductor layer 108 from an insulating layer in contact with the semiconductor layer 108, and oxygen vacancies (V Ｏ ) and V Ｏ An increase in H can be suppressed. Furthermore, the degree of freedom in the process temperature can be increased in the steps after the formation of the semiconductor layer 108. Specifically, the process temperature can be increased in the steps after the formation of the semiconductor layer 108. Therefore, the transistor 100 exhibits favorable electrical characteristics and is highly reliable.

[0138] [Insulating Layer 110] An inorganic insulating material or an organic insulating material can be used for the insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c). The insulating layer 110 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0139] An inorganic insulating material can be suitably used for the insulating layer 110. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. For example, the insulating layer 110 can include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0140] The insulating layer 110 may have a stacked structure of two or more layers. In Fig. 1B and other figures, the insulating layer 110 has a stacked structure of an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. Note that the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c may be made of the same material or different materials.

[0141] It is preferable that the insulating layer 110 releases little impurities (for example, water and hydrogen) from itself.

[0142] The insulating layer 110b can be thicker than the insulating layer 110a and the insulating layer 110c. As described above, the insulating layer 110b is an insulating layer containing oxygen to be supplied to the semiconductor layer 108. Therefore, by making the insulating layer 110b the thickest among the three insulating layers (insulating layer 110a, insulating layer 110b, and insulating layer 110c) that constitute the insulating layer 110, the amount of oxygen that can be contained in the insulating layer 110 as a whole can be increased. The deposition rate of the insulating layer 110b is preferably faster than the deposition rate of the insulating layer 110a and the deposition rate of the insulating layer 110c. By increasing the deposition rate of a thick film, productivity can be improved.

[0143] The insulating layer 110a and the insulating layer 110c each function as a blocking film that suppresses gas desorption from the insulating layer 110b. It is preferable to use a material that is difficult for gas to diffuse into the insulating layer 110a and the insulating layer 110c. It is preferable that the insulating layer 110a and the insulating layer 110c each have a region with a higher film density than the insulating layer 110b. Increasing the film density of the insulating layer can improve the blocking ability against gas. Slowing the film formation rate of the insulating layer increases the film density, thereby improving the blocking ability against gas.

[0144] The insulating layer 110b is preferably formed using an oxide or an oxynitride. The insulating layer 110b is preferably formed using a film that releases oxygen when heated. For example, silicon oxide or silicon oxynitride can be suitably used for the insulating layer 110b.

[0145] The insulating layer 110b releases oxygen, which allows oxygen to be supplied from the insulating layer 110b to the semiconductor layer 108. The insulating layer 110b preferably has a high oxygen diffusion coefficient. A high oxygen diffusion coefficient makes it easier for oxygen to diffuse through the insulating layer 110b, allowing oxygen to be efficiently supplied to the semiconductor layer 108. Furthermore, as described above, by making the insulating layer 110b thicker than the insulating layer 110a and the insulating layer 110c, more oxygen can be supplied to the semiconductor layer 108.

[0146] The insulating layer 110 is preferably formed by a film formation method such as a sputtering method, an ALD method, or a plasma CVD method.

[0147] In particular, by using a sputtering method without using a gas containing hydrogen in the deposition gas, a film with an extremely low hydrogen content can be obtained. Therefore, hydrogen supply to the semiconductor layer 108 can be suppressed, and the electrical characteristics of the transistor 100 can be stabilized. When silicon oxide is deposited by a sputtering method, for example, it can be deposited using a silicon target in an atmosphere containing an oxygen gas. When silicon nitride is deposited by a sputtering method, for example, it can be deposited using a silicon target in an atmosphere containing nitrogen gas. When aluminum oxide is deposited by a sputtering method, for example, it can be deposited using an aluminum target in an atmosphere containing an oxidizing gas.

[0148] Silicon oxide and silicon nitride can be formed by, for example, the PEALD method. Aluminum oxide and hafnium oxide can be formed by, for example, the thermal ALD method. By forming an insulating layer by the PEALD method and the thermal ALD method, a dense insulating film can be formed, and thus the blocking property against oxygen and hydrogen can be improved.

[0149] The insulating layers 110a and 110c can be formed using a material that contains more nitrogen than the insulating layer 110b. By increasing the nitrogen content of the insulating layer, the blocking properties against oxygen and hydrogen can be improved.

[0150] The insulating layer 110a and the insulating layer 110c may have a region where the hydrogen concentration is lower than that of the insulating layer 110b.

[0151] The insulating layers 110a and 110c are preferably impermeable to oxygen. Furthermore, the insulating layers 110a and 110c are preferably impermeable to hydrogen. The insulating layers 110a and 110c function as blocking films that prevent hydrogen from diffusing from the outside of the transistor to the semiconductor layer 108 through the insulating layers 110a and 110c. The film density of the insulating layers 110a and 110c is preferably higher than that of the insulating layer 110b. Increasing the film density of the insulating layer can improve the blocking properties of oxygen and hydrogen. When silicon oxide or silicon oxynitride is used for the insulating layer 110b, silicon nitride or silicon nitride oxide can be used for the insulating layers 110a and 110c, respectively. Hafnium oxide or aluminum oxide can be preferably used for the insulating layers 110a and 110c.

[0152] The insulating layer 110a and the insulating layer 110c can each have a stacked structure of two or more materials selected from silicon nitride, silicon nitride oxide, hafnium oxide, and aluminum oxide.

[0153] When oxygen contained in the insulating layer 110b diffuses downward (toward the substrate 102) from the insulating layer 110b, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 may decrease. By providing the insulating layer 110a below the insulating layer 110b, it is possible to prevent the oxygen contained in the insulating layer 110b from diffusing downward. Furthermore, by providing the insulating layer 110c on the insulating layer 110b, it is possible to prevent the oxygen contained in the insulating layer 110b from diffusing upward. Therefore, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0154] Furthermore, by providing the insulating layer 110a and the insulating layer 110c, the diffusion of hydrogen into the semiconductor layer 108 is suppressed, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0155] The insulating layers 110a and 110c preferably have a thickness that functions as a blocking film for oxygen and hydrogen. If the insulating layers 110a and 110c are too thin, their function as a blocking film may be reduced. On the other hand, if the insulating layers 110a and 110c are too thick, the region of the semiconductor layer 108 in contact with the insulating layer 110b may be narrowed, and the amount of oxygen supplied to the semiconductor layer 108 may be reduced. The thicknesses of the insulating layers 110a and 110c (with respect to the surface on which they are formed) are preferably 1 nm to 200 nm, 1 nm to 100 nm, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 2 nm to 5 nm, respectively.

[0156] [Insulating Layer 106] The insulating layer 106, which functions as a gate insulating layer, preferably has a low defect density. A low defect density in the insulating layer 106 enables a transistor to exhibit favorable electrical characteristics. Furthermore, the insulating layer 106 preferably has a high withstand voltage. A high withstand voltage of the insulating layer 106 enables a highly reliable transistor.

[0157] The insulating layer 106 is preferably an insulating layer containing oxygen. Furthermore, the insulating layer 106 is preferably an insulating layer that releases oxygen by heating. Thus, for example, when a metal oxide is used for the semiconductor layer 108, oxygen contained in the insulating layer 106 can be supplied to the metal oxide. Thus, oxygen vacancies in the metal oxide can be repaired, thereby improving the electrical characteristics and reliability of the transistor 100.

[0158] The insulating layer 106 can be formed using, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layer 106 can be formed using, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide. The insulating layer 106 can be formed as a single layer or a stacked layer. The insulating layer 106 can be formed as, for example, a stacked layer of an oxide and a nitride.

[0159] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0160] The insulating layer 106 preferably releases little impurities (for example, water and hydrogen) from itself. When the insulating layer 106 releases little impurities, the impurities are prevented from diffusing into the semiconductor layer 108, and the transistor can have good electrical characteristics and high reliability.

[0161] Because the insulating layer 106 is formed over the semiconductor layer 108, it is preferable that the insulating layer 106 be formed under conditions that cause little damage to the semiconductor layer 108. For example, it is preferable that the insulating layer 106 be formed under conditions that cause a sufficiently slow film formation rate. For example, when the insulating layer 106 is formed by a plasma CVD method, damage to the semiconductor layer 108 can be reduced by forming the insulating layer 106 under low power conditions.

[0162] Here, the insulating layer 106 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 108 .

[0163] In order to improve the interface characteristics with the semiconductor layer 108, it is preferable to use one or more of oxide and oxynitride at least on the side of the insulating layer 106 that is in contact with the semiconductor layer 108. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 106. It is more preferable to use a film that releases oxygen by heating for the insulating layer 106.

[0164] Note that the insulating layer 106 may have a stacked structure. The insulating layer 106 can have a stacked structure of an oxide film or an oxynitride film on the side in contact with the semiconductor layer 108 and a nitride film on the side in contact with the conductive layer 104. As the oxide film or the oxynitride film, for example, one or more of silicon oxide and silicon oxynitride can be preferably used. As the nitride film, silicon nitride can be preferably used.

[0165] The thickness of the insulating layer 106 (thickness relative to the surface where the insulating layer 106 is formed) is more preferably 1 nm to 100 nm. The insulating layer 106 may have a region with the above thickness in at least a part thereof.

[0166] [Conductive Layer 112a and Conductive Layer 112b] The conductive layer 112a and the conductive layer 112b, which function as a source electrode and a drain electrode, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, respectively, or an alloy containing one or more of the above metals. For the conductive layer 112a and the conductive layer 112b, a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum can be preferably used. Copper and aluminum are particularly preferred because of their excellent mass productivity.

[0167] The conductive layer 112a and the conductive layer 112b can each be formed using a metal oxide film (also referred to as an oxide conductor). Examples of the oxide conductor (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0168] Here, oxide conductors (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0169] The conductive layers 112a and 112b may each have a stacked-layer structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0170] The conductive layer 112 a and the conductive layer 112 b may each be a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu—X alloy film, they can be processed by wet etching, which makes it possible to reduce manufacturing costs.

[0171] Note that the conductive layers 112a and 112b may be formed using the same material or different materials.

[0172] Here, the conductive layers 112a and 112b will be specifically described using an example in which the semiconductor layer 108 is formed using a metal oxide.

[0173] When an oxide semiconductor is used for the semiconductor layer 108, the conductive layers 112a and 112b are oxidized by oxygen contained in the semiconductor layer 108, which may increase the resistance. The conductive layers 112a and 112b are oxidized by oxygen contained in the insulating layer 110, which may increase the resistance. Furthermore, the conductive layers 112a and 112b are oxidized by oxygen contained in the semiconductor layer 108, which may increase the oxygen vacancy (V Ｏ When the conductive layers 112a and 112b are oxidized by oxygen contained in the insulating layer 110, the amount of oxygen supplied from the insulating layer 110 to the semiconductor layer 108 may decrease.

[0174] The conductive layer 112a and the conductive layer 112b are preferably made of a material that is resistant to oxidation. The conductive layer 112a and the conductive layer 112b are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layer 112a and the conductive layer 112b may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 112a and the conductive layer 112b may each have a stacked structure of the above-mentioned materials.

[0175] By using a material that is difficult to oxidize for the conductive layer 112a and the conductive layer 112b, it is possible to prevent the conductive layer 112a and the conductive layer 112b from being oxidized by oxygen contained in the semiconductor layer 108 or oxygen contained in the insulating layer 110, which can prevent the resistance from increasing. Ｏ ) can be suppressed, and the amount of oxygen supplied from the insulating layer 110 to the semiconductor layer 108 can be increased.

[0176] [Conductive Layer 104] The conductive layer 104 functioning as a gate electrode can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above-mentioned metals. Alternatively, the conductive layer 104 may be formed using any of the materials that can be used for the conductive layers 112a and 112b.

[0177] 1B and other drawings, the conductive layer 104 is shown as having a single-layer structure, but this is not limited thereto. For example, the conductive layer 104 may have a stacked structure of two or more layers. For example, when the conductive layer 104 has a two-layer stacked structure, a nitride or an oxide can be used as the first conductive layer (the conductive layer on the insulating layer 106 side), and a second conductive layer can be made of one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above-mentioned metals. Furthermore, for example, when the conductive layer 104 has a three-layer stacked structure, the first conductive layer (the conductive layer on the insulating layer 106 side) can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy; the second conductive layer can be an alloy containing one or more of the above-mentioned metals as components; and the third conductive layer can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy.

[0178] [Insulating Layer 197, Insulating Layer 198] The insulating layer 197, which is a planarizing layer for the conductive layer 112a that functions as one of the source electrode and the drain electrode, and the insulating layer 198, which is a planarizing layer for the conductive layer 112b that functions as the other of the source electrode and the drain electrode, are preferably made of an organic insulating material or an inorganic insulating material, and are particularly preferably made of an organic insulating material. For example, by using an organic insulating material for the insulating layer 197 and the insulating layer 198, a film with excellent planarity can be easily formed at a relatively low temperature on a formation surface having steps.

[0179] Specific examples of organic insulating materials that can be used for the insulating layers 197 and 198 include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. For the insulating layers 197 and 198, it is preferable to use, for example, a polyimide resin.

[0180] An inorganic insulating material can also be used for the insulating layer 197 and the insulating layer 198. Specific examples of the inorganic insulating material that can be used for the insulating layer 197 and the insulating layer 198 include the inorganic insulating materials that can be used for the insulating layer 110. For example, the insulating layer 197 and the insulating layer 198 are preferably made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

[0181] [Insulating Layer 195] The insulating layer 195, which functions as a protective layer and a planarization layer of the transistor 100, is preferably made of an insulating material that does not easily diffuse impurities. Providing the insulating layer 195 can effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the transistor. Examples of impurities include water and hydrogen. The insulating layer 195 can be an insulating layer containing an inorganic insulating material, or an insulating layer containing an inorganic insulating material and an organic insulating material. Examples of inorganic insulating materials that can be used for the insulating layer 195 include oxide, oxynitride, nitride oxide, and nitride. More specifically, one or more of silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used.

[0182] Examples of organic insulating materials that can be used for the insulating layer 195 include the organic insulating materials that can be used for the insulating layers 197 and 198. For example, one or more of an acrylic resin and a polyimide resin can be used. A photosensitive material may also be used as the organic insulating material. For example, a polyimide resin is preferably used. By using these organic insulating materials for the insulating layer 195, steps or irregularities in the transistor 100 due to the opening 143 can be easily filled and the top surface can be planarized. Two or more of the above insulating films may be stacked. Note that when an insulating layer containing an organic insulating material is used for the insulating layer 195, it is preferable to stack an insulating layer containing the above inorganic insulating material on the insulating layer. This can prevent impurities from diffusing into the transistor through the insulating layer 195.

[0183] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0184] A flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 and the like. The peeling layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate 102 and transfer the semiconductor device to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0185] [Composition of Metal Oxide in Semiconductor Layer 108] The composition of the metal oxide in the semiconductor layer 108 will be described below.

[0186] The composition of the metal oxide in the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 100 .

[0187] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0188] When an In—Zn oxide is used for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a ratio close to these, can be used.

[0189] When an In—Sn oxide is used for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these values, can be used.

[0190] When an In-M-Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 108 may be formed using metal oxides in which the atomic ratios of metal elements are In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1. :6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides thereof having a similar structure can be used.

[0191] In addition, when the element M has a plurality of metal elements, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as the element M, the sum of the atomic ratio of gallium and the atomic ratio of tin can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range.

[0192] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 108, it is preferable that the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms be in the above-mentioned range.

[0193] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0194] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that is required to have a large on-state current, a semiconductor device with excellent electrical characteristics can be obtained.

[0195] The composition of a metal oxide can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, or quantification may be difficult, or element M may not be detected.

[0196] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of element M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of element M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of element M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0197] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which a transistor is held at a high temperature while an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and the drain potential while the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate while the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0198] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of change in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0199] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 108, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of fluctuation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This makes it possible to realize a highly reliable transistor.

[0200] One factor that causes the threshold voltage to fluctuate in the PBTS test is carrier trapping into defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the greater the number of carriers trapped in the defect levels, resulting in significant degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0201] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0202] More specifically, when an In—Ga—Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer 108. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 108.

[0203] For the semiconductor layer 108, a metal oxide is preferably used in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V) in the metal oxide can be prevented. Ｏ ) is less likely to occur.

[0204] A metal oxide that does not contain gallium may be used for the semiconductor layer 108. For example, In—Zn oxide may be used for the semiconductor layer 108. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Alternatively, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 108. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0205] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108. In this case, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3 or a ratio close thereto can be used.

[0206] Although gallium has been described as a representative example, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M.

[0207] A transistor having high reliability when a positive bias is applied can be obtained by using a metal oxide having a low content of the element M for the semiconductor layer 108. When the transistor is used as a transistor that is required to have high reliability when a positive bias is applied, a highly reliable semiconductor device can be obtained.

[0208] Next, the reliability of the transistor against light will be described.

[0209] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0210] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide in the semiconductor layer 108 is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0211] For example, the semiconductor layer 108 can be made of metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or similar ratios.

[0212] For the semiconductor layer 108, a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0213] When an In—Ga—Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is equal to or less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a ratio close to these can be used.

[0214] For the semiconductor layer 108, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is 20 atomic % or more and 60 atomic % or less, preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0215] A transistor with high reliability to light can be obtained by using a metal oxide having a high content of element M for the semiconductor layer 108. By using the transistor as a transistor that is required to have high reliability to light, a highly reliable semiconductor device can be obtained.

[0216] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0217] The semiconductor layer 108 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0218] The two or more metal oxide layers included in the semiconductor layer 108 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto, provided on the first metal oxide layer, can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0219] FIG. 3 shows a structural example of a semiconductor device in which transistors 100 of one embodiment of the present invention are stacked. In FIG. 3 , the transistor in the first layer is denoted as transistor 100_1, and the transistor in the second layer is denoted as transistor 100_2. Components of the transistor 100_1 and planarization layers of the transistor are distinguished by adding "1" or "_1" to the end of their reference numerals, and components of the transistor 100_2 and planarization layers of the transistor are distinguished by adding "2" or "_2" to the end of their reference numerals. As shown in FIG. 3 , a transistor 100_2 having the exact same shape as the transistor 100_1 is stacked on the transistor 100_1 in which the step portions of the components are filled with the insulating layer 197_1, the insulating layer 198_1, and the insulating layer 195_1. By filling the step portions of the components of the transistor with the planarization layer and making the top surfaces of the transistors approximately flat, transistors of the same shape can be stacked with a high yield. 3 illustrates a structure in which transistors of the same shape are stacked, but the present invention is not limited to this. For example, in one embodiment of the present invention, a structure in which transistors of different shapes are stacked or a structure in which different components (e.g., wirings, contact holes, and the like) are stacked over a transistor can be achieved by filling step portions of each component of the transistor with a planarizing layer to make the top surface of the transistor approximately flat.

[0220] <Configuration Example 2> Fig. 4A shows a configuration example of a transistor 100A having a different configuration from the transistor 100 shown in Fig. 1A to Fig. 2. Fig. 4A is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view shown in Fig. 1A.

[0221] The transistor 100A shown in FIG. 4A differs from the transistor 100 shown in FIG. 1B mainly in that the height of the top surface of the insulating layer 195 is approximately the same as the height of the top surface of the conductive layer 104 in the highest region as viewed from the substrate surface.

[0222] In the transistor 100A, a part of the top surface of the conductive layer 104 in the highest region seen from the substrate surface may be exposed. For example, consider a case where an element such as another transistor is stacked on the transistor 100A and an electrode of the element is connected to the gate electrode (conductive layer 104) of the transistor 100A. In this case, the conductive layer 104 and the element can be connected simply by providing an electrode of the element directly on the exposed portion of the conductive layer 104, so there is no need to separately form an opening in the insulating layer 195 for providing a plug for connecting them. Therefore, the number of steps required for manufacturing a semiconductor device may be reduced compared to the case where the transistor 100 is used.

[0223] Regarding the transistor 100A, the contents described for the transistor 100 can be referred to for the points other than those mentioned above.

[0224] <Configuration Example 3> Fig. 4B shows a configuration example of a transistor 100B having a different configuration from the transistor 100 shown in Fig. 1A to Fig. 2. Fig. 4B is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view shown in Fig. 1A.

[0225] The transistor 100B shown in FIG. 4B differs from the transistor 100 shown in FIG. 1B primarily in that it does not have an insulating layer 198.

[0226] In the transistor 100B, the insulating layer 198 that flattens the step caused by the formation of the conductive layer 112b is not provided on the insulating layer 110c, and the insulating layer 106 is provided in contact with the top and side surfaces of the semiconductor layer 108, the top and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110c.

[0227] Since the transistor 100B has the above structure, the number of steps can be reduced compared to the transistor 100 because the insulating layer 198 is not provided.

[0228] Regarding the transistor 100B, the contents described for the transistor 100 can be referred to for the points other than those mentioned above.

[0229] 5A illustrates a structural example of a transistor 100C that has a different structure from the transistor 100 illustrated in FIGS. 1A to 2. FIG. 5A is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view illustrated in FIG.

[0230] The transistor 100C shown in FIG. 5A is different from the transistor 100 shown in FIG. 1B mainly in that it includes a conductive layer 114 that functions as a second gate electrode (also referred to as a back gate electrode), an insulating layer 110s that functions as a second gate insulating layer (also referred to as a back gate insulating layer), and an insulating layer 116 that functions as a blocking film for oxygen and hydrogen, and in the shape of the insulating layer 110a.

[0231] In the transistor 100C, the end of the insulating layer 110a on the opening 143 side has a shape that protrudes further than the side of the insulating layer 110b on the opening 143 side, the side of the insulating layer 110c on the opening 143 side, and the side of the conductive layer 112b on the opening 143 side.

[0232] Furthermore, a conductive layer 114 is provided on the insulating layer 110a so as to overlap with the insulating layer 110b, the insulating layer 110c, and the conductive layer 112b. An insulating layer 116 is provided in contact with the top surface and side surfaces of the conductive layer 114. An insulating layer 110s is provided in contact with the top surface of the insulating layer 110a in the opening 143, the side surface of the insulating layer 116 on the opening 143 side, the side surface of the insulating layer 110b on the opening 143 side, the side surface of the insulating layer 110c on the opening 143 side, and the side surface of the conductive layer 112b on the opening 143 side. The upper end of the insulating layer 110s has a curved shape.

[0233] The semiconductor layer 108 is provided in contact with the upper surface of the conductive layer 112a in the opening 143, the side surface of the insulating layer 110a on the opening 143 side, the side surface of the insulating layer 110s on the opening 143 side, the curved portion of the insulating layer 110s, and the upper surface of the conductive layer 112b.

[0234] An insulating layer 198 having a planarized top surface is provided so as to fill in steps or unevenness formed on the conductive layer 112b and the insulating layer 110c outside the opening 143. In the transistor 100C, the steps or unevenness formed on the conductive layer 112b and the insulating layer 110c outside the opening 143 are larger than in the transistor 100 due to the presence of the conductive layer 114 and the insulating layer 116, and therefore the thickness of the insulating layer 198 functioning as a planarization layer is also thicker.

[0235] In the transistor 100C, one surface of the semiconductor layer 108 in the opening 143 faces the conductive layer 104 with the insulating layer 106 interposed therebetween, and the other surface of the semiconductor layer 108 in the opening 143 faces the conductive layer 114 with the insulating layer 110s and the insulating layer 116 interposed therebetween. As described above, the conductive layer 114 functions as a second gate electrode. The insulating layer 110s functions as a second gate insulating layer. The insulating layer 116 in the region sandwiched between the conductive layer 114 and the insulating layer 110s can also function as a second gate insulating layer.

[0236] Since the transistor 100C has two gate electrodes sandwiching the semiconductor layer 108, a gate electric field can be applied to carriers in the channel formation region from both sides of the semiconductor layer 108. Therefore, a larger on-state current and a smaller off-state current can be realized than the transistor 100 having only one gate electrode (conductive layer 104). Furthermore, the threshold voltage can be shifted toward the normally-off state. Furthermore, the saturation characteristics of the current flowing when operating in the saturation region can be improved (i.e., the magnitude of the drain current hardly changes with an increase in the drain voltage).

[0237] The insulating layer 110s functioning as the second gate insulating layer is preferably formed using a material that contains oxygen and releases oxygen by heat treatment or the like. For example, the insulating layer 110s can be formed using the same material as that used for the insulating layer 110b. As a result, for example, when a metal oxide is used for the semiconductor layer 108, oxygen contained in the insulating layer 110s can be supplied to the metal oxide. Furthermore, oxygen contained in the insulating layer 110b can be supplied to the metal oxide through the insulating layer 110s. As a result, oxygen vacancies in the metal oxide can be repaired, thereby improving the electrical characteristics and reliability of the transistor 100C.

[0238] As mentioned above, by positioning the insulating layer 110a between the insulating layer 110s and the conductive layer 112a, it is possible to prevent problems such as the oxygen contained in the insulating layer 110s diffusing toward the conductive layer 112a, causing the conductive layer 112a to oxidize and become highly resistant, resulting in a decrease in the on-state current of the transistor 100C.

[0239] The insulating layer 116 is preferably formed of a material that functions as a blocking film for oxygen and hydrogen. For example, the insulating layer 116 can be formed of the material that can be used for the insulating layers 110a and 110c described above. By covering the top and side surfaces of the conductive layer 114 with the insulating layer 116 formed of such a material as shown in FIG. 5A , it is possible to prevent problems, such as a decrease in the conductivity of the conductive layer 114 due to the diffusion of oxygen contained in the insulating layers 110s and 110b into the conductive layer 114.

[0240] The conductive layer 114 can be formed using the same materials as those used for the conductive layer 104 .

[0241] Here, the insulating layer 116 can be formed by a deposition method such as plasma CVD or sputtering. Alternatively, for example, the surface of the conductive layer 114 can be oxidized by plasma treatment or the like in an oxygen atmosphere to form the insulating layer 116 covering the top and side surfaces of the conductive layer 114. In this case, the insulating layer 116 having the same function as the insulating layer 110a and the insulating layer 110c can be formed without using a deposition method such as plasma CVD or sputtering, which may reduce the number of times the above deposition method is applied and improve productivity. In this case, it is preferable to use a material that is easily oxidized by plasma treatment or the like in an oxygen atmosphere for the conductive layer 114. For example, aluminum is preferably used. In this case, the insulating layer 116 is an insulating layer made of an oxide of an element contained in the conductive layer 114. For example, when aluminum is used as the material of the conductive layer 114, the insulating layer 116 becomes aluminum oxide.

[0242] With respect to the transistor 100C, the contents described for the transistor 100 can be referred to except for the points mentioned above.

[0243] <Configuration Example 5> Fig. 5B shows a configuration example of a transistor 100E having a different configuration from the transistor 100C shown in Fig. 5A. Fig. 5B is a cross-sectional view corresponding to the same cut surface as Fig. 5A.

[0244] Transistor 100D shown in FIG. 5B differs from transistor 100C shown in FIG. 5A primarily in that it does not have insulating layer 198.

[0245] Unlike the transistor 100C, the transistor 100D does not have an insulating layer 198 that fills in the steps or unevenness formed on the conductive layer 112b and the insulating layer 110c outside the opening 143, and the insulating layer 106 is provided in contact with the top and side surfaces of the semiconductor layer 108, the top surface of the conductive layer 112b, and the top surface of the insulating layer 110c.

[0246] In addition, an insulating layer 195 having a planarized upper surface is provided on the insulating layer 106 and the conductive layer 104 so as to fill the opening 143 and the steps or irregularities formed on the insulating layer 106 outside the opening 143.

[0247] The transistor 100D does not have the insulating layer 198, and therefore the number of manufacturing steps can be reduced compared to the transistor 100C.

[0248] With respect to the transistor 100D, the contents described for the transistor 100C can be referred to except for the points mentioned above.

[0249] 6A illustrates a structural example of a transistor 100E having a different structure from the transistor 100 illustrated in FIGS. 1A to 2. FIG. 6A is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view illustrated in FIG.

[0250] The transistor 100E shown in FIG. 6A differs from the transistor 100 shown in FIG. 1B mainly in that the conductive layer 112a has a stacked-layer structure.

[0251] In the transistor 100E, the conductive layer 112a has a stacked-layer structure of a conductive layer 112a_1 and a conductive layer 112a_2 over the conductive layer 112a_1. The conductive layer 112a_1 is provided to be embedded in an opening formed in an insulating layer 115 over the substrate 102, and the top surfaces of the conductive layer 112a_1 and the insulating layer 115 are planarized. The conductive layer 112a_2 is located over the conductive layer 112a_1 and the insulating layer 115. In the transistor 100E, the height of the top surface of the insulating layer 115 and the height of the conductive layer 112a_1 are the same or approximately the same.

[0252] In the transistor 100E, the height of the top surface of the insulating layer 115 and the height of the top surface of the conductive layer 112a_1 are the same or approximately the same, so that the steps on the surfaces where the insulating layer 110 and the conductive layer 112b are formed can be reduced. As a result, the steps that can be formed on the top surface of the conductive layer 112b and the top surface of the insulating layer 110 can be reduced.

[0253] Note that in the transistor 100E, an example is shown in which the end of the conductive layer 112a_2 is located outside the end of the conductive layer 112a_1, but the end of the conductive layer 112a_2 may be located inside the end of the conductive layer 112a_1. Furthermore, when a plug is provided to connect the conductive layer 112a to an upper conductive layer, the conductive layer 112a_2 may be extended outside the conductive layer 112a_1, and the top surface of the conductive layer 112a_2 may be in contact with the plug in the extended region. The plug is provided to fill openings in the insulating layers 110, 195, and the like.

[0254] As described above, the conductive layers 112a and 112b in contact with the semiconductor layer 108 are preferably made of a material that is resistant to oxidation. However, when a material that is resistant to oxidation is used, the resistance of the conductive layers 112a and 112b may become high. Since the conductive layers 112a and 112b function as wirings, their resistance is preferably low. Therefore, by using a material that is resistant to oxidation for the conductive layer 112a_2 having a region in contact with the semiconductor layer 108 and using a material with low resistance for the conductive layer 112a_1 not having a region in contact with the semiconductor layer 108, the resistance of the entire conductive layer 112a can be reduced.

[0255] As described above, when the channel length L100 is short, oxygen vacancies (V Ｏ ) and V Ｏ By using a material that is not easily oxidized for the conductive layer 112a_2, oxygen vacancies (V Ｏ ) and V Ｏ It is possible to suppress an increase in H. Therefore, a transistor having a short channel length, good electrical characteristics, and high reliability can be realized.

[0256] The conductive layer 112a_2 can preferably be made of one or more of an oxide conductor and a nitride conductor. The conductive layer 112a_1 is preferably made of a material having lower resistance than the conductive layer 112a_2. The conductive layer 112a_1 can preferably be made of, for example, one or more of copper, aluminum, titanium, tungsten, and molybdenum, or an alloy containing one or more of the above metals. Specifically, In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112a_2, and tungsten can be preferably used for the conductive layer 112a_1.

[0257] The insulating layer 115 can be formed using an inorganic insulating material or an organic insulating material. The insulating layer 115 may have a stacked structure of an inorganic insulating material and an organic insulating material. For example, the insulating layer 115 can be formed using the materials and structures listed for the insulating layer 110b, the insulating layer 195, and the like.

[0258] With respect to the transistor 100E, the contents described for the transistor 100 can be referred to except for the points mentioned above.

[0259] 6B shows a structural example of a transistor 100F having a different structure from the transistor 100 shown in FIGS. 1A to 2. FIG. 6B is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view shown in FIG.

[0260] The transistor 100F shown in FIG. 6B differs from the transistor 100 shown in FIG. 1B mainly in the structure of the conductive layer 104 and the structure of the insulating layer 195.

[0261] In the transistor 100F, the conductive layer 104 is provided to fill recesses formed on the semiconductor layer 108 and the insulating layer 106 that reflect the shape of the opening 143, and the insulating layer 195 is provided to fill the conductive layer 104. Furthermore, in the transistor 100F, the top surfaces of the conductive layer 104 and the insulating layer 195 are planarized, and the heights of the conductive layer 104 and the insulating layer 195 are the same or approximately the same.

[0262] When the transistor 100F has the above structure, the coverage of films provided over the conductive layer 104 and the insulating layer 195 can be improved.

[0263] With respect to the transistor 100F, the contents described for the transistor 100 can be referred to for the points other than those mentioned above.

[0264] 7A illustrates a structural example of a transistor 100G having a different structure from the transistor 100 illustrated in FIGS. 1A to 2. FIG. 7A is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view illustrated in FIG.

[0265] The transistor 100G shown in FIG. 7A differs from the transistor 100 shown in FIG. 1B mainly in that the transistor 100G does not include the conductive layer 112b and that the end portion of the semiconductor layer 108 extends to the outside of the conductive layer 112a in a plan view.

[0266] In the transistor 100G, the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a in the opening 143, the side surfaces of the insulating layer 110 (insulating layers 110a, 110b, and 110c) in the opening 143, and the top surface of the insulating layer 110c. In the transistor 100G, the semiconductor layer 108 can function as both a semiconductor layer having a channel formation region and the other of the source and drain electrodes. For example, a region of the semiconductor layer 108 in contact with the side surface of the insulating layer 110 in the opening 143 can function as the channel formation region. A region outside the opening 143 in contact with the top surface of the insulating layer 110c can function as the other of the source and drain electrodes.

[0267] By reducing the resistance of a portion of the semiconductor layer 108, the region can be used as the source and drain regions of a transistor. For example, the resistance of the semiconductor layer 108 can be reduced by supplying an impurity that functions as a dopant, such as boron, to the semiconductor layer 108 from a direction perpendicular to the substrate surface using ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. Alternatively, when an oxide semiconductor is used for the semiconductor layer 108, a silicon nitride film or the like can be formed on a region of the semiconductor layer 108 that does not overlap with the opening 143 to make the region an oxide conductor (OC), thereby forming a low-resistance region in the semiconductor layer 108. In this manner, the resistance of the regions corresponding to the source and drain regions of the semiconductor layer 108 can be made lower than that of the channel formation region. Therefore, the channel formation region and the source and drain regions having lower resistance than the channel formation region can be separately formed in the semiconductor layer 108. As a result, in the transistor 100G, regions corresponding to the source and drain electrodes can be formed in the semiconductor layer 108 without providing the conductive layer 112b. Therefore, in the transistor 100G, the conductive layer 112b is not provided, and therefore the number of steps required for manufacturing the transistor can be reduced.

[0268] With respect to the transistor 100G, the contents described for the transistor 100 can be referred to for the points other than those mentioned above.

[0269] 7B illustrates a structural example of a transistor 100H that has a different structure from the transistor 100 illustrated in FIGS. 1A to 2. FIG. 7B is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view illustrated in FIG.

[0270] The transistor 100H shown in FIG. 7B differs from the transistor 100 shown in FIG. 1B primarily in that the insulating layer 195 is provided only inside the opening 143 and not on the insulating layer 106 outside the opening 143.

[0271] In a vertical transistor such as the transistor 100, the area with the largest step or unevenness is on the conductive layer 104 within the opening 143. Therefore, simply filling this area with the insulating layer 195, as in the case of the transistor 100H, can effectively improve the flatness of the top surface of the transistor. Furthermore, because the side surfaces of the conductive layer 104 are exposed outside the opening 143, for example, when stacking an element such as another transistor on the transistor 100H, the conductive layer 104 and the element can be connected simply by depositing a conductive layer that serves as an electrode of the element on the transistor 100H. This eliminates the need to provide a separate plug for connecting them, potentially reducing the number of processes.

[0272] Regarding the transistor 100H, the contents described for the transistor 100 can be referred to for the points other than those mentioned above.

[0273] <Configuration Example 10> Fig. 8 shows a configuration example of a transistor 100I having a different configuration from the transistor 100D shown in Fig. 4B. Fig. 8 is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view shown in Fig. 1A.

[0274] 8 has a structure in which the conductive layer 104 is removed from the transistor 100D shown in FIG. 5B. In this structure, the conductive layer 114 functions as the only gate electrode of the transistor 100I.

[0275] 1A to 2 also have only one gate electrode, but the transistor 100 differs from the transistor 100 in that the semiconductor layer (semiconductor layer 108) surrounds the gate electrode (conductive layer 104) in a plan view, whereas the transistor 100I has a gate electrode (conductive layer 114) surround the semiconductor layer (semiconductor layer 108) in a plan view.

[0276] In the transistor 100I, the surface of the semiconductor layer 108 on which a channel is formed faces the conductive layer 114, and therefore, the surface can be prevented from being directly affected by damage caused by film formation of a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108. Therefore, the transistor 100I may be able to have a semiconductor layer 108 (particularly a channel formation region) with fewer defects than the transistor 100.

[0277] With respect to the transistor 100I, the contents described for the transistor 100 and the transistor 100D can be referred to except for the points described above.

[0278] <Manufacturing Method Example> A manufacturing method of a transistor according to one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100 illustrated in FIG. 1B and the like will be described as an example.

[0279] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0280] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when forming films using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0281] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0282] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0283] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0284] CVD and ALD differ from sputtering, in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity. Therefore, it is suitable, for example, for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0285] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film whose composition changes continuously by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0286] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0287] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0288] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0289] There are two typical photolithography methods: one is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed; the other is a method in which a photosensitive thin film is formed, and then the thin film is exposed to light and developed to be processed into a desired shape.

[0290] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0291] For etching the thin film, for example, dry etching, wet etching, or sandblasting can be used.

[0292] Typically, a polishing method such as CMP can be suitably used as the planarization treatment of the thin film. Alternatively, a reflow method, in which the conductive layer is subjected to a heat treatment to fluidize it, can be suitably used. Alternatively, a combination of the reflow method and CMP can be used.

[0293] Alternatively, a process may be used in which a planarizing film is formed on an uneven film surface and then highly anisotropically etched (e.g., dry etching) on ​​the planarizing film to form a film with a flat upper surface, or a process may be used in which a planarizing film and a photoresist are formed in that order on the uneven film surface and then highly anisotropically etched on the planarizing film and the photoresist to fill the recesses with only the planarizing film and flatten the entire upper surface (these processes are sometimes referred to as etch-back processes). The etch-back process does not require a high-temperature (e.g., about 800°C) heating process as in the reflow process, and therefore there is no need to worry about damage to the device during fabrication due to the heating process. Furthermore, the etch-back process is suitable because it can be applied to devices on large substrates that are difficult to process using CMP due to the effects of warping, etc.

[0294] Other examples of the planarization treatment for a thin film include dry etching and plasma treatment. The polishing, dry etching, and plasma treatment may be performed multiple times, or a combination of these may be performed. When a combination of these treatments is performed, the order of the steps is not particularly limited, and may be appropriately determined according to the unevenness of the surface to be treated.

[0295] To precisely process a thin film to a desired thickness, for example, a CMP method is used. In this method, the thin film is first polished at a constant processing speed until a portion of the top surface thereof is exposed. Then, the thin film is polished at a slower processing speed until the thin film reaches the desired thickness, thereby enabling highly precise processing.

[0296] Methods for detecting the end point of polishing include an optical method in which light is irradiated onto the surface of the surface to be treated and changes in the reflected light are detected, a physical method in which changes in the polishing resistance that the processing device receives from the surface to be treated are detected, and a method in which magnetic field lines are applied to the surface to be treated and changes in the magnetic field lines due to the eddy currents that are generated are used.

[0297] After the upper surface of the thin film is exposed, the thickness of the thin film can be controlled with high precision by performing a polishing process at a slow processing speed while monitoring the thickness of the thin film by an optical method such as a laser interferometer. If necessary, the polishing process may be performed multiple times until the thin film reaches the desired thickness.

[0298] 9A to 14B illustrate a method for manufacturing the transistor 100. Each diagram illustrates a cross-sectional view taken along dashed dotted line A1-A2 in the plan view of FIG.

[0299] First, a conductive film to be the conductive layer 112a is formed over the substrate 102, and then part of the conductive film is removed to form the conductive layer 112a (FIG. 9A). The conductive film can be formed by, for example, a sputtering method. The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0300] Subsequently, an insulating film 197f is formed on the conductive layer 112a and the substrate 102 (FIG. 9B).

[0301] The insulating film 197f can be made of any of the materials that can be used for the insulating layer 197 described above. For example, when an organic insulating material such as polyimide resin is used as the insulating film 197f, a thick insulating film 197f can be easily formed by a method such as spin coating. Therefore, the insulating film 197f having a substantially flat upper surface as shown in FIG. 9B can be formed simply by a film formation process.

[0302] In contrast, for example, when an inorganic insulating material such as silicon oxide is used as the insulating film 197f, it is necessary to form the film using a method such as CVD or sputtering, and therefore it is difficult from the standpoint of productivity to form a thick insulating film 197f made of the organic insulating material described above.

[0303] Therefore, when an inorganic insulating material is used for the insulating film 197f, it is preferable to form the insulating film 197f at least thicker than the conductive layer 112a, and then form a photoresist 191a on the insulating film 197f, as shown in FIG. 13A . Because the photoresist can be formed thick using techniques such as spin coating, the upper surface of the photoresist 191a can be made roughly flat by overlaying it on the insulating film 197f. While either a positive or negative material may be used for the photoresist 191a, it is preferable that the material have an etching rate roughly equal to that of the insulating film 197f during the subsequent etch-back process. This allows for highly anisotropic etching of the photoresist 191a and the insulating film 197f.

[0304] 9B, the insulating film 197f is etched back, and in the next step shown in FIG. 13A, the photoresist 191a and the insulating film 197f are etched back to expose the conductive layer 112a. This process forms an insulating layer 197 whose upper surface is approximately the same height as the conductive layer 112a (FIG. 9C).

[0305] Although the above example shows the case where insulating layer 197 is formed by etching back insulating film 197f, this is not a limitation. For example, when an organic insulating material such as polyimide resin is used as insulating film 197f, it may be possible to form insulating layer 197 shown in Fig. 9C simply by a process such as spin coating by adjusting the film thickness of insulating film 197f when formed as shown in Fig. 9B to be approximately the same as that of conductive layer 112a. In this case, the subsequent etch-back process is not required, which is preferable because it reduces the number of steps.

[0306] Subsequently, the insulating films 110a_f, 110b_f, and 110c_f are formed in this order over the conductive layer 112a and the insulating layer 197 (FIG. 9D).

[0307] The insulating film 110a_f can be formed using any of the materials that can be used for the insulating layer 110a described above.

[0308] For example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be suitably used for the insulating film 110a_f.

[0309] Specifically, the insulating film 110a_f can be formed by, for example, a silicon nitride film by a sputtering method, a PEALD method, or an aluminum oxide film by a sputtering method.

[0310] Alternatively, for example, a structure in which aluminum oxide and silicon nitride are stacked can be used, for example, a structure in which aluminum oxide formed by sputtering and silicon nitride formed by PEALD are stacked.

[0311] The insulating film 110b_f can be formed using any of the materials that can be used for the insulating layer 110b described above.

[0312] For example, silicon oxide, silicon oxynitride, or the like can be suitably used as the insulating film 110b_f.

[0313] Specifically, as the insulating film 110b_f, for example, a silicon oxide film can be formed by a sputtering method, a silicon oxide film can be formed by a PECVD method, or a silicon oxynitride film can be formed by a PECVD method.

[0314] Alternatively, for example, a silicon oxide film formed by sputtering and a silicon oxide or silicon oxynitride film formed by PECVD can be stacked and used.

[0315] After the insulating film 110b_f is formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be released from the surface and the interior of the insulating film 110b_f.

[0316] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating film 110b_f as much as possible. The heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. By using an RTA device, the heat treatment time can be shortened.

[0317] After the heat treatment, a step of supplying oxygen to the insulating film 110b_f may be performed. For example, after the insulating film 110b_f is formed, a metal oxide layer may be formed over the insulating film 110b_f to supply oxygen to the insulating film 110b_f. Alternatively, heat treatment may be performed after the metal oxide layer is formed. By performing heat treatment after the metal oxide layer is formed, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110b_f, and oxygen can be contained in the insulating film 110b_f. The oxygen supplied to the insulating film 110b_f is supplied to the semiconductor layer 108 in a later step, thereby forming oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0318] After the metal oxide layer is formed or after the heat treatment, oxygen may be supplied to the insulating film 110b_f through the metal oxide layer. Examples of a method for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be preferably used. Examples of apparatus that convert gas into plasma using high-frequency power include a plasma etching apparatus and a plasma ashing apparatus.

[0319] The metal oxide layer may be an insulating layer or a conductive layer, and may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0320] For the metal oxide layer, it is preferable to use an oxide material containing one or more of the same elements as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be applied to the semiconductor layer 108. This allows the metal oxide layer to be formed using the same sputtering target as that for the semiconductor layer 108, thereby reducing manufacturing costs.

[0321] When a metal oxide material containing indium and gallium is used for the metal oxide layer, a material having a higher gallium content than the semiconductor layer 108 can be used. By using a material having a higher gallium content for the metal oxide layer, the blocking property against oxygen can be further improved. This is preferable because oxygen contained in the insulating film 110b_f can be prevented from being released to the outside.

[0322] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, the metal oxide layer is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be suitably supplied to the insulating film 110b_f during the formation of the metal oxide layer.

[0323] Next, the metal oxide layer is removed, for example, by wet etching.

[0324] The process of supplying oxygen to the insulating film 110b_f is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like may be supplied to the insulating film 110b_f by ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that suppresses oxygen desorption may be formed over the insulating film 110b_f, and then oxygen may be supplied to the insulating film 110b_f through the film. The film is preferably removed after supplying oxygen. The film that suppresses oxygen desorption may be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten.

[0325] The insulating film 110c_f can be formed using any of the materials that can be used for the insulating layer 110c described above.

[0326] For a material and a deposition method that can be used for the insulating film 110c_f, the above description of a material and a deposition method that can be used for the insulating film 110a_f can be referred to.

[0327] Next, a conductive film to be the conductive layer 112b is formed over the insulating film 110c_f, and part of the conductive film is removed to form the conductive layer 112b_e ( FIG. 10A ). The conductive layer 112b_e is formed to have a region overlapping with the conductive layer 112a.

[0328] The conductive layer 112b_e can be formed using any of the above-described materials that can be used for the conductive layer 112b as appropriate. The conductive layer 112b_e can be formed by a sputtering method, for example.

[0329] Subsequently, an insulating film 198f is formed on the conductive layer 112b_e and the insulating film 110c_f (FIG. 10B).

[0330] The insulating film 198f can be made of any of the materials that can be used for the insulating layer 198 described above. For example, when an organic insulating material such as polyimide resin is used as the insulating film 198f, a thick insulating film 198f can be easily formed by a method such as spin coating. Therefore, the insulating film 198f having a substantially flat upper surface as shown in FIG. 10B can be formed simply by the film formation process.

[0331] In contrast, for example, when an inorganic insulating material such as silicon oxide is used as the insulating film 198f, it is necessary to form the film using a method such as CVD or sputtering, and therefore it is difficult from the standpoint of productivity to form a thick insulating film 198f made of the above-mentioned organic insulating material.

[0332] Therefore, when an inorganic insulating material is used for the insulating film 198f, it is preferable to form the insulating film 198f at least thicker than the conductive layer 112b_e, and then form a photoresist 191b on the insulating film 198f, as shown in FIG. 13B . Because the photoresist can be formed into a thick film using a technique such as spin coating, the upper surface of the photoresist 191b can be made substantially flat by overlaying it on the insulating film 198f. While either a positive or negative material may be used for the photoresist 191b, it is preferable for the material to have an etching rate substantially equal to that of the insulating film 198f during the subsequent etch-back process. This allows for highly anisotropic etching of the photoresist 191b and the insulating film 198f.

[0333] 10B, the insulating film 198f is etched back, and in the next step of FIG. 13B, the photoresist 191b and the insulating film 198f are etched back to expose the conductive layer 112b_e. This process forms an insulating layer 198 whose upper surface is approximately the same height as the conductive layer 112b_e (FIG. 10C).

[0334] Although the above example shows the formation of the insulating layer 198 by etching back the insulating film 198f, this is not a limitation. For example, when an organic insulating material such as polyimide resin is used as the insulating film 198f, the insulating layer 198 shown in FIG. 10C may be formed by simply performing a process such as spin coating by adjusting the film thickness of the insulating film 198f when it is formed to be approximately the same as that of the conductive layer 112b_e shown in FIG. 10B. In this case, the subsequent etch-back process is not required, which is preferable because it reduces the number of steps.

[0335] Next, a process is performed to remove parts of the conductive layer 112b_e, the insulating film 110c_f, the insulating film 110b_f, and the insulating film 110a_f, thereby forming an opening 143 that reaches the conductive layer 112a. For example, a dry etching method can be suitably used for this process. By this process, the conductive layer 112b, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a, each having an opening, are formed ( FIG. 11A ).

[0336] Next, a semiconductor film that will become the semiconductor layer 108 is formed in contact with the top surface of the conductive layer 112a in the opening 143, the side surfaces of the insulating layer 110 (insulating layers 110a, 110b, and 110c) in the opening 143, the side surfaces of the conductive layer 112b in the opening 143, and the top surface of the conductive layer 112b. Then, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108 ( FIG. 11B ). The semiconductor layer 108 is provided so as to have a region that overlaps with the opening 143. Furthermore, the semiconductor layer 108 is provided so as to have a region where an end portion thereof is in contact with the conductive layer 112b.

[0337] For the semiconductor film that becomes the semiconductor layer 108, the above-described materials that can be used for the semiconductor layer 108 can be used as appropriate.

[0338] A sputtering method, for example, can be used to form the semiconductor film that becomes the semiconductor layer 108. For example, when a metal oxide is used for the semiconductor layer 108, the semiconductor layer 108 can be formed by a sputtering method using a metal oxide target. The sputtering method is preferable because a film with a low hydrogen content can be formed relatively easily.

[0339] When a metal oxide is used for the semiconductor layer 108, the semiconductor layer 108 can be formed by an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0340] For example, when forming an In—Ga—Zn oxide, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0341] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and the like can be used.

[0342] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0343] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0344] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0345] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0346] The ALD method is preferably used to form the semiconductor film that becomes the semiconductor layer 108 because the semiconductor layer 108 can be formed on the side surface of the insulating layer 110 with a uniform thickness.

[0347] Heat treatment may be performed after the semiconductor film to be the semiconductor layer 108 is formed. The heat treatment can reduce water and hydrogen contained in the semiconductor film and supply oxygen to the semiconductor film from the insulating layer 110. Note that the heat treatment may be performed after the semiconductor film is processed.

[0348] The substrate temperature during the formation of the semiconductor layer 108 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0349] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the oxygen flow rate ratio, the higher the crystallinity of the formed metal oxide layer.

[0350] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, and the insulating layer 198 (FIG. 11C). The insulating layer 106 has regions in contact with the top and side surfaces of the semiconductor layer 108, the top surface of the conductive layer 112b, and the top surface of the insulating layer 198.

[0351] The insulating layer 106 can be formed using any of the materials described above as appropriate.

[0352] The insulating layer 106 can be formed by, for example, an ALD method. The ALD method is preferable because it allows the insulating layer 106 to be formed with good coverage over the semiconductor layer 108 formed to cover the opening 143. Note that, if the semiconductor layer 108 can be sufficiently covered, a method other than the ALD method may be used to form the insulating layer 106. For example, a PECVD method, a sputtering method, or the like can be used. This allows the insulating layer 106 to be formed at a higher rate than when the ALD method is used, thereby improving productivity.

[0353] Subsequently, a conductive film to be the conductive layer 104 is formed over the insulating layer 106. The conductive film can be formed using any of the materials that can be used for the conductive layer 104 described above. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate. The conductive film is preferably formed in contact with the insulating layer 106 that faces the side surface of the insulating layer 110 in the opening 143. Therefore, the conductive film is preferably formed using a method that has good coverage or embedding properties, and more preferably using a CVD method, an ALD method, or the like.

[0354] Next, the conductive film that becomes the conductive layer 104 is processed to form the conductive layer 104 ( FIG. 12A ). The conductive layer 104 is formed so as to have a region that overlaps with the semiconductor layer 108 in a plan view. The conductive layer 104 may be formed by photolithography. The above processing can be performed by dry etching or wet etching. Processing by dry etching is suitable for microfabrication.

[0355] Subsequently, an insulating film 195f is formed on the conductive layer 104 and the insulating layer 106 (FIG. 12B).

[0356] The insulating film 195f can be made of any of the materials that can be used for the insulating layer 195 described above. For example, when an organic insulating material such as polyimide resin is used as the insulating film 195f, a thick insulating film 195f can be easily formed by a method such as spin coating. Therefore, the insulating film 195f having a substantially flat upper surface as shown in FIG. 12B can be formed simply by a film formation process.

[0357] In contrast, for example, when an inorganic insulating material such as silicon nitride is used as the insulating film 195f, it is necessary to form the film using a method such as CVD or sputtering, and therefore it is difficult from the standpoint of productivity to form a thick insulating film 195f made of the above-mentioned organic insulating material.

[0358] Therefore, when an inorganic insulating material is used for the insulating film 195f, it is preferable to form the insulating film 195f to a thickness sufficient to fill at least the entire opening 143, and then form a photoresist 191c on the insulating film 195f, as shown in FIG. 14A. Because the photoresist can be formed thick using techniques such as spin coating, the upper surface of the photoresist 191c can be made roughly flat by overlaying it on the insulating film 195f. While either a positive or negative material may be used for the photoresist 191c, it is preferable for the material to have an etching rate roughly equal to that of the insulating film 195f during the subsequent etch-back process. This allows for highly anisotropic etching of the photoresist 191c and the insulating film 195f.

[0359] 12B, the insulating film 195f is etched back, and in the next step of FIG. 14A, the photoresist 191c and the insulating film 195f are etched back. This process forms an insulating layer 195 that has a flat upper surface and fills the entire opening 143 (FIG. 1B).

[0360] Although the above example shows the case where the insulating layer 195 is formed by etching back the insulating film 195f, this is not limitative. For example, if an organic insulating material such as polyimide resin is used as the insulating film 195f, the insulating layer 195 can be formed without etching back.

[0361] 12A is formed, the insulating film 195f is formed on the conductive layer 104 and the insulating layer 106. However, at this time, the insulating film 195f is formed to have a thickness thinner than that in the case where the etch-back process is performed.

[0362] 14B , light 139 (for example, visible light or ultraviolet light) is irradiated onto insulating film 195f through mask 136 to expose regions of insulating film 195f that do not overlap with mask 136. Here, when a positive photosensitive resin composition such as polyimide resin is used for insulating film 195f, light 139 is irradiated via mask 136 onto regions where insulating layer 195 will not be formed in a later step.

[0363] Subsequently, development is performed to remove the exposed regions of the insulating film 195f, thereby forming the insulating layer 195. At this time, the insulating layer 195 is formed only in the region overlapping the opening 143, and the insulating film 195f outside the opening 143 is removed. For example, as in the transistor 100H shown in FIG. 7B , the insulating layer 195 is formed embedded inside the opening 143. When a polyimide resin is used for the insulating film 195f, an alkaline solution is preferably used as the developer, such as a tetramethylammonium hydroxide (TMAH) aqueous solution. After development, a process for removing residues (so-called scum) from development may be performed. For example, the residues can be removed by ashing using oxygen plasma. Forming the insulating layer 195 without an etch-back process is preferable because it reduces the number of processes compared to when an etch-back process is performed.

[0364] Through the above steps, a semiconductor device including the transistor 100 (or the transistor 100I in the case where the insulating layer 195 is formed without etch-back treatment) can be manufactured.

[0365] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0366] Embodiment 2 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0367] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used in electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0368] The display device of the present embodiment can be a high-definition display device, and can therefore be used as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and eyeglass-type AR devices.

[0369] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0370] [Display Device 50A] FIG. 15 shows a perspective view of the display device 50A.

[0371] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 15, the substrate 152 is indicated by a dashed line.

[0372] The display device 50A has a display unit 168, a connection unit 140, a circuit unit 164, wiring 165, etc. Fig. 15 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 15 can also be said to be a display module having the display device 50A, an IC, and an FPC.

[0373] The connection portion 140 is provided outside the display portion 168. The connection portion 140 can be provided along one side or multiple sides of the display portion 168. There may be one or multiple connection portions 140. FIG. 15 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 168. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0374] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0375] The wiring 165 has a function of supplying signals and power to the display portion 168 and the circuit portion 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.

[0376] 15 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method, or the like.

[0377] A transistor of one embodiment of the present invention can be applied to, for example, one or both of the display portion 168 and the circuit portion 164 of the display device 50A.

[0378] For example, when the transistor of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the transistor of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the transistor of one embodiment of the present invention has favorable electrical characteristics, its use in a display device can improve the reliability of the display device.

[0379] The display section 168 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 210. Fig. 15 shows an enlarged view of one pixel 210.

[0380] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0381] The pixel 210 shown in FIG. 15 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light.

[0382] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0383] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that employ a microcapsule system, an electrophoresis system, an electrowetting system, or an electronic liquid powder (registered trademark) system, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may also be used.

[0384] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0385] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs, OLEDs (organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0386] Examples of the light-emitting substance contained in the light-emitting element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (quantum dot material, etc.).

[0387] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0388] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0389] In this embodiment, a case where a light-emitting element is used as a display element will be mainly described as an example.

[0390] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0391] Figure 16 shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 168, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0392] 16 includes transistors 205D, 205R, 205G, and 205B, as well as light-emitting elements 130R, 130G, and 130B between substrates 151 and 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0393] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations, and facilitating improvements in brightness and reliability.

[0394] The display device 50A is a top-emission type, which allows transistors and the like to be arranged overlapping the light-emitting region of the light-emitting element, thereby enabling a higher pixel aperture ratio than a bottom-emission type.

[0395] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured using the same material and through the same process.

[0396] In this embodiment, OS transistors are used as the transistors 205D, 205R, 205G, and 205B. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistors according to one embodiment of the present invention in both the display portion 168 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 168, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. The description of the previous embodiment can be referred to for the transistors according to one embodiment of the present invention.

[0397] Specifically, the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B each include a conductive layer 104 functioning as one of the first gate electrode and the second gate electrode, a conductive layer 114 functioning as the other of the first gate electrode and the second gate electrode, an insulating layer 106 functioning as a gate insulating layer, an insulating layer 110s functioning as a gate insulating layer, a conductive layer 112a functioning as one of the source electrode and the drain electrode, a conductive layer 112b functioning as the other of the source electrode and the drain electrode, and a semiconductor layer 108 having a metal oxide.

[0398] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0399] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0400] The display device of this embodiment mode may also include a transistor using silicon for a channel formation region (Si transistor).

[0401] Examples of silicon include single-crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, a transistor having an LTPS semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used. The LTPS transistor has high field-effect mobility and favorable frequency characteristics.

[0402] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher source-drain breakdown voltage than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0403] Furthermore, when a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0404] Furthermore, in terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage is changed, thereby stabilizing the light-emitting luminance of the light-emitting element.

[0405] The transistors included in the circuit portion 164 and the transistors included in the display portion 168 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 168 may all have the same structure or may have two or more types.

[0406] All the transistors included in the display portion 168 may be OS transistors, all the transistors included in the display portion 168 may be Si transistors, or some of the transistors included in the display portion 168 may be OS transistors and the rest may be Si transistors.

[0407] For example, by using both an LTPS transistor and an OS transistor in the display portion 168, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0408] For example, one of the transistors included in the display portion 168 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and the drain of the driving transistor is connected to a pixel electrode of the light-emitting element. An LTPS transistor is preferably used as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0409] On the other hand, another transistor included in the display portion 168 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly reduced (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0410] An insulating layer 195 is provided to cover the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B.

[0411] The insulating layer 195 preferably functions as a protective layer for the transistor. The insulating layer 195 is preferably made of a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 195 to function as a barrier layer. Specific examples of materials that can be used for the insulating layer 195 can be referred to the description of the previous embodiment. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device.

[0412] Furthermore, it is preferable that the outermost layer of the insulating layer 195 functions as an etching protection layer, which can prevent recesses from being formed in the insulating layer 195 when processing the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 195 when processing the pixel electrodes 111R, 111G, 111B, etc.

[0413] On the insulating layer 195, the light emitting elements 130R, 130G, and 130B are provided.

[0414] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 195, an EL layer 113R on the pixel electrode 111R, and a common electrode 135 on the EL layer 113R. The light-emitting element 130R shown in Fig. 16 emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0415] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 195, an EL layer 113G on the pixel electrode 111G, and a common electrode 135 on the EL layer 113G. The light-emitting element 130G shown in Fig. 16 emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0416] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 195, an EL layer 113B on the pixel electrode 111B, and a common electrode 135 on the EL layer 113B. The light-emitting element 130B shown in Fig. 16 emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0417] 16, the EL layers 113R, 113G, and 113B are all shown with the same film thickness, but this is not limited to this. The film thicknesses of the EL layers 113R, 113G, and 113B may be different. For example, it is preferable to set the film thicknesses of the EL layers 113R, 113G, and 113B to thicknesses corresponding to the optical path lengths that intensify the light emitted by each layer. This realizes a microcavity structure and can increase the color purity of the light emitted from each light-emitting element.

[0418] The pixel electrode 111R is connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106 and the insulating layer 195. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0419] Ends of the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall (also referred to as a bank, spacer, or bank). The insulating layer 237 can be formed to have a single-layer structure or a stacked-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the material that can be used for the insulating layer 195 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0420] The common electrode 135 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 135 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0421] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0422] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. That is, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0423] Materials for forming the pair of electrodes of the light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Examples of such materials include aluminum alloys, such as an aluminum-nickel-lanthanum alloy (Al-Ni-La), and silver-magnesium alloys and silver-palladium-copper alloys (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0424] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0425] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0426] The EL layer 113R, the EL layer 113G, and the EL layer 113B are each provided in an island shape. In FIG. 16 , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 16 , but this is not limited to this. In other words, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both overlapping portions between adjacent EL layers and portions between adjacent EL layers that do not overlap but are spaced apart.

[0427] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0428] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0429] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and high hole-transport properties) or a TADF material may be used.

[0430] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, the energy transfer becomes smooth, allowing efficient emission. This configuration allows the light-emitting element to simultaneously achieve high efficiency, low-voltage operation, and a long life.

[0431] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar material and a TADF material.

[0432] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. Each of the layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink-jet method, or a coating method.

[0433] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, compared to a single structure, the tandem structure can reduce the current required to achieve the same brightness, thereby improving reliability. The tandem structure may also be called a stack structure.

[0434] In Figure 16, when light-emitting elements with a tandem structure are used, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0435] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 149. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 16 , the space between the substrates 152 and 151 is filled with the adhesive layer 149, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 149 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 149.

[0436] The protective layer 131 is preferably provided in at least the display portion 168, and is preferably provided so as to cover the entire display portion 168. The protective layer 131 is preferably provided so as to cover not only the display portion 168, but also the connection portion 140 and the circuit portion 164. The protective layer 131 is preferably provided up to the edge of the display device 50A. On the other hand, in the connection portion 204, the FPC 172 and the conductive layer 167 are connected to each other, so that a portion where the protective layer 131 is not provided is generated.

[0437] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0438] The protective layer 131 may have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0439] The protective layer 131 has an inorganic film, which prevents oxidation of the common electrode 135 and prevents impurities (e.g., water, oxygen, etc.) that cause deterioration of the light-emitting element from entering, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0440] For the protective layer 131, for example, an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an insulating oxynitride film, or an insulating nitride oxide film can be used. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably includes an insulating nitride film or an insulating nitride oxide film, and more preferably includes an insulating nitride film.

[0441] Alternatively, an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like may be used for the protective layer 131. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 135. The inorganic film may further contain nitrogen.

[0442] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0443] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (for example, water, oxygen, etc.) that may cause deterioration of the light-emitting element can be prevented from entering the EL layer side.

[0444] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 195.

[0445] A connection portion 204 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 204, a wiring 165 is connected to the FPC 172 via a conductive layer 166, a conductive layer 167, and a connection layer 242. The wiring 165 is an example of a conductive layer having a single-layer structure obtained by processing the same conductive film as the conductive layer 112a. The conductive layer 166 is an example of a conductive layer having a single-layer structure obtained by processing the same conductive film as the conductive layer 112b. The conductive layer 167 is an example of a conductive layer having a single-layer structure obtained by processing the same conductive film as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B. The conductive layer 167 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 172 to be connected via the connection layer 242.

[0446] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 135) contains a material that transmits visible light.

[0447] A light-shielding layer 117 is preferably provided on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, the circuit section 164, and the like.

[0448] Furthermore, a colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0449] Various optical members can be disposed on the outer side of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. Furthermore, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outer side of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0450] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate may be used for at least one of the substrates 151 and 152.

[0451] Substrates 151 and 152 may each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrates 151 and 152 may be made of glass having a thickness sufficient to provide flexibility.

[0452] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0453] The adhesive layer 149 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0454] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0455] 17 is different from the display device 50A mainly in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used for each subpixel of each color. Note that in the following description of the display device, descriptions of parts that are the same as those of the display devices described above may be omitted.

[0456] The display device 50B shown in Figure 17 has, between the substrate 151 and the substrate 152, a transistor 205D, a transistor 205R, a transistor 205G, a transistor 205B, a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0457] The light emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 135 on the EL layer 113. The light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0458] The light emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0459] The light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0460] The light-emitting elements 130R, 130G, and 130B each share the EL layer 113 and the common electrode 135. The configuration in which the EL layer 113 is common to the subpixels of each color can reduce the number of manufacturing steps compared to the configuration in which different EL layers are provided for the subpixels of each color.

[0461] 17 emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, respectively, to obtain light of a desired color.

[0462] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers may be selected such that the emission colors of the two light-emitting layers have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer have a complementary color relationship, a configuration in which the light-emitting element as a whole emits white light can be obtained. Furthermore, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers may be combined to form a configuration in which the light-emitting element as a whole emits white light.

[0463] The EL layer 113 preferably includes, for example, a light-emitting layer having a light-emitting substance that emits blue light and a light-emitting layer having a light-emitting substance that emits visible light with a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0464] A tandem structure is preferably used for the light-emitting element emitting white light. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light, in this order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and red light, and a light-emitting unit that emits blue light, in this order, or the like can be applied. For example, the number of layers of the light-emitting units and the order of the colors can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, and the number of layers of the light-emitting layers in light-emitting unit X and the order of the colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, another layer can be provided between the two light-emitting layers.

[0465] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 17 emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer can be provided between the light-emitting element 130R or 130G and the substrate 152 to convert the blue light emitted by the light-emitting element 130R or 130G into light with a longer wavelength, thereby extracting red or green light. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. A portion of the light emitted by the light-emitting element may be transmitted directly without being converted by the color conversion layer. By extracting the light transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0466] [Display Device 50C] A display device 50C shown in FIG. 18 differs from the display device 50B mainly in that it is a bottom-emission display device.

[0467] Light emitted from the light-emitting element is emitted toward the substrate 151. A material that is highly transparent to visible light is preferably used for the substrate 151. On the other hand, the light-transmitting property of a material used for the substrate 152 does not matter.

[0468] 18 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153. In addition, the coloring layer 132R (not shown), the coloring layer 132G, and the coloring layer 132B are provided on the insulating layer 106, and the insulating layer 195 is provided on the coloring layer 132R, the coloring layer 132G, and the coloring layer 132B.

[0469] The light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113, and a common electrode 135.

[0470] The light emitting element 130B overlapping the colored layer 132B has a pixel electrode 111B, an EL layer 113 and a common electrode 135.

[0471] The pixel electrodes 111G and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 135. In a bottom-emission display device, a low-resistance metal or the like can be used for the common electrode 135, which can suppress voltage drops caused by the resistance of the common electrode 135 and achieve high display quality.

[0472] The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced; therefore, in a bottom-emission display device, the aperture ratio of a pixel can be increased or the pixel size can be reduced.

[0473] [Display Device 50D] A display device 50D shown in FIG. 19 differs from the display device 50A mainly in that it has a light receiving element 130S.

[0474] The display device 50D has a light-emitting element and a light-receiving element in each pixel. In the display device 50D, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element.

[0475] In the display device 50D, in which pixels have a light-emitting element and a light-receiving element, the pixels have a light-receiving function, so that it is possible to detect contact or proximity of an object while displaying an image. Therefore, the display unit 168 has one or both of an imaging function and a sensing function in addition to an image display function. For example, in addition to displaying an image using all of the sub-pixels of the display device 50D, it is also possible for some sub-pixels to emit light as a light source, other sub-pixels to perform light detection, and the remaining sub-pixels to display an image.

[0476] Therefore, there is no need to provide a light receiving unit and a light source separately from the display device 50D, and the number of components in the electronic device can be reduced. For example, there is no need to provide a separate biometric authentication device or a capacitive touch panel for scrolling, etc. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing costs.

[0477] When a light receiving element is used as an image sensor, the display device 50D can capture an image using the light receiving element. For example, the image sensor can capture an image for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, etc.

[0478] The light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor). A touch sensor can detect an object (such as a finger, hand, or pen) when the object comes into direct contact with the display device. A non-contact sensor can detect an object without the object touching the display device.

[0479] The light receiving element 130S has a pixel electrode 111S on an insulating layer 195, a functional layer 113S on the pixel electrode 111S, and a common electrode 135 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50D.

[0480] The pixel electrode 111S is connected to a conductive layer 112b of the transistor 205S through an opening provided in the insulating layer 106 and the insulating layer 195.

[0481] The end of the pixel electrode 111S is covered with an insulating layer 237.

[0482] The common electrode 135 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B. The common electrode 135 shared by the light emitting element and the light receiving element is connected to the conductive layer 123 provided in the connection portion 140.

[0483] The functional layer 113S has at least an active layer (also referred to as a photoelectric conversion layer). The active layer includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors including organic compounds. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer will be described. By using an organic semiconductor, the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), which is preferable because a common manufacturing apparatus can be used.

[0484] The functional layer 113S may further include a layer containing a substance with high hole transport properties, a substance with high electron transport properties, or a bipolar substance (a substance with high electron transport properties and high hole transport properties) as a layer other than the active layer. Furthermore, without being limited to the above, the functional layer 113S may further include a layer containing a substance with high hole injection properties, a hole blocking material, a substance with high electron injection properties, or an electron blocking material. For the layer other than the active layer of the light-receiving element, for example, the material that can be used for the light-emitting element described above can be used.

[0485] The light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-receiving element can be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, ink-jet printing, or coating.

[0486] 20 is an example of a display device employing an MML (metal maskless) structure. That is, the display device 50E has light-emitting elements fabricated without using a fine metal mask. The stacked structure from the substrate 151 to the insulating layer 195 and the stacked structure from the protective layer 131 to the substrate 152 are similar to those of the display device 50A, and therefore will not be described here.

[0487] In FIG. 20, a light emitting element 130R, a light emitting element 130G, and a light emitting element 130B are provided on an insulating layer 195.

[0488] The light-emitting element 130R includes a conductive layer 124R on the insulating layer 195, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 134 on the layer 133R, and a common electrode 135 on the common layer 134. The light-emitting element 130R shown in FIG. 20 emits red light (R). The layer 133R includes a light-emitting layer that emits red light. In the light-emitting element 130R, the layer 133R and the common layer 134 can be collectively referred to as an EL layer. One or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.

[0489] The light-emitting element 130G includes a conductive layer 124G on the insulating layer 195, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 134 on the layer 133G, and a common electrode 135 on the common layer 134. The light-emitting element 130G shown in FIG. 20 emits green light (G). The layer 133G includes a light-emitting layer that emits green light. In the light-emitting element 130G, the layer 133G and the common layer 134 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

[0490] The light-emitting element 130B has a conductive layer 124B on the insulating layer 195, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 134 on the layer 133B, and a common electrode 135 on the common layer 134. The light-emitting element 130B shown in FIG. 20 emits blue light (B). The layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, the layer 133B and the common layer 134 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.

[0491] In this specification and the like, among the EL layers included in the light-emitting elements, layers provided in an island shape for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is referred to as a common layer 134. Note that in this specification and the like, the layers 133R, 133G, and 133B may be referred to as island-shaped EL layers, EL layers formed in an island shape, or the like, without including the common layer 134.

[0492] The layers 133R, 133G, and 133B are spaced apart from one another. By providing an island-shaped EL layer for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This makes it possible to prevent unintended light emission due to crosstalk, and realize a display device with extremely high contrast.

[0493] 20, the layers 133R, 133G, and 133B are all shown to have the same film thickness, but this is not limitative. The layers 133R, 133G, and 133B may have different film thicknesses.

[0494] The conductive layer 124R is connected to the conductive layer 112b of the transistor 205R through an opening provided in the insulating layer 106 and the insulating layer 195. Similarly, the conductive layer 124G is connected to the conductive layer 112b of the transistor 205G, and the conductive layer 124B is connected to the conductive layer 112b of the transistor 205B.

[0495] The conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 195. A layer 128 is buried in the recesses of the conductive layers 124R, 124G, and 124B, respectively.

[0496] The layer 128 has a function of planarizing the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B. The conductive layers 126R, 126G, and 126B, which are connected to the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B, are provided on the conductive layer 124R, the conductive layer 124G, and the conductive layer 128, respectively. Therefore, the regions overlapping with the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixel. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layer 124R and the conductive layer 126R.

[0497] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. In particular, the layer 128 is preferably formed using an insulating material, and more preferably using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 237 can be used for the layer 128.

[0498] 20 shows an example in which the top surface of layer 128 has a flat portion, but there are no particular limitations on the shape of layer 128. The top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0499] Furthermore, the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other. For example, the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.

[0500] The end of the conductive layer 126R may be flush with the end of the conductive layer 124R, or may cover the side surface of the end of the conductive layer 124R. The end of each of the conductive layers 124R and 126R preferably has a tapered shape. Specifically, the end of each of the conductive layers 124R and 126R preferably has a tapered shape with a taper angle of less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By tapering the side surface of the pixel electrode, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0501] The conductive layers 124G, 126G, 124B, and 126B are similar to the conductive layers 124R and 126R, respectively, and therefore will not be described in detail.

[0502] The top surface and side surfaces of the conductive layer 126R are covered with the layer 133R. Similarly, the top surface and side surfaces of the conductive layer 126G are covered with the layer 133G, and the top surface and side surfaces of the conductive layer 126B are covered with the layer 133B. Therefore, the entire regions where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting regions of the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B, respectively, thereby increasing the aperture ratio of the pixel.

[0503] Part of the top surface and side surfaces of each of the layers 133R, 133G, and 133B are covered with the insulating layer 125 and the insulating layer 127. A common layer 134 is provided on the layers 133R, 133G, and 133B and the insulating layer 125 and the insulating layer 127, and a common electrode 135 is provided on the common layer 134. The common layer 134 and the common electrode 135 are each a continuous film provided in common to a plurality of light-emitting elements.

[0504] 20, the insulating layer 237 shown in FIG. 16 and other figures is not provided between the conductive layer 126R and the layer 133R. In other words, the display device 50E does not have an insulating layer (also called a partition, bank, spacer, or the like) that contacts the pixel electrode and covers the upper edge of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This allows a high-definition or high-resolution display device to be obtained. Furthermore, a mask for forming the insulating layer is not required, thereby reducing the manufacturing cost of the display device.

[0505] As described above, the layers 133R, 133G, and 133B each have a light-emitting layer. The layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer. Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Because the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, providing one or both of a carrier transport layer and a carrier block layer on the light-emitting layer can prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.

[0506] The common layer 134 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 134 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 134 is shared by the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.

[0507] The side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layers 133R, 133G, and 133B with the insulating layer 125 interposed therebetween.

[0508] The side surfaces (and even part of the upper surfaces) of the layers 133R, 133G, and 133B are covered with at least one of the insulating layer 125 and the insulating layer 127, which prevents the common layer 134 (or the common electrode 135) from contacting the pixel electrodes and the side surfaces of the layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements, thereby improving the reliability of the light-emitting elements.

[0509] The insulating layer 125 is preferably in contact with each side surface of the layer 133R, the layer 133G, and the layer 133B. The insulating layer 125 being in contact with the layer 133R, the layer 133G, and the layer 133B can prevent the layer 133R, the layer 133G, and the layer 133B from peeling off, thereby improving the reliability of the light-emitting element.

[0510] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. The insulating layer 127 preferably covers at least a part of the side surface of the insulating layer 125.

[0511] By providing the insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, which reduces large unevenness in height on the surface on which layers (for example, the carrier injection layer and the common electrode) are formed on the island-shaped layers, thereby making the surface flatter, thereby improving the coverage of the carrier injection layer, the common electrode, and the like.

[0512] The common layer 134 and the common electrode 135 are provided over the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, a step is generated between a region where the pixel electrode and the island-shaped EL layer are provided and a region where the pixel electrode and the island-shaped EL layer are not provided (a region between light-emitting elements). In the display device of one embodiment of the present invention, the insulating layer 125 and the insulating layer 127 can flatten the step, thereby improving the coverage of the common layer 134 and the common electrode 135. Therefore, poor connection due to a step disconnection of the common layer 134 or the common electrode 135 can be suppressed. Furthermore, an increase in electrical resistance caused by a local thinning of the common electrode 135 due to the step can be suppressed.

[0513] The upper surface of the insulating layer 127 preferably has a highly flat shape. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of the insulating layer 127 preferably has a highly flat, smooth convex curved surface shape.

[0514] The insulating layer 125 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 125. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Aluminum oxide is particularly preferable because it has a high etching selectivity with respect to the EL layer and protects the EL layer in the formation of the insulating layer 127 described later. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method for the insulating layer 125, the insulating layer 125 can be formed with few pinholes and excellent protection of the EL layer. Alternatively, the insulating layer 125 may have a stacked-layer structure of a film formed by an ALD method and a film formed by a sputtering method. For example, the insulating layer 125 may have a stacked-layer structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.

[0515] The insulating layer 125 preferably functions as a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has a function of suppressing diffusion of at least one of water and oxygen. The insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) at least one of water and oxygen.

[0516] Note that in this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In addition, in this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of gettering a corresponding substance.

[0517] The insulating layer 125 has a function as a barrier insulating layer or a gettering function, which can suppress the intrusion of impurities (substances that can induce deterioration of the light-emitting element, typically at least one of water and oxygen) that can diffuse from the outside into each light-emitting element. With this structure, a highly reliable light-emitting element and further a highly reliable display device can be provided.

[0518] The insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. Furthermore, a low impurity concentration in the insulating layer 125 can improve the barrier properties against at least one of water and oxygen. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both of them.

[0519] The insulating layer 127 provided on the insulating layer 125 has a function of flattening large unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 135 is formed.

[0520] An insulating layer containing an organic material can be suitably used as the insulating layer 127. As the organic material, a photosensitive organic resin is preferably used, for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0521] The insulating layer 127 may also be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, or precursors of these resins. The insulating layer 127 may also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. The photosensitive resin may also be a photoresist. Either a positive-type material or a negative-type material may be used as the photosensitive resin.

[0522] The insulating layer 127 may be made of a material that absorbs visible light. The insulating layer 127 absorbs light emitted from the light-emitting element, thereby suppressing leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0523] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to form a black or nearly black resin layer.

[0524] This embodiment mode can be combined with other embodiment modes as appropriate.

[0525] Embodiment 3 In this embodiment, a structural example of a display device to which a semiconductor device of one embodiment of the present invention can be applied will be described.

[0526] Since the semiconductor device of one embodiment of the present invention can be extremely fine, a display device using the semiconductor device of one embodiment of the present invention can be a very high-resolution display device. For example, the display device of one embodiment of the present invention can be used in the display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a head-mounted display (HMD) for VR devices, and a glasses-type AR device.

[0527] 21A shows a perspective view of a display module 280. The display module 280 has a display device 200A and an FPC 290. Note that the display panel of the display module 280 is not limited to the display device 200A, and may be a display device 200B or a display device 200C, which will be described later.

[0528] The display module 280 has a substrate 291 and a substrate 292. The display module 280 has a display unit 281. The display unit 281 is an area for displaying an image.

[0529] 21B is a perspective view schematically illustrating the configuration on the substrate 291 side. A circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are stacked on the substrate 291. A terminal portion 285 for connecting to the FPC 290 is provided in a portion of the substrate 291 that does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are connected by a wiring portion 286 composed of a plurality of wirings.

[0530] The pixel section 284 has a plurality of periodically arranged pixels 284a. An enlarged view of one pixel 284a is shown on the right side of Fig. 21B. The pixel 284a has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light.

[0531] The pixel circuit portion 283 has a plurality of pixel circuits 283a arranged periodically. Each pixel circuit 283a is a circuit that controls the light emission of three light-emitting devices included in one pixel 284a. One pixel circuit 283a may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 283a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0532] The circuit portion 282 includes a circuit for driving each pixel circuit 283a of the pixel circuit portion 283. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. In addition, it may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 282 may constitute a part of the pixel circuit 283a. That is, the pixel circuit 283a may be composed of a transistor included in the pixel circuit portion 283 and a transistor included in the circuit portion 282.

[0533] The FPC 290 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 282. An IC may be mounted on the FPC 290.

[0534] The display module 280 can be configured such that one or both of the pixel circuit unit 283 and the circuit unit 282 are provided overlapping below the pixel unit 284, thereby enabling the aperture ratio (effective display area ratio) of the display unit 281 to be extremely high. For example, the aperture ratio of the display unit 281 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 284a can be arranged at an extremely high density, enabling the resolution of the display unit 281 to be extremely high. For example, the pixels 284a are preferably arranged in the display unit 281 at a resolution of 2,000 ppi to 30,000 ppi, preferably 3,000 ppi to 20,000 ppi, more preferably 5,000 ppi to 20,000 ppi, and even more preferably 6,000 ppi to 20,000 ppi.

[0535] Because such a display module 280 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays or eyeglass-type AR devices. For example, even in a configuration in which the display unit of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display unit 281, so even if the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 280 is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0536] 22 includes a substrate 331, a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a capacitor 240, and a transistor 320. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0537] Substrate 331 corresponds to substrate 291 in FIG. 21A.

[0538] The transistor 320 is a vertical channel transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. Any of the transistors described as examples in Embodiment 1 can be used as the transistor 320.

[0539] An insulating layer 332 is provided over the substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities, such as water or hydrogen, which may adversely affect the electrical characteristics of the transistor from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 108 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0540] An insulating layer 197 is provided on the insulating layer 332, and a conductive layer 112a is provided so as to be embedded in the insulating layer 197. Furthermore, an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and a conductive layer 112b on the insulating layer 110c are provided on the insulating layer 197 and the conductive layer 112a. Openings reaching the conductive layer 112a are provided in each of the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, and the conductive layer 112b. A semiconductor layer 108 is provided in contact with the top surface of the conductive layer 112a in the opening, the side surface of the insulating layer 110a in the opening, the side surface of the insulating layer 110b in the opening, the side surface of the insulating layer 110c in the opening, the side surface of the conductive layer 112b in the opening, and the top surface of the conductive layer 112b. An insulating layer 106 is provided on the semiconductor layer 108, and a conductive layer 104 is provided on the insulating layer 106. An insulating layer 195 is provided on the insulating layer 106 and the conductive layer 104. The top surface of the insulating layer 195 is planarized, and an insulating layer 266 is provided on the insulating layer 195.

[0541] The insulating layer 195 and the insulating layer 266 function as interlayer insulating layers. A barrier layer that prevents impurities, such as water or hydrogen, which may adversely affect the electrical characteristics of the transistor, from diffusing from the insulating layer 266 or the like to the transistor 320 may be provided between the insulating layer 266 and the insulating layer 195. An insulating film similar to the insulating layer 332 can be used as the barrier layer.

[0542] The plug 274 connected to the conductive layer 112b is provided so as to be embedded in the insulating layer 266, the insulating layer 195, and the insulating layer 106. Here, the plug 274 preferably includes a conductive layer 274a covering the side surfaces of the openings of the insulating layer 266, the insulating layer 195, and the insulating layer 106 and part of the top surface of the conductive layer 112b, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, the conductive layer 274a is preferably made of a conductive material through which hydrogen and oxygen do not easily diffuse.

[0543] Furthermore, a capacitor 240 is provided on the insulating layer 266. The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0544] The conductive layer 241 is provided over the insulating layer 266 and is buried in the insulating layer 254. The conductive layer 241 is connected to the conductive layer 112b of the transistor 320 by a plug 274. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0545] An insulating layer 255a is provided to cover the capacitor 240, an insulating layer 255b is provided over the insulating layer 255a, and an insulating layer 255c is provided over the insulating layer 255b.

[0546] An inorganic insulating film can be preferably used for each of the insulating layers 255a, 255b, and 255c. For example, it is preferable to use a silicon oxide film for the insulating layer 255a and the insulating layer 255c, and a silicon nitride film for the insulating layer 255b. This allows the insulating layer 255b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 255c is etched to form a recess, but the insulating layer 255c does not necessarily have to have a recess.

[0547] The light-emitting elements 130R, 130G, and 130B are provided over the insulating layer 255c. The above embodiments can be referred to for details of the light-emitting elements 130R, 130G, and 130B.

[0548] The light-emitting element 130R has a pixel electrode 111R, a layer 133R, a common layer 134, and a common electrode 135. The light-emitting element 130G has a pixel electrode 111G, a layer 133G, a common layer 134, and a common electrode 135. The light-emitting element 130B has a pixel electrode 111B, a layer 133B, a common layer 134, and a common electrode 135. The common layer 134 and the common electrode 135 are provided in common to the light-emitting elements 130R, 130G, and 130B.

[0549] Layer 133R of light-emitting element 130R contains a light-emitting organic compound that emits at least red light. Layer 133G of light-emitting element 130G contains a light-emitting organic compound that emits at least green light. Layer 133B of light-emitting element 130B contains a light-emitting organic compound that emits at least blue light. Layer 133R, layer 133G, and layer 133B can also be called EL layers, and each contains at least a layer (light-emitting layer) containing a light-emitting organic compound.

[0550] In the display device 200A, a separate light-emitting device is fabricated for each emitted color, resulting in a small change in chromaticity between light emitted at low and high luminance. Furthermore, because the layers 133R, 133G, and 133B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This allows for the realization of a high-resolution, high-quality display panel.

[0551] Insulating layers 125, 127, and 119 are provided in regions between adjacent light-emitting elements.

[0552] The insulating layer 119 is a part of the insulating film provided on the layer 133 (the layer 133R, the layer 133G, and the layer 133B) that remains when the layer 133 is processed, and is also referred to as a mask layer, a sacrificial layer, or the like. The insulating layer 119 can be formed using the same material as the insulating layer 125 described above.

[0553] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are connected to the conductive layer 112b of the transistor 320 via a plug 256 embedded in the insulating layers 255a, 255b, and 255c, a conductive layer 241 embedded in the insulating layer 254, and a plug 274. The height of the top surface of the insulating layer 255c and the height of the top surface of the plug 256 are the same or approximately the same. Various conductive materials can be used for the plug.

[0554] A protective layer 131 is provided on the light emitting elements 130R, 130G, and 130B. A substrate 170 is attached to the protective layer 131 with an adhesive layer 171.

[0555] Between two adjacent pixel electrodes 111 (pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B), there is no insulating layer covering the upper surface end of the pixel electrode 111. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. Therefore, a high-definition or high-resolution display device can be obtained.

[0556] [Display Device 200B] The following describes a display device that has a configuration that is partially different from that described above. Note that parts that are common to the above will be referred to, and descriptions thereof may be omitted.

[0557] 23 shows an example in which a transistor 320A, which is a planar transistor having a semiconductor layer formed on a plane, and a transistor 320B, which is a vertical channel transistor, are stacked. The transistor 320B has a configuration similar to that of the transistor 320 in the display device 200A.

[0558] The transistor 320A includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 356 , and a conductive layer 357 .

[0559] An insulating layer 352 is provided over the substrate 331. The insulating layer 352 functions as a barrier layer that prevents impurities, such as water or hydrogen, which may adversely affect the electrical characteristics of the transistor from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 351 toward the insulating layer 352. The insulating layer 352 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0560] A conductive layer 357 is provided over the insulating layer 352, and an insulating layer 356 is provided to cover the conductive layer 357. The conductive layer 357 functions as a first gate electrode of the transistor 320A, and part of the insulating layer 356 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 356 that is in contact with the semiconductor layer 351. The top surface of the insulating layer 356 is preferably planarized.

[0561] The semiconductor layer 351 is provided over the insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 355 is provided over and in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.

[0562] Insulating layers 358 and 350 are provided to cover top surfaces and side surfaces of the pair of conductive layers 355 and side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer that prevents impurities, such as water or hydrogen, which may adversely affect the electrical characteristics of the transistor from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351. The insulating layer 358 can be an insulating film similar to the insulating layer 352.

[0563] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 in contact with a top surface of the semiconductor layer 351 and a conductive layer 354 are buried in the opening. The conductive layer 354 functions as a second gate electrode, and the insulating layer 353 functions as a second gate insulating layer.

[0564] The top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are the same or approximately the same, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer that prevents impurities, such as water or hydrogen, which may adversely affect the electrical characteristics of the transistor from diffusing into the transistor 320. The insulating layer 359 can be an insulating film similar to the insulating layer 352.

[0565] The transistor 320 has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0566] [Display Device 200C] A display device 200C shown in FIG. 24 has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a vertical channel transistor 320.

[0567] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with an impurity that functions as a dopant, and functions as either a source or a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0568] An element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0569] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0570] Embodiment 4 In this embodiment, a circuit, a layout, and the like that can be applied to a display device of one embodiment of the present invention will be described.

[0571] 25 is a block diagram illustrating the display device 300. The display device 300 has a display unit 435, a first drive circuit unit 431, and a second drive circuit unit 432.

[0572] The display unit 435 has a plurality of pixels 230 arranged in a matrix of m rows (m is an integer of 1 or more) and n columns (n ​​is an integer of 1 or more).

[0573] The display unit 435 corresponds to, for example, the display unit 168 in FIG. 15, and the pixel 230 corresponds to, for example, the subpixel 11R, the subpixel 11G, the subpixel 11B, and the pixel 210 in FIG.

[0574] 21A, and the pixel 230 corresponds to, for example, the subpixel 11R, the subpixel 11G, the subpixel 11B, and the pixel 284a in FIG. 21B.

[0575] 25, the pixel 230 in the first row and nth column is indicated as pixel 230[1,n], the pixel 230 in the mth row and first column is indicated as pixel 230[m,1], and the pixel 230 in the mth row and nth column is indicated as pixel 230[m,n]. Also, any pixel 230 included in the display unit 435 may be indicated as pixel 230[r,s]. r is an integer greater than or equal to 1 and less than or equal to m, and s is an integer greater than or equal to 1 and less than or equal to n.

[0576] The circuit included in the first drive circuit unit 431 functions as, for example, a scanning line drive circuit. The circuit included in the second drive circuit unit 432 functions as, for example, a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 431 across the display unit 435. Note that some kind of circuit may be provided at a position facing the second drive circuit unit 432 across the display unit 435. Note that the circuits included in the first drive circuit unit 431 and the second drive circuit unit 432 are collectively referred to as a peripheral drive circuit 433.

[0577] The peripheral driver circuit 433 can include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit. The transistor 100 according to one embodiment of the present invention or the like can be used for the peripheral driver circuit 433. Note that the transistor included in the peripheral driver circuit and the transistor included in the pixel 230 may be formed in the same process.

[0578] The display device 300 also has m wires 436 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the first drive circuit unit 431, and n wires 437 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the second drive circuit unit 432.

[0579] 25 shows an example in which the wiring 436 and the wiring 437 are connected to the pixel 230. However, the wiring 436 and the wiring 437 are just an example, and the wirings connected to the pixel 230 are not limited to the wiring 436 and the wiring 437.

[0580] 26A, 26B, 27A to 27C show configuration examples of a pixel 230. The pixel 230 includes a pixel circuit 51 (a pixel circuit 51A, a pixel circuit 51B, a pixel circuit 51C, a pixel circuit 51D, or a pixel circuit 51E) and a light-emitting element 61.

[0581] The light-emitting element described in the present embodiment and the like refers to a self-luminous display element such as an organic EL element (also referred to as an OLED). Note that the light-emitting element connected to the pixel circuit can be a self-luminous light-emitting element such as an LED, a micro LED, a QLED, or a semiconductor laser.

[0582] A pixel circuit 51A shown in FIG. 26A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitor 53.

[0583] One of the source and drain of the transistor 52A is connected to the wiring SL, and the gate of the transistor 52A is connected to the wiring GL. One of the source and drain of the transistor 52A is connected to the gate of the transistor 52B and one terminal of the capacitor 53. One of the source and drain of the transistor 52B is connected to the wiring ANO. The other of the source and drain of the transistor 52B is connected to the other terminal of the capacitor 53 and the anode of the light-emitting element 61. The cathode of the light-emitting element 61 is connected to the wiring VCOM. A region where the other of the source and drain of the transistor 52A, the gate of the transistor 52B, and one terminal of the capacitor 53 are connected functions as a node ND.

[0584] The wiring GL corresponds to the wiring 436, and the wiring SL corresponds to the wiring 437. The wiring VCOM is a wiring that applies a potential for supplying a current to the light-emitting element 61. The transistor 52A has a function of controlling the conduction state (a state in which a current can flow) or the non-conduction state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0585] By turning on the transistor 52A, an image signal is supplied from the wiring SL to the node ND. Then, by turning off the transistor 52A, the image signal is held in the node ND. In order to reliably hold the image signal supplied to the node ND, it is preferable to use a transistor with low off-state current as the transistor 52A. For example, it is preferable to use an OS transistor as the transistor 52A.

[0586] The transistor 52B has a function of controlling the amount of current flowing through the light-emitting element 61. The capacitor 53 has a function of holding the gate potential of the transistor 52B. The intensity of light emitted by the light-emitting element 61 is controlled in response to an image signal supplied to the gate (node ​​ND) of the transistor 52B.

[0587] 26B is a 3Tr1C type pixel circuit having a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The pixel circuit 51B shown in Fig. 26B has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in Fig. 26A.

[0588] The source or the drain of the transistor 52C is connected to the other of the source or the drain of the transistor 52B. The other of the source or the drain of the transistor 52C is connected to a wiring V0. For example, a reference potential is supplied to the wiring V0.

[0589] The transistor 52C has a function of controlling conduction or non-conduction between the other of the source and the drain of the transistor 52B and the wiring V0 based on the potential of the wiring GL. The wiring V0 is a wiring for applying a reference potential. When an n-channel transistor is used as the transistor 52B, the reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source voltage of the transistor 52B.

[0590] Furthermore, the wiring V0 can be used to acquire a current value that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.

[0591] 27A has a configuration in which a transistor 52D is added to the pixel circuit 51B shown in Fig. 26B. The pixel circuit 51C shown in Fig. 27A is a 4Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, and a capacitor 53.

[0592] The pixel circuit 51C is connected to a wiring GL1, a wiring GL2, and a wiring GL3. The wiring GL1 is connected to the gate of the transistor 52A, the wiring GL2 is connected to the gate of the transistor 52C, and the wiring GL3 is connected to the gate of the transistor 52D. Note that in this embodiment and the like, the wirings GL1, GL2, and GL3 may be collectively referred to as wirings GL. Therefore, the number of wirings GL is not limited to one, and there may be multiple wirings GL.

[0593] By simultaneously turning on the transistors 52C and 52D, the source and gate of the transistor 52B have the same potential, and the transistor 52B can be turned off. This makes it possible to forcibly cut off the current flowing through the light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0594] The pixel circuit 51D shown in Fig. 27B is an example in which a capacitor 53A is added to the pixel circuit 51C. The capacitor 53A functions as a storage capacitor. The pixel circuit 51C shown in Fig. 27A is a 4Tr1C type pixel circuit. The pixel circuit 51D shown in Fig. 27B is a 4Tr2C type pixel circuit.

[0595] A pixel circuit 51E shown in FIG. 27C is a 6Tr1C type pixel circuit having a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, a transistor 52E, a transistor 52F, and a capacitor 53.

[0596] One of the source and drain of the transistor 52A is connected to the wiring SL, and the gate of the transistor 52A is connected to the wiring GL1. One of the source and drain of the transistor 52D is connected to the wiring ANO, and the gate of the transistor 52D is connected to the wiring GL2. The other of the source and drain of the transistor 52D is connected to the one of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52B is connected to the other of the source and drain of the transistor 52A and the one of the source and drain of the transistor 52F. The gate of the transistor 52F is connected to the wiring GL3.

[0597] One of the source or the drain of the transistor 52E is connected to the other of the source or the drain of the transistor 52D and one of the source or the drain of the transistor 52B. The other of the source or the drain of the transistor 52E is connected to the gate of the transistor 52B and one terminal of the capacitor 53. The other terminal of the capacitor 53 is connected to the other of the source or the drain of the transistor 52F, the anode of the light-emitting element 61, and one of the source or the drain of the transistor 52C. The gates of the transistors 52E and 52C are connected to a wiring GL4. The other of the source or the drain of the transistor 52C is connected to a wiring V0. A region where the other of the source or the drain of the transistor 52E, the gate of the transistor 52B, and one terminal of the capacitor 53 are connected functions as a node ND.

[0598] By using a transistor according to one embodiment of the present invention in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced. Therefore, the resolution of the display device can be improved. For example, a display device having a resolution of 1,000 ppi to 10,000 ppi, preferably 2,000 ppi to 9,000 ppi, more preferably 3,000 ppi to 8,000 ppi, further preferably 4,000 ppi to 8,000 ppi, further preferably 5,000 ppi to 8,000 ppi, and further preferably 6,000 ppi to 8,000 ppi can be realized.

[0599] Furthermore, by reducing the area occupied by the pixel circuit, it is possible to increase the number of pixels (resolution) of the display device, and it is possible to realize a display device with extremely high resolution, such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels).

[0600] Therefore, by using a transistor according to one embodiment of the present invention in a pixel circuit of a display device, the display quality of the display device can be improved. Furthermore, in a bottom-emission display device using an EL element, the aperture ratio of the pixel can be increased. A pixel with a high aperture ratio can emit light with the same luminance as a pixel with a low aperture ratio, but with a lower current density than a pixel with a low aperture ratio. Therefore, the reliability of the display device can be improved.

[0601] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0602] Embodiment 5 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 28A to 30G.

[0603] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0604] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0605] In particular, the display device of one embodiment of the present invention can be suitably used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0606] The display device of one embodiment of the present invention preferably has an extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0607] The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0608] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out programs or data recorded on a recording medium, etc.

[0609] 28A to 28D , examples of wearable devices that can be worn on the head are described. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content. By having an electronic device have the function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the sense of immersion for the user.

[0610] The electronic device 700A shown in Figure 28A and the electronic device 700B shown in Figure 28B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0611] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can provide an extremely high-definition display.

[0612] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0613] The electronic device 700A and the electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, the electronic device 700A and the electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in the display area 756.

[0614] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0615] The electronic device 700A and the electronic device 700B are provided with a battery (not shown), which can be charged wirelessly and / or by wire.

[0616] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can broaden the range of operations.

[0617] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0618] When an optical touch sensor is used, a photoelectric conversion element can be used as the light receiving element. The active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0619] The electronic device 800A shown in Figure 28C and the electronic device 800B shown in Figure 28D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0620] The display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided. This allows a user to feel a high sense of immersion.

[0621] The display unit 820 is provided inside the housing 821 at a position where it can be viewed through the lens 832. Also, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0622] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0623] It is preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the left-right positions of the lens 832 and the display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the focus by changing the distance between the lens 832 and the display unit 820.

[0624] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that in Fig. 28C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0625] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0626] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0627] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0628] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0629] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, an electronic device 700A shown in FIG. 28A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, an electronic device 800A shown in FIG. 28C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0630] The electronic device may have an earphone unit. Electronic device 700B shown in Fig. 28B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0631] Similarly, electronic device 800B shown in Fig. 28D has earphone unit 827. For example, earphone unit 827 and control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or wearing unit 823. Furthermore, earphone unit 827 and wearing unit 823 may have magnets. This allows earphone unit 827 to be fixed to wearing unit 823 by magnetic force, which is preferable as it makes storage easier.

[0632] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0633] As described above, as electronic devices of one embodiment of the present invention, both glasses-type devices (such as the electronic devices 700A and 700B) and goggle-type devices (such as the electronic devices 800A and 800B) are suitable.

[0634] An electronic device according to one embodiment of the present invention can transmit information to an earphone via a wired or wireless connection.

[0635] The electronic device 6500 shown in FIG. 29A is a portable information terminal that can be used as a smartphone.

[0636] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0637] The display device of one embodiment of the present invention can be applied to the display portion 6502 .

[0638] FIG. 29B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0639] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0640] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0641] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0642] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, the thickness of the electronic device can be reduced and a large-capacity battery 6518 can be mounted thereon. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the display portion 6502, an electronic device with a narrow frame can be realized.

[0643] 29C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0644] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0645] 29C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0646] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0647] 29D shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7000.

[0648] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0649] 29E and 29F show an example of digital signage.

[0650] 29E includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power...

Claims

a transistor, a first insulating layer, and a second insulating layer; the transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer; the first conductive layer and the first insulating layer have upper surfaces substantially aligned at the same height; the second insulating layer is provided on the first conductive layer and on the first insulating layer; the second conductive layer is provided on the second insulating layer; the second conductive layer and the second insulating layer each have an opening reaching the first conductive layer; In the opening, the semiconductor layer is provided in contact with an upper surface of the first conductive layer, a side surface of the second insulating layer, and a side surface of the second conductive layer. Semiconductor device. 　 In claim 1, a third insulating layer on the second insulating layer; the second conductive layer and the third insulating layer have upper surfaces at approximately the same height; Semiconductor device. 　 In claim 1 or 2, the transistor has a fourth insulating layer, a fifth insulating layer, and a third conductive layer; the fourth insulating layer is provided in contact with an upper surface of the semiconductor layer and an upper surface of the second conductive layer; the third conductive layer is provided in contact with an upper surface of the fourth insulating layer so as to have a region overlapping with the opening; the fifth insulating layer is provided on the third conductive layer so as to fill the opening; Semiconductor device. 　 In claim 1, the semiconductor layer comprises a metal oxide; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; The second insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 4, the second insulating layer includes a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer; the sixth insulating layer and the eighth insulating layer each include silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; The seventh insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 a transistor, a first insulating layer, and a second insulating layer; The transistor includes a semiconductor layer and a first conductive layer, the first conductive layer and the first insulating layer have upper surfaces substantially aligned at the same height; the second insulating layer is provided on the first conductive layer and the first insulating layer, and has an opening reaching the first conductive layer; the semiconductor layer is provided in contact with an upper surface of the first conductive layer in the opening, a side surface of the second insulating layer in the opening, and an upper surface of the second insulating layer; Semiconductor device. 　 In claim 6, the transistor has a third insulating layer, a fourth insulating layer, and a second conductive layer; the third insulating layer is provided in contact with an upper surface of the semiconductor layer, the second conductive layer is provided in contact with an upper surface of the third insulating layer so as to have a region overlapping with the opening; the fourth insulating layer is provided on the second conductive layer so as to fill the opening; Semiconductor device. 　 In claim 6, the semiconductor layer comprises a metal oxide; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; The second insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 8, the second insulating layer includes a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer; the fifth insulating layer and the seventh insulating layer each include silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; The sixth insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 forming a first conductive layer and a first insulating layer having an upper surface substantially equal in height to the first conductive layer; forming a first insulating film on the first conductive layer and the first insulating layer; forming a second conductive layer on the first insulating film so as to have a region overlapping with the first conductive layer; removing a portion of each of the second conductive layer and the first insulating layer to form an opening reaching the first conductive layer, and forming a third conductive layer and a second insulating layer; forming a semiconductor layer in contact with a side surface of the third conductive layer, a side surface of the second insulating layer, and an upper surface of the first conductive layer, respectively, within the opening; A method for manufacturing a semiconductor device. 　 In claim 10, forming a third insulating layer on the second conductive layer and on the first insulating film after forming the second conductive layer and before forming the opening, the third insulating layer having an upper surface at approximately the same height as that of the second conductive layer; A method for manufacturing a semiconductor device. 　 In claim 10 or 11, forming a fourth insulating layer in contact with an upper surface and a side surface of the semiconductor layer and an upper surface of the third conductive layer after the semiconductor layer is formed; forming a fourth conductive layer in contact with an upper surface of the fourth insulating layer and having a region overlapping the semiconductor layer; forming a second insulating film on the fourth conductive layer and the fourth insulating layer so as to fill the opening; processing the second insulating film to form a fifth insulating layer having a flat upper surface and embedded in the opening; A method for manufacturing a semiconductor device. 　 In claim 10, forming a third insulating film and a first photoresist in this order on the first conductive layer after forming the first conductive layer; Etching the first photoresist and the third insulating film to form the first insulating layer. A method for manufacturing a semiconductor device. 　 In claim 10 or 13, forming a fourth insulating film and a second photoresist in this order on the second conductive layer and the first insulating film after forming the second conductive layer and before forming the opening; etching the second photoresist and the fourth insulating film to form a sixth insulating layer having an upper surface substantially equal in height to the second conductive layer; A method for manufacturing a semiconductor device. 　 In claim 10 or 13, After the semiconductor layer is formed, a seventh insulating layer is formed in contact with an upper surface and a side surface of the semiconductor layer and an upper surface of the third conductive layer; forming a fifth conductive layer in contact with an upper surface of the seventh insulating layer and having a region overlapping the semiconductor layer; forming a fifth insulating film and a third photoresist in this order on the fifth conductive layer and the seventh insulating layer so as to fill the opening; Etching the third photoresist and the fifth insulating film to form an eighth insulating layer having a flat upper surface and embedded in the opening; A method for manufacturing a semiconductor device.

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