Ceramic wiring board, electronic device, electronic module, and multi-patterned wiring board

Abstract

This ceramic wiring board comprises a ceramic substrate and a via conductor. The ceramic substrate includes one or more ceramic layers and has a first surface and a second surface which are orthogonal to the thickness direction. The via conductor penetrates at least one of the ceramic layers in the thickness direction. The aspect ratio (height / diameter) of the via conductor is less than 1.

Description

Ceramic wiring boards, electronic devices, electronic modules and multi-cavity wiring boards

[0001] The present disclosure relates to a ceramic wiring substrate, an electronic device, an electronic module, and a multi-cavity wiring substrate.

[0002] A ceramic wiring substrate has a ceramic layer and a wiring conductor, and if the thermal expansion coefficients of these differ, the difference in the thermal expansion coefficients can cause the ceramic wiring substrate to warp when heated during processes such as the electronic device mounting process.

[0003] Patent Document 1 discloses a light emitting device in which warping due to heat is reduced by adjusting the amount of metal material provided on the front and back surfaces of a ceramic substrate. Even in a ceramic wiring substrate, if the ceramic layer is thick, warping can be reduced to some extent by adjusting the amount of wiring conductor on the front and back surfaces.

[0004] JP 2012-84733 A

[0005] (1) One aspect of a ceramic wiring board according to the present disclosure comprises: a ceramic substrate including one or more ceramic layers and having a first surface and a second surface perpendicular to a thickness direction; and a via conductor penetrating at least one of the ceramic layers in the thickness direction, wherein the aspect ratio (height / diameter) of the via conductor is less than 1.

[0006] (2) One aspect of the ceramic wiring board according to the present disclosure is the ceramic wiring board according to (1) above, wherein the via conductor has an aspect ratio (height / diameter) of 0.5 or less.

[0007] (3) One aspect of the ceramic wiring board according to the present disclosure is the ceramic wiring board according to (1) or (2) above, wherein the via conductors are located at the outer edge of the ceramic layer in a plan view.

[0008] (4) One aspect of the ceramic wiring board according to the present disclosure is the ceramic wiring board of any one of (1) to (3) above, wherein at least one of the ceramic layers comprises, as the via conductors, a plurality of first via conductors and a plurality of second via conductors each having a diameter smaller than that of the first via conductors, and the shortest distance between the second via conductors is shorter than the shortest distance between the first via conductors.

[0009] (5) One aspect of the ceramic wiring board according to the present disclosure is the ceramic wiring board according to any one of (1) to (4) above, further comprising a frame-shaped conductor on an outer periphery of the first surface.

[0010] (6) One aspect of the ceramic wiring board according to the present disclosure is the ceramic wiring board according to (5) above, wherein at least one of the via conductors is connected to the frame-shaped conductor.

[0011] (7) One aspect of the ceramic wiring board according to the present disclosure is the ceramic wiring board of (6) above, wherein when the ceramic layer constituting the first surface is divided evenly into four areas, two vertically and two horizontally, in a planar view, the ceramic layer constituting the first surface has one or more first areas in which the via conductors are connected to the corners of the frame-shaped conductor and one or more second areas in which the via conductors are not connected to the corners of the frame-shaped conductor, and the number of via conductors not connected to the frame-shaped conductor is greater in the second area than in the first area.

[0012] (8) One aspect of the ceramic wiring board according to the present disclosure is the ceramic wiring board of any one of (1) to (7) above, wherein the ceramic substrate includes a plurality of the ceramic layers, and the ceramic wiring board has an internal wiring conductor located between the ceramic layers, and the internal wiring conductor is connected to the via conductor and is drawn out to a side surface of the ceramic wiring board that is perpendicular to the first surface.

[0013] (9) One aspect of the ceramic wiring substrate according to the present disclosure is the ceramic wiring substrate according to any one of (1) to (8) above, comprising: a first external wiring conductor located on the first surface; and a first plating layer covering the first external wiring conductor, wherein the thickness of the first plating layer is at least half the thickness of the first external wiring conductor.

[0014] (10) One aspect of the ceramic wiring board according to the present disclosure is the ceramic wiring board of any one of (1) to (9) above, wherein the ceramic substrate includes a plurality of the ceramic layers, and the ceramic wiring board comprises: an internal wiring conductor located between the ceramic layers; a first external wiring conductor located on the first surface; a first plating layer covering the first external wiring conductor; a second external wiring conductor located on the second surface; and a second plating layer covering the second external wiring conductor, and the total thickness of the internal wiring conductor, the first external wiring conductor, the first plating layer, the second external wiring conductor, and the second plating layer is ⅓ or more of the total thickness of the plurality of ceramic layers.

[0015] (11) One aspect of the ceramic wiring board according to the present disclosure is the ceramic wiring board according to any one of (1) to (10) above, wherein the ceramic layer contains alumina crystal particles and zirconia crystal particles, the particle diameter of the alumina crystal particles is larger than the particle diameter of the zirconia crystal particles, and the zirconia crystal particles are scattered around the alumina crystal particles.

[0016] (12) An aspect of an electronic device according to the present disclosure includes: a ceramic wiring substrate according to any one of (1) to (11) above; and an electronic element mounted on the ceramic wiring substrate.

[0017] (13) One aspect of an electronic module according to the present disclosure includes: a module substrate; and the electronic device according to (12) above mounted on the module substrate.

[0018] (14) In one aspect of the multi-cavity wiring board according to the present disclosure, a plurality of ceramic wiring substrates according to any one of (1) to (11) above are arranged lengthwise and breadthwise to be integrated.

[0019] 1A is an enlarged view of a portion B of FIG. 1A; and FIG. 1B is an enlarged view of a portion C of FIG. 1A. It is a perspective view of a ceramic wiring substrate. It is a perspective view of a ceramic wiring substrate. It is a schematic cross-sectional view of the ceramic wiring substrate taken along line A-A of FIG. 2. It is an enlarged view of a portion D of FIG. 4. It is a view of a first external wiring conductor and a frame-shaped conductor as viewed from the first surface side. It is a view of an internal wiring conductor as viewed from the first surface side. It is a view of a second external wiring conductor as viewed from the first surface side. It is an SEM image of a cross-section of a ceramic layer mainly composed of alumina crystal grains and zirconia crystal grains.

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, for the sake of convenience, each of the drawings below shows a simplified view of only the main components necessary for explaining the embodiments. Therefore, the embodiments of the present disclosure may include any components not shown in the drawings. Furthermore, the dimensions of the components in each drawing do not faithfully represent the dimensions, dimensional ratios, etc. of the actual components.

[0021] In the following description, expressions such as "constant," "orthogonal," "vertical," or "parallel" may be used. These expressions do not necessarily mean "constant," "orthogonal," "vertical," or "parallel" in the strict sense. In other words, these expressions allow for deviations due to, for example, manufacturing accuracy, installation accuracy, etc.

[0022] In this disclosure, "plan view" refers to a view in the thickness direction (Z direction) of the ceramic wiring substrate 21, and includes a planar perspective view. "Planar direction" refers to a direction (X-Y direction) perpendicular to the thickness direction (Z direction) of the ceramic wiring substrate 21. "Cross-sectional view" refers to a view in a direction (X-Y direction) perpendicular to the thickness direction (Z direction) of the ceramic wiring substrate 21.

[0023] In recent years, the demand for ceramic wiring boards with thin ceramic layers has increased, and warping cannot be sufficiently reduced simply by adjusting the amount of wiring conductor. Warping due to heating subsides when the temperatures on the front and back surfaces are approximately the same, but if the thermal conductivity between the front and back surfaces is low, it takes a long time for the warping to subside. Since the next process cannot proceed until the warping subsides, if the warping takes a long time to subside, productivity in the manufacture of electronic devices using ceramic wiring boards decreases. In particular, when electronic components are mounted on a multi-cavity wiring board in which ceramic wiring boards are arranged in a matrix, the large size of the multi-cavity wiring board results in significant warping. Therefore, in this case, productivity in the manufacture of electronic devices is particularly reduced. According to one aspect of the present disclosure, it is possible to obtain a ceramic wiring board and a multi-cavity wiring board in which warping that occurs during heating is easily subsided in a short time, as well as an electronic device and an electronic module including the ceramic wiring board.

[0024] [Electronic Device and Electronic Module] The electronic device of the present embodiment includes the ceramic wiring substrate of the present embodiment and an electronic element mounted on the ceramic wiring substrate. The electronic module of the present embodiment includes a module substrate and the electronic device of the present embodiment mounted on the module substrate.

[0025] Fig. 1A is a cross-sectional view showing a schematic configuration of an electronic module 100 according to this embodiment. Fig. 1B is an enlarged view of a portion B in Fig. 1A. Fig. 1C is an enlarged view of a portion C in Fig. 1A.

[0026] As shown in FIG. 1A , an electronic module 100 includes a module substrate 10 mounted on an external main board 500 incorporated in an electronic device, for example, and various electronic devices 20 mounted on the module substrate 10. The electronic devices 20 may be, for example, a surface acoustic wave (SAW) filter or a quartz crystal device, but are not limited thereto. The module substrate 10 and the electronic devices 20 may form a functional module related to some function. The functional module may include, for example, a front-end module related to a communication function. In addition to the electronic devices 20, the module substrate 10 may also mount electronic components 30 such as switching elements, filter components, antenna components, and power amplifiers. Each component is electrically connected via connection pads or the like. This electrical connection allows power and signals to be exchanged between the components.

[0027] 1B and 1C, the electronic device 20 includes a ceramic wiring substrate 21 and an electronic element 22. The electronic element 22 on the ceramic wiring substrate 21 may be sealed by being covered with a lid or, as shown in FIG. 1B, a sealing resin 23. The electronic element 22 is electrically connected to the ceramic wiring substrate 21 via a connection pad or the like. This electrical connection allows power and signals to be exchanged between the ceramic wiring substrate 21 and the electronic element 22.

[0028] As shown in Fig. 1B, the electronic device 20 may be mounted on a module substrate 10 and then mounted on a main board 500 via the module substrate 10. Alternatively, as shown in Fig. 1C, the electronic device 20 may be mounted directly on the main board 500 without using the module substrate 10.

[0029] 1B , when the electronic device 20 is mounted on the module substrate 10, it is preferable that the electronic device 20 is thin so that it can be resin-sealed at the same height as other thin electronic components 30 that are mounted together. However, if the ceramic wiring substrate 21 is thinned to thin the electronic device 20, warping is likely to occur when heated. Therefore, the ceramic wiring substrate 21 of the present disclosure, which tends to quickly resolve warping that occurs when heated, is particularly suitable for use in an electronic device 20 that is mounted on a main board 500 via the module substrate 10.

[0030] The electronic device 20 can be manufactured, for example, by mounting electronic elements 22 on each ceramic wiring substrate 21 of a multi-cavity wiring substrate, collectively sealing the plurality of electronic elements 22 with sealing resin 23, and then dividing the substrate into individual pieces. The multi-cavity wiring substrate used here is described in detail below, but is one in which the ceramic wiring substrates 21 are arranged, for example, in a matrix and integrated together. Mounting of the electronic elements 22 on each ceramic wiring substrate 21 of the multi-cavity wiring substrate may be performed, for example, by a method in which a wafer on which the electronic elements 22 are arranged in a matrix is ​​stacked on the multi-cavity wiring substrate, and each ceramic wiring substrate 21 and each electronic element 22 are connected.

[0031] The manufacturing method of the electronic device 20 is not limited to the above-mentioned method. For example, the electronic device 20 can also be obtained by dividing the ceramic wiring substrates 21 into individual pieces from a multi-cavity wiring substrate, and then mounting the electronic elements 22 on each ceramic wiring substrate 21. The electronic device 20 can also be obtained by mounting the electronic elements 22 on ceramic wiring substrates 21 that have been individually manufactured from the beginning.

[0032] The ceramic wiring board 21 of this embodiment may be any one of the ceramic wiring boards 21 of a multi-cavity wiring board, the ceramic wiring board 21 cut from the multi-cavity wiring board before the electronic elements 22 are mounted, or the ceramic wiring board 21 made from individual pieces from the beginning.

[0033] [Configuration of Ceramic Wiring Board] Figures 2 to 5 are diagrams showing the configuration of a ceramic wiring board 21, which is an example of this embodiment. Figures 2 and 3 are perspective views of the ceramic wiring board 21. Figure 2 is a perspective view of the ceramic wiring board 21, seen from the first surface S1 side, which is the surface on which electronic elements are mounted. Figure 3 is a perspective view of the ceramic wiring board 21, seen from the second surface S2 side, which is the surface on which the module substrate 10 or the like is mounted. Figure 4 is a schematic diagram of a cross section of the ceramic wiring board taken along line A-A in Figure 2. Figure 5 is an enlarged view of portion D in Figure 4.

[0034] 2 to 5 includes a ceramic substrate 211, a via conductor 213, an internal wiring conductor 214, a first external wiring conductor 215, a first plating layer 217, a second external wiring conductor 216, a second plating layer 218, a frame-shaped conductor 219, and a third plating layer 220. Note that the ceramic wiring substrate 21 of this embodiment does not necessarily have to include the internal wiring conductor 214, the first plating layer 217, the second plating layer 218, the frame-shaped conductor 219, and the third plating layer 220.

[0035] The ceramic substrate 211 includes two ceramic layers 212 and has a first surface S1 and a second surface S2 that are perpendicular to the thickness direction. The number of ceramic layers 212 is not particularly limited and may be one or more. The number of ceramic layers 212 is also not particularly limited and may be, for example, one to three. If the number of ceramic layers 212 is large, the effectiveness of the via conductors 213 as heat conduction paths tends to decrease. Therefore, the ceramic wiring substrate 21 is preferably a thin substrate having two or less ceramic layers 212. While internal wiring conductors 214 are typically provided between each ceramic layer 212, this is not limited thereto and there may be ceramic layers 212 between which no internal wiring conductors 214 are provided.

[0036] The via conductor 213 is a conductor that penetrates in the thickness direction of at least one ceramic layer 212. In Fig. 4, the via conductor 213 penetrates in the thickness direction of the ceramic layer 212 located between the internal wiring conductor 214 and the second external wiring conductor 216.

[0037] In this embodiment, the aspect ratio (height h / diameter d) of the via conductor 213 is less than 1. That is, in this embodiment, the diameter d of the via conductor is greater than the height h. The via conductor 213 is the main heat conduction path in the thickness direction (Z direction) of the ceramic wiring substrate 21. Because the diameter d of the via conductor 213 is greater than the height h, the thermal conductivity between the front and back surfaces of the ceramic wiring substrate 21 is increased, and warping that occurs during heating is likely to be reduced in a short period of time. Furthermore, when the diameter d of the via conductor 213 is large, the thermal conductivity in the planar direction (X-Y direction) of the ceramic wiring substrate 21 is also increased. Therefore, even if there is a temperature difference between the front and back surfaces, the time until the temperature difference disappears is shortened because the diameter d of the via conductor 213 is greater than the height h.

[0038] Fig. 5 is an enlarged view of a portion D in Fig. 4. Fig. 5 shows the diameter d and height h of the via conductor 213 and the state of heat conduction in the via conductor 213.

[0039] The diameter d of the via conductor 213 is the diameter of the via conductor 213 in a planar view, and is the length in the planar direction (X direction in FIG. 5 ) as shown in Fig. 5. If the via conductor 213 is not a perfect circle in a planar view, the diameter of the via conductor 213 is the diameter of a perfect circle having the same area as the area of ​​the via conductor 213 in a planar view. The height h of the via conductor 213 is the size of the via conductor 213 in the thickness direction Z of the ceramic wiring substrate 21 as shown in Fig. 5.

[0040] The thick arrows in the via conductors 213 in FIG. 5 indicate the state of heat conduction within the via conductors 213 when the ceramic wiring substrate 21 is heated from the bottom (the second surface S2 side). When the ceramic wiring substrate 21 is heated, for example, from the bottom (the second surface S2 side), the heat conduction in the thickness direction (Z direction) of the via conductors 213 is accompanied by diffusion in the planar directions (X-Y directions). The diffusion of heat conduction is in a direction at 45 degrees from the thickness direction (Z direction), and the heat conduction path is substantially contained within a range extending 45 degrees from the thickness direction (Z direction) to the planar directions (X-Y directions). Therefore, when the aspect ratio (height h / diameter d) of the via conductors 213 is 0.5 or less, the thermal conductivity is higher.

[0041] On the other hand, if the aspect ratio (height h / diameter d) of via conductor 213 is relatively large, the contact area between the green sheet and the conductive paste that will become via conductor 213 during the manufacturing process becomes large, making it difficult for the conductive paste that will become via conductor 213 to fall off from the green sheet. Therefore, from this point of view, the aspect ratio (height h / diameter d) of via conductor 213 may be 0.3 or more.

[0042] The height h of the via conductor 213 is not particularly limited, but is, for example, 10 to 50 μm, specifically, for example, about 20 to 40 μm. The height h of the via conductor 213 is approximately equal to the thickness of the ceramic layer 212 through which the via conductor 213 passes. The diameter d of the via conductor 213 is not particularly limited as long as it is greater than the height h, but is, for example, 100 μm or less, specifically, for example, about 50 to 90 μm.

[0043] The internal wiring conductor 214 is located between the plurality of ceramic layers 212. The first external wiring conductor 215 is located on the first surface S1. The second external wiring conductor 216 is located on the second surface S2. The frame-shaped conductor 219 is located on the outer periphery of the first surface S1.

[0044] 4 , the internal wiring conductor 214 and the second external wiring conductor 216 are electrically connected through the via conductor 213. The internal wiring conductor 214 and the first external wiring conductor 215 are electrically connected through a via conductor (not shown) that penetrates the ceramic layer 212 located between them in the thickness direction. The internal wiring conductor 214 and the frame-shaped conductor 219 are also electrically connected through a via conductor (not shown) that penetrates the ceramic layer 212 located between them in the thickness direction.

[0045] The first plating layer 217 covers the first external wiring conductor 215. The second plating layer 218 covers the second external wiring conductor 216. The third plating layer 220 covers the frame-shaped conductor 219. The first plating layer 217, the second plating layer 218, and the third plating layer 220 increase the corrosion resistance of the first external wiring conductor 215, the second external wiring conductor 216, and the frame-shaped conductor 219, respectively.

[0046] The thickness of one ceramic layer 212 is not particularly limited, but is, for example, 50 μm or less, and specifically, for example, about 20 to 40 μm.

[0047] The thickness t1 of the first external wiring conductor 215, the thickness t2 of the second external wiring conductor 216, and the thickness t3 of the internal wiring conductor 214 are each, for example, 20 μm or less, and more specifically, for example, about 5 to 10 μm. If the thicknesses t1 to t3 are not uniform, the thicknesses t1 to t3 refer to the maximum thickness of each. The thicknesses t1 to t3 may be the same or different.

[0048] The thickness t11 of the first plating layer 217 and the thickness t21 of the second plating layer 218 are each, for example, 20 μm or less, specifically, for example, about 5 to 10 μm. If the thicknesses t11 and t21 are not uniform, the thicknesses t11 and t21 refer to the maximum thicknesses of the respective layers. The thicknesses t11 and t21 may be the same or different.

[0049] The plating layers 217, 218 typically have a higher density and thermal conductivity than the external wiring conductors 215, 216. Therefore, when the plating layers 217, 218 have a thickness equal to or greater than a certain value, the thermal conductivity of the ceramic wiring substrate 21 as a whole tends to be high. From this perspective, the thickness t11 of the first plating layer 217 may be equal to or greater than half the thickness t1 of the first external wiring conductor 215. Furthermore, the thickness t21 of the second plating layer 218 may be equal to or greater than half the thickness t2 of the second external wiring conductor 216.

[0050] The wiring conductors 214 to 216 and the plating layers 217 and 218 typically have higher thermal conductivity than the ceramic layer 212. Therefore, when the total thickness of the wiring conductors 214 to 216 and the plating layers 217 and 218 is equal to or greater than a certain value, the ceramic wiring board 21 tends to have high thermal conductivity as a whole. Furthermore, when the total thickness of the wiring conductors 214 to 216 and the plating layers 217 and 218 is equal to or greater than a certain value, the ceramic wiring board 21 has high toughness and is less likely to crack. From this perspective, the total thickness (t3 + t1 + t11 + t2 + t21) of the internal wiring conductor 214, the first external wiring conductor 215, the first plating layer 217, the second external wiring conductor 216, and the second plating layer 218 may be one-third or greater of the total thickness T of the plurality of ceramic layers 212.

[0051] The overall thickness of the ceramic wiring substrate 21 is not particularly limited, but may be, for example, 25 to 300 μm, 25 to 100 μm, 25 to 50 μm, etc. If the overall thickness of the ceramic wiring substrate 21 is not uniform, the thickness refers to the maximum thickness.

[0052] 6A to 6C are plan views or plan see-through views from the first surface S1 side of the ceramic wiring substrate 21 shown in Fig. 2. The ceramic wiring substrate 21 includes a first external wiring conductor 215, an internal wiring conductor 214, and a second external wiring conductor 216, and further includes a frame-shaped conductor 219 on the outer periphery of the first surface S1.

[0053] Fig. 6A is a view of the first external wiring conductor 215 and the frame-shaped conductor 219 provided on the ceramic wiring substrate 21, viewed from the first surface S1 side. Fig. 6B is a view of the internal wiring conductor 214 provided on the ceramic wiring substrate 21, viewed from the first surface S1 side. Fig. 6C is a view of the second external wiring conductor 216 provided on the ceramic wiring substrate 21, viewed from the first surface S1 side. An outer frame P in Figs. 6A to 6C indicates the outer edge of the ceramic wiring substrate 21. Line A-A in Figs. 6A to 6C indicates the same position in a plan view as line A-A in Fig. 2.

[0054] 6A and 6B represent the positions of via conductors 213a to 213c that penetrate the ceramic layer 212 in the thickness direction (Z direction) and are located between the first external wiring conductor 215, the frame-shaped conductor 219, and the internal wiring conductor 214. The via conductor 213a is a first via conductor with a relatively large diameter and is not connected to the frame-shaped conductor 219. The via conductor 213b is a second via conductor with a relatively small diameter and is not connected to the frame-shaped conductor 219. The via conductors 213a to 213c are a second via conductor with a relatively small diameter and are connected to the frame-shaped conductor 219. Details of the via conductors 213a to 213c will be described later.

[0055] The dashed-dotted circles in FIGS. 6B and 6C indicate the positions of via conductors 213d that penetrate the ceramic layer 212 between the internal wiring conductor 214 and the second external wiring conductor 216 in the thickness direction (Z direction).

[0056] The first external wiring conductor 215 functions as a connection pad when the electronic element 22 is mounted on the ceramic wiring substrate 21 .

[0057] The second external wiring conductor 216 functions as a connection pad when the ceramic wiring substrate 21 is mounted on the module substrate 10 .

[0058] The frame-shaped conductor 219 promotes heat conduction in the planar direction (X-Y direction) on the first surface S1. The frame-shaped conductor 219 may also serve as a seal ring when sealing the electronic device 20 with a lid after the electronic element 22 is mounted on the ceramic wiring substrate 21. The width of the frame-shaped conductor 219 depends on the size of the ceramic wiring substrate 21, but is, for example, about 50 to 300 μm.

[0059] The via conductor 213c is connected to the frame-shaped conductor 219. By connecting at least one via conductor 213 (two via conductors 213c in FIG. 6A ) to the frame-shaped conductor 219 in this manner, heat is conducted directly to the frame-shaped conductor 219 via the via conductor 213, thereby further promoting heat conduction in the planar direction (X-Y direction) by the frame-shaped conductor 219. Note that even if the ceramic wiring substrate 21 includes the frame-shaped conductor 219, it is not necessary for at least one via conductor 213 to be connected to the frame-shaped conductor 219.

[0060] The two-dot chain lines in Figure 6A divide the ceramic layer 212 constituting the first surface S1 into four equal areas, two vertically and two horizontally, in a plan view. Of these four areas, the area in which at least one of the via conductors 213a-c (via conductor 213c in Figure 6A) located on the ceramic layer 212 constituting the first surface S1 is connected to a corner of the frame-shaped conductor 219 is referred to as the first area E1. The area in which none of the via conductors 213a-c located on the ceramic layer 212 constituting the first surface S1 is connected to a corner of the frame-shaped conductor 219 is referred to as the second area E2. As shown in Figure 6A, the ceramic layer 212 constituting the first surface S1 may have one or more first areas E1 and one or more second areas E2. In this case, as shown in Figure 6A, the number of via conductors 213a, b not connected to the frame-shaped conductor 219 may be greater in the second area E2 than in the first area E1. In this case, when there are multiple first areas E1, the number of via conductors 213a, b that are not connected to the frame-shaped conductor 219 in each first area E1 may be the same or different. When there are multiple second areas E2, the number of via conductors 213a, b that are not connected to the frame-shaped conductor 219 in each second area E2 (i.e., the number of via conductors in each second area E2) may be the same or different. "The number of via conductors that are not connected to the frame-shaped conductor is greater in the second area than in the first area" means that the number of via conductors 213a, b that are not connected to the frame-shaped conductor 219 in any first area E1 is greater than the number of via conductors 213a, b that are not connected to the frame-shaped conductor 219 in any second area E2. The number of via conductors 213a, b that are not connected to the frame-shaped conductor 219 is greater in the second area E2 than in the first area E1, so even if heat is conducted to the frame-shaped conductor 219 in the first area E1, there is no shortage of heat that is conducted inward in the planar direction (X-Y direction) of the first surface S1 due to the greater number of via conductors 213a, b that are not connected to the frame-shaped conductor 219. This makes it easier for heat to be conducted uniformly.

[0061] 6A , when there are two first areas E1 and two second areas E2, the number of via conductors 213a, b that are not connected to the frame-shaped conductor 219 in each first area E1 may be two, and the number of via conductors 213a, b that are not connected to the frame-shaped conductor 219 in each second area E2 may be one. The number of via conductors 213a, b that are not connected to the frame-shaped conductor 219 in each first area E1 may be three, and the number of via conductors 213a, b that are not connected to the frame-shaped conductor 219 in each second area E2 may be two.

[0062] In a plan view, via conductors 213a-d may be located at the outer edge of ceramic layer 212. The outer edge refers to eight areas excluding the central area (center) when ceramic layer 212 is evenly divided into nine areas, three by three, in a plan view. The division of ceramic layer 212 into nine areas, three by three, in a plan view, is indicated by the outer edge of ceramic wiring substrate 21 and the two-dot chain line in FIG. 6B . When ceramic wiring substrate 21 is an individual piece, heat dissipation from the side surfaces tends to reduce heat conduction in the thickness direction (Z direction) at the outer edge. When ceramic wiring substrate 21 is included in a multi-cavity wiring substrate having dividing grooves between regions of ceramic wiring substrate 21, heat dissipation from the dividing grooves tends to reduce heat conduction in the thickness direction (Z direction) at the outer edge. When the ceramic wiring substrate 21 is included in a multi-cavity wiring substrate having a cut margin between regions of the ceramic wiring substrate 21, if there are few conductors in the cut margin, the outer edge portion adjacent to the cut margin is likely to have less heat conducted in the thickness direction (Z direction). The cut margin between the regions of the ceramic wiring substrate typically does not have via conductors, and therefore has few conductors. Furthermore, although an internal frame conductor may be present between the regions of the ceramic wiring substrate 21 that are cut margins, if no internal frame conductor is present, there is little conductor between the regions of the ceramic wiring substrate 21. In contrast to such an outer edge portion, even if via conductors 213a-d are not located in the center, sufficient heat conduction can be achieved as long as it is surrounded by multiple via conductors 213a-d located in the outer edge portion. Therefore, by locating the via conductors 213a-d in the outer edge portion of the ceramic layer 212, heat conduction is facilitated more uniformly. As shown in FIG. 6B, if all of the via conductors 213a-d are located in the outer edge portion of the ceramic layer 212, heat conduction is facilitated more uniformly. It is not necessary that all of the via conductors 213 a to 213 d are located on the outer edge of the ceramic layer 212 .

[0063] As shown in Figures 6A and 6B, the ceramic layer 212, located between the first external wiring conductor 215 and the frame-shaped conductor 219 and the internal wiring conductor 214, includes a plurality of first via conductors 213a and a plurality of second via conductors 213b and 213c as via conductors. The second via conductors 213b and 213c have a smaller diameter than the first via conductor 213a. The shortest distance between the second via conductors 213b and 213c is also smaller than the shortest distance between the first via conductors 213a. Here, the "shortest distance" refers to the shortest distance in a planar view. The diameters of the via conductors 213a to 213c may differ due to factors such as the routing of the wiring. The second via conductors 213b and 213c, which have a smaller diameter, have relatively poorer thermal conductivity. However, even when the same ceramic layer 212 includes a plurality of first via conductors 213a and a plurality of second via conductors 213b, 213c, thermal conductivity is ensured by ensuring that the shortest distance between the second via conductors 213b, 213c is shorter than the shortest distance between the first via conductors 213a. In other words, by arranging a plurality of second via conductors 213b, 213c having small diameters close to each other, thermal conductivity equivalent to that of a single first via conductor 213a having a large diameter is ensured. Note that the ceramic layer 212 does not necessarily include a plurality of first via conductors 213a and a plurality of second via conductors 213b, 213c. Furthermore, even when the same ceramic layer 212 includes a plurality of first via conductors 213a and a plurality of second via conductors 213b, 213c, the shortest distance between the second via conductors 213b, 213c does not necessarily have to be shorter than the shortest distance between the first via conductors 213a.

[0064] As shown in FIG. 6B , the internal wiring conductor 214 is connected to the via conductors 213a-d. The internal wiring conductor 214 is also drawn out to one of the side surfaces perpendicular to the first surface S1. As described above, the outer edge portion near the side surface is prone to heat dissipation and therefore has low thermal conductivity. The internal wiring conductor 214 is connected to the via conductors 213a-d and drawn out to the side surface, thereby increasing the thermal conductivity in the planar direction (X-Y) between the ceramic layers 212. Furthermore, when the ceramic wiring substrate 21 is a multi-cavity wiring substrate, as described above, the thermal conductivity in the thickness direction (Z direction) is likely to be low in the portions of the side surface where the dividing grooves or cutting margins are present. However, because the internal wiring conductor 214 is connected to the via conductors 213a-d and drawn out to the side surface, the thermal conductivity in the thickness direction (Z direction) is less likely to be low even in the portions where the dividing grooves or cutting margins are present. The internal wiring conductor 214 does not necessarily have to be connected to all of the via conductors 213a-d. Furthermore, the internal wiring conductor 214 does not necessarily have to be drawn out to any of the side surfaces perpendicular to the first surface S1.

[0065] The size of the ceramic wiring substrate 21 in the X direction is, for example, about 0.8 to 1.6 mm, and the size of the ceramic wiring substrate 21 in the Y direction is, for example, about 0.6 to 1.2 mm.

[0066] [Multi-cavity wiring board] A multi-cavity wiring board is a board in which a plurality of ceramic wiring substrates 21 are arranged lengthwise and widthwise and integrated together. In the multi-cavity wiring board, the plurality of ceramic wiring substrates 21 are arranged, for example, in a matrix. The multi-cavity wiring board has, for example, dividing grooves or cutting margins between each ceramic wiring substrate 21 or on the periphery of the multi-cavity wiring board.

[0067] The multi-cavity wiring board may have an internal frame-shaped conductor. The internal frame-shaped conductor is located in the cutting margin outside the ceramic wiring board 21 so as to surround each ceramic wiring board 21 between the ceramic layers 212. Adjacent internal frame-shaped conductors may be connected to each other to form a lattice (mesh) shape as a whole.

[0068] When the internal wiring conductor 214 is drawn out to any side surface perpendicular to the first surface S1, the internal wiring conductor 214 may be connected to an internal frame conductor, which increases the thermal conductivity in the planar direction (X-Y) inside the multi-cavity wiring substrate.

[0069] When the multi-cavity wiring board is divided into individual ceramic wiring substrates 21, the internal frame conductor is cut away. Therefore, in the divided ceramic wiring substrates 21, the internal frame conductor does not appear on the side surface of each ceramic wiring substrate 21. Therefore, in the divided ceramic wiring substrates 21, short circuits do not occur between the internal wiring conductors 214.

[0070] The outermost periphery of the internal frame conductor located on the outer periphery of the multi-cavity wiring board may be wider than the internal frame conductor between the regions of each ceramic wiring board 21. The outer periphery of the multi-cavity wiring board also tends to have low thermal conductivity due to the influence of heat radiation from the side surfaces, but by making the outermost periphery of the internal frame conductor wider, it is possible to reduce the decrease in thermal conductivity in the outer periphery of the multi-cavity wiring board.

[0071] The number of ceramic wiring substrates 21 in the multi-cavity wiring board is, but is not limited to, for example, 30 x 40. The size of the multi-cavity wiring board in plan view is, for example, about 50 mm x 50 mm.

[0072] [Components] The components of the ceramic layer 212 are, for example, aluminum oxide sintered body, glass ceramic sintered body, mullite sintered body, aluminum nitride sintered body, or the like.

[0073] The ceramic layer 212 is made of alumina (aluminum oxide, Al ２ O ３ ) crystal particles and zirconia (zirconium oxide, ZrO ２ The ceramic layer 212 mainly composed of alumina crystal grains and zirconia crystal grains tends to have small and few voids, and therefore has high thermal conductivity.

[0074] The zirconia crystal particles are stabilized by a stabilizer such as yttria (yttrium oxide, Y ２ O ３) or the like.

[0075] 7 is an SEM image of a portion of a cross section of a ceramic layer 212 composed primarily of alumina crystal grains 40 and zirconia crystal grains 41. In the SEM image of FIG. 7, the dark-colored particles are alumina crystal grains 40, and the light-colored particles are zirconia crystal grains 41.

[0076] 7, the grain size of the alumina crystal grains 40 is approximately 0.5 to 5 μm, and the grain size of the zirconia crystal grains 41 is approximately 0.2 to 2 μm. In this manner, the grain size of the alumina crystal grains 40 may be larger than the grain size of the zirconia crystal grains 41. The grain sizes are, for example, average grain sizes.

[0077] 7 , the alumina crystal particles 40 may be arranged contiguously with the zirconia crystal particles 41 scattered around the alumina crystal particles 40. The alumina crystal particles 40 have higher thermal conductivity than the zirconia crystal particles 41. For example, the thermal conductivity of a 96% alumina material at 20° C. is 24 W / (m·K), while the thermal conductivity of a zirconia material at 20° C. is 3 to 4 W / (m·K). Therefore, by having the alumina crystal particles 40 arranged contiguously with the zirconia crystal particles 41 scattered around the alumina crystal particles 40, the thermal conductivity of the ceramic layer 212 is increased.

[0078] The ceramic layer 212 contains manganese oxide (Mn ２ O ３ ), silica (silicon dioxide, SiO ２ ), magnesia (magnesium oxide, MgO), or calcia (calcium oxide, CaO), which function as sintering aids for alumina and zirconia, for example.

[0079] The component ratios of the ceramic layer 212 are not particularly limited, but an example is 65 wt% alumina, 30 wt% zirconia, 3 wt% silica, 1 wt% magnesium oxide, and 1 wt% calcium oxide. The zirconia ratio may be greater than 30 wt%. A zirconia ratio greater than 30 wt% provides high toughness and makes the ceramic wiring substrate 21 less likely to crack even when it is extremely thin. The component ratios of the ceramic layer 212 are not limited to these.

[0080] The via conductors 213, the internal wiring conductors 214, the first external wiring conductors 215, the second external wiring conductors 216, and the frame conductor 219 contain conductive components that transmit signals, power, etc. Examples of conductive components contained in each conductor include tungsten, molybdenum, manganese, copper, silver, palladium, gold, platinum, nickel, cobalt, and alloys thereof. The components contained in each conductor may be the same or different.

[0081] The first plating layer 217 and the second plating layer 218 contain nickel, gold, etc. The components contained in each plating layer may be the same or different.

[0082] The combination of components of each member is not particularly limited, but can be, for example, as follows: The thermal conductivity shown in parentheses is the thermal conductivity at 20°C. Ceramic layer: alumina crystal particles and zirconia crystal particles (thermal conductivity: 14 W / (m·K)) Via conductor: molybdenum (thermal conductivity: 142 W / (m·K)) Wiring conductors such as first external wiring conductor, second external wiring conductor, and internal wiring conductor: tungsten (thermal conductivity: 168 W / (m·K)) Plating layers such as first plating layer and second plating layer: nickel (thermal conductivity: 91 W / (m·K))

[0083] The melting point of molybdenum is 2623°C, and the melting point of tungsten is 3387°C. As such, molybdenum has a relatively low melting point, and therefore is easily densified during sintering. Therefore, when the via conductor 213 contains molybdenum, the thermal conductivity of the via conductor 213 is likely to be high, and the via conductor 213 is less likely to protrude from the ceramic layer 212, forming a convex via shape.

[0084] When the wiring conductor contains tungsten, even if the end faces of the wiring conductor are exposed to the outside when the multi-cavity wiring substrate is cut, the wiring conductor is less likely to be ionized by moisture, which makes the wiring conductor less likely to dissolve and cause short circuits.

[0085] The wiring conductor may be composed of tungsten, and the tungsten may be diffused into the via conductor 213. This increases the adhesion between the via conductor 213 and the wiring conductor, thereby increasing the connection reliability of the ceramic wiring substrate 21.

[0086] The wiring conductor may be made of tungsten, and the tungsten may be diffused into the ceramic layer, thereby increasing the thermal conductivity of the ceramic layer 212.

[0087] [Method for Manufacturing Ceramic Wiring Board] There is no particular limitation on the method for manufacturing the ceramic wiring board 21 of this embodiment. The ceramic wiring board 21 of this embodiment can be manufactured, for example, by molding ceramic powder that forms the ceramic layer 212 and a metallized member that forms the wiring conductor using a mold or the like, and then sintering them together.

[0088] Specifically, the ceramic wiring substrate 21 can be manufactured, for example, by the following procedure. First, a ceramic powder, a binder, and a solvent are kneaded to prepare a slurry. This slurry is formed into a sheet using a molding method such as a doctor blade method to form a green sheet that will become the ceramic layer 212. The ceramic powder contains, for example, 65 wt % alumina, 30 wt % zirconia, 3 wt % silica, 1 wt % magnesium oxide, and 1 wt % calcium oxide. A wiring pattern is formed on the resulting green sheet using a conductive paste that will become the metallized member. Through holes are formed in predetermined positions on the green sheet using a mold or the like. The through holes are filled with the conductive paste to form a via conductor pattern that will become the via conductors 213. A conductive paste is printed in a predetermined pattern shape in predetermined positions on the green sheet on which the via conductor pattern has been formed, to produce a green sheet on which a wiring pattern of a wiring conductor has been formed. Multiple green sheets on which the wiring pattern has been formed are stacked to produce a laminate. This laminate is then fired to produce the ceramic wiring substrate 21 formed by co-firing the ceramic layer 212 and the wiring conductor.

[0089] The method for forming the plating layers such as the first plating layer 217 and the second plating layer 218 is not particularly limited, and may be an electrolytic plating method or an electroless plating method.

[0090] As described above, the ceramic wiring board 21 of the present disclosure includes a ceramic substrate 211 and a via conductor 213. The ceramic substrate 211 includes one or more ceramic layers 212 and has a first surface S1 and a second surface S2 that are perpendicular to the thickness direction. The via conductor 213 penetrates at least one ceramic layer 212 in the thickness direction. The aspect ratio (height / diameter) of the via conductor 213 is less than 1. This increases the thermal conductivity of the ceramic wiring board 21.

[0091] The aspect ratio (height / diameter) of the via conductor 213 may be 0.5 or less, which increases the thermal conductivity of the ceramic wiring board 21.

[0092] In a plan view, the via conductors 213 may be located at the outer edge of the ceramic layer 212. This facilitates uniform heat conduction.

[0093] The ceramic wiring board 21 may include, as via conductors 213, a plurality of first via conductors 213a and a plurality of second via conductors 213b having diameters smaller than those of the first via conductors 213a in at least one of the ceramic layers 212. In this case, the shortest distance between the second via conductors 213b may be shorter than the shortest distance between the first via conductors 213a. This ensures thermal conductivity even when the second via conductors 213b have small diameters and relatively poor thermal conductivity.

[0094] The ceramic wiring substrate 21 may have a frame-shaped conductor 219 on the outer periphery of the first surface S1, which promotes heat conduction in the planar direction (XY direction) on the first surface S1.

[0095] At least one via conductor 213 may be connected to the frame-shaped conductor 219. This allows heat to be directly conducted to the frame-shaped conductor 219 via the via conductor 213, further promoting heat conduction in the planar direction (X-Y direction) by the frame-shaped conductor 219.

[0096] When the ceramic layer 212 constituting the first surface S1 is divided evenly into four areas, two by two, in a plan view, the ceramic layer 212 constituting the first surface S1 may have one or more first areas E1 in which the via conductors 213 are connected to the corners of the frame-shaped conductor 219 and one or more second areas E2 in which the via conductors 213 are not connected to the corners of the frame-shaped conductor 219. In this case, the number of via conductors 213 not connected to the frame-shaped conductor 219 may be greater in the second area E2 than in the first area E1. This facilitates uniform heat conduction.

[0097] The ceramic substrate 211 may include a plurality of ceramic layers 212, and the ceramic wiring substrate 21 may include internal wiring conductors 214 located between the ceramic layers 212. In this case, the internal wiring conductors 214 may be connected to the via conductors 213 and may be drawn out to a side surface of the ceramic wiring substrate 21 that is perpendicular to the first surface S1. This increases the thermal conductivity in the planar direction (X-Y) between the ceramic layers 212. In addition, the thermal conductivity in the thickness direction (Z direction) is less likely to decrease even in the areas where the dividing grooves are present.

[0098] The ceramic wiring substrate 21 may include a first external wiring conductor 215 and a first plating layer 217. The first external wiring conductor 215 is located on the first surface S1. The first plating layer 217 covers the first external wiring conductor 215. In this case, the thickness of the first plating layer 217 may be half or more of the thickness of the first external wiring conductor 215. This makes it easier for the thermal conductivity of the ceramic wiring substrate 21 to be high as a whole.

[0099] The ceramic substrate 211 may include a plurality of ceramic layers 212, and the ceramic wiring substrate 21 may include an internal wiring conductor 214, a first external wiring conductor 215, a first plating layer 217, a second external wiring conductor 216, and a second plating layer 218. The internal wiring conductor 214 is located between the ceramic layers 212. The first external wiring conductor 215 is located on the first surface S1. The first plating layer 217 covers the first external wiring conductor 215. The second external wiring conductor 216 is located on the second surface S2. The second plating layer 218 covers the second external wiring conductor 216. In this case, the total thickness of the internal wiring conductor 214, the first external wiring conductor 215, the first plating layer 217, the second external wiring conductor 216, and the second plating layer 218 may be one-third or more of the total thickness of the plurality of ceramic layers 212. This tends to increase the thermal conductivity of the ceramic wiring substrate 21 as a whole. Furthermore, the toughness of the ceramic wiring board 21 is increased, making the ceramic wiring board 21 less likely to crack.

[0100] The ceramic layer 212 may contain alumina crystal particles 40 and zirconia crystal particles 41. In this case, the particle size of the alumina crystal particles 40 may be larger than the particle size of the zirconia crystal particles 41, and the zirconia crystal particles 41 may be scattered around the alumina crystal particles 40. This increases the thermal conductivity of the ceramic layer 212.

[0101] The electronic device 20 of the present disclosure includes a ceramic wiring board 21 of the present disclosure and an electronic element 22 mounted on the ceramic wiring board 21. As described above, the ceramic wiring board 21 of the present disclosure has high thermal conductivity between its front and back surfaces, and therefore high heat dissipation from the electronic element 22. For example, when the electronic element 22 is mounted on the first surface S1 of the ceramic wiring board 21, heat generated from the electronic element 22 is conducted in a direction from the first surface S1 to the second surface S2 and dissipated from the second surface S2. The high heat dissipation of the ceramic wiring board 21 improves the operational reliability of the electronic element 22 in the electronic device 20. Furthermore, the high heat dissipation of the ceramic wiring board 21 reduces thermal stress, thereby improving the mounting reliability of the electronic element 22 in the electronic device 20.

[0102] The electronic module 100 of the present disclosure includes a module substrate 10 and an electronic device 20 of the present disclosure mounted on the module substrate 10. In the electronic module 100, the high heat dissipation properties of the ceramic wiring substrate 21 also improve the operational reliability and mounting reliability of the electronic element 22.

[0103] The multi-cavity wiring board of the present disclosure is formed by integrating a plurality of ceramic wiring boards of the present disclosure arranged lengthwise and widthwise.

[0104] Although the embodiments of the present disclosure have been described above, the ceramic wiring substrate, electronic device, electronic module, and multi-cavity wiring substrate of the present disclosure are not limited to the above-described embodiments.

[0105] For example, although the ceramic wiring substrate 21 shown in the above embodiment is flat, the ceramic wiring substrate 21 may have a recess (cavity). In this case, the ceramic wiring substrate 21 may have a recess on the first surface S1, and the first external wiring conductor 215 may be provided on the bottom surface of the recess. The recess may be formed by the ceramic wiring substrate 21 having a frame-shaped ceramic layer on the outer periphery of the first surface S1.

[0106] In addition, the details shown in the above embodiments can be modified as appropriate without departing from the spirit of the present disclosure. The scope of the present invention includes the scope of the invention described in the claims and its equivalents. Various combinations of the embodiments are not limited to the examples of the above embodiments. Furthermore, combinations of the embodiments with each other are also possible.

[0107] The present disclosure can be used for ceramic wiring substrates, electronic devices, electronic modules, and multi-cavity wiring substrates.

[0108] REFERENCE SIGNS LIST 10 Module substrate 20 Electronic device 21 Ceramic wiring substrate 211 Ceramic substrate 212 Ceramic layer 213 Via conductor 214 Internal wiring conductor 215 First external wiring conductor 216 Second external wiring conductor 217 First plating layer 218 Second plating layer 219 Frame-shaped conductor 220 Third plating layer 22 Electronic element 23 Sealing resin 30 Electronic component 40 Alumina crystal particle 41 Zirconia crystal particle 100 Electronic module 500 Main board

Claims

1. A ceramic wiring board comprising: a ceramic substrate including one or more ceramic layers and having a first surface and a second surface perpendicular to a thickness direction; and a via conductor penetrating at least one of the ceramic layers in the thickness direction, wherein the aspect ratio (height / diameter) of the via conductor is less than 1.

2. The ceramic wiring board according to claim 1, wherein the aspect ratio (height / diameter) of the via conductor is 0.5 or less.

3. The ceramic wiring board according to claim 1 or 2, wherein the via conductor is located on the outer edge of the ceramic layer in a plan view.

4. A ceramic wiring board according to any one of claims 1 to 3, wherein at least one of the ceramic layers comprises, as the via conductors, a plurality of first via conductors and a plurality of second via conductors having a diameter smaller than that of the first via conductors, and the shortest distance between the second via conductors is shorter than the shortest distance between the first via conductors.

5. The ceramic wiring board according to any one of claims 1 to 4, further comprising a frame-shaped conductor on the outer periphery of the first surface.

6. The ceramic wiring board according to claim 5, wherein at least one of the via conductors is connected to the frame-shaped conductor.

7. A ceramic wiring board as described in claim 6, wherein, when the ceramic layer constituting the first surface is divided evenly into four areas, two by two in a plan view, the ceramic layer constituting the first surface has one or more first areas in which the via conductors are connected to corners of the frame-shaped conductor and one or more second areas in which the via conductors are not connected to corners of the frame-shaped conductor, and the number of via conductors not connected to the frame-shaped conductor is greater in the second area than in the first area.

8. The ceramic wiring board according to any one of claims 1 to 7, wherein the ceramic substrate includes a plurality of the ceramic layers, the ceramic wiring board has an internal wiring conductor located between the ceramic layers, the internal wiring conductor being connected to the via conductor and extending to a side surface of the ceramic wiring board perpendicular to the first surface.

9. A ceramic wiring board as claimed in any one of claims 1 to 8, comprising: a first external wiring conductor located on said first surface; and a first plating layer covering said first external wiring conductor, wherein a thickness of said first plating layer is at least half of a thickness of said first external wiring conductor.

10. A ceramic wiring board according to any one of claims 1 to 9, wherein the ceramic substrate includes a plurality of the ceramic layers, the ceramic wiring substrate comprises: an internal wiring conductor located between the ceramic layers; a first external wiring conductor located on the first surface; a first plating layer covering the first external wiring conductor; a second external wiring conductor located on the second surface; and a second plating layer covering the second external wiring conductor, and the total thickness of the internal wiring conductor, the first external wiring conductor, the first plating layer, the second external wiring conductor, and the second plating layer is ⅓ or more of the total thickness of the plurality of ceramic layers.

11. The ceramic wiring board according to any one of claims 1 to 10, wherein the ceramic layer contains alumina crystal grains and zirconia crystal grains, the grain size of the alumina crystal grains is larger than the grain size of the zirconia crystal grains, and the zirconia crystal grains are scattered around the alumina crystal grains.

12. An electronic device comprising: the ceramic wiring board according to any one of claims 1 to 11; and an electronic element mounted on the ceramic wiring board.

13. An electronic module comprising: a module substrate; and an electronic device according to claim 12 mounted on the module substrate.

14. A multi-piece wiring board comprising a plurality of ceramic wiring boards according to any one of claims 1 to 11 arranged lengthwise and crosswise to form an integrated circuit.

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