Printed wiring board

Abstract

A printed wiring board according to the present disclosure comprises a first base film, a first wire, an adhesive layer, a second base film, and a seed layer. The first wire is disposed on the first base film. The adhesive layer is disposed on the first base film so as to cover the first wire. The second base film is disposed on the adhesive layer. The seed layer is disposed on the second base film. A through hole for exposing a part of the first wire is formed in the adhesive layer, the second base film, and the seed layer. The constituent material of the seed layer is a nickel-chromium alloy containing zinc. In the seed layer on the inner wall surface of the through hole, the zinc concentration in the constituent material of the seed layer is 5 atomic percent or more. The seed layer has a main surface facing the second base film. The surface roughness of the main surface is 1.5 μm or less.

Description

printed wiring board

[0001] The present disclosure relates to a printed wiring board. This application claims priority to Japanese Patent Application No. 2023-185588, filed on October 30, 2023. The entire contents of the Japanese patent application are incorporated herein by reference.

[0002] A printed wiring board has a base film and wiring arranged on the base film. To create multiple layers of wiring, a substrate may be laminated on the printed wiring board. More specifically, an adhesive layer is arranged on the base film so as to cover the wiring, and the substrate is arranged on the adhesive layer.

[0003] The substrate described in JP 2005-48269 A (Patent Document 1) has an insulating layer, a rust-proofing layer disposed on the insulating layer, and a copper layer disposed on the rust-proofing layer.

[0004] Japanese Patent Application Laid-Open No. 2005-48269

[0005] The printed wiring board of the present disclosure comprises a first base film, a first wiring, an adhesive layer, a second base film, and a seed layer. The first wiring is disposed on the first base film. The adhesive layer is disposed on the first base film so as to cover the first wiring. The second base film is disposed on the adhesive layer. The seed layer is disposed on the second base film. A through hole exposing a portion of the first wiring is formed in the adhesive layer, the second base film, and the seed layer. The constituent material of the seed layer is a nickel-chromium alloy containing zinc. In the seed layer on the inner wall surface of the through hole, the zinc concentration in the constituent material of the seed layer is 5 atomic percent or more. The seed layer has a main surface facing the second base film. The surface roughness of the main surface is 1.5 μm or less.

[0006] FIG. 1 is a plan view of a printed wiring board 100. FIG. 2 is a plan view of the printed wiring board 100 as viewed from the opposite side to that of FIG. 1. FIG. 3 is a plan view of the printed wiring board 100, omitting the adhesive layer 30, the base film 40, and the wiring 50. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a manufacturing process diagram of the printed wiring board 100. FIG. 6 is a cross-sectional view illustrating a conductive layer forming step S2. FIG. 7 is a cross-sectional view illustrating a resist pattern forming step S3. FIG. 8 is a cross-sectional view illustrating an electrolytic plating step S4. FIG. 9 is a cross-sectional view illustrating a resist pattern removing step S5. FIG. 10 is a cross-sectional view illustrating an etching step S6. FIG. 11 is a cross-sectional view illustrating a substrate attaching step S7. FIG. 12 is a cross-sectional view illustrating a through-hole forming step S8. FIG. 13 is a cross-sectional view illustrating a conductive layer forming step S9. FIG. 14 is a cross-sectional view illustrating a resist pattern forming step S10. FIG. 15 is a cross-sectional view illustrating an electrolytic plating step S11. FIG. 16 is a cross-sectional view illustrating a resist pattern removing step S12. Fig. 17 is a cross-sectional view of modified example 1 of printed wiring board 100. Fig. 18 is a cross-sectional view of printed wiring board 100A. Fig. 19 is an enlarged cross-sectional view of printed wiring board 100A near the inner wall surface of through hole 40a. Fig. 20 is an enlarged cross-sectional view of printed wiring board 100 near the inner wall surface of through hole 40a.

[0007] [Problem to be Solved by the Present Disclosure] When laminating the substrates described in Patent Document 1 to form a multi-layer wiring, through-holes are formed in the adhesive layer, insulating layer, rust-proofing layer, and copper layer to expose a portion of the wiring. However, in this case, a protrusion made of the rust-proofing layer may remain on the inner wall surface of the through-hole. Such a protrusion can reduce the reliability of the multi-layer wiring.

[0008] The printed wiring board of the present disclosure has been made in consideration of the above-described problems of the conventional technology. More specifically, the present disclosure provides a printed wiring board that can improve the reliability between multilayered wiring.

[0009] [Advantages of the Present Disclosure] According to the printed wiring board of the present disclosure, it is possible to improve the reliability between multilayered wirings.

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0011] (1) A printed wiring board according to one embodiment includes a first base film, a first wiring, an adhesive layer, a second base film, and a seed layer. The first wiring is disposed on the first base film. The adhesive layer is disposed on the first base film so as to cover the first wiring. The second base film is disposed on the adhesive layer. The seed layer is disposed on the second base film. A through hole is formed in the adhesive layer, the second base film, and the seed layer, exposing a portion of the first wiring. The seed layer is made of a nickel-chromium alloy containing zinc. In the seed layer on the inner wall surface of the through hole, the zinc concentration in the seed layer material is 5 atomic percent or more. The seed layer has a main surface facing the second base film. The surface roughness of the main surface is 1.5 μm or less. The printed wiring board described above in (1) enables increased reliability between multilayered wiring.

[0012] (2) In the printed wiring board of (1) above, a protrusion made of a seed layer may be formed on the inner wall surface of the through hole. The height of the protrusion may be 2.0 μm or less. The printed wiring board of (2) above can improve the reliability between multilayered wiring.

[0013] (3) In the printed wiring board of (1) or (2), the zinc concentration in the constituent material of the seed layer is 0.42 μg / cm ２ It may be more than that.

[0014] (4) The printed wiring boards of (1) to (3) above may further include a second wiring having a seed layer, a conductive layer disposed on the seed layer, and an electroplated layer disposed on the conductive layer.

[0015] (5) In the printed wiring boards of (1) to (4) above, the first wiring may have a first coil portion wound in a spiral shape in a planar view, and the second wiring may have a second coil portion wound in a spiral shape in a planar view. The first wiring may have a top surface. The thickness of the adhesive layer between the top surface and the second base film may be 1 μm or more and 50 μm or less. The thickness of the second base film may be 1 μm or more and 35 μm or less. The printed wiring board of (5) above can improve the performance of the coil device while increasing the reliability between the multilayered wiring.

[0016] [Details of the embodiment of the present disclosure] The details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated. The printed wiring board according to the embodiment is referred to as a printed wiring board 100.

[0017] <Configuration of Printed Wiring Board 100> The configuration of the printed wiring board 100 will be described below.

[0018] FIG. 1 is a plan view of printed wiring board 100. FIG. 2 is a plan view of printed wiring board 100 viewed from the opposite side to that of FIG. 1. FIG. 3 is a plan view of printed wiring board 100 omitting adhesive layer 30, base film 40, and wiring 50. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. As shown in FIGS. 1 to 4, printed wiring board 100 has base film 10, wiring 20 and wiring 21, adhesive layer 30 and adhesive layer 31, base film 40, wiring 50, and base film 60.

[0019] The base film 10 has a main surface 10a and a main surface 10b. The main surfaces 10a and 10b are end surfaces of the base film 10 in the thickness direction. The main surface 10b is the surface opposite to the main surface 10a. The base film 10 is made of a flexible, electrically insulating material. For example, the base film 10 is made of polyimide.

[0020] The wiring 20 is disposed on the main surface 10a. The wiring 20 has a coil portion 20a. The coil portion 20a is formed by winding the wiring 20 in a spiral shape in a plan view. The wiring 21 is disposed on the main surface 10b. The wiring 21 has a coil portion 21a. The coil portion 21a is formed by winding the wiring 21 in a spiral shape in a plan view.

[0021] The first end and the second end of the wiring 20 are located at the outermost and innermost peripheries of the coil portion 20a, respectively. The first end and the second end of the wiring 21 are located at the innermost and outermost peripheries of the coil portion 21a, respectively.

[0022] Each of the wiring 20 and the wiring 21 has a seed layer 22, a conductive layer 23, and an electrolytic plating layer 24. The seed layer 22 is disposed on the main surfaces (main surfaces 10a and 10b) of the base film 10. The constituent material of the seed layer 22 is, for example, a nickel-chromium alloy.

[0023] The conductive layer 23 is disposed on the seed layer 22. A through hole 10c (not shown) is formed in the base film 10, the seed layer 22 at the second end of the wiring 20, and the seed layer 22 at the first end of the wiring 21. The conductive layer 23 is formed on the seed layer 22 as well as on the inner wall surface of the through hole 10c.

[0024] The conductive layer 23 is made of, for example, copper. The electrolytically plated layer 24 is disposed on the conductive layer 23. The electrolytically plated layer 24 is made of, for example, copper. The second end of the wiring 20 and the first end of the wiring 21 are electrically connected to each other by the conductive layer 23 and the electrolytically plated layer 24, which are disposed on the inner wall surface of the through hole 10c.

[0025] The adhesive layer 30 is disposed on the main surface 10a so as to cover the wiring 20. The adhesive layer 31 is disposed on the main surface 10b so as to cover the wiring 21. The adhesive layer 30 and the adhesive layer 31 are made of, for example, an epoxy adhesive.

[0026] The base film 40 is disposed on the adhesive layer 30. The base film 40 is made of a flexible, electrically insulating material. The base film 40 is made of, for example, polyimide. The wiring 20 has a top surface 20b. The thickness of the adhesive layer 30 between the top surface 20b and the base film 40 is defined as thickness T. Thickness T may be 1 μm or more and 50 μm or less. Thickness T may be 1 μm or more and 5 μm or less. The thickness of the base film 40 is defined as thickness T1. Thickness T1 is, for example, 1 μm or more and 35 μm or less. Thickness T1 may be 5 μm or more and 25 μm or less, or 12 μm or more and 18 μm or less.

[0027] The wiring 50 is disposed on the base film 40. The wiring 50 has a coil portion 50a. The coil portion 50a is formed by winding the wiring 50 in a spiral shape in a plan view.

[0028] The wiring 50 includes a seed layer 51, a copper layer 52, a conductive layer 53, and an electrolytic plating layer 54. The seed layer 51 is disposed on the base film 40. The constituent material of the seed layer 51 is a nickel-chromium alloy containing zinc. The zinc concentration in the constituent material of the seed layer 51 is, for example, 0.42 μg / cm ２ That is all. The zinc concentration in the constituent material of the seed layer 51 is measured as follows. First, a wiring 50 of an arbitrary size is cut out. Next, the cut out wiring 50 is treated with a mixed solution of 80 g / L hydrogen peroxide and 60 g / L sulfuric acid to remove the copper layer (copper layer 52, conductive layer 53, and electrolytic plating layer 54) and expose the seed layer 51. Thereafter, the exposed seed layer 51 is dissolved in 10 g / L hydrochloric acid, and the hydrochloric acid in which the seed layer 51 has been dissolved is subjected to ICP (Inductively Coupled Plasma) analysis to measure the zinc concentration in the constituent material of the seed layer 51.

[0029] The seed layer 51 has a principal surface 51a and a principal surface 51b. The principal surface 51a and the principal surface 51b are end surfaces of the seed layer 51 in the thickness direction. The principal surface 51a faces the base film 40. The principal surface 51b is the surface opposite to the principal surface 51a. The surface roughness of the principal surface 51a is 1.5 μm or less. The surface roughness of the principal surface 51a may be, for example, 1.3 μm or less, or 1.1 μm or less. The surface roughness of the principal surface 51a is measured by the following method. First, a cross-sectional image is acquired using a scanning electron microscope (SEM). Second, a straight line parallel to the interface between the seed layer 51 and the base film 40 is drawn on the acquired cross-sectional image. If microscopic irregularities exist at the interface between the seed layer 51 and the base film 40, this straight line is the average line of the cross-sectional curve of the interface. The average line is a straight line drawn so that the area defined by the average line and the portion of the cross-sectional curve located above the average line is equal to the area defined by the portion of the cross-sectional curve located below the average line. Third, the maximum and minimum values ​​of the distance between this straight line and the main surface 51a are calculated. The difference between these maximum and minimum values ​​represents the surface roughness of the main surface 51a.

[0030] The copper layer 52 is disposed on the seed layer 51. The copper layer 52 is made of copper. The conductive layer 53 is disposed on the seed layer 51 with the copper layer 52 interposed therebetween. The conductive layer 53 is made of, for example, copper. The wiring 50 does not necessarily have to have the copper layer 52. In this case, the conductive layer 53 is disposed directly on the seed layer 51.

[0031] The first and second ends of the wiring 50 are located at the outermost and innermost peripheries of the coil portion 50a, respectively. The through hole 40a is formed in the adhesive layer 30, the base film 40, and the seed layer 51 and copper layer 52 at the first end of the wiring 50. The wiring 20 is partially exposed from the through hole 40a (more specifically, the top surface 20b at the first end of the wiring 20 is exposed). The conductive layer 53 is also formed on the top surface 20b exposed from the through hole 40a and on the inner wall surface of the through hole 40a. The zinc concentration in the constituent material of the seed layer 51 on the inner wall surface of the through hole 40a is, for example, 5 atomic percent or more. The zinc concentration in the constituent material of the seed layer 51 on the inner wall surface of the through hole 40a may be 10 atomic percent or more, or may be 20 atomic percent or more. The zinc concentration in the constituent material of seed layer 51 on the inner wall surface of through hole 40 a is measured by observing the cross section using a transmission electron microscope (TEM) and performing EDX (Energy Disperse X-ray Spectroscopy) analysis during the cross section observation. The measurement range is set to a range of 5 μm from the inner wall surface of through hole 40 a in the substrate planar direction (planar direction of base film 40).

[0032] The electrolytic plating layer 54 is disposed on the conductive layer 53. The second end of the wiring 20 and the first end of the wiring 50 are electrically connected to each other by the conductive layer 53 and the electrolytic plating layer 54, which are disposed on the inner wall surface of the through hole 40a and on the top surface 20b exposed from the through hole 40a. The constituent material of the electrolytic plating layer 54 is, for example, copper.

[0033] The base film 60 is disposed on the adhesive layer 31. The base film 60 is made of a flexible, electrically insulating material, such as polyimide.

[0034] <Method for Manufacturing Printed Wiring Board 100> A method for manufacturing the printed wiring board 100 will be described below.

[0035] 5 is a manufacturing process diagram of printed wiring board 100. As shown in Fig. 5, the manufacturing method of printed wiring board 100 includes a preparation step S1, a conductive layer forming step S2, a resist pattern forming step S3, an electrolytic plating step S4, a resist pattern removing step S5, an etching step S6, a substrate attaching step S7, a through-hole forming step S8, a conductive layer forming step S9, a resist pattern forming step S10, an electrolytic plating step S11, a resist pattern removing step S12, and an etching step S13.

[0036] In the preparation step S1, a base film 10 is prepared. In the base film 10 prepared in the preparation step S1, seed layers 22 are disposed on the main surfaces 10a and 10b. Before the conductive layer formation step S2 is performed, through holes 10c are formed in the seed layer 22 disposed on the main surface 10a and the seed layer 22 disposed on the main surface 10b.

[0037] 6 is a cross-sectional view illustrating the conductive layer forming step S2. As shown in FIG. 6, in the conductive layer forming step S2, a conductive layer 23 is formed on the seed layer 22. The conductive layer 23 is formed by, for example, electroless plating or sputtering. Although not shown, the conductive layer 23 is also formed on the inner wall surface of the through hole 10c.

[0038] 7 is a cross-sectional view illustrating the resist pattern forming step S3. As shown in FIG. 7, in the resist pattern forming step S3, a resist pattern 25 is formed on the conductive layer 23. The resist pattern 25 has openings 25a. The conductive layer 23 is exposed through the openings 25a. The resist pattern 25 is formed, for example, by applying a dry film resist to the conductive layer 23 and then exposing and developing the applied dry film resist.

[0039] Fig. 8 is a cross-sectional view illustrating the electrolytic plating step S4. As shown in Fig. 8, in the electrolytic plating step S4, an electrolytic plating layer 24 is formed on the conductive layer 23 exposed from the opening 25a by electrolytic plating. Fig. 9 is a cross-sectional view illustrating the resist pattern removal step S5. As shown in Fig. 9, in the resist pattern removal step S5, the resist pattern 25 is removed from the conductive layer 23.

[0040] 10 is a cross-sectional view for explaining the etching step S6. As shown in FIG. 10, in the etching step S6, the conductive layer 23 and the seed layer 22 that were under the resist pattern 25 are removed by etching.

[0041] 11 is a cross-sectional view illustrating the substrate attaching step S7. As shown in FIG. 11, in the substrate attaching step S7, the substrate 70 is attached to the base film 10 by the adhesive layer 30. In the substrate attaching step S7, first, the substrate 70 is prepared. The substrate 70 has a base film 40, a seed layer 51 disposed on the base film 40, and a copper layer 52 disposed on the seed layer 51. Note that if the wiring 50 does not have the copper layer 52, the copper layer 52 is peeled off at this stage.

[0042] Secondly, in the substrate attachment step S7, the substrate 70 is pressed toward the base film 10 with the uncured adhesive layer 30 interposed between the substrate 70 and the base film 10. Heating is also performed at this time. This cures the adhesive layer 30, and the substrate 70 (base film 40) is attached to the base film 10. In the substrate attachment step S7, the base film 60 is attached to the base film 10 by the adhesive layer 31 in a similar manner.

[0043] 12 is a cross-sectional view illustrating the through hole forming step S8. As shown in FIG. 12, in the through hole forming step S8, a through hole 40a is formed in the adhesive layer 30, the base film 40, the seed layer 51, and the copper layer 52. The through hole 40a is formed by irradiating with laser light. As a result, the top surface 20b at the first end of the wiring 20 is exposed from the through hole 40a.

[0044] 13 is a cross-sectional view illustrating the conductive layer forming step S9. As shown in FIG. 13, in the conductive layer forming step S9, a conductive layer 53 is formed on the copper layer 52. The conductive layer 53 is formed by, for example, electroless plating or sputtering. The conductive layer 53 is also formed on the inner wall surfaces of the through holes 40a and on the top surfaces 20b exposed from the through holes 40a.

[0045] 14 is a cross-sectional view illustrating the resist pattern forming step S10. As shown in FIG. 14, in the resist pattern forming step S10, a resist pattern 55 is formed on the conductive layer 53. The resist pattern 55 has openings 55a. The conductive layer 53 is exposed through the openings 55a. The resist pattern 55 is formed, for example, by applying a dry film resist to the conductive layer 53 and then exposing and developing the applied dry film resist.

[0046] 15 is a cross-sectional view illustrating the electrolytic plating step S11. As shown in FIG. 15, in the electrolytic plating step S11, an electrolytic plating layer 54 is formed on the conductive layer 53 exposed from the opening 55 a by an electrolytic plating method.

[0047] 16 is a cross-sectional view illustrating the resist pattern removal step S12. As shown in FIG. 16, in the resist pattern removal step S12, the resist pattern 55 is removed from the conductive layer 53. In the etching step S13, the conductive layer 53, the copper layer 52, and the seed layer 51 that were present under the resist pattern 55 are removed by etching. As a result, the printed wiring board 100 having the structure shown in FIGS. 1 to 4 is formed.

[0048] <Variation 1> Fig. 17 is a cross-sectional view of Variation 1 of printed wiring board 100. Although Figs. 1 to 4 show an example in which wiring 21 is arranged on main surface 10b, wiring 21 may also be arranged on the main surface (main surface 60a) of base film 60 facing main surface 10b, as shown in Fig. 17. In this case, two single-sided boards (a single-sided board having wiring 20 arranged on main surface 10a, and a single-sided board having wiring 21 arranged on main surface 60a) are continuously stacked in the thickness direction.

[0049] <Variation 2> Although an example in which the number of wiring layers is three is shown in Figures 1 to 4, the number of wiring layers of printed wiring board 100 may be two or more, and may be five or more. Printed wiring board 100 may be configured by combining a double-sided board and a single-sided board, or by combining multiple single-sided boards. Note that a double-sided board refers to a case in which wiring is arranged on both main surfaces of a single base film. In the example shown in Figures 1 to 4, base film 10, wiring 20, and wiring 21 form a single double-sided board.

[0050] Effects of Printed Wiring Board 100 The effects of printed wiring board 100 will be described below in comparison with a printed wiring board according to a comparative example. The printed wiring board according to the comparative example is designated as printed wiring board 100A.

[0051] Fig. 18 is a cross-sectional view of printed wiring board 100A. Fig. 19 is an enlarged cross-sectional view of printed wiring board 100A near the inner wall surface of through hole 40a. As shown in Figs. 18 and 19, printed wiring board 100A has base film 10, traces 20 and 21, adhesive layers 30 and 31, base film 40, traces 50, and base film 60. In this respect, the configuration of printed wiring board 100A is common to the configuration of printed wiring board 100.

[0052] In the printed wiring board 100A, the zinc concentration in the constituent material of the seed layer 51 is 0.42 μg / cm ２ In printed wiring board 100A, the surface roughness of main surface 51a is greater than 1.5 μm. In printed wiring board 100A, protrusions 40aa are present on the inner wall surfaces of through holes 40a. Protrusions 40aa are formed of seed layer 51. In these respects, the configuration of printed wiring board 100A differs from the configuration of printed wiring board 100.

[0053] In the through-hole forming step S8, the through-hole 40a is formed by irradiating a laser beam as described above. The intensity of the laser beam needs to be set low to minimize damage to the wiring 20 (top surface 20b). As a result, the seed layer 51, which is made of a nickel-chromium alloy and has poor workability, may not be sufficiently processed, resulting in the formation of a protrusion 40aa on the inner wall surface of the through-hole 40a. If the conductive layer forming step S9 and the electrolytic plating step S11 are performed with the protrusion 40aa formed on the inner wall surface of the through-hole 40a, a void will be formed near the protrusion 40aa. This void can reduce the reliability of the connection between the wiring 20 and the wiring 50.

[0054] On the other hand, the surface roughness of the main surface 51a is 1.5 μm or less, which improves the workability of the seed layer 51. In addition, in the printed wiring board 100, the zinc concentration in the constituent material of the seed layer 51 is 0.42 μg / cm ２ This also lowers the melting point of the constituent material of seed layer 51, improving the workability of seed layer 51. As a result, in printed wiring board 100, protrusions 40aa are less likely to be formed on the inner wall surfaces of through holes 40a.

[0055] FIG. 20 is an enlarged cross-sectional view of the printed wiring board 100 near the inner wall surface of the through hole 40a. As shown in FIG. 20 , in the printed wiring board 100, the processability of the seed layer 51 is improved, so that even if a protrusion 40aa is formed on the inner wall surface of the through hole 40a, the protrusion height (height H) of the protrusion 40aa is reduced. The height H is the difference in height between the inner wall surface of the through hole 40a in the base film 40 and the inner wall surface of the through hole 40a in the seed layer 51. In the printed wiring board 100, the height H may be 2.0 μm or less, or may be 1.5 μm or less. Furthermore, in the printed wiring board 100, the height H may be 0 μm, 0.2 μm or more, or 0.3 μm or more. The height H is measured on a cross-sectional image acquired using an SEM.

[0056] In this way, in the printed wiring board 100, the convex portion 40aa is no longer formed on the inner wall surface of the through hole 40a or the height H is reduced, making it difficult for a gap to form near the convex portion 40aa, thereby improving the connection reliability between the wiring 20 and the wiring 50.

[0057] In the printed wiring board 100, as the thickness T decreases, the distance between the coil portion 20a and the coil portion 50a decreases, and the magnetic flux generated by the printed wiring board 100 becomes stronger, thereby improving the performance of the printed wiring board 100 as a coil device. On the other hand, as the thickness T increases, the intensity of the laser light must be reduced when forming the through hole 40a, making it easier to form the convex portion 40aa. Therefore, when the thickness T is 1 μm or more and 50 μm or less, the connection reliability between the wiring 20 and the wiring 50 can be increased while improving the performance of the coil device.

[0058] <Evaluation of Connection Reliability> Samples 1 to 8 were prepared to evaluate connection reliability. As shown in Table 1, the zinc concentration in the constituent material of seed layer 51 on the inner wall surface of through hole 40a was changed in Samples 1 to 4. The surface roughness of main surface 51a was constant at 1.5 μm in Samples 1 to 4. The surface roughness of main surface 51a was changed in Samples 5 to 8. The zinc concentration in the constituent material of seed layer 51 on the inner wall surface of through hole 40a was constant at 5 atomic percent in Samples 5 to 8. As a result, the height H changed in Samples 1 to 8.

[0059]

[0060] The zinc concentration in the constituent material of the seed layer 51 on the inner wall surface of the through hole 40a is 5 atomic percent or more (0.42 μg / cm ２Condition A is that the surface roughness of the main surface 51a is 1.5 μm or less, and Condition B is that the surface roughness of the main surface 51a is 1.5 μm or less. Conditions A and B were satisfied in Sample 3, Sample 4, and Samples 6 to 8. On the other hand, either Condition A or Condition B was not satisfied in Sample 1, Sample 2, and Sample 5. In Sample 3, Sample 4, and Samples 6 to 8, the height H was 2.0 μm or less. On the other hand, in Sample 1, Sample 2, and Sample 5, the height H was greater than 2.0 μm. This comparison shows that when Conditions A and B are satisfied, the processability of the seed layer 51 is improved and the height H is reduced.

[0061] A thermal cycle test was performed on Samples 1 to 8, and the connection reliability between the wiring 20 and the wiring 50 was evaluated by observing whether or not cracks occurred after the thermal cycle test. The thermal cycle test was performed according to the method specified in IEC 60068-2-14-Na. The high-temperature temperature of the thermal cycle was 85°C, and the low-temperature temperature was -40°C. The thermal cycle was repeated 100 times. The results of the thermal cycle test are shown in Table 1. In Table 1, a sample was evaluated as "A" if the change in electrical resistivity after the thermal cycle test was within ±10% of the electrical resistivity before the thermal cycle test, and a sample was evaluated as "B" if the change in electrical resistivity after the thermal cycle test was not within ±10% of the electrical resistivity before the thermal cycle test.

[0062] The results of the thermal cycle test for Samples 3, 4, and 6 to 8 were better than the results of the thermal cycle test for Samples 1, 2, and 5. This comparison shows that when Condition A and Condition B are satisfied, the height H is reduced, making it difficult for voids to form near the protrusion 40aa, and improving the connection reliability between the wiring 20 and the wiring 50.

[0063] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims.

[0064] 10 base film, 10a main surface, 10b main surface, 10c through hole, 20 wiring, 20a coil portion, 20b top surface, 21 wiring, 21a coil portion, 22 seed layer, 23 conductive layer, 24 electroplated layer, 25 resist pattern, 25a opening, 30 adhesive layer, 31 adhesive layer, 40 base film, 40a through hole, 40aa convex portion, 50 wiring, 50a coil portion, 51 seed layer, 51a main surface, 51b main surface, 52 copper layer, 53 conductive layer, 54 electroplated layer, 55 resist pattern, 55a opening, 60 base film, 60a main surface, 70 substrate, 100, 100A printed wiring board, H height, S1 preparation step, S2 conductive layer forming step, S3 resist pattern forming step, S4 Electrolytic plating step, S5 resist pattern removal step, S6 etching step, S7 substrate attachment step, S8 through hole formation step, S9 conductive layer formation step, S10 resist pattern formation step, S11 electrolytic plating step, S12 resist pattern removal step, S13 etching step, T, T1 thickness.

Claims

1. A printed wiring board comprising: a first base film, a first wiring, an adhesive layer, a second base film, and a seed layer, wherein the first wiring is disposed on the first base film, the adhesive layer is disposed on the first base film so as to cover the first wiring, the second base film is disposed on the adhesive layer, and the seed layer is disposed on the second base film, a through hole exposing a portion of the first wiring is formed in the adhesive layer, the second base film and the seed layer are made of a nickel-chromium alloy containing zinc, and in the seed layer on the inner wall surface of the through hole, the zinc concentration in the material of the seed layer is 5 atomic percent or more, the seed layer has a main surface facing the second base film, and the surface roughness of the main surface is 1.5 μm or less.

2. The printed wiring board according to claim 1, wherein the inner wall surface of the through hole has a protrusion formed of the seed layer, and the height of the protrusion is 2.0 μm or less.

3. The zinc concentration in the constituent material of the seed layer is 0.42 μg / cm ２ The printed wiring board according to claim 1 or 2, wherein 4. A printed wiring board according to any one of claims 1 to 3, further comprising a second wiring having the seed layer, a conductive layer disposed on the seed layer, and an electrolytic plating layer disposed on the conductive layer.

5. The printed wiring board as described in claim 4, wherein the first wiring and the second wiring respectively have a first coil portion and a second coil portion wound in a spiral shape in a planar view, the first wiring has a top surface, the thickness of the adhesive layer between the top surface and the second base film is 1 μm or more and 50 μm or less, and the thickness of the second base film is 1 μm or more and 35 μm or less.

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